Symbolic analysis of electronic circuits based on a

tree enumeration technique

M. Sharif-Bakhtiar
M. AN Ahmad

Indexing terms: Electronic circuits, Symbolic analysis, Unistor graphs

For the two-port network of Fig. 1 the transfer func-

Abstract: A topological method for symbolic tion H(s) = V0(s)/Iin(s) can be written as
analysis of electronic circuits is presented. The
method is based on the derivation of the tree pro- A12(s) - A12.(s)
H(s) = (1)
ducts of unistor graphs. A straightforward pro-
cedure to produce all directed trees of a unistor where An and A o s are the determinant and cofactors of
graph in independent groups is given. The the network node-admittance matrix Yn, respectively.
network cofactor is obtained by calculating the
network determinant of a modified unistor graph. Ii h
A computer program based on the given method 1 2
written for PCs is also described. +

V H(s) v2=v
) 1

V 21
1 Introduction Fig. 1 Two-port network with transfer function H(s) = V0(s)/Iin(s)
Network transfer function in its symbolic form can be
used as an effective tool in the analysis and design of Using the Binet-Cauchy theorem it can be shown that
electronic circuits [1, 2]. For this reason several attempts [12]
to produce computer programs for the derivation of the An = Y, e/complete-tree product of tree j) (2)
symbolic transfer function of electronic networks have
been made [3, 4]. The methods for generating the sym- and
bolic transfer function of a network may be categorised
into five different groups as: all complete 2-trees

(i) Matrix manipulation [5] x complete 2-tree f . J product (3)

(ii) Parameter extraction [6]
(iii) Numerical interpolation [7]
(iv) Flow graph techniques [8]
(v) Tree enumeration [9]
Amongst these, topological algorithms based on tree enu-
meration are considered to suffer from excessive require-
ments for computer time and memory [10]. However,
this is also the case with the algorithms based on matrix
manipulation and eigenvalue methods when the circuit
includes more than a few nodes. This is due to the great
number of terms that have to be manipulated. Recent
work on matrix manipulation techniques [11] has shown
that, to extend the usefulness of these techniques to larger
electronic networks, application of methods such as hier-
archical decomposition and the use of other topological
methods is unavoidable.
In this paper it is shown that topological methods
based on tree enumeration can be efficiently used for
symbolic analysis of fairly large electronic networks
without the need for excessive computer time and
memory.
Paper 9083G (E10), first received 10th February and in revised form 6th
July 1992
The authors are with the Department of Electrical Engineering, Sharif
University of Technology, PO Box 11365-8639, Azadi Ave, Tehran,
Iran
68
where e, and et = ± 1 and r is the reference node.
Application of eqns. 2 and 3 requires the time-
consuming enumeration of all complete trees and com-
plete 2-trees of the graph. Sign permutation must also be
done for each enumerated complete tree or 2-tree. Sign
permutation can be avoided by the application of unistor
graphs [13], where for a unistor graph eqns. 2 and 3 can
be written as
An = X (directed tree admittance product) (4)
all directed trees
and
[ directed 2-tree (
/.
\J r
admittance product (5)
To use eqns. 4 and 5 for calculating network determinant
and cofactors, an efficient algorithm to enumerate all
directed trees and 2-trees is given in the following
Section.
2 Generation of all directed trees of a unistor
graph
The algorithm presented for enumeration of the directed
trees of a given graph has two basic properties:
(i) Generation of directed trees in independent groups
IEE PROCEEDINGS-G, Vol. 140, No. 1, FEBRUARY 1993
 (ii) Automatic generation of directed trees without the
need to examine the direction of the branches for each
enumerated tree.
To explain the algorithm a few basic definitions are given
first.
Definition 1: Graph G{A, B} is obtained from G by
removing the branches of subgraph A and contracting
the branches of B. Collection of all trees of G{A, B} is
denoted by T{A, B}.
Definition 2: A 'series operation' in a graph is referred to
the contraction of a branch from two series branches.
Definition 3: A 'parallel operation' is referred to the
removal of one branch from two parallel branches.
Definition 4: A 'parallel-series graph' (PS graph) is a
graph which can be reduced to a single branch by apply-
ing a sequence of parallel and series operations.
With the application of the properties of directed trees
[13], the proof of the following properties is trivial.
Property 1: Let bt be a directed branch of a graph G with
the directed trees T, and add another directed branch bj
in series with b{ to form G} in which bx is connected to
nodes i and k, and bj is connected to nodes j and k. The
directed trees 7} of graph G} can then be derived from T
as follows:
Case 1:ft,and bj are incident to nodes i and j respec-
tively. Then
bj)T{bi,0} (6)
Case 2: b{ and bj are both incident to node k. Then Gj
has no directed tree, i.e. 7} = 0.
Case 3: bj is incident to node k and the direction of bt
is from node k toward node i. Then
Tj = biT{bi,0}+bibjT{0,bi} (7)
Case 4: bt is incident to node k and the direction of bj
is from node k toward node j . Then
= bjT{bt,0}+btbjT{0,bt} (8)
Property 2: Let b{ be a branch of G, and add another
branch bj in parallel with bt to form graph Gj. The
directed trees 7} can than be derived from T as follows:
Case 1: bt and bj are of the same direction. Then
Tj=T{bi,0}+(bi + bJ)T{0,bi} (9)
Case 2: b( and bj are of opposite directions. Then
Tj = T{bt, 0} + bt T{0, bt} + bj T'{0, bt) (10)
where T" is the set of trees that could not be directed
trees due to the direction of bt. These trees constitute
directed trees in combination with bj.
Properties 1 and 2 suffice for the tree enumeration of a
PS graph. The number of branches in a PS graph can be
reduced by applying a parallel or series operation. The
order of a PS graph can also be reduced by applying the
series operation. Consecutive application of parallel and
series operations reduces a PS graph to a single branch.
Starting from this remaining single branch, the original
PS graph can be reconstructed by following the reverse
sequence of parallel-series operations. Using properties 1
and 2 the directed trees of the PS graph can be also enu-
merated when reconstructing the original graph.
1EE PROCEEDINGS-G, Vol. 140, No. 1, FEBRUARY 1993
Property 3: Let bt be a branch of G incident to the refer-
ence node, then
Tj=T{bi,0} + biT{0,bi} (11)
Note that the expression for T has a grouping property.
The two groups of trees, i.e. T{fc,-, 0} and T{0, b,}, can be
independently generated. 7} can then be derived by
grouping the two sets of trees using property 3.
Theorem 1: Given a directed graph G, there exists a set
of PS graphs each obtained from G by removing some
branches or contracting some others, such that the trees
of G are the sum of the trees of these PS graphs.
The proof of this theorem directly results from the
above properties ans is similar to that given in Reference
14 for undirected graphs.
Thus, directed trees of a given graph can be obtained
in independent groups by the following steps:
Step 1: Apply parallel-series operation to reduce the
number of branches and nodes of the graph G. In appli-
cation of series operation it must be noted that this oper-
ation does not apply to two series unistors when the
reference node is the common node between the two uni-
stors.
Step 2: When no further parallel-series operation is
possible, remove (and contract) a branch incident to the
reference node to produce two independent but smaller
graphs.
Step 3: For the smaller subgraphs produced in Step 2
proceed to Step 1 until all subgraphs are reduced to a
single branch.
Step 4: Starting from each remaining single branch, by
following the reverse process of parallel-series operations
performed to reduce the graph, an independent set of
trees of the given graph can be constructed using proper-
ties 1, 2 and 3.
The successive parallel-series operations performed for
the reduction of the original graph or subgraphs are
stored in a table called a PS table. The PS table contains
all the information needed to rebuild the original graph
from the remaining single branches. It also serves as a
guideline to construct trees of the graph and contains all
the information about the trees in a small memory space.
Trees of a given graph will be generated from the PS
table only when the final expression of the tree products
is needed. The size of each group of trees can also be
controlled by the application of property 3 when con-
structing the PS table.
2.1 Example 1
For the unistor graph shown in Fig. 2 the PS table and
corresponding parallel-series operations are shown in
Table 1 and Fig. 3, respectively. Table 2 shows the evolu-
Fig. 2 Unistor graph of example 1
69
tion of the directed trees by following the PS table from
bottom to the top. The directed trees are produced in
two independent groups. One group corresponds to the
sponding to the network determinant. This is the price
that is paid for calculating the directed trees in a straight-
forward procedure without having to either perform any
test to assure the completeness of the trees or to calculate
the sign permutation for each tree.

Table 2: Tree evolution of graph in Fig. 2

row 1 row 6
PS table row V Comments
First group:
5 a+b (0) property 2, case 1
4 ab+bd (a) property 1, case 1
3 ab+bd + ae (0) property 2, case 2
2 abf + bdf + aef (0) property 1, case 4
1 abf + bdf + aef (0) property 3
row 7 Second group:
10 b (0) property 2, case 2
9 a+b (0) property 2, case 1
8 ab + bd (0) property 1, case 3
7 ab+ae+bd + de (0) property 2, case 1
6 abc + aec + bdc + dec ( 0 ) property 3
T = {abf + bdf + aef) + (abc + aec + bdc + dec)

Once generated, the admittance product terms, corres-

ponding to each directed tree, are grouped in terms of the
power of the s terms. The search for cancellation is then
performed in each group independently. This results in a
considerably less computer time compared with the com-
row 10
puter time that is needed for sign permutation.

4 Calculation of network cofactors

The application of eqn. 5 to calculate the cofactor A,-,- of a

Fig. 3 Graph reduction sequence corresponding to PS table of Table 1
graph with the unistor c removed and the other group
corresponds to the graph with the unistor c contracted.
3 Calculation of the network determinant
Once all the directed trees of a network have been gener-
ated, the network determinant can be calculated using
eqn. 4. It should be noted that, owing to the unistor
models chosen for the circuit elements, redundant terms
with opposite signs may be generated. These terms must
be cancelled when sorting the polynomial of s corre-
given network requires the derivation of all directed
2-trees of the network. The following theorems show that
the problem of calculating AfJ- can be reduced to the enu-
meration of the directed trees of a properly modified
graph.
Definition 5: A unistor connected to nodes i and j with
the direction toward node; is denoted by yu.
Theorem 2: In a unistor graph (GJ with node j as the
output, disconnecting any unistor yki from the input node
i and connecting it to the reference node (graph G2) does
not change the cofactor A y .

Proof: Fig. Aa shows a general unistor graph GY with

Table 1 : PS table of unistor graph in Fig. 2
unistor yki incident to the input node i. Let us take the
Row First Second Operation Branch Branches network functions of G2 shown in Fig. Ab as
branch branch deleted producing
r YL- (12)
c — c —
e f f —
d e e e(d)
a d d e(d) (13)
a b b e(d)
End of first group then, for the unistor graph G l5
6 c — c
7 6 e e —
8 6 d d — (14)
9 a b b —
10 6 f f fib)
End of second group (15)
End of PS table
R Removed Solving eqns. 14 and 15 for Vj/Iin results in
S Series
P Parallel (16)
C Contracted Un A - A t t y H
70 IEE PROCEEDINGS-G, Vol. 140, No. 1, FEBRUARY 1993
Comparing eqn. 16 with eqn. 12 proves that the cofactors Proof: Fig. 5 shows the unistor graph G2 which is derived
A(J- for Gx and G2 are the same. from Gl by replacing yjt with yjr = yjt. If the network
function for G2 is taken as

(17)
=

then the voltage at node; of Gx can be written as

(18)

The network function for G^ can be calculated from eqn.

18 as

AIL (19)
/,„ A- Auyn
which proves that the cofactor A y remains unchanged.
y = y
kr ki

Theorem 4: The cofactor Ao- of the unistor graph Gx is

Fig. 4 Unistor graph
a General unistor graph with node i as input
b Unistor graph G, with unistor yki connected to reference node
Fig. 5 General unistor graph with node j as output and with unistor yJt
connected to reference node
Theorem 3: In a unistor graph (GJ and for a unistor yjt,
where / is any internal node in G l5 replacing yjt with a
unistor yjr = yu results in a new graph G2 whose cofactor
Atj is the same as the cofactor Au of Gv
the same as the network determinant calculated from
graph G 2 , where graph G2 is derived from graph G^ by
the following operations:
(i) For unistors incident to the input node, change the
terminating node from node i to the reference node.
(ii) Remove all unistors connected to the output node ;
whose direction is away from node;.
(iii) For each unistor connected to node j , add a
unistor with the same weight from node ; to the reference
node.
(iv) Negate the weight of the unistors connected to
node i, and then reduce the order of the graph by con-
necting node i to node;.
Proof: Fig. 6a shows a general unistor graph Gx with
nodes i and ; as the input and output nodes, respectively.

for all y jk 's

c d
Fig. 6 Unistor graph
a General unistor graph G,
b Unistor graph G, with all unistors incident to input node and all unistors with direction away from output node connected to reference node
c Graph G2 with input source equal to — Vjyi and with voltage source connected to output
d Modified graph for calculating cofactor A y

IEE PROCEEDINGS-G, Vol. 140, No. 1, FEBRUARY 1993 71

Let us assume the network function of Gj to be
(20)
/._
By application of theorems 1 and 2 to Gl5 the unistor
graph G2 shown in Fig. 6b is obtained in which yjr is a
unistor whose value is the sum of the value of all unistors
incident to the reference node from node j . The network
function of G2 can be written as Vj/Iin = A y /A' where,
A' = yjr A" because yjr exists in all directed trees of G 2 .
The total current injected to node) can then be written as
Considering the direction of yik s the directed trees of G2
can be grouped as
T = (yikl + yik2 + ••• + y i k l ) { ( y i k l , y i k 2 , • •.,)>,*„),0} (23)
Thus, the network determinant of G2 can be written as
A" = (^ k l +3', f t 2 + ---+}; lkn )A"' (24)
where, A'" is the directed-tree product of G2 when yik s are
removed.
Application of eqn. 24 to eqn. 22 yields

(25)
(21)
Eqn. 25 shows that the network determinant of G2 when
From eqn. 21 the impedance seen at the output node of yjr is removed and a current equal to
G2 when yjr is removed and a current equal to — JjCViki + yik2 + • • • + yik) is injected to node i is the
- V £ y i k l + yik2 + ••• + yikn) is injected t o node i, as cofactor of Gv
shown in Fig. 6c, can be calculated as The KCL equation at node i proves that the current
injected into each internal node kp is equal to -Vjyik .
(22) By connecting node i to node j and negating the value of
the unistors yik s the current injected to the internal nodes

circuit component equivalent unistor model

1/R f I 1/R

0
©
cs/ \ cs
CD

1/LS i M/LS
-o-
X

"pq pq

Fig. 7 LJnistor models for basic circuit components

72 IEE PR0CEED1NGS-G, Vol. 140, No. 1, FEBRUARY 1993

kp does not change. However, to keep the output equa-
tions unchanged a unistor yjr = (yikl + yik2 + ••• + yikn)
has to be connected to the output node. Therefore, the
output impedance of a network (G3) derived from G2 by
the above operation (Fig. 6d) is the output impedance of
G2 given in eqn. 25, i.e. the network determinant of G3 is
equal to the cofactor Atj of Gv
4 Computer program
A computer program for the derivation of the symbolic
transfer function of electronic circuits was written based
on the algorithm described in the preceding Sections. The
input to this program is a net list similar to that of
SPICE. Active elements are first replaced by their corres-
ponding small signal model. A unistor network is then
generated by replacing each circuit component with its
equivalent unistor model. Fig. 7 shows unistor models for
basic circuit components. The network determinant and
the desired cofactor are consequently calculated from the
unistor graph.
The program was written for an IBM compatible per-
sonal computer based on an 80386 microprocessor with
2MB of RAM and a clock frequency of 26 MHz. Analysis
of different electronic circuits with this program proved
that the symbolic transfer function of fairly large elec-
tronic circuits can be calculated in a fairly short time and
the algorithm efficiency is not restricted to a particular
class of circuit topology.
Fig. 8 Second-order active filter
Fig. 9 Circuit with bipolar transistors to test program performance
a Wide-band amplifer with compensation capacitor Cc
b Small signal model of transistors
IEE PROCEEDINGS-G, Vol. 140, No. 1, FEBRUARY 1993
The computer time for the derivation of the symbolic
transfer function of the second-order active filter shown
in Fig. 8 was 29 s. The amplifier shown in Fig. 9a was
chosen as another example. The transfer function of this
circuit using the transistor hybrid-II model shown in Fig.
9b with all circuit components taken as parameter was
derived in 63 s.
5 Conclusions
A topological method for the derivation of the symbolic
transfer function of electronic circuits has been presented.
Unistor graphs were used for tree enumeration to avoid
sign permutation for each individual tree. An algorithmic
method to enumerate directed trees, without the need to
inspect the direction of the branches of each enumerated
tree, has been also given. The application of a unistor
model for circuit components produces multiple terms
with opposite signs in the transfer function that are can-
celled out when the final sorting of the coefficients is per-
formed.
A method to calculate the cofactors of a given network
by calculating a network determinant from a properly
modified unistor graph was described and the rules to
produce the modified unistor graph were also given.
The performance of the program written for a PC,
based on the given algorithm, proves the effectiveness of
the algorithm for symbolic analysis of electronic circuits.
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