IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO.
5, MAY 2000
On-Chip Characterization of Interconnect Parameters
and Time Delay in 0.18 m CMOS Technology for
ULSI Circuit Applications
Hi-Deok Lee, Member, IEEE, Dae M. Kim, and Myoung-Jun Jang
Abstract—A real time, on-chip characterization technique is
presented for extracting the interconnect parameters and for de-
termining the associated time delays for ULSI circuit applications.
To demonstrate the method, test chips were fabricated in both 0.25
and 0.18 m CMOS technologies, using state of the art process
technologies. Results obtained in these two cases are compared
and the changing trends and issues for interconnect parameters in
making transition from the 0.25 m to the 0.18 m technologies
are discussed. A completed look-up table in conjunction with a
working analytic expression of the time delay enables accurate
modeling and optimization of interconnect parameters and time
delays for a given specification of chip performance.
Index Terms—Interconnect delay time, interconnect param-
eters, multilevel metallization, RC delay in 0.18 m CMOS
technology.
I. INTRODUCTION
T HE CONTINUED improvement of CMOS integrated cir-
cuit density and performance was made possible by the
scale-down of MOSFET’s over the past several decades. How-
ever, the simultaneous reduction of the width and pitch of the
metal line drastically increased the interconnect- induced time
delay, [1]–[5]. For example, induced by mm length metal
interconnect is larger than the gate delay in 0.18 m CMOS
technology by several orders of magnitude. The shrinking width
and space of the line to less than 0.25 m [6], [7] also made the
geometrical variation of the line an important issue in multilevel
metallization technology [8]–[11]. The geometrical line varia-
tion results from nonuniform pattern density or proximity ef-
fect and it occurs even in test patterns for capacitance measure-
ment. This renders the interconnect parameter extraction am-
biguous. It is therefore important for ULSI circuit design to de-
vise a method by which to extract accurately the interconnect
parameters and determine associated . The interconnect ca-
pacitances were extracted on chip by using test circuit [12] or
were measured with the use of capacitance-intensive test pat-
terns, followed by calibration with the field-solver [8]. However,
to date no characterization technique has been reported, which
can extract, on-chip, both the capacitance and resistance simul-
taneously and can also determine the associated time delays.
Manuscript received July 28, 1999; revised December 19, 1999. The review
of this paper was arranged by Editor C. Y. Yang.
H.-D. Lee and M.-J. Jang are with the Memory R&D Division, Hyundai
Electronics Industries Co., Ltd., Choongbuk, 361-480, Korea (e-mail:
hdlee@hmec.co.kr).
D. M. Kim is with the Department of Electronic Engineering, Pohang Uni-
versity of Science and Technology, Kyungbuk, 790-784, Korea.
Publisher Item Identifier S 0018-9383(00)03419-5.
0018-9383/00$10.00 © 2000 IEEE
1073
In this paper, we present a simple electrical means for system-
atically characterizing the interconnect parameters. The method
enables a real time and on-chip characterization of intercon-
nect parameters and related time delay. In this method, the de-
signed novel test patterns are inserted in between CMOS in-
verters constituting a ring oscillator and the resulting difference
of oscillation frequencies are correlated to those parameters.
The method was first applied to 0.25 m CMOS technology
[13] and scaled-down test patterns were fabricated for 0.18 m
CMOS technology for examination. Here the patterns were fur-
ther refined to represent more realistic interconnect routing. The
results obtained in 0.18 m technology are presented and dis-
cussed in this paper. Also presented are issues for intercon-
nect parameters in making transition from 0.25–0.18 m CMOS
technologies.
In Section II, designed test patterns and the parameter extrac-
tion scheme are detailed. In Section III, the measured data are
discussed in comparison with those of 0.25 m CMOS tech-
nology, so that a general trend for changing interconnect pa-
rameters with shrinking device feature size and accompanying
reduction of line width and space are presented. The highlights
of the work are summarized in Section IV.
II. ON-CHIP CHARACTERIZATION OF INTERCONNECT
Three interconnect routing configurations are sketched in
Fig. 1. Fig. 1(a) shows the signal line with dummy upper metal
layer on top. In this case, the capacitance between the signal
line and substrate ( ) and the dummy metal layer ( )
come into play concurrently, i.e., . In the
presence of adjacent or over-laying interconnect line, the cou-
pling ( ) or cross-over ( ) capacitance is added as shown
in Fig. 1(b) and (c), respectively. The value of in Fig. 1(a)
becomes different in the presence of or due to the
variation of the geometrical profile or electric field distribution
of the interconnect line. However, what is important is the total
capacitance for a given signal line and this total cumulatively
added capacitance is characterized in this work.
A. Test Patterns
Three capacitance components are measured by using test pat-
terns shown in Fig. 2. Fig. 2(a) shows the comb-type pattern for
characterizing in Fig. 1(a). Superposed in succession to this
is the adjacent or upper ground line to examine [Fig. 2(b)] and
[Fig. 2(c)], respectively. Fig. 2(d) shows the serpentine-type
pattern whose area is identical to the comb-type one in Fig. 2(a).
1074 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 5, MAY 2000

Fig. 1. Schematic diagrams of interconnect lines: (a) signal line with C =C , (b) with C =C +C , and (c) with C = C +C +C .

Fig. 2. Interconnect test patterns: (a) comb- and (d) serpentine-type patterns with same area and those two patterns superposed by coupling (b), (e) and coupling
plus cross-over (c), (f) capacitances, respectively.

Again the adjacent and upper ground metal lines are superposed
in Fig. 2(e) and (f), respectively. The comb-type patterns are used
for extracting the capacitance components, while serpentine-type
patterns are for investigating the usual RC time delay.
These test patterns are incorporated in between two succes-
sive inverters constituting a ring oscillator. In this case those
identical stage ring oscillators will have different oscillation
frequencies, depending on the type of interconnect load. The
essence of the present method is to correlate difference in the
oscillation frequency to the interconnect parameters. The equiv-
alent circuit of the inverter with a test load is shown in Fig. 3.
Here the metal line is modeled by the distributed resistance and
capacitance [14]. The effective resistance consists of the series
connection of the interconnect ( ) and ON ( ) resistance
LEE et al.: 0.18 m CMOS TECHNOLOGY FOR ULSI CIRCUIT APPLICATIONS 1075

where
interconnect length;
capacitance per length;
resistance per length;
inverter gate capacitance.
The on-resistance, is given in
terms of the supply voltage, saturation currents on NMOS and
PMOS, respectively. The total gate delay in (1) is contributed
by – – , and – combinations.
For the comb-type case where
is well approximated as
(2)
Thus, with known the components of is readily de-
Fig. 3. Equivalent circuit of CMOS inverter loaded with interconnect line, termined by measured from the rest patterns of Fig. 2(a)–(c).
taken here as distributed resistance and capacitance.
For serpentine test patterns, where
is mainly given by the first term in (1), viz. for
of the previous stage inverter, while the capacitance is sum of the large . Thus is again specified from measured since
interconnect ( ) and gate ( ) capacitance of the latter is known from the corresponding comb-type data. In this
stage inverter. The test patterns have been designed in such a way interconnect parameters and associated are systemati-
way that is either larger or smaller than , while cally characterized.
is always much larger than . It is convenient to rewrite (1) in terms of the line length,
The comb-type pattern in Fig. 2(a) consists of 80 m-long and the NMOS gate width, as
lines, connected in parallel in the direction normal to the line
(3)
joining the two successive inverters. The resulting resistance is
negligible, compared with . Thus the effective resistance of where and , and are
the equivalent circuit is given by , while its capacitance is constants to be determined later.
determined by .
The difference in the ring oscillator frequency measured in III. EXPERIMENTAL RESULTS AND DISCUSSION
the presence and absence of the interconnect load of Fig. 2(a) A. Fabrication Process
results from the charging delay of . Similarly the oscillation
In fabricating test patterns was split into 0.96, 1.92, 2.88,
frequency differences between the loads of Fig. 2(b) and (a) and
4.8, and 9.6 mm and of the inverter NMOS (or of
of Fig. 2(c) and (b) are to be ascribed to and , respec-
PMOS) was also split into 2/4, 5/10, and 10/20 m. The test chips
tively. In this way three capacitance components are singled out
were processed, using 0.18 m CMOS technology with six-level
and determined in actual circuit operation conditions and under
metallization. In so doing the following steps or processes were
a pure charging condition, i.e., in the limit where .
applied; shallow trench isolation (STI), retrograde twin well, NO
It is noted that the adjacent or overlaying lines are to be con-
annealed 35 Å gate dielectric, LDD implantation, sidewall forma-
nected to the ground, i.e., there is no electrical connection to the
tion, halo implantation, novel arsenic and phosphorus double im-
dummy metal layers.
plantation for NMOSFET and BF implantation for PMOSFET
The serpentine pattern in Fig. 2(d) has the area equal to the
source/drain and novel Ti-capped cobalt salicide [15]–[17]. Also,
comb type one in Fig. 2(a) and hence have idential . The only
advanced back end of line processes such as low-k material in
difference is that those parallel 80 m-long lines are connected
IMD layers to reduce parasitic capacitance, especially coupling
in series for forming long interconnects, so that .
capacitance, were used. Hydrogen silesquioxane (HSQ) with a
Thus, the difference in oscillation frequency and/or the gate
dielectric constant of 3.1 was spin-coated directly on the metal
delay between the interconnect load of Fig. 2(d) and (a) is due
layers and then PETEOS was deposited on the HSQ to enhance
to its usual RC delay. Similarly the gate delay differences be-
the adhesion between IMD and metal layers. Dummy metal layers
tween the loads in Fig. 2(e) and (d) and Fig. 2(f) and (e) are due
were generated in a sparse region to reduce pattern dependent
to RC delay with additions of and , respectively, to
critical dimension variation of interconnect linewidth and space
at fixed .
by maintaining uniform metal density over the chips. The critical
design rule of the MLM processes is summarized in Table I to-
B. Interconnect-Induced Gate Delay
gether with that of the 0.25 m technology for comparison. The
The concept described in the preceding paragraphs is quanti- design rule of interconnect linewidth and space was down-scaled
fied as follows. The gate delay, of the ring oscillator due to by more than 30%, while the drain current of the transistors was
the interconnect load excluding the inverter delay time in Fig. 3 maintained at about the same level.
is given by [14] Fig. 4 shows the fabricated six-level MLM structures. The
linewidth ( ) and space ( ) of metal 1 is 0.23 and 0.23 m. In
the 0.18 m CMOS technology, the sheet resistance was made
(1) about 20% smaller than in 0.25 m technology by reducing
1076 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 5, MAY 2000

TABLE I
KEY INTERCONNECT AND DEVICE PARAMETERS FOR 0.18 AND 0.25m CMOS
TECHNOLOGIES USED FOR EXPERIMENTS

Fig. 5. Delay time versus interconnect length, L with: (a) comb- and (b)
serpentine-type interconnect loads at V = 1:8 V. Three different line
capacitance components are considered. For comb-type L is simply one half
of its total periphery.

the NMOS gate width of 5 m is 15.6, 73.4, and 5.4 ps/mm, re-
spectively. Clearly, is the dominant factor comprising about
78% of the total , while in the 0.25 m technology
amounted to about 51% of [13]. In the former and
are understandably smaller than the values in the latter due to re-
duced width of the line. However, in the former is larger than
the latter value by more than 60%. This increase in is ob-
viously attributed to shrinking spacing between the metal lines,
Fig. 4. SEM micrograph of fabricated six-level metallization. while the same metal height has been used to keep the sheet re-
sistance low and to maintain electromigration (EM) immunity.
barrier metal thickness with the introduction of CMP process The extracted capacitance components in these two technolo-
in forming contact and via tungsten plugs, while etchback was gies are tabulated in Table II together with .
used in the 0.25 m technology. The data from the serpentine-type patterns is presented
in Fig. 5(b). In this case – curves are different from the
B. Parameter Extraction comb-type case because of the added effect of . These
Fig. 5 shows the delay time per stage, versus the inter- data are analyzed as follows. The – curves divide into two
connect length, for supply voltage of 1.8 V. For comb-type parts, viz. small region in which and large where
loads in Fig. 5(a) increases linearly with , as expected from . The slope in the former is contributed by the sum of
(2). From the measured slope of – curves in Fig. 5(a) and and in (3) but is already known from Fig. 5(a), hence
the known value of the capacitance components are deter- is determined. The constant can be found by fitting –
mined from (2). Equivalently, in (3) is directly determined curves for large where . Once is determined,
from these slopes, since is known. The contribution of area is found directly with the use of whose components
( ), coupling ( ) and crossover ( ) capacitance to for have already been extracted from Fig. 5(a) [see (1) and (3)].
LEE et al.: 0.18 m CMOS TECHNOLOGY FOR ULSI CIRCUIT APPLICATIONS 1077

TABLE II
LOOK-UP TABLE FOR INTERCONNECT CAPACITANCES AND ASSOCIATED
TIME DELAY PER NMOS WIDTH IN 0.18 m CMOS TECHNOLOGY.
INTERCONNECT RESISTANCE OF SERPENTINE, SERPENTINE + COUPLING, AND
SERPENTINE + COUPLING + CROSSOVER TYPE LOADS IS 397, 431, AND 423
(
/mm), RESPECTIVELY. CORRESPONDING DATA FROM 0.25 m CMOS
TECHNOLOGY ARE SHOWN FOR COMPARISON

TABLE III
LOOK-UP TABLE FOR EXTRACTED DELAY TIME INDUCED BY INTERCONNECT
LINE IN 0.18 m CMOS TECHNOLOGY

The values of , and are presented in

Tables II and III.
It is interesting to point out that the extracted values of
differ by about 8%, depending on interconnect routing configu-
rations shown in Fig. 1. This detected difference of supposedly
same provides a clear proof for the accuracy of the present Fig. 6. Delay time versus NMOS gate width from: (a) comb- and (b)
serpentine-type interconnects at V = 1:8 V for different L and
extraction scheme, since should in practice differ because C = C + C + C . Also plotted are theoretically calculated values
of the geometrical line variation induced by the optical prox- for comparison. Filled symbols denote experimental data and open ones the
calculated values.
imity effect (OPC).
A simple calculation using the values of , and in
(3) reveals that the pure charging time, i.e., linear terms in in – curves follow the power law, . In the serpen-
(3) are comparable to RC delay time up to mm. However, tine-type patterns on the other hand, decreases with increasing
RC delay time becomes dominant for greater than 3 mm, com- to a certain level at which point is mainly contributed by
prising about 80% of total delay at mm, for example. the first term in (3) becoming independent of . These mea-
For the worst case where , due to 10 sured – curves are consistent with (3), as evidenced by an
mm-long line made of zero resistivity is about 1 ns. Although excellent agreement between theory and experiment. The agree-
this delay time is shorter than the corresponding value of 5 ns in ment is remarkable in view of the fact that the parameters, ,
the case of normal metal line [Fig. 5(b)], is still substantial. and used for calculation were extracted from different param-
This is understandable, since contributes to the finite ef- eter plane, i.e., from – curves in Fig. 5. This renders credence
fective resistance of the interconnect loaded inverter regardless to both the present extraction scheme and the simple analytical
of (see Fig. 3). It thus becomes clear that making formula describing .
zero does not necessarily lead to drastically reduced . What The application of the extracted data in designing repeaters is
is most crucial for making small is to minimize . discussed in Fig. 7. In this figure calculated is plotted as a func-
In Fig. 6 the data measured as a function of NMOS gate tion of for the range of NMOS varying from 1 to 10 m in
width, are compared with the theoretically calculated values steps of 1 m for the worst case . Clearly if two 10 mm long
using (3). Here the worst case corresponding to interconnect lines with m, for instance, are placed 0.23
from comb [Fig. 6(a)] and serpentine [Fig. 6(b)] type m apart from each other, the maximum chip frequency is 200
patterns are compared with theory for different . For given , MHz as the associated delay time is about 5 ns. When this inter-
becomes smaller with increasing , as the drain current connect is divided into two and five segments, for example, in
increases in proportion to and charges up the line faster. In each segment is 1.49 and 0.36 ns, leading to 2.98 and 1.80 ns total
the comb-type patterns where the second term in (3) is dominant time delay, respectively. Hence the maximum chip frequency is
1078 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 5, MAY 2000

Fig. 7. Calculated delay time versus interconnect length L for different NMOS
widths. Inset shows that interconnect delay time versus gate width at the length
of 5 mm.

increased to 336 and 556 MHz, respectively. When the number of

repeaters used is increased further, the maximum chip frequency
is also increased but this rate of increase slows down, as is clear
from Fig. 7. This kind of design consideration is explicitly an-
alyzed with the use of the analytical expression of with the
constants , and determined in real time.

C. Comparison with 0.25 m CMOS Technology

The interconnect-induced time delay resulting in the 0.18 m
CMOS technology is compared with data in the 0.25 m
technology. Because of the slight difference in the designed test
patterns, only four patterns can be directly compared with each Fig. 8. Delay time versus interconnect line, L from: (a) comb- and (b)
serpentine-type test loads in 0.18, 0.25 m CMOS technologies operating at
other. Fig. 8 shows – data from the comb and serpentine V = 18 : and 2.5 V, respectively, for C = C , and C + C . Also
patterns in these two technologies. The transistors used in the shown are the corresponding theoretical curves with C and C + C specified
ring oscillator had the aspect ratio, 5/0.18, 5/0.25 for NMOS for clarity. For comb-type interconnect L denotes one half of its total periphery.
and 10/0.18, 10/0.25 m/ m for PMOS, respectively, and were
driven by the supply voltage of 1.8 and 2.5 V, respectively. normal versus zero resistance interconnects of identical length.
For comb-type interconnect in 0.18 m technology is Although the time delays in Fig. 8(a) are generally smaller
smaller, as is quite evident for the case where consists than the corresponding value in Fig. 8(b), the advantage of
of area component only, i.e., . In this case either low or zero will become apparent only for much
is reduced by about one half because both and the larger than 3 mm. An upshot of Fig. 8 is that scaling down
transistor ON resistance, ( ) decrease. Here the the width and space of metal lines in 0.18 m technology
supply voltage is reduced from 2.5 to 1.8 V, while the drain does not necessarily entail significant degradation in the
current remains more or less same [see Table I, and (1), (3)]. maximum chip frequency. Only for the worst case where
However, when includes the coupling component, i.e., , becomes significantly larger in 0.18 m
, larger in 0.18 m technology makes technology when is greater than 5 mm. Also, is affected
about same in both cases. Fig. 8(b) shows data from both by the interconnect parameters and the performance of
serpentine-type interconnects. Again for comprised of the transistors involved. It is therefore always desirable to specify
area component only, in the 0.18 m technology is smaller the time delay in actual circuit operation conditions, as in the
because of reduced , and , as discussed. case of present measurement scheme.
However, when becomes large with added on to it,
is dominated by the first term in (1), viz. and
IV. CONCLUSION
becomes larger than in 0.25 m technology for greater
than 3 mm or more. A simple electrical scheme for characterizing the intercon-
As previously noted, using the corresponding data in nect-induced time delay has been presented. In this technique
Figs. 8(a) and (b) one can compare the ’s resulting from pertinent interconnect parameters are systematically extracted
LEE et al.: 0.18 m CMOS TECHNOLOGY FOR ULSI CIRCUIT APPLICATIONS
on chip and correlated to the time delays in actual circuit op-
erating conditions. The test chips were fabricated in both 0.25
and 0.18 m CMOS technologies by utilizing the state of the art
process technologies. The results obtained have been discussed
in specific comparison with each other to give a general trend
for changing interconnect parameters with shrinking device fea-
ture size and concomitant reduction of line width and space.
An advantage of the present method is its ability to complete a
look-up table. When the parameters in this table are used in con-
junction with a working analytical expression of it enables
realistic modeling and optimization of interconnect parameters
including the number of repeaters to be used for given specifi-
cation of chip performance.
The transition from 0.25 to 0.18 m CMOS technology dose
not necessarily entail larger interconnect time delay. In fact both
and are decreased with reduced and is also
made significantly smaller via improved processing. The re-
sulting time delays in both technologies are thus about the same
unless exceeds 3 mm. A major concern however is the drastic
increase of lateral coupling capacitance, which comprises
about 80% of the total in 0.18 m technology, as com-
pared with about 50% in 0.25 m technology. Hence, in the
presence of and for exceeding 5 mm the time delay be-
comes an important issue in 0.18 m technology.
An interesting byproduct is that the time delay measured at
room temperature under a pure charging condition has been
shown the same time delay resulting from interconnects made of
zero resistivity. The advantage of using zero resistivity intercon-
nects is again not so apparent for less than 3 mm. This is due to
the transistor ON resistance providing finite effective resistance
regardless of . The advantage of using low or zero
becomes progressively evident, however, for greater than 5
mm. In this range of , a parameter equally important is
whose associated cross-talk could additionally induce signifi-
cant line noises, and this coupling noise is currently under ac-
tive investigation for later communication elsewhere.
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Hi-Deok Lee (S’94–M’98) received the B.S., M.S.
and Ph.D. degrees from the Korea Advanced Insti-
tute of Science and Technology (KAIST), Taejon, in
1990, 1992, and 1996, respectively, all in electrical
engineering.
In 1996, he joined LG Semicon, Co., Ltd, (merged
with Hyundai Electronics Industries Co., Ltd.),
Choongbuk, Korea, where he has been involved in
the development of 0.35, 0.25, and 0.18 m CMOS
technologies, respectively. His research interests are
in the areas of next generation CMOS technologies
including reliability physics in VLSI devices, rf CMOS devices, crosstalk, and
time delay of interconnection lines. He is now responsible for the development
of 0.15 and 0.13 m CMOS technologies.
Dr. Lee is a member of the Institute of Electronics Engineers of Korea.
Dae M. Kim received the B.S. degree in 1960
from Seoul National University, Seoul, Korea, and
the M.S. and Ph.D. degrees in 1965 and 1967,
respectively, from Yale University, New Haven, CT,
all in physics.
He was a Research Associate at the Massachusetts
Institute of Technology, Cambridge, MA, and taught
at three levels of professorship with the Department
of Electrical and Computer Engineering, Rice Uni-
versity, Houston, TX, from 1970 to 1984. He also was
a Professor at Oregon Graduate Institute of Science
and Technology and a Principal Scientist at Tektronix, Inc., OR. Currently, he
is a Professor with the Department of Electronics and Electrical Engineering,
Pohang University of Science and Technology, Pohang, Korea. He served both
as the Chairman of the department and the Dean of the graduate school. His
research interests are in semiconductor devices and circuits, focused on flash
memory devices and single electron devices.
Dr. Kim is a Member of the American Physical Society, Korean Institute of
Electrical and Electronics Engineering, and Fellow of the Korean Academy of
Science and Technology.
Myoung-Jun Jang received the B.S. and M.S.
degrees from SungKyunKwan University, Suwon,
Korea, in 1995 and 1997, respectively, all in
electronics engineering.
In 1997, he joined LG Semicon, Co., Ltd.,
(merged with Hyundai Electronics Industries Co.,
Ltd., in 1999), Choongbuk, Korea, where he has
been involved in the development of 0.25, and 0.18
m CMOS technologies, respectively. His research
interests are in the areas of CMOS devices, analog
circuit design, and time delay of interconnection
lines.