CH-02. Central Processing Unit (Instruction Set Architecture & Alu)

B.
TECH 6TH SEMESTER – CSE -2
COMPUTER ARCHITECTURE
CH-02 Central Processing

Unit (Instruction Set
Architecture & ALU)
Prepared By:
Prof. Smita Dash, Assistant Professor, Dept. of CSE
CH-02 CENTRAL PROCESSING UNIT (INSTRUCTION SET ARCHITECTURE &
ALU)
❖ CENTRAL PROCESSING UNIT:

The primary and ultimate function of the CPU and other instruction-set processors is to do the actual work
by executing the set of instructions which are available in an external secondary memory to be brought into
main memory at the time of execution.
The things that the CPU must do to execute the stored sequence of instructions are:
i) Fetch Instruction: The CPU must read instructions from memory one at a time.
ii) Decode Instructions: The instruction must be interpreted to determine what action is required and to
be taken.
iii) Fetch Data: The execution of an instruction may require reading data from memory or an I/O
module.
iv) Execute Instructions: the execution of an instruction may require the performance of some
arithmetic or logical operation on the data.
v) Write Data: The result of an execution may require writing data to targeted memory location or to
an I/O module.
The part of the computer performs the bulk of data processing operations is called the central processing
unit
The CPU is made up of three major parts:
i) The Control Unit: It is responsible for fetching instructions from the main memory and determining
their type. It supervises, monitors and controls the movement of data and instructions into and out of
the CPU and also controls the operation of ALU.
ii) The Arithmetic and Logic Unit (ALU):It performs the required micro-operations for executing the
instructions .
iii) Registers: The CPU also contains a small, high speed memory used to store temporary results and
certain control information. This memory consists of a number of registers, each of which has a
certain functions. These registers store the intermediate data during the execution of instructions.
PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 1

❖ STACK ORGANIZATION:
The one-bit register FULL is set to 1 when the stack is full, and the one-bit register EMTY is set to 1 when
the stack is empty of items. DR is the data register that holds the binary data to be written into or read out of
the stack.

:

❖ INSTRUCTION FORMAT:

1. Single Accumulator Organization:
2. General Register Organization:

3. Stack Organization:

❖ INSTRUCTION SET ARCHITECTURE:

❖ FETCH DECODE EXECUTION CYCLE:
The CPU executes each instruction in a series of small steps:
1. Fetch the next instruction from memory into the instruction register (IR).
2. Change the Program counter (PC) to point to the following instruction.
3. Determine the type of instruction just fetched (Decode).
4. If the instruction uses data in memory, determine where they are.
5. Fetch the data, if any, into internal CPU registers (DR).
6. Execute the instruction.
7. Store the result in the appropriate place.
8. Go to step 1 to begin executing the following instruction.
This sequence of steps (micro-operations) is central to the operation of all computers and is frequently
referred to as fetch-decode-execute cycle or Instruction cycle.

❖ ADDRESSING MODES:
➢
➢
The control unit of a computer is designed to go through an instruction cycle that is divided into three
major phases:

Def. Of Addressing Mode:
1. IMPLIED MODE:
2. IMMEDIATE MODE:
• Operand is part of instruction

• Operand = address field
• e.g. ADD 5
— Add 5 to contents of accumulator
— 5 is operand
• No memory reference to fetch data
• Fast

3.
• Operand is held in register named in address filed

• EA = R
• Limited number of registers
• Very small address field needed
— Shorter instructions
— Faster instruction fetch
• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance
— Requires good assembly programming or compiler writing
— N.B. C programming
• register int a;
• c.f. Direct addressing
4.

5.
6.
• Address field contains address of operand

• Effective address (EA) = address field (A)
• e.g. ADD A
— Add contents of cell A to accumulator
— Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space
7.
• Memory cell pointed to by address field contains the address of (pointer to) the operand
• EA = (A)
— Look in A, find address (A) and look there for operand
• e.g. ADD (A)
— Add contents of cell pointed to by contents of A to accumulator
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
— e.g. EA = (((A)))
• Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower

8.
9.
10.

:
❖ INSTRUCTION SETS:
1. DATA TRANSFER INSTRUCTION:

2. DATA MANIPULATION INSTRUCTIONS:
2.1. ARITHMETIC INSTRUCTIONS:

http://www.slideshare.net/9840596838/instruction-set-of-8086-16837268
2.2. LOGICAL & BIT MANIPULATION INSTRUCTIONS:

2.3. SHIFT INSTRUCTION:

3. PROGRAM CONTROL INSTRUCTIONS:

4. STRING INSTRUCTIONS:

5. PROCESSOR CONTROL INSTRUCTIONS:

❖ SUBROUTINE CALL & RETURN:

❖ PROGRAM INTERRUPT:

1. External Interrupts:
2. Internal Interrupts:

Difference Between external & internal Interrupts:
3. Software Interrupts:

❖ THE ARITHMETIC AND LOGIC UNIT:
An ALU is that part of the computer that mainly performs arithmetic, logic + shift operations. All the other
components control unit, memory registers. Input output is there mainly to bring the data into ALU to
process it and then take the result back out. The complexity of ALU depends on the type of instructions set
that has been realized for it. The simple ALU can be constructed for fixed point numbers. On the other hand
floating point arithmetic implementation requires more complex control logic and data processing
capabilities i.e. the hardware for floating point arithmetic or other complex functions, an auxiliary special
purpose unit is used. This unit is called arithmetic co-processor.
What is ALU? An arithmetic logic unit (ALU) represents the fundamental building block of the central
processing unit of a computer. An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic
and logic operations. Modern CPUs contain very powerful and complex ALUs. In addition to ALUs,
modern CPUs contain a control unit (CU).
Most of the operations of a CPU are performed by one or more ALUs, which load data from input registers.
A register is a small amount of storage available as part of a CPU. The control unit tells the ALU what
operation to perform on that data and the ALU stores the result in an output register. The control unit moves
the data between these registers, the ALU, and memory.
******************************************************************************************
 PREVIOUS YEAR QUESTIONS:
1. Short Note: CPU [2013]

2. Explain fetch decode execution cycle? [2014] [10 marks]
3. Explain stack based architecture of a CPU with help of a diagram? [2014][10marks]
4. What are addressing modes? Explain the various addressing modes with examples. Give the difference
between auto increment and auto decrement addressing mode. [2019][10marks]
******************************************************************************************

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B.

TECH 6TH SEMESTER – CSE -2

CH-02 Central Processing

❖ CENTRAL PROCESSING UNIT:

The CPU is made up of three major parts:

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 1

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 3

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 7

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 8

2. General Register Organization:

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 9

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 10

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 13

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 14

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 15

• Operand is part of instruction

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 16

• Operand is held in register named in address filed

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 17

• Address field contains address of operand

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 18

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 19

1. DATA TRANSFER INSTRUCTION:

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 20

2.1. ARITHMETIC INSTRUCTIONS:

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2.2. LOGICAL & BIT MANIPULATION INSTRUCTIONS:

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PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 30

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 PREVIOUS YEAR QUESTIONS:

1. Short Note: CPU [2013]

PROF. SMITA DASH (ASST. PROF., DEPT OF CSE) Page 39

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