Sequential Logic Circuits: Objective

Lab 4: Implementation of Sequential Logic Circuits.
Lab 4: Sequential logic circuits
Objective:
- Verifying flip-flop operation and obtaining their truth table.
- Investigating the binary counters and obtaining their operation principles.
Electronics Department
Ho Chi Minh City University of Technology, Vietnam
1
I- Flip-flop
In the previous experiments, combinational logic circuits such as decoders, encoders, multiplexers
anddemultiplexers were considered. On the other hand, in a sequential logic circuit; in addition to logic gates
there are also memory elements. Flip-flops are basic memory elements used in a sequential logic circuit. When
the memory elements are removed from a sequential logic circuit the remaining part of the circuit is just the
combinational part. In the experiment, flip-flops are considered. One of the basic devices storing and
processing the digital data (1s and 0s) is the flip-flop. There are basically four types of flip-flops:
1- SR flip-flop (latch)
2- D flip-flop
3- JK flip-flop
4- T flip-flop
1. Examination of JK Flip-flop
- Preliminary information: The schematic symbol and the function table of 74LS112 dual JK flip-flops
with Preset and Clear is shown in Fig. 4.1.
Fig 4. 1 The schematic symbol and the function table 74LS112 dual JK flip-flops with Preset and Clear.
- Equipment:
o Analog Discovery Studio
o Integrated Circuits (ICs) :
74LS112 Dual JK Flip-flops with Preset and Clear 1 IC
o Connection wires.
2
Fig 4. 2 The dual JK flip-flop circuit with Preset and Clear.
Fig 4. 3 The dual JK flip-flop circuit with Preset and Clear – Application circuits
Note: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
- Procedure:
1) Construct the circuit [as given in Fig. 4.2. and as] drawn by you in Fig. 4.3 and apply the power.
2) Apply first the following Preset, Clear, J and K and then the CLK to the inputs of the circuit, given
in Table 4.1 and experimentally obtain the output values and take note of the outputs in the Table:
Notes: Output status changes only when falling edge clock appears. Falling edge clock is created
when you turn the switch from level 1 to level 0.
3
Table 4. 1
2. Examination of D Flip-flop:
- Preliminary information: The schematic symbol and the function table of 74LS74 dual rising edge
triggered D flip-flops is shown in Fig. 4.4.
Fig 4. 4 The schematic symbol and the function table of 74LS74 dual rising edge triggered D flip-flops.
- Equipment:
o Integrated Circuits (ICs):
4
o Connection wires.
Fig 4. 5 Rising edge triggered D flip-flop circuit.
Fig 4.6 Rising edge triggered D flip-flop – application circuit

- Procedure:
2) Apply first the following Preset, Clear, D and then the CLK to the inputs of the circuit, given in
Table 4.2 (follow the given inputs from top to down) and experimentally obtain the output values
and take note of the outputs in the Table.
Notes: Output status changes only when rising edge clock appears. Rising edge clock is created when
you turn the switch from level 0 to level 1.
5
Table 4. 2
3. Converting a JK flip-flop into a D flip-flop
- Equipment :
74LS112 Dual JK Flip-flop with Preset and Clear 1 IC
74LS04 Hex inverters (six independent gates) 1 IC
o Connection wires.
Fig 4. 7 Converting a JK flip-flop into a D flip-flop.
6
Fig 4. 8 Converting a JK flip-flop into a D flip-flop – application circuit
Note: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
- Procedure:
Notes: Output status changes only when falling edge clock appears. Falling edge clock is created when
7
Table 4.3
4. Examination of T Flip-flop:
- Equipment:
o Connection wires.
Fig 4. 9 Converting a JK flip-flop into a T flip-flop.
8
Fig 4.10 Converting a JK flip-flop into a T flip-flop – application circuit
- Procedure:
Notes: Output status changes only when falling edge clock appears. Falling edge clock is created when
Table 4. 4
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II- Asynchronous (Ripple) Counters

In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of
times a particular event or process has occurred, often in relationship to a clock signal. Counters are the logic
circuits that take specific state with the clock ticks applied to their inputs. They are widely used in the digital
electronics area. Some of those application areas are, Digital Clocks, Frequency Counters, Decoders, Digital
Alarms, Traffic Lights etc.
The base of the counters are logic circuits and the flip-flops. Generally counters are obtained with cascade
connection of flip-flops in a specific rule. With each clock tick the counter changes its state. A counter
composed of n flip-flops with no feedback may have 2 n different states depending on the number of clock
ticks. For example, if 4 flip-flops are used in the counter structure, there will totally be 24=16 different states.
So, the counter can count from 0 to 15.
The total number of counts or stable states a counter can indicate is called MODULUS (MOD). For
instance, the modulus of a four-stage counter would be 1610, since it is capable of indicating 0000 . The term
modulo is used to describe the count capability of counters; that is, modulo-16(MOD16) for a four-stage
binary counter, modulo-10 (MOD10) for a decade counter, modulo-8 (MOD8) for a three-stage binary
counter, and so forth. Counters can be up counters, whose count value increments, and down counters, whose
count value decrements, A counter is usually considered in conjunction with a finite-state machine (FSM).
Counters can be divided into two groups: 1. asynchronous (ripple) counters, 2. synchronous counters.
Asynchronous counters are counters that are configured such that all flip-flops are not triggered
simultaneously by a common clock. Since each flip-flop in the counter is triggered by the flip-flop in series
before it, these counters are also referred to as ripple counters. There are many types of asynchronous
counters. An UP counter counts in an ascending sequence while a DOWN counter counts in a descending
sequence. A counter can also count UP and DOWN on command; such a counter is known as an UP/DOWN
counter.
Asynchronous counters are limited in speed since all the flip-flops are not synchronized by the same clock.
Therefore the propagation delay in each flip-flop often affects the counting sequence at very high operation
frequencies. The flip-flops used in asynchronous counters are usually “T” flip-flops or JK or D type flip-flops
that have been configured as T flip-flops.
Asynchronous counters can be constructed from discrete flip-flops or are readily available in the form of
ICs. The IC implementations are designed so that the counters can be configured for a wide variety of
applications ranging from simple counting to frequency division.
The flip-flop output in an asynchronous counter is used to trigger the next flip-flop. In other words, all the
flip-flops except for the first one are triggered with the state transition of the previous flip-flops. However, in
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synchronous counters the input ticks are applied to all the Clk inputs of the flip-flops at the same time. The
fact that a flip-flop changes state depends on the states of other flip-flops. All flipflops work in toggle mode in
an asynchronous counter.
1. Examination of 4 bit asynchronous binary up counter:

- Equipment:
o Connection wires.
Fig 4. 11 The 4 bit asynchronous binary up counter circuit.
11
Fig 4. 12 The 4 bit asynchronous binary up counter – application circuit

Note: Do not forget connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
- Procedure:
1) Construct the circuit [as given in Fig. 4.11 and as] drawn by you in Fig. 4.12 and apply the power.
In the beginning of the experiment, connect the Clock to a DIO and set it as a switch.
2) Set the input A = 0 and B = 1, note the result.
4) Set A = B =1, turn on the switch and then turn off to make a pulse into CLK input. Note down your
observation in Table 4.2.
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Table 4. 5
5) Set A = B = 1, supply Clock signal using Digital Pattern Generator. Set the parameter as below:
- Click to Add channels  Signal  DIOx (x: 0 – 15)

- Output: PP (Push – Pull)
- Type: Clock
- Parameter1: change the frequency from 1Hz, 10Hz and 100Hz,… and observe the operation of the
counter. After which frequencies you cannot observe the changing of count values by your eyes?
Explain why?
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2. Examination of MOD10 asynchronous up counter:

- Equipment:
74LS00 Quad 2-input NAND gates 1 IC
o Connection wires.
Fig 4.13 The 4 bit asynchronous binary up counter circuit.

`
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Fig 4. 14 The MOD10 asynchronous counter – application circuit
- Procedure:
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2) Set the input A = 0, note the result (this means all preset inputs of flip-flops are inactive).
3) Set A = 1, turn on the switch and then turn off to make a pulse into CLK input. Note down your
observation in Table 4.
Table 4. 6
6) Set A = 1, supply Clock signal using Digital Pattern Generator. Set the parameter as below:
- Click to Add channels  Signal  DIOx (x: 0 – 15)

- Type: Clock
counter. After which frequencies you cannot observe the changing of count values by your eyes?
Explain why?
16
3. Examination of 4 bit asynchronous binary down counter:

- Equipment:
o Connection wires.
Fig 4. 15 The 4 bit asynchronous binary up counter circuit.
Fig 4. 16 The 4 bit asynchronous binary up counter – application circuit
- Procedure:
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4) Set A = B =1, turn on the switch and then turn off to make a pulse into CLK input. Note down your
observation in Table 4.7.
Table 4. 7
5) Set A = B = 1, supply Clock signal using Digital Pattern Generator. Set the parameter as below:
- Parameter1: change the frequency from 1Hz,

10Hz and 100Hz,… and observe the operation of
the counter. After which frequencies you cannot
observe the changing of count values by your eyes?
Explain why?
- Click to Add channels  Signal  DIOx (x: 0 –
15)
- Type: Clock
18
4. Examination of the 74LS93 4 bit asynchronous binary up counter:

- Preliminary information:
The 74LS93 is an example of a specific TTL IC asynchronous up counter. Fig. 8.8 shows the
schematic symbol, the logic diagram, the reset/count truth table and the count sequence of the 74LS93
4 bit asynchronous up counter IC. As the logic diagram in Fig. 8.8 shows, this device actually consists
of a single flip-flop and a 3-bit asynchronous counter. This arrangement is for flexibility. It can be used
as a divide-by-2 device if only the single flip-flop is used, or it can be used as a MOD8 counter if only
3-bit counter is used. This device also provides gated reset inputs, MR1 and MR2. When both of these
inputs are HIGH, the counter is reset to 0000 state.
- Equipment:
o Integrated Circuits (ICs): 74LS93 4 bit binary counter 1 IC
o Connection wires.
Fig 4. 17 The 74LS93 4 bit asynchronous up counter circuit.
Fig 4. 18 The 74LS93 4 bit asynchronous up counter circuit – application circuit

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- Procedure:
2) Set the input A = 1, turn on the switch and then turn off to make a pulse into CLK input and note
the output value.
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3) Set the input A = 0, turn on the switch and then turn off to make a pulse into CLK input. Note
down your observation in Table 4.8.
Table 4. 8
4) Set the input A = 0, supply Clock signal using Digital Pattern Generator. Set the parameter as
below:
- Click to Add channels  Signal  DIOx (x: 0

– 15)
- Type: Clock
counter. After which frequencies you cannot observe the changing of count values by your eyes? Explain
why?
21
5. Examination of the 74LS93 used as a BCD counter:

- Preliminary information:
The 74LS93 can be used as a 4-bit MOD16 counter (counts 0 through 15). It can also be configured
as a decade counter (counts 0 through 9) with asynchronous recycling by using the gated reset inputs
MR1 and MR2.
- Equipment:
o Integrated Circuits (ICs): 74LS93 4 bit binary counter 1 IC
o Connection wires.
Fig 4. 19 Configuration of the 74LS93 as a decade counter (74LS93).
Fig 4. 20 Configuration of the 74LS93 as a decade counter (74LS93) – application circuit
- Procedure:
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2) Turn on the switch and then turn off to make a pulse into CLK input. Note down your observation
in Table 4.9.
Table 4. 9
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Sequential Logic Circuits: Objective

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Lab 4: Implementation of Sequential Logic Circuits.

Lab 4: Sequential logic circuits

Fig 4. 2 The dual JK flip-flop circuit with Preset and Clear.

Fig 4. 5 Rising edge triggered D flip-flop circuit.

Fig 4.6 Rising edge triggered D flip-flop – application circuit

Fig 4. 7 Converting a JK flip-flop into a D flip-flop.

Fig 4. 8 Converting a JK flip-flop into a D flip-flop – application circuit

Fig 4. 9 Converting a JK flip-flop into a T flip-flop.

Fig 4.10 Converting a JK flip-flop into a T flip-flop – application circuit

II- Asynchronous (Ripple) Counters

1. Examination of 4 bit asynchronous binary up counter:

Fig 4. 11 The 4 bit asynchronous binary up counter circuit.

Fig 4. 12 The 4 bit asynchronous binary up counter – application circuit

- Click to Add channels  Signal  DIOx (x: 0 – 15)

2. Examination of MOD10 asynchronous up counter:

Fig 4.13 The 4 bit asynchronous binary up counter circuit.

Fig 4. 14 The MOD10 asynchronous counter – application circuit

- Click to Add channels  Signal  DIOx (x: 0 – 15)

3. Examination of 4 bit asynchronous binary down counter:

Fig 4. 15 The 4 bit asynchronous binary up counter circuit.

- Parameter1: change the frequency from 1Hz,

4. Examination of the 74LS93 4 bit asynchronous binary up counter:

Fig 4. 17 The 74LS93 4 bit asynchronous up counter circuit.

Fig 4. 18 The 74LS93 4 bit asynchronous up counter circuit – application circuit

- Click to Add channels  Signal  DIOx (x: 0

5. Examination of the 74LS93 used as a BCD counter:

Fig 4. 19 Configuration of the 74LS93 as a decade counter (74LS93).

Fig 4. 20 Configuration of the 74LS93 as a decade counter (74LS93) – application circuit

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