INTERNSHIP PROJECT

Report

On

Design and Implementation of Vedic Multiplier

Submitted

To

Digital System Design using Verilog HDL Internship-2021

By

E.Vinod Kumar, II year,(20315A0423), SNIST

G.Vinay Sai, II year,(20315A0422),SNIST

M.Shiva Sai, II year,(20315A0419),SNIST

UNDER THE SUPERVISION OF

Dr.D Asha Devi, and

Internship Organizing Team.

Microchip Academy.

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 CERTIFICATE

Date: 28 June 2021

This is to certify that the project report entitled “Design and implementation of Vedic Multiplier using
VHDL” is being submitted by E.Vinod Kumar(20315A0423) , G.Vinay Sai (20315A0422) and M.Shiva
Sai (20315A0419) in partial fulfilment of the requirements for the award of Bachelor of Technology degree
in Electronics and Communication Engineering to Sreenidhi Institute of Science and Technology affiliated
to Jawaharlal Nehru Technological University, Hyderabad (Telangana).

This record is a bona fide work carried out by them under our guidance and supervision. The results
embodied in the report have not been submitted to any other University or Institution for the award of any
degree or diploma.
.

Dr. G. Prasad Acharya Dr. S.P.V. Subba Rao

Associate Professor, Professor and HoD, ECE

Dept.

Coordinator, SNIST-Microchip Academy SNIST

ECE Department

CONTENTS
Page No.

Abstract 4
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CHAPTER1 INTRODUCTION 5-6
1. 2x2 Vedic Multiplier
CHAPTER 2 EXPERIMENTAL WORK 6-9
2.1 Design Module
2.2 Test bench Module
2.3 Explanation of the Design Logic
CHAPTER 3 EXPERIMENTAL PROCEDURE 9-14
CHAPTER 4 RESULTS 14-18
4.1 RTL Schematic
4.2 Simulated Waveforms
4.3 Implementation schematic
4.4 Power Report
4.5 Utilization Report
4.6 Noise Report
CHAPTER 5 CONCLUSION 19

REFERENCES 19

ABSTRACT

Today, complex circuits are described in high-level description languages, like VHDL or
Verilog, and synthesized to gate-level. A core operation in actual circuits, especially in digital
signal processing such as Filtering, Modulation, or Video Processing or Satellite
Communication or Graphics or Control systems etc, is multiplication. The computational
performance of a DSP system is limited by its multiplication performance. This project presents
fundamental of some multiplication array multiplier and its implementation . Hardware
multiplier implementation will have better speed than implementing the same using sequential
statements in any higher level language.Traditionally shift and add algorithm has been
implemented to design, however this is not suitable for VLSI implementation and also from
delay point of view. Some of the important algorithm proposed in literature for VLSI
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implementable fast multiplication is Booth multiplier, array multiplier and Wallace tree
multiplier. This project presents the vedicmultiplier fundamental technical aspects behind this
approach. Recently, several experimental systems based on programmable logic have been
designed and implemented which are programmed using a hardware design methodology. One
necessary component of the software environment will be a library of standard macro cells
corresponding to commonly used arithmetic and logical operations. In this project Vedic
multiplier is designed especially for programmable logic. This multiplier is cellular, highly
pipelined and uses only of local interconnections. The design is particularly carried out for a 2-
bit multiplier.

1. Introduction

Multipliers are used in a wide range of digital signal processing and other applications. Due to
advancements in current technologies, many researchers have mainly concentrated on the
design factors, for better performance. Some of the design targets are – high speed, accuracy,
low power consumption, the regularity of layout, less area.DSP processor has various
computational blocks, like multiplexers, adders. The speed of operation and execution of these
blocks have advanced when compared to previous versions. The execution speed of multipliers
depends on two factors, semiconductor technology and multiplier architecture. Adders are the
basic building block of digital multiplexers, where we perform a series of repeated additions, to
speed up the multiplier operation, the adder’s operation speed has to be increased. There are
many digital signal processing applications, where critical delay path and the performance of
the processor lies in the multiplier. There are different types of multipliers among which
2×2vedic multiplier is an advanced one which is described in our project.
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1.1. Multiplication Schemes in 2×2Vedic Multiplier

In this bock the perfect use of the UrdhavTribhayam technique is used for the
implementation of the 2x2 Vedic multiplier. For simple 1 bit binary multiplication the
AND gate is used. Considered the 2 inputs value A and B having A1A0 and B1B0
respectively. Where A0 and B0 are the LSB(least significant bits). A0 and B0 are
multiplied vertically and stored in the LSB of the Product output register. Next step is
to multiply LSB of number A with MSB of number B that is (A0 x B1) and MSB of
number A with LSB of number B that is (A1 x B0) as shown in Figure 1. Thus two AND
gates are required for this multiplication. These generated product are added that is
(A0 x B1) + (A1 x B0) using half adder (HA0). This summation generates output of 2
bits. LSB of this generated output is stored as second bit of final result and MSB of this
generated output is stored as pre carry for next step. Last step is to multiply MSB of A
with MSB of B that is (A1 x B1). One AND gate is required for this multiplication. This
generated product is added with pre carry of previous step. Thus again one more half
adder is required for it.

This halfadder(HA1)generates 2 bits output which is taken as 3rd and 4th bit of final
result. A1 bit wire carry is defined. The result of the multiplication is store in the 4 bit
register named as Prod i.e. Prod(3:0).

Prod(0) = A0 B0

Prod(1)= A0 B1 + A1 B0

Prod(2) = A1 B1 + carry(prod(1))

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6
2.IMPLEMENTATION://submodule

Testbench:

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//test bench for half adder

3.EXPERIMENT PROCEDURE:

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Step-1: Open Vivado and Enter the “Project Name” at the desired location and Click “Next” as shown
below

Figure 6: create new project

Step-2: Select RTL project and also click the check box “Do not specify sources at this time”

Figure7: project type

Step-3: Select “ZedBoardZynq Evaluation and Development Kit” and then Click Next.

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Figure8: specification selection

Click finish to create the project

Step-4: Click on “Add Sources” in Flow Navigator, then click on “Add or Create design sources” Figure9:
add design sources

Then create a filename as per the naming the variables in verilog since it is used as the module name then
click “OK” and then click “Finish”.

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 Figure10: create file
name

Step-5: Then click the “Port name” and the “Direction” as per the design of the blackbox of the circuit and
then click “OK” to create the design file. But in our project we directly clicked “OK” and gave the
inputoutput parameters directly in the code.

Figure 11: adding I/O ports and

directions
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Step-6: To create testbench module again click on “Add sources” and then click “Add or Create simulation
sources”.

Figure12: add simulation sources

Then create a filename as per the naming the variables in verilog since it is used as the module name then
click “OK” and then click “Finish”.

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13
4.1 RTL SCHMANTIC:

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4.2 TIMING DIAGRAM:

Fig.Timing diagram

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4.3 IMPLEMENTATION:

Fig.Implementation block

4.4 POWER REPORT:

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 Figure 13: power report

4.5 UTILIZATION REPORT:

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 Figure: utilization report

4.6 NOISE REPORT:

Figure : noise report

5.CONCLUSION:

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 The “UrdhavTribhayam” technique is used to design the 2bit Vedic Multiplier in efficient
and innovative way . The coding is done in Verilog and it has been synthesis using Xilinx
vivadosoftware. The proposed Multiplier is faster than the array and conventional
multiplier because of an efficient and structural use of Adder and AND gate. The difference
in the blocks used is due to the structural modeling. The frequency of the proposed
multiplier is higher than the conventional multiplier. Moreover, the number of gates count
used is lesser as compared to conventional multiplier. In future,using Vedic Mathematics it
is possible to make very fast and efficient ALU or Math Co-processor. Vedic mathematics
can be implemented in the field of DSP and ADSP processor to Employ the complex
calculation by calculating the various Terms like FFT and IFFT. The proposed technique for
Multiplication can be used in latest processors for efficient Design in terms of area and
speed.
6.REFERENCES:

• https://www.ijser.in/archives/v4i11/IJSER151038.pdf
• https://ttuir.tdl.org/bitstream/handle/
2346/21613/31295013250955.pdf?sequ ence=1
• http://data.conferenceworld.in/ICSTM9/11.pdf
• https://www.slideshare.net/Mathewvattamala/vedic -multiplier
• https://www.ijert.org/research/design-and-implementation-
ofadvanced-vedic-multiplier-for-binary-multiplication-on-
fpgaIJERTV5IS080161.pdf

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