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Sit 2007
Sit 2007
3, SEPTEMBER 2007
A Low-Power Blocking-Capacitor-Free
Charge-Balanced Electrode-Stimulator Chip
With Less Than 6 nA DC Error for 1-mA
Full-Scale Stimulation
Ji-Jon Sit, Member, IEEE, and Rahul Sarpeshkar, Senior Member, IEEE
Abstract—Large dc blocking capacitors are a bottleneck in highly correlated with neural tissue damage [2], and since stim-
reducing the size and cost of neural implants. We describe an ulation currents may need to be as high as 1 mA, a dc error of
electrode-stimulator chip that removes the need for large dc 0.01% is required. Some means of correcting any charge im-
blocking capacitors in neural implants by achieving precise
balance such that it presents 100 nA of dc error must therefore
charge-balanced stimulation with 6 nA of dc error. For cochlear
implant patients, this is well below the industry’s safety limit of be implemented.
25 nA. Charge balance is achieved by dynamic current balancing One of the simplest solutions is to insert a large dc blocking
to reduce the mismatch between the positive and negative phases capacitor with a typical shunt impedance of 5G in series
of current to 0.4%, followed by a shorting phase of at least 1ms with each electrode, to guarantee that negligible ( 1 nA) dc
between current pulses to further reduce the charge error. On
+ 6 and 9 V rails in a 0.7- m AMI high voltage process, the
current will be able to flow across the electrode. However, to
handle the clinical levels of charge that are required for stim-
power consumption of a single channel of this chip is 47 W when
biasing power is shared by 16 channels. ulation, which in cochlear implant users has a median max-
imum comfortable level around 15 nC/phase [3], the size of a
Index Terms—Biphasic current pulse, charge balancing, typical blocking capacitor must be 100 nF or larger so that
cochlear implants, electrode stimulation, neural implants.
the voltage drop across the capacitor does not add appreciably
to the voltage compliance required for driving the electrode
I. INTRODUCTION impedance. The size of a large (100 nF) blocking capacitor
is hugely detrimental for implantable electronics, which is re-
ANY biomedical implants currently convey information
M to nervous tissue by pulsatile current stimulation via an
implanted microelectrode array. Examples of such implants in-
quired to be small. Hence, safe levels of charge-balance that can
be achieved by capacitor-free precision electronics is attractive.
Since the cost of packaging is often a highly nonlinear function
clude cochlear implants for the deaf, deep brain stimulators for of the size of the implant, capacitor-free stimulation reduces cost
Parkinson’s disease and retinal implants for the blind. In order as well.
to avoid irreversible electrochemical reactions leading to toxic Several methods to achieve safely charge-balanced stimula-
by-product generation and eventual rejection of the implant, tion without using large dc blocking capacitors have been pro-
the pulse of current is typically made up of equal-sized neg- posed. The first and perhaps simplest solution is to short out
ative and positive phases, with the goal of delivering no net the electrode between current pulses [4]. The degree to which
charge through the electrode at the end of the pulse [1]. A per- shorting is effective will depend on the initial charge imbalance,
fect balance of zero net charge is difficult to achieve because the electrode time constant of discharge, and the time available
current source and sink drivers will typically be mismatched for discharge, set by the minimum inter-pulse interval. At stim-
by 1%–2% in the fabrication process even when great care is ulation rates as high as 2000 pulses-per-second (pps)/channel,
taken to ensure good matching in the layout and design. Studies shorting has been shown in clinical trials to achieve 100 nA dc
have shown that a residual dc current of more than 100 nA is error and safe long-term electrical stimulation [5], [6]. However,
for reasons of patient safety, it is desirable to achieve charge bal-
ance which is significantly lower than 100 nA, and more precise
Manuscript received June 29, 2007; revised October 23, 2007. This work was than that achieved by shorting alone. We propose to do this by
supported in part by the Packard Foundation and in part by the McGovern In-
stitute for Neuro Technology (MINT) Program at the Massachusetts Institute
reducing the initial charge imbalance below the usual 1%–2%
of Technology, Cambridge. This paper was recommended by Associate Editor mismatch error, and getting closer to the level produced by dc
B.-D. Liu. blocking capacitors (on the order of 1 nA dc error).
J.-J. Sit was with the Analog VLSI and Biological Systems group at the Mass- Besides shorting, the use of many tiny charge dumps from
achusetts Institute of Technology, Cambridge MA 02139 USA. He is now with
Advanced Bionics Corporation, Sylmar, CA 91342 USA. filling and emptying four small-sized (25 pF) blocking capac-
R. Sarpeshkar is with the Analog VLSI and Biological Systems Group, itors at 10 MHz has been proposed to reduce but not elimi-
Massachusetts Institute of Technology, Cambridge MA 02139 USA (e-mail: nate the blocking capacitors [7]. The technique was verified in a
rahuls@mit.edu).
Color versions of one or more of the figures in this paper are available online
discrete implementation and simulated in CADENCE. Experi-
at http://ieeexplore.ieee.org. mental evaluation of such ultrahigh-frequency stimulation in ac-
Digital Object Identifier 10.1109/TBCAS.2007.911631 tual nerve environments that exhibit refractoriness and lowpass
1932-4545/$25.00 © 2007 IEEE
SIT AND SARPESHKAR: LOW-POWER BLOCKING-CAPACITOR-FREE CHARGE-BALANCED ELECTRODE-STIMULATOR CHIP 173
Fig. 2. Timing diagram showing the order of operations. Gray blocks indicate a short delay.
Fig. 3. (a) Sample phase in dynamic current balancing: SAMP1 and SAMP switches are closed. (b) Hold phase in dynamic current balancing: SAMP1 opens
first, followed by SAMP, after which HOLD is closed.
III. STRATEGY TO ACHIEVE PRECISE CHARGE BALANCE sample-and-hold [16] which attenuates noise and other distur-
bances to by the gain of the loop around transconductor
A. Overview . Errors due to the charge injection of the switch
Fig. 2 shows that the strategy we employ to achieve charge but not the switch limit the precision of the sample and
balance is two-fold: First, a dynamic current-balancing phase hold [16].
is performed to match a pMOS current source with an nMOS The sampling phase preceding the hold phase is 4 clock
current sink. Second, after the biphasic pulse is generated, any cycles in duration, counting from the first rising clock edge
residual charge error left on the electrode is shorted to ground. after . Then, a negative pulse is generated by closing the
A biphasic current pulse is initiated by the falling edge of OUTPUT NEG PULSE switch for 8 clock cycles. A positive
an asynchronous trigger signal , shown in Fig. 2. The use pulse immediately follows the negative pulse via the closing of
of Vox enables an asynchronous stimulation strategy, which the OUTPUT POS PULSE switch for the next 8 clock cycles.
encodes phase information for conveying better music and Finally, after a small delay, the SHORT switch is closed to
speech perception in cochlear implants [14]. Immediately after discharge any residual charge on the electrode. This scheme
Vox arrives, a sample-and-hold (S&H) phase begins, shown as was chosen such that an asynchronous stimulation pulse would
in Fig. 2. In this phase, the pMOS gate voltage have a fixed latency of 4 clock cycles, and an additive variable
required to support an nMOS current is sampled on a hold latency between 0–1 clock cycles after the arrival of . Since
capacitor as shown in Fig. 3(a), and exploits the same basic 1 clock cycle is 4 s, the variable latency is a small fraction of
idea as a dynamic current mirror [15]. the output pulsewidth.
and form a source-follower that diode-connects
transistor M1, and is biased with enough current to drive at a B. Low-Leakage Sample and Hold
reasonable speed. The source-follower also level-shifts to A conventional differential-mode closed-loop sample-and-
a diode drop below , which keeps the active-cascode formed hold is shown in Fig. 4(a).
by and in saturation. After the circuit has settled, Differential sampling allows for partial cancellation of
is opened first. is then opened followed by the charge injection errors of the SAMP1 switches in a closed-loop
closing of the switch as shown in Fig. 3(b). This circuit sample-and-hold. An additional improvement, shown in
of Fig. 3(b) incorporates a closed-loop switched-capacitor Fig. 4(b), includes the addition of a low-leakage sampling
SIT AND SARPESHKAR: LOW-POWER BLOCKING-CAPACITOR-FREE CHARGE-BALANCED ELECTRODE-STIMULATOR CHIP 175
Fig. 4. (a) Conventional differential-mode closed-loop sample-and-hold: Vref is also sampled onto a capacitor. (b) Improved with a low-leakage switch.
Fig. 5. Full circuit of differential, low-leakage analog storage within the dynamic current mirror, showing the use of diffusion-MOS (DMOS) devices with lightly
doped drains (with up to 35 V of breakdown voltage, indicated by a thick drain terminal) to withstand large voltage drops where needed. The reference voltage
0
Vref is buffered from Vref in by an identical Gmh transconductor and bypassed by a capacitor Cref , shown in gray.
switch adapted from the ultralow power analog storage cell of C. Full Circuit Implementation
[17] and [18]. It works to minimize the switch leakage onto
node by matching source and drain voltages (at ), thus The full circuit which implements the differential
nullifying leakage diffusion currents between source and drain low-leakage analog storage within the dynamic current mirror
[17], [18]. Note that this equality occurs automatically for the is shown in Fig. 5.
switch, but must be enforced explicitly for the In order to achieve the high-voltage compliance necessary for
switch, by switching its rightmost terminal to during the electrode stimulation, DMOS devices available in the Europrac-
phase. The SPDT switch labeled tice AMI 0.7- m 30 V (I2T30E) process were used to protect
enforces the equality. The “d” suffix indicates that its switching junctions that were exposed to large voltage drops.
time is slightly delayed from the onset of sampling and holding, Additional circuit details that are required to improve the cir-
the reason for which is explained in the next section. cuit’s settling time during its sampling phase are as follows.
176 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 1, NO. 3, SEPTEMBER 2007
Fig. 6. Timing diagram showing the switching signals required for the various operations in dynamic current balancing.
is low when the circuit is waiting for the input IV. FEEDBACK STABILITY AND NOISE ANALYSIS
signal, and prebiases to start out near the positive rail. This A simplified schematic of the dynamic mirror in closed-loop
initial condition improves the settling time, because at the onset sampling is shown in Fig. 8.
of sampling, it is faster for the pMOS source-follower to pull was not shown in earlier schematics because it is a para-
down on rather than pull up on it. For the same reason, sitic capacitance, but is important for this analysis. We will make
the switch is closed for to pull up to the the simplifying assumption that the active cascode is fast and
rail when waiting for the trigger, as it is faster for to does not contribute to the loop dynamics, and only increases
pull down on than to rely on a gradually stabilizing cur- the output resistance of the transistor by a factor of to
rent sourced from to pull up on . The switch . The block diagram for this loop can then be written out
is closed to supply current to the active-cascode, whenever in Fig. 9(a) and simplified to that of Fig. 9(b).
needs to source current. This saves power in the active-cascode
by turning it off when it is not needed. is simply A. Loop Bandwidth
, just as . A third technique used to
shorten the settling time during the sample phase was to delay From Fig. 9(b), the transfer function can be treated
the closure of all the feedback loops in Fig. 5 until turn-on tran- as unity since the source-follower dynamics are comparatively
sients had died out. Note that when the switch is closed, fast. We can read off the loop bandwidth of to
shoots upwards from the negative rail to equalize be , as the feedback term is only sig-
with near the positive rail, and thereby creates a large spike nificant above crossover. A Bode plot of the forward transmis-
on the value of Iin. This spike, while short-lived, can cause sion together with the inverse of the feedback transmis-
all the feedback loops to take much longer to settle. Hence, sion, is shown in Fig. 10.
and also are both Since the minimum input current is set by our application
delayed from switching until slightly after the onset of at 1 A, we can expect an upper bound for one time constant to
and , in order for the initial turn-on spike to die out before be at most 1 pF mV A ns. There may be some
the feedback loops are closed. A timing diagram which summa- degradation in this value due to a lag effect (reduction in loop
rizes these timing relationships is shown in Fig. 6. gain) from falling below unity, but the loop should still
Select capacitor placement was found to be necessary for ro- be fast enough to achieve full settling within the 4 clock cycles
bust operation. A capacitor pF was added to bypass allotted, which is 16 s in our application. In general, since the
noise on . The capacitors and were both 1 pF settling is governed solely by , we can expect
and helped to stabilize the settling behavior of the active cas- fast first-order settling.
code. The capacitor pF was added to dampen a voltage
B. Loop Stability
spike on when switching from to mode. The
capacitor pF was necessary to compensate the dy- Since , it is indicated in Fig. 10 by the
namic mirror feedback loop and improve its phase margin. The continuation of as a dotted line, having a right-half-plane
stability of this circuit is further described in the next section. (RHP) zero at . Since the RHP zero occurs after
The schematic of the transconductor is shown in Fig. 7. crossover by a factor of , it does not adversely affect
loop stability as long as is not too small compared with
D. Shorting . Thus, we can see that the loop should be stable with nearly
The shorting phase is implemented by a simple nMOS switch 90 of phase margin.
to ground that is sized to have a small on-resistance 2k , In addition to the usual pole-splitting compensation provided
which is small in comparison with the electrode resistance. by , we can identify two additional sources of improvement
SIT AND SARPESHKAR: LOW-POWER BLOCKING-CAPACITOR-FREE CHARGE-BALANCED ELECTRODE-STIMULATOR CHIP 177
Fig. 7. Topology of the high-output impedance transconductor Gmh. The output is cascoded and protected with DMOS output devices to allow a wide voltage
swing from Vref Vin
to .
C. Noise Performance
Fig. 8. Simplified schematic of our dynamic mirror circuit in the sample phase. From the block diagram in Fig. 9(b), we see that noise sources
from and Iin experiences the full bandwidth of the loop
and have a frequency dependence just like Iin. However, noise
in the phase margin: Firstly, without , a nondominant pole is sources from , and will be strongly attenuated at
178 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 1, NO. 3, SEPTEMBER 2007
Fig. 9. (a) Block diagram of the dynamic mirror feedback loop. (b) Simplified block diagram containing unitless transfer functions within the loop. is defined
as C=Gmh.
Fig. 10. Bode plot of the closed loop transfer function G(s) // (1/H(s)) shaded in gray and the loop transmission L(s), which continues after G(s) as a dashed line.
because of the large gain of at dc in their feed- the noise appearing at is attenuated by the loop over all fre-
back path to . To understand this attenuation more clearly and quencies. Although current noise from does not inject di-
over all frequencies, we can again draw the forward transmis- rectly into , it is capacitively coupled through , and has a
sion together with the inverse of the feedback transmission highpass nature which further attenuates low frequency com-
, as shown in Fig. 11. ponents. Hence, we can expect the noise contribution from the
The transmission can be observed to be the same as , , and sources to to be negligible compared to
except without the zero at , and reveals and injections into , reducing the effective number
the strong attenuation of at low frequencies. At higher fre- of noise sources in this circuit to only .
quencies, intersects with the rolloff from , hence
SIT AND SARPESHKAR: LOW-POWER BLOCKING-CAPACITOR-FREE CHARGE-BALANCED ELECTRODE-STIMULATOR CHIP 179
Fig. 11. Bode plot of G(s)==(1=H(s)) shaded in gray, showing the transfer function from Ibs and similar noise sources to Vp. The gain of g 1 A r is defined
as A and the dominant time constant of (Cc + Cpo)A r is defined as .
where
mV
pF V. MEASUREMENTS
A 2.3 mm 2.3 mm stimulator chip was fabricated by the
Europractice IC fabrication service in an AMI 0.7- m 30 V
At the highest current level, using a maximum of 1 mA/V, (I2T30E) process. The die photo is shown in Fig. 12.
this sampled noise is converted to 75 nA in current noise. With
a pulsewidth of 32 , the standard deviation in charge A. Sample Output Waveforms
is then 2.4 pC, which is very small compared to the full-scale The output Vo was loaded with a discrete resistor and a
charge of 30 nC. This circuit is, therefore, a very low noise low-leakage 10 nF Teflon capacitor in series, to simulate a typ-
circuit, which is borne out by measurements presented in the ical electrode impedance. Seven digital bits ( ) were used to
next section. set the value of via a 7-bit DAC on chip, and the value of
180 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 1, NO. 3, SEPTEMBER 2007
Fig. 14. Residual charge error over the range of DAC currents.
Note that the residual charge error captures the net effect of
any inaccuracies in the positive current pulse causing a mis-
match with the negative current pulse in magnitude, duration
or shape. Ultimately, charge balance rather than current balance
determines the safety of current drivers in an implant.
Fig. 15. Capacitor voltage scope captures at the end of a biphasic pulse, which allow measurements of residual voltage and to be made.
Fig. 17. Multiple (N = 1600) scope acquisitions are used to compute the mean () and standard deviation ( ) of the residual error voltage, taken at 80.8 s.
This measurement was taken with Din = 64, which exhibited the worst-case error of 12 mV. The end of the biphasic pulse occurs at 80.5 s, and shorting
begins at 81 s.
TABLE I
PERFORMANCE COMPARISON OF BLOCKING-CAPACITOR-FREE ELECTRODE STIMULATOR DESIGNS
scale current of 1 mA should be achievable, suggesting that fu- Our results suggest that a future generation of neural implants
ture improvements may result in a 1.5 nA error. can implement charge balancing in active electronics and re-
move the need for dc blocking capacitors, thus removing a big
VI. CONCLUSION bottleneck in reducing their size.
This paper shows that the two-step technique of cascading
dynamic current balancing followed by shorting can achieve a
ACKNOWLEDGMENT
level of dc current error of 6 nA and a residual voltage error
of 12 mV, comparable to dc blocking capacitor performance. The authors would like to thank M. O’Halloran for helpful
Table I summarizes our electrode-stimulator performance rela- discussions regarding the design and use of the low-leakage
tive to other designs. analog storage cell.
SIT AND SARPESHKAR: LOW-POWER BLOCKING-CAPACITOR-FREE CHARGE-BALANCED ELECTRODE-STIMULATOR CHIP 183
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[4] J. F. Patrick, P. M. Seligman, D. K. Money, and J. A. Kuzma, “En- Ji-Jon Sit received the B.S. degree in electrical en-
gineering,” in Cochlear Prostheses. Edinburgh, U.K.: Churchill-Liv- gineering and computer science at Yale University,
ingstone, 1990. New Haven, CT, in 2000, and the M.S. degree in
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Millard, “Cochlear pathology following chronic electrical stimulation stitute of Technology, Cambridge, in 2002, where he
of the auditory nerve. I: Normal hearing kittens,” Hearing Res., vol. 62, received the Ph.D. degree in electrical engineering,
pp. 63–81, 1992. in the Analog VLSI and Biological Systems Group
[6] J. Xu, R. K. Shepherd, R. E. Millard, and G. M. Clark, “Chronic elec- in 2007.
trical stimulation of the auditory nerve at high stimulus rates: A physio- He is now with Advanced Bionics Corporation,
logical and histopathological study,” Hearing Res., vol. 105, pp. 1–29, Sylmar, CA, and works on emerging cochlear
1997. implant technology.
[7] X. Liu, A. Demosthenous, and N. Donaldson, “A stimulator output
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Proc. IEEE ISCAS, 2006, pp. 641–644.
[8] X. Fang, J. Wills, J. Granacki, J. LaCoss, A. Arakeliana, and J. Weiland, Rahul Sarpeshkar received the B.S. degrees in elec-
“Novel charge-metering stimulus amplifier for biomimetic implantable trical engineering and physics at the Massachussetts
prosthesis,” in Proc. IEEE ISCAS, 2007, pp. 569–572. Institute of Technology (MIT), Cambridge, and the
[9] E. K. F. Lee and A. Lam, “A matching technique for biphasic stimula- Ph.D. degree from California Institute of Technology,
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[10] M. Ortmanns, N. Unger, A. Rocke, M. Gehrke, and H. J. Tietdke, “A After completing the Ph.D., he joined Bell Labs
0.1 mm , digitally programmable nerve stimulation pad cell with high- as a member of technical staff in the Department of
voltage capability for a retinal implant,” in Proc. IEEE ISSCC, 2006, Biological Computation within its Physics division.
pp. 89–98. Since 1999, he has been on the faculty of MIT’s
[11] P. T. Bhatti and K. D. Wise, “A 32-site 4-channel high-density elec- Electrical Engineering and Computer Science De-
trode array for a cochlear prosthesis,” IEEE J. Solid-State Circuits, vol. partment where he heads a research group on Analog
41, no. 12, pp. 2965–2973, Dec. 2006. VLSI and Biological Systems. He holds over twenty patents and has authored
[12] X. Liu, A. Demosthenous, and N. Donaldson, “A miniaturized, power- more than 70 publications including one that was featured on the cover of
efficent stimulator output stage based on the bridge rectifier circuit,” in Nature. He has given over 100 invited lectures. His research interests include
Proc. IEEE APCCAS , 2006, pp. 498–501. analog and mixed-signal VLSI, biomedical systems, ultra low power circuits
[13] E. C. Field-Fote, B. Anderson, V. J. Robertson, and N. I. Spielholz, and systems, biologically inspired circuits and systems, molecular biology,
“Monophasic and biphasic stimulation evoke different responses,” neuroscience, and control theory.
Muscle & Nerve, vol. 28, pp. 239–241, 2003. Prof. Sarpeshkar has received several awards including the Packard Fellow
[14] J.-J. Sit, A. M. Simonson, A. J. Oxenham, M. A. Faltys, and R. award given to outstanding young faculty, the ONR Young Investigator Award,
Sarpeshkar, “A low-power asynchronous interleaved sampling al- the NSF Career Award, and the Indus Technovator Award. He is currently an
gorithm for cochlear implants that encodes envelope and phase Associate Editor of the IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND
information,” IEEE Trans. Biomed. Eng., vol. 54, no. 1, pp. 138–149, SYSTEMS. He has received the Junior Bose award and the Ruth and Joel Spira
Jan. 2007. award for excellence in teaching at MIT.