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VDD
STATUS REGISTER AND
SCL CONTROL LOGIC
SDA
A0 TEMPERATURE
ADDRESS AND
SENSOR
I/O CONTROL
A1
A2
EEPROM MEMORY
GND (256 BYTES)
DS1624
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
(VDD = 2.7V to 5.5V, TA = -55°C to +125°C, unless otherwise noted.) (Note 3)
AC Electrical Characteristics
(VDD = 2.7V to 5.5V, TA = -55°C to +125°C, unless otherwise noted. All values referred to VIH = 0.9VDD and VIL = 0.1VDD.)
Timing Diagram
SDA
tBUF
tSP
tLOW
tR tF tHD:STA
SCL
NOTE: THE DS1624 DOES NOT DELAY THE SDA LINE INTERNALLY WITH RESPECT TO SCL FOR ANY LENGTH OF TIME
1
ERROR (°C)
0
-55 -35 -15 5 25 45 65 85 105 125
LOWER LIMIT
TYPICAL
SPECIFICATION
-1 ERROR
-2
-3
TEMPERATURE (°C)
GND 4 5 A2
4 GND Ground
5 A2 Address Input
SO (208 mils) 6 A1 Address Input
7 A0 Address Input
8 VDD 2.7V to 5.5V Input Power-Supply Voltage
1 SDA VDD 8
DS1624
2 SCL A0 7
3 N.C. A1 6
4 GND A2 5
The information is transferred byte-wise and each receiv- 2. Data transfer from a slave transmitter to a master
er acknowledges with a ninth bit. receiver. The first byte (the slave address) is transmit-
Within the bus specifications a standard mode (100kHz ted by the master. The slave then returns an acknowl-
clock rate) and a fast mode (400kHz clock rate) are edge bit. Next follows a number of data bytes transmit-
defined. The DS1624 works in both modes. ted by the slave to the master. The master returns an
acknowledge bit after all received bytes other than the
Acknowledge: Each receiving device, when addressed, last byte. At the end of the last received byte, a ‘not
is obliged to generate an acknowledge after the reception acknowledge’ is returned.
of each byte. The master device must generate an extra
clock pulse, which is associated with this acknowledge bit. The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended
A device that acknowledges must pull down the SDA line with a STOP condition or with a repeated START condi-
during the acknowledge clock pulse in such a way that tion. Since a repeated START condition is also the begin-
the SDA line is stable low during the high period of the ning of the next serial transfer, the bus is not released.
acknowledge related clock pulse. Of course, setup and
hold times must be taken into account. A master must The DS1624 can operate in the following two modes:
signal an end of data to the slave by not generating an 1. Slave receiver mode: Serial data and clock are
acknowledge bit on the last byte that has been clocked received through SDA and SCL. After each byte is
out of the slave. In this case, the slave must leave the received an acknowledge bit is transmitted. START
data line high to enable the master to generate the STOP and STOP conditions are recognized as the begin-
condition. ning and end of a serial transfer. Address recognition
Figure 2 details how data transfer is accomplished on the is performed by hardware after reception of the slave
two-wire bus. Depending upon the state of the R/W bit, address and direction bit.
two types of data transfer are possible: 2. Slave transmitter mode: The first byte is received
1. Data transfer from a master transmitter to a slave and handled as in the slave receiver mode. However,
receiver. The first byte transmitted by the master in this mode the direction bit indicates that the transfer
is the slave address. Next follows a number of data direction is reversed. Serial data is transmitted on SDA
bytes. The slave returns an acknowledge bit after each by the DS1624 while the serial clock is input on SCL.
received byte. START and STOP conditions are recognized as the
beginning and end of a serial transfer.
SDA
SCL 1 2 6 7 8 9 1 2 3-8 8 9
ACK ACK
START REPEATED IF MORE BYTES STOP CONDITION
CONDITION ARE TRANSFERRED OR
REPEATED
START CONDITION
WRITE TO DS1624
CONTROL COMMAND DATA
BYTE PROTOCOL BYTE
START
BUS ACTIVITY:
STOP
MASTER
R/W = 0
SDA LINE
A2
A1
A0
1
0
0
1
BUS ACTIVITY
ACK
ACK
ACK
START
BUS ACTIVITY:
MASTER
R/W = 0
R/W = 1
A2
A1
A0
A2
A1
A0
1
0
0
1
1
0
0
1
SDA LINE
BUS ACTIVITY
ACK
ACK
ACK
ACK
NACK
STOP
Temperature is represented in the DS1624 in terms of a 0.0625°C LSB, yielding the following 12-bit example:
MSB LSB
0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0
= +25.0625°C
CONFIGURATION/STATUS REGISTER
DONE 0 0 0 1 0 1 1SHOT
where:
DONE = Conversion Done bit, “1” = Conversion complete, “0” = conversion in progress.
1SHOT = One Shot Mode. If 1SHOT is “1,” the DS1624 performs one temperature conversion upon receipt of the Start
Convert T protocol. If 1SHOT is “0,” the DS1624 continuously performs temperature conversions. This bit is nonvolatile
and the DS1624 is shipped with 1SHOT = “0.”
Since the configuration register is implemented in E2, writes to the register require 10ms to complete. After issuing a
command to write to the configuration register, no further accesses to the DS1624 should be made for at least 10ms.
Note 1: In continuous conversion mode, a Stop Convert T command halta continuous conversion. To restart, the Start Convert T
command must be issued. In one-shot mode, a Start Convert T command must be issued for every temperature reading
desired.
Note 2: Writing to the E2 typically requires 10ms at room temperature. After issuing a write command, no further reads or writes
should be requested for at least 10ms.
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
Updated Ordering Information and Package Information; updated the soldering
0 5/12 1, 2, 7, 14, 18
information in the Absolute Maximum Ratings section
Updated the Features and Description, removed the Overview section; replaced
the Operation—Measuring Temperature section and Figure 4; added the Package 1, 2, 5,
1 12/13
Thermal Characteristics section; updated the DC Electrical Characteristics and 13, 14, 15
AC Electrical Characteristics tables and related notes
Updated the EEPROM Data Retention parameter in the AC Electrical
2 3/14 14
Characteristics table
3 5/14 Updated the Electrical Characteristics 13, 14
4 1/15 Updated Benefits and Features sections 1
5 8/15 Updated AC Electrical Characteristics 3
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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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