Lectures 1-7 Diode Circuit Applications

Part I
Lectures 1-7
Diode Circuit Applications
University of Technology The PN Junction Diode
Electrical and Electronic Engineering Department Lecture One - Page 1 of 7
Second Year, Electronics I, 2009 - 2010 Dr. Ahmed Saadoon Ezzulddin
The PN Junction Diode
Basic Construction:
When acceptor impurities are introduced into one side and donors into the other side of
a single crystal of a semiconductor, a p-n junction is formed. In general, the acceptor
ion is indicated by a minus sign because, after this atom "accepts" an electron, it
becomes a negative ion. The donor ion is represented by a plus sign because, after this
impurity atom "donates" an electron, it becomes a positive ion. Now, if a junction is
formed between a sample of p-type and one of an n-type semiconductor, this
combination possesses the properties of a rectifier (permits the flow of charge in one
direction). Such a two-terminal device is called a p-n junction diode.
W The two single crystal semiconductors (having four valence electrons) used
most frequently in the construction of p-n junction diodes are silicon (Si) and
germanium (Ge).
W The p-type is created by introducing those impurity elements (acceptors) that have
three valence electrons (trivalent), such as boron, gallium, and indium.
W The n-type is created by introducing those impurity elements (donors) that have five
valence electrons (pentavalent), such as antimony, arsenic, and phosphorus.
W In a p-type material the hole is the majority carrier and the electron is the minority
carrier.
W In an n-type material the electron is called the majority carrier and the hole the
minority carrier.
W The electrons and holes in the region of the junction will combine, resulting in a
lack of carriers in the region near the junction. This region of uncovered positive
and negative ions is called the "depletion region" due to the depletion of carriers in
this region.
Essential Characteristics:
The essential electrical characteristic of a p-n junction is that it constitutes a rectifier
which permits the easy flow of charge in one direction but restrains the flow in the
opposite direction. We consider now how this diode rectifier action comes above.
No Applied Bias (VD = 0 V):

In the absence of an applied bias voltage, the net flow of charge in any one direction for
a semiconductor diode is zero (see Fig. 1-1).
Fig. 1-1
Reverse Bias (VD < 0 V):

The current that exists under reverse-bias conditions is called the reverse saturation
current and is represented by Is (see Fig. 1-2).
Fig. 1-2
Forward Bias (VD > 0 V):

A semiconductor diode is forward-biased when the association p-type and positive and
n-type and negative has been established (see Fig. 1-3).
Fig. 1-3
I-V Characteristic Carve and Current Equation:
N P
Cathode
Anode
Forward-bias region
Reverse-bias region
Reverse-breakdown region
Fig. 1-4
I D = I S (e kVD / TK − 1) [1.1]
Where k = 11600/η with η = 1 for Ge and η = 2 for Si for relatively low levels of diode
current and η =1 for Ge and Si for higher levels of diode current.
TK = TC + 273o.
Resistance Levels:
1. DC or Static Resistance:
The application of a dc voltage to a circuit containing a p-n junction diode will result in
an operating point on the characteristic carve that will not change with time. The
resistance of the diode at the operating point can found simply by finding the
corresponding levels of VD and ID as shown in Fig. 1-5 and applying the following
equation:
VD
RD = [1.2]
ID
Fig. 1-5
2. Ac or Dynamic Resistance:
If a sinusoidal rather than dc input is applied, the varying input will move the
instantaneous operating point up and down a region of the characteristics and thus
defines a specific change in current and voltage as shown in Fig. 1-6. With no applied
varying signal, the point of operation would be the Q-point determined by the applied
dc levels. A straight line drawn tangent to the curve through the Q-point will define a
particular change in voltage and current that can be used to determine the ac or
dynamic resistance for this region of the diode characteristics. In equation form,
ΔVd
rd = [1.3]
ΔI d
Fig. 1-6
In differential calculus, the derivative of a function at a point is equal to the slope

of the tangent line drawn at that point. Eq. [1.3], as defined by Fig. 1-6, is, therefore,
essentially finding the derivative of the function at the Q-point of operation. If we find
the derivative of the general Eq. [1.1] for the p-n junction diode with respect to the
applied forward bias and then invert the result, we will have an equation for the
dynamic or ac resistance in that region. That is;
d d
(I D ) = [ I S (e kVD / TK − 1)]
dVD dV
dI D k
= (I D + I S )
dVD TK
dI D k
≅ ID ( Generally, I D >> I S )
dVD Tk
dI D K 11600
= 38.93I D ( η = 1 & TK = 298o => = ≅ 38.93 )
dVD TK 298
dV 0.026
r = v/i = D ≅
dI D ID
26mV
rd = [1.4]
ID
All the resistance levels determined thus far have been defined by the p-n
junction and do not include the resistance of the semiconductor material itself
(called body resistance) and the resistance introduce by the connection between the
semiconductor material and the external metallic conductor (called contact resistance).
These additional resistance levels can be included in Eq. [1.4] by adding resistance
denoted by rB appearing in Eq. [1.5].
26mV
rd′ = + rB [1.5]
ID
3. Average AC Resistance:
If the input signal is sufficiently large to produce a board swing such as indicated in
Fig. 1-7, the resistance associated with the device for this region is called the average
ac resistance. The average ac resistance is, by definition, the resistance determined by a
straight line drawn between the two intersection establish by the maximum and
minimum value of input voltage. In equation form,
ΔVd
rav = [1.6]
ΔI d pt . to pt .
Fig. 1-7
Equivalent Circuits (Models):
1. Piecewise-Linear Model: (see Fig.1-8);

Forward-bias;
+ VD − + VT − rav ( F ) ID
VD > VT ID
Reverse-bias; rav (F ) Fig. 1-8
− VD + rav ( R )
VD
VD < VT
rav (R ) 0 VT
ID
2. Simplified Model: (see Fig. 1-9);

Forward-bias & Rnetwork >> rav(F);
+ VD − + VT −
ID
V D > VT ID
Reverse-bias, rav(R) = ∞ Ω & ID = 0 A; Fig. 1-9

− VD +
VD
0 VT
VD < VT
3. Ideal Model: (see Fig. 1-9);

Forward-bias, Enetwork >> VT, Rnetwork >> rav(F) & VD = 0 V;
+ VD −
ID
VD > 0 ID
Reverse-bias, rav(R) = ∞ Ω & ID = 0 A; Fig. 1-10

− VD +
VD
0
VD < 0
Load-Line Analysis:
From Fig. 1-11:

E − VD − VR = 0
ID
E = VD + I D R
V E + +VD − +
ID = − D + [1.7] E R VR
R R − −
Eq. [1.7] is a linear equation;

y = mx + c ,
where m = −1 / R & c = E / R .
I D = 0 ⇒ VD = E
E [1.8] Fig. 1-11
VD = 0 ⇒ I D =
R
Example 1-1:
Determine the currents I D1 , I D2 , and I R1 for the network of Fig. 1-12.
D1 R1
Si 3.3kΩ
E 20V D2 Si
R2
5.6kΩ
Fig. 1-12
Solution:
VD20.7
I R1 = = = 0.212mA.
R1 3.3k
Appling KVL yields:
− VR2 + E − VD1 − VD2 = 0
and VR2 = E − VD1 − VD2 = 20 − 0.7 − 0.7 = 18.6V ,
VR 18.6
with I D1 = 2 = = 3.32mA.
R2 5.6k
Finally, I D2 = I D1 − I R1 = 3.32m − 0.212m = 3.108mA .
Exercises:
Find the values of ID and Vo in the circuits shown in Fig. 1-13.
− 10V + 10V
+ 16V
ID Ge
ID Si I D1 Si Si
Si 2kΩ 2kΩ
Vo1 Ge Si
1.2kΩ I D2 Ge
Vo
Vo2 Vo
3kΩ
3.3kΩ 2kΩ
+ 12V
(a) (b) (c)
Vo1
rav ( F ) = 0.1kΩ
1kΩ 0.47kΩ 10Sinωt I d (t ) Si r
Vo2 av ( R ) = 1MΩ
Vo (t )
20V I D1 Si I D2 Ge
2kΩ
(d) (e)
Fig. 1-13
University of Technology Diode Switching Circuits
Electrical and Electronic Engineering Department Lecture Two - Page 1 of 3
Diode Switching Circuits
Basic Concepts:
Diode switching circuits typically contain two or more diodes, each of which is
connected to an independent voltage source. Understanding the operation of a diode
switching circuit depends on determining which diodes, if any, are forward biased and
which, if any, are reverse biased. The key to this determination is remembering that
a diode is forward biased only if its anode is positive with respect to its cathode
(see Fig. 2-1). One of the very import applications of diode switching circuits is
logic gates.
+ 5V − 5V − 2V + 3V − 7V
I I I I I
Fig. 2-1
1kΩ 1kΩ 1kΩ 1kΩ 1kΩ
+ 3V + 8V − 2V
Logic Gates:
Diodes can be used to form logic gates, which perform some of the logic operations
required in digital computers.
OR Gate:
It has output when there a signal in any input channels (see Fig. 2-2).
D1
VA Input voltages State of diodes Output voltage
D2 VA VB D1 D2 Vo
VB Vo 0 0 off off 0
0 1 off on 1
R
1 0 on off 1
1 1 on on 1
Fig. 2-2
AND Gate:
It has output only when all inputs are present (see Fig. 2-3).
+V Input voltages State of diodes Output voltage

VA VB D1 D2 Vo
R
D1 0 0 on on 0
VA Vo 0 1 on off 0
D2 1 0 off on 0
VB 1 1 off off 1
Fig. 2-3
Example 2-1:
Determine which diodes are forward biased and which are reverse biased in the circuits
shown in Fig. 2-4. Assuming a 0.7-V drop across each forward-biased diode, determine
the output voltage Vo.
+ 5V + 15V − 10V
R R R
D1 D1 D1
+ 5V Vo + 5V Vo − 5V Vo
D2 D2 D2
− 5V 0V + 5V
D3 D3
+ 5V − 10V
D4
− 5V
(a) (b) (c)
Fig. 2-4
Solution:
In (a) the net forward-biasing voltage between supply and input for each diode is
D1 & D3: +5 - (+5) = 0V,
D2 & D4: +5 - (-5) = 10V.
Therefore, D2 and D4 are forward biased and D1 and D3 are reverse biased.
Vo = -5 + 0.7 = -4.3V.
While in (b) the net forward-biasing voltage between supply and input for each diode is
D1: +15 - (+5) = +10V,
D2: +15 - 0 = +15V,
D3: +15 - (-10) = +25V.
Therefore, D3 is forward biased and D1 and D2 are reverse biased.
Vo = -10 + 0.7 = -9.3V.
Finally, in (c) the net forward-biasing voltage between supply and input for each
diode is
D1: -5 - (-10) = +5V,
D2: +5 - (-10) = +15V.
Therefore, D2 is forward biased and D1 is reverse biased.
Vo = +5 - 0.7 = +4.3V.
Exercises:
Determine Vo and I for each circuit in Fig. 2-5. Assume that each of the diodes in these
circuits has a forward voltage drop of 0.7 V.
D1 + 10V − 15V
+ 2V
D2 2kΩ 2kΩ
− 4V
D3 D1 I D1 I
+ 5V − 4V Vo − 8V Vo
D4 D2 D2
− 1V Vo + 6V + 3V
I D3 D3
− 2V − 5V
2kΩ D4 D4
(a) (b) (c)
+ 20V
2kΩ
D1 1kΩ C D1 I
VA A
D2 1kΩ 1kΩ D3
VB Vo Vo1 Vo2
I − 15V
C D2 1kΩ
5.1kΩ B
1kΩ
− 15V
1. V A = VB = 0V , 1. No pulses at either A or B,
2. V A = VB = 5V , and 2. A 30 V positive pulse at A or B, and
3. V A = 0V & VB = 5V . 3. Positive pulses (30 V) at both A and B.
(d) (e)
Fig. 2-5
University of Technology Diode Clipping Circuits
Electrical and Electronic Engineering Department Lecture Three - Page 1 of 8
Diode Clipping Circuits
Basic Definition:
There are a variety of diode circuits called clippers (limiters or selectors) that have the
ability to "clip" off a portion of the input signal above (positive) or below (negative)
certain level without distorting the remaining part of the alternating waveform.
Depending on the orientation of the diode, the positive or negative region of the input
signal is "clipped" off.
There are two general categories of clippers: series and parallel. The series
configuration is dined as one where the diode is in series with the load. While the
parallel variety has the diode in a branch parallel to the load (see Fig. 3-1).
vi D vo
V
+ +
T T/2 T
vi R vo t
0 T/2 t − −
0
−V −V
Simple Series (Positive) Clipper
vi R vo
V V
+ +
T D vo
vi
0 T/2 t − − 0 T/2 T t
−V
Simple Parallel (Negative) Clipper
Fig. 3-1
Example 3-1:
Biased Series (Negative) Clipper, see Fig. 3-2.

vi
E D
vi vo
0 5.2V Si
T/2 T t R
-9
Fig. 3-2
E − VT Vi D Vi
vi vo
4.5V Ideal 13.5
R
4.5
For t = 0 → t1 and t2 → T; D ON, T/2 t1 t2 T
and vo = vi + 4.5 V. 0
t
For t = t1 → t2; D OFF, - 4.5
and vo = 0 V.
vo vo
13.5 13.5
4.5 4.5
-9 - 4.5 0 9 vi 0
t
Fig. 3-2 (cont.)
Example 3-2:
Biased Parallel (Positive) Clipper, see Fig. 3-3.
vi
10
R
vi vo
D Si
0 T/2 T t
E 5.7V
- 10
Fig. 3-3
R
vo
vi
+ id = 0
Vtransition D Si
10
− E 5.7V
t1 t2
Vtransition – id R – Vd + E = 0; 0 T/2 T
t
Vtransition = 0.7 – 5.7 = – 5 V. -5 Vtransition
For t = 0 → t1 and t2 → T; D ON,
and vo = – 5 V. - 10
For t = t1 → t2; D OFF,

and vo = vi.
vo vo
- 10 -5 10
0 vi 0
t
-5
-5
- 10 - 10
Fig. 3-3 (cont.)
Summary:
A variety of series and parallel clippers with the resulting output for the sinusoidal
input are provided in Fig. 3-4.
Fig. 3-4
Fig. 3-4 (cont.)
Example 3-3:
Double Diode Series Clipper, see Fig. 3-5.
vi
E1 D1
12
3.3V Si
vi vo
E2 D2
0 T/2 T t R
7.7V Ge
-12
D1
E1 + VT1 Vi1
4V Ideal
vi D2 vo
E2 + VT2 Vi2
R
8V Ideal
Fig. 3-5
vi
For t = 0 → t1, t2 → t3, and t4 → T; Vi2
20
both D1 and D2 will be OFF,
and vo = 0 V.
For t = t1 → t2; D1 ON while D2 OFF, 8
T/2 T
and vo = Vi1 = vi – 4 V. t1 t2 t3 t4
For t = t3 → t4; D1 OFF while D2 ON, 0 t
-4
and vo = Vi2 = vi + 8 V.
vo - 16
8
Vi1
vo
- 12 -8 8
0 4 12 vi
-4 0
-4 t
Fig. 3-5 (cont.)
Example 3-4:
Double Diode Parallel Clipper, see Fig. 3-6.

vi
9
R
vi vo
T D1 Si D2 Si
0 T/2 t
E1 2.3V E 2 5.3V
-9
R R
vo vo
+ id1 = 0D Si
+ id 2 = 0D Si
Vtr1 1 Vtr2 2
− E1 2.3V − E2 5.3V
Vtr1 – id1 R – Vd – E1 = 0; Vtr2 + id2 R + Vd + E2 = 0;

Vtr1 = 0.7 + 2.3 = 3 V. Vtr2 = – 0.7 – 5.3 = – 6 V.
Fig. 3-6
For t = 0 → t1, t2 → t3, and t4 → T; vi

both D1 and D2 will be OFF, 9
and vo = vi.
For t = t1 → t2; D1 ON while D2 OFF, 3
t1 t2 t3 t4 T
Vtr1
and vo = 3 V. 0 T/2 t
For t = t3 → t4; D1 OFF while D2 ON, -6 Vtr2
and vo = – 6 V. -9
vo vo
3 3
-9 -6
0 3 9 vi 0 t
-6 -6
Fig. 3-6 (cont.)
Example 3-5:
Special Type Clipper: A Comparator, see Fig. 3-7.
vi
10
D
vi vo
Idial
0 T/2 T t R
E 5V
- 10
Fig. 3-7
vi
10
5 E
For t = 0 → t1 and t2 → T; D OFF,
t1 t2 T/2
and vo = E = 5 V. T
0 t
For t = t1 → t2; D ON,
and vo = vi.
- 10
vo
10 vi
5
10
5
- 10 0 5 10 vi
0 t
Fig. 3-7 (cont.)
Exercises:
1. Design biased parallel clippers (with silicon diodes) to perform the functions
indicated in the transfer characteristics of Fig. 3-8.
vo vo
12 12
- 12 -6
- 12 0 6 12 vi 0 12 vi
-6
(a) (b)
Fig. 3.8
2. Sketch the output voltage (vo) and the transfer characteristics (vo against vi) for each
circuit of Fig. 3-9 for the input (vi) shown.
vi
8 D
vi vo
T/2 T
Ideal R (a)
0 t
E 4V
-8
vi
E1
R
10 vi vo
4V
D Si
(b)
E2 2.3V
0 T t
vi
9
R
vi vo
T/2 T D1 D2
Ge Si (c)
0 t
E1 3.3V E 2 5.3V
-9
vi
D1 D2
150 vi vo
Ideal Ideal
R1 100kΩ R2 200kΩ (d)
E1 25V E 2 100V
0 T t
Fig. 3-9
University of Technology Diode Clamping Circuits
Electrical and Electronic Engineering Department Lecture Four - Page 1 of 4
Diode Clamping Circuits
Basic Definition:
The clamping circuit (clamper) is one will "clamp" a signal to a different dc level.
The circuit must have a capacitor, a diode, and a resistive element, but it can also
employ an independent dc supply to introduce an additional shift. The magnitude of
R and C must be chosen such that the time constant τ = RC is large enough to ensure
that the voltage across the capacitor does not discharge significantly during the interval
(T/2) the diode is nonconducting. Throughout the analysis we will assume that for all
practical purposes the capacitor will fully charge or discharge in five time constants.
Therefore, the condition required for the capacitor to hold its voltage during the
discharge period between pulses of the input signal is
T 1
5τ = 5 RC >> = [4.1]
2 2f
Example 4-1:
Determine the output (vo) for the circuit of Fig. 4-1 for the input (vi) shown.
vi
C
10 f = 1kHz vi vo
0.1μF
D Si
-5
0 T/2 T 3T/2 2T t R 50kΩ
E 5V
- 20
Fig. 4-1
Solution:
The analysis of clamping circuits are started by considering that the part of the input
signal that will forward bias the diode. For the circuit of Fig. 4-1, the diode is forward
bias ("on" state) during the negative half period of the input signal (vi) and the capacitor
will charge up instantaneously to a voltage level determined by the circuit of Fig. 4-2.
_ VC
+
_ _ +
0.7V
20V + 50kΩ vo
+ 5V _
Fig. 4-2
For the input section KVL will result in

– 20 + VC + 0.7 – 5 = 0 => VC = 24.3 V.
The output voltage (vo) can be determined by KVL in the output section
+ 5 – 0.7 – vo = 0 => vo = 4.3 V.
Now check that the capacitor will hold on or not its establish voltage level during
the period (positive half period in case of Example 4-1) when the diode is in the
"off" state (reverse bias). The total time constant 5τ of the discharging circuit of
Fig. 4-3 is determined by the product 5RC and has the magnitude
5τ = 5RC = 5 (50×103) (0.1×10-6) = 25 ms.
The frequency ( f ) is 1 kHz, resulting in a period of 1 ms and an interval of 0.5 ms
between levels, that is
T/2 = 1/( 2f ) = 1/(2 × 1×103) = 0.5 ms.
We find that
5 τ >> T/2 ( 25ms / 0.5ms = 50 times).
So that, it is certainly a good approximation that the capacitor will hold its voltage
(24.3 V) during the discharge period between pulses of the input signal.
_24.3V
+
+ +
10V 50kΩ vo
_ 5V _
Fig. 4-3
The open-circuit equivalent for the diode will remove the 5-V battery from having any
effect on vo, and applying KVL around the outside loop of circuit will result in
+ 10 + 24.3 – vo = 0 => vo = 34.3 V.
The resulting output appears in Fig. 4-4, where the input and the output swing
are the same.
vo
34.3
19.3
4.3
0 T/2 T 3T/2 2T 5T/2 t
Fig. 4-4
Example 4-2:
Using silicon diode, design a clamper circuit that will produce output vo = 10Sinωt–5 V
when the input is vi = 10Sinωt+5 V. Draw the circuit diagram and the input and output
signals.
Solution:
From the input (vi) and output (vo) signals, we have a negative biased clamper.
Therefore, the diode is forward bias ("on" state) during the positive half period of the
input signal (vi). The output voltage (vo) at this positive period can be determined by
KVL in the output section of the circuit shown in Fig. 4-5.
E + 0.7 – vo = 0 => E = 5 – 0.7 = 4.3 V.
For the input section KVL will result in VC _
+
15 – VC – 5 = 0 => VC = 10 V.
+ + +
0_.7V
Fig. 4-5 vi = 15V R vo = 5V
_ E _
The circuit diagram and the input and output signals are shown in Fig. 4-6.
vi
15
C
vi vo
5
D Si
T/2 T 3T/2 2T R
0 t E 4.3V
-5
vo
0 T/2 T 3T/2 2T t
-5
-15
Fig. 4-6
Summary:
A number of clamping circuits and their effect on the square-wave input signal are
shown in Fig. 4-7.
Negative Clampers Positive Clampers
Clampers with ideal diodes and 5τ = 5RC >> T/2
Fig. 4-7
Exercise:
Sketch the output (vo) for the circuit of Fig. 4-8 for the input (vi) shown. Assume ideal
diodes.
vi
E0 R1 C
15
+ 3V D1 D2 +
T
vi R2 vo
0 T/2 t − E1 7V E 2 10V −
-15
Fig. 4-8
University of Technology Diode Rectifier Circuits
Electrical and Electronic Engineering Department Lecture Five - Page 1 of 10
Diode Rectifier Circuits
Basic Definition:
A diode circuit that converts an ac voltage to a pulsating dc voltage and permits current
to flow in one direction only is called "rectifier" and the ac-to-dc conversion process is
termed "rectification".
Half-Wave Rectifier (HWR):

N1 N2 D
+ + _ i +
+ VT
vi V1 V2 VP RL vo
_ _ _
vi = V1 V2 vo
VP/n VP VPR
2π 2π
0 π ωt 0 π ωt 0 π 2π
ωt
T
N V
n= 2 = 2 fo = fi = 1/ T
N1 V1
Fig. 5-1
For the half-wave rectifier circuit of Fig. 5-1:
W The average (dc) value of a half-wave rectified sine-wave voltage (Vdc) is

T π
1 1 V
Vdc = ∫ vo (ωt ) ⋅ dωt = ∫ VPR Sinωt ⋅ dωt = PR
T0 2π 0 π
For VP close to VT,
Vdc = 0.318(VP − VT ) [5.1a]
For VP >> VT,
Vdc = 0.318VP [5.1b]
W The root mean square (rms) value of the load voltage (Vrms) is
T π
1 2 1 VPR
T ∫0 2π ∫0
Vrms = vo (ωt ) ⋅ dωt = V 2
PR Sin 2
ω t ⋅ d ωt =
2
For VP close to VT,
Vrms = 0.5(VP − VT ) [5.2a]
For VP >> VT,
Vrms = 0.5VP [5.2b]
W The rms value of the ac component (or the ripple voltage) of the rectified signal
[Vr(rms)] is
2
Vr (rms ) = Vrms − Vdc2 = (0.5VPR ) 2 − (0.318VPR ) 2 = 0.385VPR
For VP close to VT,
Vr (rms) = 0.385(VP − VT ) [5.3a]
For VP >> VT,
Vr (rms ) = 0.385VP [5.3b]
W The percent ripple (r) in the rectified waveform (also called the ripple factor) is
V (rms) 0.385VPR
r= r × 100% = × 100% = 121%
Vdc 0.318VPR
W Efficiency (η) = [ Pdc(load) / Ptotal(circuit) ] × 100%

2
I dc RL (0.318 I P ) 2 RL 40.5
η= 2 × 100% = × 100% = %
I rms (rd + RL ) 2
(0.5I P ) (rd + RL ) 1 + rd / RL
For ideal diode (rd = 0 Ω), η = ηmax = 40.5 %
W The peak inverse voltage (PIV) of the diode is

PIV = VP [5.4]
W The frequency of the output rectified signal (fo) is

fo = fi [5.5]
Full-Wave Rectifiers (FWRs):
1. A Bridge Full-Wave Rectifier:

N1 N2 + (-)
+ (-) D4
+ D1
i1 i
vi V1 V2 VP
(i2) +
_ - (+) D2 D3 R L vo
_
- (+)
vi = V1 V2 vo
VP/n VP VPR
2π 2π
ωt
T
N V fo = 2 fi
n= 2 = 2
N1 V1 i = i1 + i2
Fig. 5-2
For the bridge full-wave rectifier circuit of Fig. 5-2:
π
1 2VPR
π ∫ PR
W Vdc = V Sinωt ⋅ dωt =
0
π
For VP close to 2VT,
Vdc = 0.636(VP − 2VT ) [5.6a]
For VP >> 2VT,
Vdc = 0.636VP [5.6b]
π
1 VPR
∫ VPR Sin ωt ⋅ dωt =
2 2
W Vrms =
π 0 2
Vrms = 0.707(VP − 2VT ) [5.7a]
For VP >> 2VT,
Vrms = 0.707VP [5.7b]
2
W Vr (rms ) = Vrms − Vdc2 = (0.707VPR ) 2 − (0.636VPR ) 2 = 0.308VPR
Vr (rms) = 0.308(VP − 2VT ) [5.8a]
For VP >> 2VT,
Vr (rms) = 0.308VP [5.8b]
Vr (rms ) 0.308VPR
W r= × 100% = × 100% = 48.4%
Vdc 0.636VPR
2
I dc RL (0.636 I P ) 2 RL 81
W η= 2 × 100% = × 100% = %
I rms (2rd + RL ) (0.707 I P ) 2 (2rd + RL ) 1 + 2rd / RL
For ideal diode (rd = 0 Ω), η = ηmax = 81 %
W PIV = VP − 2VT [5.9]
W fo = 2 fi [5.10]
2. A Center-Tapped (CT) Full-Wave Rectifier:

N1 N2 D1
+ (-)
+ V2 VP i1 i
- (+)
vi V1 + (-) +
_ V2 VP (i2) RL vo
- (+) _
N2 D2
vi = V1 V2 vo
VP/n VP VPR
2π 2π
ωt
T
N V fo = 2 fi
n= 2 = 2
N1 V1 i = i1 + i2
Fig. 5-3
For the center-tapped full-wave rectifier circuit of Fig. 5-3:
π
1 2VPR
π ∫ PR
W Vdc = V Sinωt ⋅ dωt =
0
π
For VP close to VT,
Vdc = 0.636(VP − VT ) [5.11a]
For VP >> VT,
Vdc = 0.636VP [5.11b]
π
1 VPR
∫ VPR Sin ωt ⋅ dωt =
2 2
W Vrms =
π 0 2
For VP close to VT,
Vrms = 0.707(VP − VT ) [5.12a]
For VP >> VT,
Vrms = 0.707VP [5.12b]
2
W Vr (rms ) = Vrms − Vdc2 = (0.707VPR ) 2 − (0.636VPR ) 2 = 0.308VPR
For VP close to VT,
Vr (rms) = 0.308(VP − VT ) [5.13a]
For VP >> VT,
Vr (rms) = 0.308VP [5.13b]
Vr (rms ) 0.308VPR
W r= × 100% = × 100% = 48.4%
Vdc 0.636VPR
2
I dc RL (0.636 I P ) 2 RL 81
W η= × 100% = × 100% = %
2
I rms (rd + RL ) (0.707 I P ) 2 (rd + RL ) 1 + rd / RL
For ideal diode (rd = 0 Ω), η = ηmax = 81 %
W PIV = 2VP − VT [5.14]
W fo = 2 fi [5.15]
Summary:
Different parameters for the HWR and FWR circuits are listed in Table 5-1.
Table 5-1
FWR
Parameter HWR
Bridge CT
VPR VP – VT VP – 2VT VP – VT
Vdc 0.318VPR 0.636VPR
Vrms 0.5VPR 0.707VPR
Vr 0.385VPR 0.308VPR
r 121% 48.4%
ηmax 40.5% 81%
PIV VP VP – 2VT 2VP – VT
fo fi 2fi
Example 5-1:
The input voltage to a full-wave rectifier employing a center-tapped step-down

transformer and two silicon diodes is 220 V rms, and the transformer has turns ratio
n = 0.125. Draw the rectifier circuit diagram when it is connected to a 100 Ω load,
and find
1. the average value of the voltage across the load.
2. the average power dissipated by the load, and
3. the minimum PIV rating required for each diode.
Solution:
The rectifier circuit diagram is shown in Fig. 5-4.
1. VP = 2vi n = 2 ∗ 220 ∗ 0.125 = 38.9V .

Vdc = 0.636(VP − VT ) = 0.636(38.9 − 0.7 ) = 24.3V .
2. Vrms = 0.707(VP − VT ) = 0.707(38.9 − 0.7 ) = 27.0V .
Pav =
2
Vrms
=
(27.0 )
2
= 7.3W .
RL 100
3. PIV ≥ (2VP − VT ) = (2 ∗ 38.9 − 0.7 ) = 77.1V .
n = 0.125 D1
+ +
V_P Si
vi = 220V
+
_ V_P D2 RL 100Ω
Si
Fig. 5-4
Capacitor Filters:
A low-pass filter is connected across the output of a rectifier to suppress the ac

components and to pass the dc component. A rudimentary low-pass filter used in power
supplies consists simply of a capacitor (C) connected across the rectifier output, that is,
in parallel with the load (RL), as illustrated in Fig. 5-5.
Vo = VC
D Charging Discharging
VPR
+ + Vr ( pp )
vi RL C Vo
_ _
D OFF t
D ON T
Half-wave rectifier with capacitor filter
D1
Vo = VC
+ Vr ( pp )
vi VPR
+
_
RL C Vo
D2 _
T t
Full-wave rectifier with capacitor filter
Fig. 5-5
Operation:
W During the positive first quarter-cycle of the input, the diode is forward-biased
(when Vi > VC), allowing the capacitor to charge quickly to within a diode drop of
the input peak (VPR).
W When the input begins to decrease below its peak, the capacitor retain its charge
and the diode becomes reverse-biased (when VC > Vi).
W During the remaining part of the cycle, capacitor C can discharge slowly only
through load resistance RL at a rate determine by RLC time constant (τ).
W The voltage fluctuation in the filtered waveforms is called the peak-to-peak ripple
voltage [Vr(pp)]. In general, Vr(pp) in FWR is smaller than it is in HWR for same
RL and C values (see Fig. 5-5).
Ripple of a Capacitor Filter:
We will now derive an expression for the ripple in the output of a rectifier having a
capacitor filter (C) and load resistance (RL). The derivation that follows is applicable to
both HWR and FWR. We can assume that the ripple voltage in a lightly loaded filter
(RLC time constant (τ) is large) is a sawtooth wave as illustrated in Fig. 5-6.
Vo = VC
Vr ( pp)
VPR 2
Vdc Vr ( pp)
t
Fig. 5-6
This approximation is equivalent to assuming that the capacitor charges instantaneously

and that its voltage decays linearly, instead of exponentially. Assuming that the voltage
decays linearly is equivalent to assuming that the discharge current (I) is constant and
equal to I = Vdc / RL where Vdc is the dc value of the filtered waveform. The total
charge in capacitor voltage is Vr(pp) volts, and this charge occurs over the period of
time T. Therefore, since ΔQ = I .Δt ,
ΔQ (Vdc / RL )T
Vr ( pp ) = =
C C
Since T=1/fr, where fr is the frequency of the fundamental component of the ripple,
that is, f r = f o = f i for HWR and f r = f o = 2 f i for FWR. So that
Vdc
Vr ( pp ) = [5.16]
f r RL C
or
Vdc = Vr ( pp) ⋅ f r RL C [5.17]
From Fig. 5-6, it is apparent that

V ( pp )
Vdc = VPR − r
2
Subsuming from Eq. [5.16], we obtain
Vdc
Vdc = VPR −
2 f r RL C
Solving for Vdc, we obtain an expression for the dc voltage (Vdc) in terms of the peak
rectifier voltage (VPR):
VPR
Vdc = [5.18]
1
1+
2 f r RL C
The rms value of a sawtooth waveform having peak-to-peak value Vr(pp) is known to
be
V ( pp)
Vr (rms) = r [5.19]
2 3
Therefore, from Eqs. [5.17] and [5.19], the percent ripple is
Vr (rms) V ( pp ) /(2 3 )
r= × 100% = r × 100%
Vdc Vr ( pp) f r RL C
1
r= × 100% [5.20]
2 3 f r RL C
Equation [5.20] confirms our analysis of the capacitor filter: a large RLC time
constant (τ) results in a small ripple voltage, and vice versa. The light-load assumption
on which our derivation is based is generally valid for percent ripple (r) less than 6.5%.
From a design standpoint, the values of fr and RL, are usually fixed, and the designer's
task is to select a value of C that keeps the ripple below a prescribed value.
Example 5-2:
A full-wave rectifier is operated from a 50 Hz line and has a filter capacitor connected
across its output. What minimum value of capacitance is required if the load is 1.2 kΩ
and the ripple must be no greater than 2.4%?
Solution:
1
r= × 100%
2 3 f r RL C
1
0.024 = =>
2 3 ∗ 2 ∗ 50 ∗1.2 ∗10 3 ∗ C
C ≥ 100 μF .
Exercises:
1. A full-wave bridge rectifier isolated from the 220 V rms power line by a transformer.
Assuming the diode voltage drops are 0.7 V.
i. What turns ratio should the transformer have in order to produce an average
current of 1 A in a 10 Ω load?
ii. What is the average current in each diode under the conditions of (i)?
iii. What minimum PIV rating should each diode have?
iv. How much power is dissipated by each diode?
2. A full-wave bridge rectifier is operated from a 50 Hz, 220 V rms line. It has a 100 μF
filter capacitor and a 2 k Ω load. Neglect diode voltage drops.
i. What is the percent ripple?
ii. What is the average current in the load?
University of Technology Voltage-Multiplier Circuits
Electrical and Electronic Engineering Department Lecture Six - Page 1 of 3
Voltage-Multiplier Circuits
Basic Concepts:
Diodes and capacitors can be connected in various configurations to produce filtered,
rectified voltages that are integer multiples of the peak value of an input sine wave. The
principle of operation of these circuits is similar to that of the clamping circuits
discussed previously. By using a transformer to change the amplitude of an ac voltage
before it is applied to a voltage multiplier, a wide range of dc levels can be produced
using this technique. One advantage of a voltage multiplier is that high voltages can be
obtained without using a high-voltage transformer.
Voltage Doubler:
1. Half-Wave Voltage Doubler:
Figure 6-1 shows a half-wave voltage doubler circuit.
VP _
+
_
+ + D2 _
C1
vi VP D1 2VP C 2 Vo = 2VP
_ _ + +
Fig. 6-1
Operation:
W During the positive half-cycle,
D1 ON and D2 OFF => Charging C1 up to VP.
W During the negative half-cycle,
D2 ON and D1 OFF => Charging C2 to 2VP.
W The output (Vo) of the half-wave voltage doubler is
Vo = VC2 = 2VP [6.1]
If a load is connected to the output of the half-wave voltage doubler, the voltage
across capacitor C2 drops during the positive half-cycle (at the input) and the capacitor
is recharged up to 2VP during the negative half-cycle. The output waveform across
capacitor C2 is that of a half-wave signal filtered by a capacitor filter.
The peak inverse voltage (PIV) rating of each diode in the half-wave voltage
doubler circuit must be at least 2VP.
2. Full-Wave Voltage Doubler:
Figure 6-2 shows a full-wave voltage doubler circuit.
D1
+ + +
+
vi VP VP _ C1
_ _
Vo = 2VP
+
VP _ C2
_
D2
Fig. 6-2
Operation:
W The output (Vo) of the full-wave voltage doubler is
Vo = VC1 + VC2 = 2VP [6.2]
If load current is drawn from the full-wave voltage doubler circuit, the voltage
across the capacitors C1 and C2 is the across a capacitor fed by a full-wave rectifier.
One difference is that of C1 and C2 in series, which is less than capacitance of either C1
and C2 alone. The lower capacitor value will provide poorer filtering action than the
single-capacitor filter circuit.
The peak inverse voltage across each diode is 2VP, as it is for filter capacitor
circuit.
Voltage Tripler and Quadrupler:
Figure 6-3 shows an extension of the half-wave voltage doubler, which develops
three and four times the peak input voltage. It should be obvious from the pattern
of the circuit connection how additional diodes and capacitors may be connected
so that the output voltage may also be five, six, seven, and so on, times the basic peak
voltage (VP).
Tripler (3VP )
VP _ 2VP_
+ +
+ +
C1 C3
vi VP D1 D2 D3 D4
_ _ C2 C4
_ _
+ +
2VP 2VP
Doubler (2VP )
Quadrupler ( 4VP )
Fig. 6-3
Operation:
D1 ON and D2, D3, D4 OFF => Charging C1 up to VP.
D2 ON and D1, D3, D4 OFF => Charging C2 to 2VP.
W During the next positive half-cycle,
D1, D3 ON and D2, D4 OFF => C2 charges C3 to 2VP.
W During the next negative half-cycle,
D2, D4 ON and D1, D3 OFF => C3 charges C4 to 2VP.
W The voltage across the combination of C1 and C3 is 3VP and that across C2 and
C4 is 4VP.
The PIV rating of each diode in the circuit must be at least 2VP.
Exercises:
1. A certain voltage doubler has 35 V rms on its input. What is the output voltage?
Sketch the circuit, indicating the output terminals and PIV for the diode.
2. Repeat Exercise 1 for a voltage tripler and quadrupler.
3. The output voltage of a quadrupler is 620 V. What minimum PIV rating must each
diode have?
University of Technology Zener Diodes and Applications
Electrical and Electronic Engineering Department Lecture Seven - Page 1 of 7
Zener Diodes and Applications
Zener Diodes:
Diodes which are designed with plate power-dissipation capabilities to operate in the
breakdown region may be employed as voltage-reference or constant-voltage devices.
Such are known as avalanche, breakdown, or zener diodes. The zener diode is made
for operation in the breakdown region. By varying the doping level, a manufacturer can
produce zener diodes with breakdown voltages from about 2 to 250 V.
When the applied reverse voltage reaches the breakdown value, minority carries
in the depletion layer are accelerated and reach high enough velocities to dislodge
valence electrons from outer orbits. The newly liberated electrons can then gain high
enough velocities to free other valence electrons. In this way, we get an avalanche of
free electrons. Avalanche occurs for reverse voltages greater than 6 V or so.
The zener effect is different. When a diode is heavily doped, the depletion layer
is very narrow. Because of this, the electric field across the depletion layer is very
intense. When the field strength reaches approximately 3×107 V/m, the field is intense
enough to pull electrons out of valence orbits. The creation of free electrons in this way
is called zener breakdown (also known as high-field emission).
The zener effect is predominant for breakdown voltages less than 4 V, the
avalanche effect is predominant for breakdown voltages greater than 6 V, and both
effects are present between 4 and 6 V. Originally, people thought the zener effect was
the only breakdown mechanism in diodes. For this reason, the name "zener diode"
came into widespread use before the avalanche effect was discovered. All diodes
optimized for operation in the breakdown region are therefore still called zener diodes.
I D (mA)
Cathode
Anode
VZ
VD (V )
I ZK
rZ IZ
I ZM
Fig. 7-1
Fig. 7-1 shows the schematic symbol and the current-voltage curve of a zener
diode. Negligible reverse current flows until we reach the breakdown voltage VZ.
In a zener diode, the breakdown has a very sharp knee, followed by an almost vertical
increase in current. Note that the voltage is approximately constant, equal to VZ over
most of the breakdown region. Data sheets usually specify the value of VZ at a
particular knee current IZK which is beyond the knee (see Fig. 7-1).
The power dissipation of a zener diode equals the product of its voltage and
current. In symbols,
PZ = VZ ⋅ I Z
As long as PZ is less than the power rating PZ(max), the zener diode will not be destroyed.
Commercially available zener diodes have power ratings from 0.25 W to more than
50 W. Data sheets often specify the maximum current a zener diode can handle without
exceeding its power rating. This maximum current is designated IZM (see Fig. 7-1).
The relation between IZM and power rating is given by
PZ (max)
I ZM = [7.1]
VZ
When a zener diode is operating in the breakdown region, a small increase in

voltage produces a large increase in current. This implies that a zener diode has a small
dynamic resistance (rZ, see Fig. 7-1). We can calculate this zener resistance by
Δv
rZ =
Δi
The complete equivalent circuit of the zener diode in the zener region includes
a small dynamic resistance (rZ) and dc battery equal to the zener potential (VZ),
as shown in Fig. 7-2a. For all applications to follow, however, we shall assume as a
first approximation that the external resistors are much larger in magnitude than the
zener-equivalent resistor and that the equivalent circuit is simply the dc battery that
equal to VZ as indicated in Fig. 7-2b.
+
IZ
VZ
VZ
rZ
≅ VZ
−
(a) (b)
Fig. 7-2
Zener Diode Applications:
1. AC Voltage Regulators (Limiters or Clippers):
Two back-to-back zeners can be used as an ac regulator or a simple square-wave

generator as shown in Examples 7-1 and 7-2 respectively.
Example 7-1:
Sinusoidal ac regulator, see Fig. 7-3.

vi
R
+12 VZ 2 + VT1 vo
+7.5 + 5kΩ +
+7.5
D1[VZ1 = 3.3V , Si]
t1 t 2 t3 t4
vi vo 2π
0 π 2π t 0 π
-4 D2 [VZ 2 = 6.8V , Si ] t
-4
_ _
VZ1 + VT2
-12
Fig. 7-3
For t = 0 → t1 and t2 → π; D1 ON and D2 OFF => vo = vi .

For t = t1 → t2; D1 ON and D2 BREAKDOWN => vo = VZ 2 + VT1 .
For t = π → t3 and t4 → 2π; D2 ON and D1 OFF => vo = vi .
For t = t3 → t4; D2 ON and D1 BREAKDOWN => vo = VZ1 + VT2 .
Example 7-2:
Simple square-wave generator, see Fig. 7-4.

vi
+40
R
+ 5kΩ + vo VZ 2
D1[VZ1 = 10V ] +10
2π vi vo 2π
π 0 π t
t -10
D2 [VZ 2 = 10V ]
_ _ VZ1
- 40
Fig. 7-4
2. DC Voltage Reference:
Two or more reference levels can be established by placing zener diodes in series as
shown in Fig. 7-5. As long as Vi is grater than the sum of VZ1 and VZ 2 , both diodes will
be in the breakdown state and the three reference voltages will be available.
+ +
D1[VZ1 = 10V ] 10V
R 5kΩ _
30V
+ +
E _ 50V D2 [VZ 2 = 20V ] 20V
_ _
Fig. 7-5
3. DC Voltage Regulators:
a. Fixed RL, Variable Vi:
For the regulator circuit shown in Fig. 7-6;
VZ
IL = (Constant) [7.2a]
RL IS
RS
IZ IL
+
I S (min) = I ZK + I L Vi VZ RL
[7.2b] −
Vi (min) = I S (min) RS + VZ
Fig. 7-6
I S (max) = I ZM + I L
[7.2c]
Vi (max) = I S (max) RS + VZ
b. Fixed Vi, Variable RL:
Vi − VZ
IS = (Constant) [7.3a]
RS
RS IS
IZ IL
I L (min) = I S − I ZM +
Vi VZ RL
VZ [7.3b] −
RL (max) =
I L (min)
Fig. 7-7
I L (max) = I S − I ZK
VZ [7.3c]
RL (min) =
I L (max)
c. Variable Vi and RL:
I ZK = I S (min) − I L (max)
Vi (min) − VZ
I S (min) = [7.4a]
RS
VZ RS IS
I L (max) =
RL (min) IZ IL
+
Vi VZ RL
−
I ZM = I S (max) − I L (min)
Vi (max) − VZ
I S (max) = [7.4b] Fig. 7-8
RS
VZ
I L (min) =
RL (max)
Example 7-3:
The reverse current in a certain 12 V, 2.4 W zener diode must be at least 5 mA to

ensure that the diode remains in breakdown. The diode is to be used in the regulator
circuit shown in Fig. 7-9, where Vi can vary from 18 V to 24 V. Find a suitable
value for RS and the minimum rated power dissipation that RS should have.
RS S
+
Vi VZ RL 600Ω
−
Fig. 7-9
Solution:
PZ 2.4
I ZK = 5mA and I ZM = = = 200mA .
VZ 12
I L (min) = 0 A (when the switch S is open, RL = RL (max) = ∞Ω ).

VZ 12
I L (max) = = = 20mA (when the switch S is closed, RL = RL (min) = 600Ω ).
RL (min) 600
I ZK = I S (min) − I L (max) => 5 ∗10 −3 = I S (min) − 20 ∗10 −3 => I S (min) = 25mA .

I ZM = I S (max) − I L (min) => 200 ∗ 10 −3 = I S (max) − 0 => I S (max) = 200mA .
Vi (min) − VZ 18 − 12
RS (max) = = = 240Ω .
I S (min) 25 ∗10 −3
Vi (max) − VZ
24 − 12
RS (min) = = 60Ω .
=
I S (max) 200 ∗10 −3
Thus, we require 60Ω ≤ RS ≤ 240Ω .
Choosing or calculating RS = RS (min) ⋅ RS (max) = 60 ∗ 240 = 120Ω .
Vi (max) − VZ 24 − 12
I S (max) = = = 100mA .
RS 120
( )
2
PRS ≥ I S2(max) ⋅ RS = 100 ∗10 −3 ∗120 = 1.2W .
Exercises:
1. Sketch the output (vo) for the circuit of Fig. 7-10 for the input shown (vi) when
|Vm| equal to (i) 5 V, and (ii) 15 V.
vi
R
+Vm
+ 5kΩ +
2π vi D[VZ = 10V , Si ] vo
0 π t
_ _
-Vm
Fig. 7-10
2. Design the voltage regulator circuit of Fig. 7-11 to maintain VL at 12 V across RL

with Vi that will vary between 16 and 20 V. That is, determine the proper value of RS
and the power rating of the zener diode (PZ).
RS
+
Vi VL RL 240Ω Fig. 7-11
−
3. The 6-V zener diode in Fig. 7-12 has a maximum rated power dissipated of
690 mW. Its reverse current must be at least 3 mA to keep it in breakdown. Find
a suitable value for RS if Vi can vary from 9 V to 12 V and RL can vary from
500 Ω to 1.2 kΩ.
RS IS
IZ IL
+
Vi 6V RL Fig. 7-12
−
4. If RS in Exercise 3 is set equal to its maximum permissible value, what is the

maximum permissible value of Vi?
5. If RS in Exercise 3 is set equal to its minimum permissible value, what is the

minimum permissible value of RL?
6. If RS in Exercise 3 is set equal to 120 Ω, what is the minimum rated power

dissipated that RS should have?

Lectures 1-7 Diode Circuit Applications

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Part I

The PN Junction Diode

No Applied Bias (VD = 0 V):

Reverse Bias (VD < 0 V):

Forward Bias (VD > 0 V):

I-V Characteristic Carve and Current Equation:

In differential calculus, the derivative of a function at a point is equal to the slope

Equivalent Circuits (Models):

1. Piecewise-Linear Model: (see Fig.1-8);

2. Simplified Model: (see Fig. 1-9);

Reverse-bias, rav(R) = ∞ Ω & ID = 0 A; Fig. 1-9

3. Ideal Model: (see Fig. 1-9);

Reverse-bias, rav(R) = ∞ Ω & ID = 0 A; Fig. 1-10

From Fig. 1-11:

Eq. [1.7] is a linear equation;

Determine the currents I D1 , I D2 , and I R1 for the network of Fig. 1-12.

Find the values of ID and Vo in the circuits shown in Fig. 1-13.

(a) (b) (c)

Diode Switching Circuits

+V Input voltages State of diodes Output voltage

(a) (b) (c)

Diode Clipping Circuits

Biased Series (Negative) Clipper, see Fig. 3-2.

Fig. 3-2 (cont.)

Biased Parallel (Positive) Clipper, see Fig. 3-3.

For t = t1 → t2; D OFF,

Fig. 3-3 (cont.)

Fig. 3-4 (cont.)

Double Diode Series Clipper, see Fig. 3-5.

Fig. 3-5 (cont.)

Double Diode Parallel Clipper, see Fig. 3-6.

Vtr1 – id1 R – Vd – E1 = 0; Vtr2 + id2 R + Vd + E2 = 0;

For t = 0 → t1, t2 → t3, and t4 → T; vi

Fig. 3-6 (cont.)

Special Type Clipper: A Comparator, see Fig. 3-7.

Fig. 3-7 (cont.)

Diode Clamping Circuits

For the input section KVL will result in

Negative Clampers Positive Clampers

Clampers with ideal diodes and 5τ = 5RC >> T/2

Diode Rectifier Circuits

Half-Wave Rectifier (HWR):

For the half-wave rectifier circuit of Fig. 5-1:

W The average (dc) value of a half-wave rectified sine-wave voltage (Vdc) is

W Efficiency (η) = [ Pdc(load) / Ptotal(circuit) ] × 100%

W The peak inverse voltage (PIV) of the diode is

W The frequency of the output rectified signal (fo) is

Full-Wave Rectifiers (FWRs):

1. A Bridge Full-Wave Rectifier:

For the bridge full-wave rectifier circuit of Fig. 5-2:

W PIV = VP − 2VT [5.9]

2. A Center-Tapped (CT) Full-Wave Rectifier:

For the center-tapped full-wave rectifier circuit of Fig. 5-3:

W PIV = 2VP − VT [5.14]

The input voltage to a full-wave rectifier employing a center-tapped step-down

The rectifier circuit diagram is shown in Fig. 5-4.

1. VP = 2vi n = 2 ∗ 220 ∗ 0.125 = 38.9V .

2. Vrms = 0.707(VP − VT ) = 0.707(38.9 − 0.7 ) = 27.0V .

3. PIV ≥ (2VP − VT ) = (2 ∗ 38.9 − 0.7 ) = 77.1V .

A low-pass filter is connected across the output of a rectifier to suppress the ac

Half-wave rectifier with capacitor filter

Full-wave rectifier with capacitor filter