CMOS

Technology

1. CMOS Fabrication
2. Layout Design Rules
3. CMOS gate design

3: CMOS Technology
 1. CMOS Fabrication
❑ CMOS transistors are fabricated on silicon wafer
❑ Lithography process similar to printing press
❑ On each step, different materials are deposited or
etched
❑ Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Inverter Cross-section
❑ Typically use p-type substrate for nMOS transistors
❑ Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

3: CMOS Technology CMOS VLSI Design 4th Ed.

Well and Substrate Taps
❑ Substrate must be tied to GND and n-well to VDD
❑ Metal to lightly-doped semiconductor forms poor
connection called Schottky Diode
❑ Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Well and Substrate Taps
What is Latchup: Latchup refers to short circuit formed between power and ground rails in an
IC leading to high current and damage to the IC. Speaking about CMOS transistors, latch up is
the phenomenon of low impedance path between power rail and ground rail due to interaction
between parasitic pnp and npn transistors. The structure formed by these resembles a Silicon
Controlled rectifier (SCR, usually known as a thyristor, a PNPN device used in power
electronics). These form a +ve feedback loop, short circuit the power rail and ground rail,
which eventually causes excessive current, and can even permanently damage the device.

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Inverter Mask Set
❑ Transistors and wires are defined by masks
❑ Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Detailed Mask Views
❑ Six masks n well

– n-well
– Polysilicon
Polysilicon

– n+ diffusion
– p+ diffusion n+ Diffusion

– Contact p+ Diffusion

– Metal Contact

Metal

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Fabrication
❑ Chips are built in huge factories called fabs
❑ Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Fabrication Steps
❑ Start with blank wafer
❑ Build inverter from the bottom up
❑ First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Oxidation
❑ Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Photoresist
❑ Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Lithography
❑ Expose photoresist through n-well mask
❑ Strip off exposed photoresist

Photoresist
SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Etch
❑ Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
❑ Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Strip Photoresist
❑ Strip off remaining photoresist
– Use mixture of acids called piranah etch
❑ Necessary so resist doesn’t melt in next step

SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 n-well
❑ n-well is formed with diffusion or ion implantation
❑ Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
❑ Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2

n well

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Strip Oxide
❑ Strip off the remaining oxide using HF
❑ Back to bare wafer with n-well
❑ Subsequent steps involve similar series of steps

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Polysilicon
❑ Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
❑ Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Polysilicon Patterning
❑ Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Self-Aligned Process
❑ Use oxide and masking to expose where n+ dopants
should be diffused or implanted
❑ N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 N-diffusion
❑ Pattern oxide and form n+ regions
❑ Self-aligned process where gate blocks diffusion
❑ Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 N-diffusion cont.
❑ Historically dopants were diffused
❑ Usually ion implantation today
❑ But regions are still called diffusion

n+ n+ n+

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 N-diffusion cont.
❑ Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 P-Diffusion
❑ Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Contacts
❑ Now we need to wire together the devices
❑ Cover chip with thick field oxide
❑ Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Metalization
❑ Sputter on aluminum over whole wafer
❑ Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 2. Layout Design Rules
❑ Describes actual layers and geometry on the silicon
substrate to implement a function
❑ Need to define transistors, interconnection
– Transistor widths (for performance)
– Spacing, interconnect widths, to reduce defects, satisfy power
requirements
– Contacts (between poly or active and metal), and vias (between
metal layers)
– Wells and their contacts (to power or ground)
❑ Layout of lower-‐level cells constrained by higher‐level
requirements:
– “floorplanning”
3: CMOS Technology CMOS VLSI Design 4th Ed.
 2. Layout Design Rules
❑ Chips are specified with set of masks
❑ Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
❑ Feature size f = distance between source and drain
– Set by minimum width of polysilicon
❑ Feature size improves 30% every 3 years or so
❑ Normalize for feature size when describing design
rules
❑ Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Simplified Design Rules
❑ Conservative rules to get you started

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Inverter Layout
❑ Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm
long

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Review
1. Which material is for a blank wafer?
2. How many masks is for a basic CMOS inverter?
3. How to create SiO2 layer on the wafer?
4. How to etch the SiO2 layer?
5. How to form the n-well on the p substrate?
6. What is self-aligned process?
7. What is feature size? What is l?
8. What are distances between two metals, two polysilicons, two
metal vias?
9. Explain the following picture:

3: CMOS Technology CMOS VLSI Design 4th Ed.

 CMOS Gate Design
❑ Activity:
– Sketch a 4-input CMOS NOR gate

A
B
C
D
Y

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Complementary CMOS
❑ Complementary CMOS logic gates
– nMOS pull-down network pMOS

– pMOS pull-up network pull-up

network
inputs
– a.k.a. static CMOS output

nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Series and Parallel
❑
a a a a
nMOS: 1 = ON g1
a
0 0 1 1

❑
g2
pMOS: 0 = ON b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON

❑ Series: both must be ON a a a a a

❑ Parallel: either can be ON g1

g2
0

0
0

1
1

0
1

1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

3: CMOS Technology CMOS VLSI Design 4th Ed.

Conduction Complement
❑ Complementary CMOS gates always produce 0 or 1
❑ Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS Y
A
B
❑ Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Compound Gates

A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Example: O3AI
❑

A
B
C D
Y
D
A B C

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Signal Strength
❑ Strength of signal
– How close it approximates ideal voltage source
❑ VDD and GND rails are strongest 1 and 0
❑ nMOS pass strong 0
– But degraded or weak 1
❑ pMOS pass strong 1
– But degraded or weak 0
❑ Thus nMOS are best for pull-down network

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Pass Transistors
❑ Transistors can be used as switches

g=0 Input g = 1 Output

g
s d 0 strong 0
s d g=1 g=1
s d 1 degraded 1

g=0 Input Output

g=0
g s d 0 degraded 0

s d g=1
g=0
s d 1 strong 1

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Transmission Gates
❑ Pass transistors produce degraded outputs
❑ Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Tristates
❑ Tristate buffer produces Z when not enabled

EN
EN A Y
0 0 Z A Y
0 1 Z
1 0 0
EN
1 1 1
A Y

EN

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Nonrestoring Tristate
❑ Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y

EN

A Y

EN
3: CMOS Technology CMOS VLSI Design 4th Ed.
 Tristate Inverter
❑ Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Multiplexers
❑ 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Gate-Level Mux Design
❑ Y = SD1 + SD0 (too many transistors)
❑ How many transistors are needed? 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Transmission Gate Mux
❑ Nonrestoring mux uses two transmission gates
– Only 4 transistors
S

D0
S Y
D1

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Inverting Mux
❑ Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
❑ Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1

3: CMOS Technology CMOS VLSI Design 4th Ed.

 4:1 Multiplexer
❑ 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3

3: CMOS Technology CMOS VLSI Design 4th Ed.

 D Latch
❑ When CLK = 1, latch is transparent
– D flows through to Q like a buffer
❑ When CLK = 0, the latch is opaque
– Q holds its old value independent of D
❑ a.k.a. transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q

3: CMOS Technology CMOS VLSI Design 4th Ed.

 D Latch Design
❑ Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

3: CMOS Technology CMOS VLSI Design 4th Ed.

 D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

3: CMOS Technology CMOS VLSI Design 4th Ed.

 D Flip-flop
❑ When CLK rises, D is copied to Q
❑ At all other times, Q holds its value
❑ a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop

CLK
CLK
D
Flop

D Q
Q

3: CMOS Technology CMOS VLSI Design 4th Ed.

 D Flip-flop Design
❑ Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

3: CMOS Technology CMOS VLSI Design 4th Ed.

 D Flip-flop Operation
QM Q
D

CLK = 0

QM
D Q

CLK = 1

CLK

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Race Condition
❑ Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition

CLK1
CLK1 CLK2 CLK2

Q1
Flop

Flop

Q1 Q2
D
Q2

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Nonoverlapping Clocks
❑ Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
❑ We will use them in this class for safe design
– Industry manages skew more carefully instead
2 1
QM
D Q

2 2 1 1

2 1

1

2

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Gate Layout
❑ Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
❑ Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Example: Inverter

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Example: NAND3
❑ Horizontal N-diffusion and p-diffusion strips
❑ Vertical polysilicon gates
❑ Metal1 VDD rail at top
❑ Metal1 GND rail at bottom
❑ 32 l by 40 l

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Stick Diagrams
❑ Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Wiring Tracks
❑ A wiring track is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
❑ Transistors also consume one wiring track

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Well spacing
❑ Wells must surround transistors by 6 l
– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Area Estimation
❑ Estimate area by counting wiring tracks
– Multiply by 8 to express in l

40 l

32 l

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Example: O3AI
❑ Sketch a stick diagram for O3AI and estimate area
–
Y = ( A+ B + C) D
VDD
A B C D

6 tracks =
48 l
Y

GND
5 tracks =
40 l

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Review

3: CMOS Technology CMOS VLSI Design 4th Ed.