Received 6 June 2020; revised 9 July 2020; accepted 15 July 2020.

Date of publication 20 July 2020;

date of current version 4 August 2020. The review of this article was arranged by Associate Editor Lina He.
Digital Object Identifier 10.1109/OJPEL.2020.3010227

A Single Stage Common Ground Three-Level

PV Inverter With Integrated Power Decoupling
YINGLAI XIA 1 (Member, IEEE), JINIA ROY 2 (Member, IEEE),
AND RAJA AYYANAR 1 (Senior Member, IEEE)
1
Arizona State University, Tempe, AZ 85287 USA
2
National Renewable Energy Laboratory, Golden, CO 80401-3393 USA
CORRESPONDING AUTHOR: YINGLAI XIA (e-mail: yinglaixia@gmail.com)
This work was supported in part by the Office of Energy Efficiency and Renewable Energy and in part by the U.S. Department of Energy with North Carolina State
University, PowerAmerica Institute, under Award DE-EE0006521.

ABSTRACT In this paper, a T-type common ground transformer-less single phase inverter with dynamic
swing of the dc-link voltage is presented for photovoltaic (PV) application. The topology is a combination
of a bi-directional, partial-power-processing boost stage and an asymmetric half-bridge inverter stage along
with a T-branch. It takes advantage of the three-level switching states with reduced voltage stress on the
main switches to achieve lower switching loss and almost one-half the inductor current ripple w.r.t. two level
implementation. The double line frequency power decoupling is addressed by a dynamic dc-link approach,
which allows a large swing of the dc-link to reduce the decoupling capacitor requirement, enabling an all-film
capacitor implementation. This topology also significantly reduces the high-frequency capacitive coupled
ground current by directly connecting the PV negative terminal to the grid neutral. Moreover, an adaptive dc-
link voltage control scheme that optimally changes the average value of the dc-link voltage as the operating
conditions (load and power factor) vary, has been proposed and thoroughly investigated from the perspective
of better utilization of passive components and further reduction of switching losses. A SiC MOSFETs-
based 1 kVA laboratory prototype has been built to validate the converter’s operation at 200 V dc nominal
input and 120 V/60 Hz ac nominal output with a wide range of power factor and load operations. Extensive
experimental results validate the superior performance of the topology with the adaptive dc-link voltage
control implementation showing a peak efficiency of 98.22% and a CEC efficiency of 98.03% at 50 kHz
switching frequency.
INDEX TERMS DC-AC power converters, leakage currents, wide band gap semiconductors.

I. INTRODUCTION three-level inverters have also been considered in the low

Power electronic converters are the key components in a grid
connected photovoltaic (PV) system for interfacing the solar
panels to the grid and extracting the maximum power from the
PV source. The single phase PV systems can be implemented
with or without galvanic isolation, with transformer-less in-
verters gaining larger market share due to their advantages
in terms of reduced cost, higher efficiency, and higher power
density.
State-of-the-art single phase inverters mostly use two-level
topologies. However, multi-level converters offer better power
density, higher efficiency, and improved harmonic perfor-
mance which have already proven beneficial in high volt-
age and high power applications [1]. In recent years, the
and medium voltage domain due to their improved harmonic
and efficiency performances and reduced ac filter components
compared to their two-level counterparts [2]. Among them
the T-type topology stands out due to its advantages of lower
conduction and switching loss and lower passive and active
component count over the nuetral point clamped (NPC) ap-
proach [3].
Recently T-type inverter has been studied for the grid-
tied application [4]. It has an additional bi-directional switch
connected between the neutral point and the switching pole.
Though the voltage rating of the main switches is not re-
duced, their commutating voltage is halved, thus decreas-
ing their switching loss. Also through improved modulation

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VOLUME 1, 2020 227
XIA ET AL.: SINGLE STAGE COMMON GROUND THREE-LEVEL PV INVERTER WITH INTEGRATED POWER DECOUPLING
techniques, the effective switching frequency can be reduced
while still maintaining the output harmonic performance same
as the two-level implementation, thereby further lowering the
switching loss. The commutation voltage and the voltage
stress on the bi-directional T-branch switches are both half
the dc-link so the associated losses with T-branch are not
significant.
In the conventional T-type inverter, the grid neutral is con-
nected to the mid-point of the half-bridge (HB) capacitors.
It is an attractive feature for applications in transforme-less
PV inverters. The HB derived structure ensures the mitigation
of the capacitive coupled ground current through the stray
capacitance between the PV terminals and ground (and there-
fore grid neutral) as a low-frequency (typically fundamental
frequency) or constant potential of the PV negative terminal
relative to the grid neutral is maintained. However, T-type
inverter has voltage balancing challenge and one of the mod-
ulation freedom of the inverter stage is lost as it is employed
for voltage balancing of HB capacitors.
The other challenge associated with single phase PV appli-
cation (which is independent of whether a two-level or three-
level topology is used) is addressing the double line frequency
power ripple, which is a common issue for all the single phase
inverters and rectifiers [5], [6]. Large electrolytic capacitors
(e-caps) are predominantly used for decoupling purposes, but
they have known failure mechanisms that lead to reliability
challenges to the PV inverter system. Alternatively, by de-
creasing the capacitance requirement through active power
decoupling techniques, e-caps can be replaced with highly re-
liable film capacitors as has been reviewed in [7], [8]. This can
be achieved by either adding an auxiliary power decoupling
stage connected in series [9] or parallel [10] to the main in-
verter, or allowing higher ripple on the main dc-link [11], [12].
However, in the later case the control needs to be properly
designed such that the ripple on the dc-link does not impact
the output grid current [13].
With the goal of achieving a simple, reliable, and effi-
cient PV system, in this paper, a T-type common ground
voltage swing inverter is presented for transformer-less PV
inverter application. The ac neutral is directly connected to the
PV negative terminal, thus completely eliminating the high-
frequency capacitive coupled common-mode ground current.
This is commonly termed as the doubly grounded or common
ground structure as adopted in a few recent works both related
to string inverter [14]–[16] as well as microinverter [17], [18]
applications. The presented circuit is a topological enhance-
ment to [13] leading to a significant improvement in the con-
verter efficiency. Unlike the conventional T-type converters, it
does not pose any HB voltage balancing issue, as the voltage
is inherently balanced without losing any modulation freedom
in the inverter stage. It integrates a bi-directional boost and
HB stages coupled with a T-branch. A large voltage swing
of the dc-link capacitor address the power decoupling with
a reduced capacitor value of only 55 μF with peak voltage
of 500 V leading to a μF*kV/kW metric [13] of 27.5. The
three-level waveform obtained by the implementation of the
228
bidirectional T-branch helps in significant reduction in the
size of the filter inductor (or reduction in THD for similar
inductors). This paper presents an in-depth analysis of the
T-type common ground voltage swing inverter topology as
applicable to the single-phase PV inverters with significant
performance gains, analytical design complexity, and wider
range of specifications, especially in terms of power factor
(pf) operation in comparison to [19]. To satisfy the emerging
grid support features, the design of the optimal switching se-
quences for the converter has also been explored considering
a wide range of power factor (pf), with extensive modulation
scheme analysis for both unity pf and non-unity pf.
Additionally, an adaptive dc-link voltage control scheme
is studied from the perspective of the dynamic dc-link active
power decoupling and thus maximizing the utilization of the
passive components (effectively designed for the worst case
operating condition) over the entire operating range to im-
prove on the overall converter efficiency performance, which
was not previously considered in [19]. This adaptive dc-link
scheme has similar concept to [20], [21], however, as they
are implemented in ac-dc application these consider only the
variation in active power. The range of different operating
conditions include the variation in the input voltage, varia-
tion in output power, and 0.7 leading pf to 0.7 lagging pf
for the output power accounting for reactive power support.
Further, [20], [21] consider a two-stage topology (an ac-dc
stage followed by dc-dc stage) to implement the variable dc-
link and thus is straightforward to design the controller. Our
proposed converter is a single stage (a boost stage and a HB
inverter stage parallelly processing power for both the power
decoupling and dc-ac conversion) and thus the implementa-
tion of the adaptive dc-link controller is more complicated.
The rest of the paper is organized as follows. Section II
presents the basic converter topology, its operating princi-
ples, and T-type modulation strategy. The performance of the
converter is compared with the state-of-the-art PV inverters
in the next Section III. A brief discussion on component
selection and the common mode analysis for this common
ground T-type inverter is provided in Section IV. The follow-
ing Section V discusses the simulation results including the
double line frequency power decoupling with the adaptive dc-
link voltage control requirement and implementation. A brief
discussion on the controller design is given in Section VI.
Finally, the experimental results for the laboratory prototype
of transformer-less string inverter with Silicon Carbide (SiC)
devices are provided in Section VII.
II. CIRCUIT CONFIGURATION
Fig. 1 shows the topology of the T-type common ground
voltage swing inverter for transformer-less string inverter ap-
plication. The converter has an input boost stage followed by
an asymmetric HB inverter stage coupled with a bi-directional
T-branch. As opposed to the conventional boost converter
which shares a common negative, here the boost input and
output shares a common positive terminal. The bi-directional
boost converter comprises of inductor Lb , dc-link capacitor
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FIGURE 1. T-type common ground voltage swing inverter for
transformer-less PV application. CPV shown correspond to the parasitic
capacitances between the PV terminals and ground.
Clink , and switches Q1 and Q2 . The three-level T-type inverter
stage is comprised of two main switches Q3 and Q4 , with an
additional bi-directional T-branch comprising of switches Q5
and Q6 which switches at line frequency for unity pf (UPF)
operation, thus having limited contribution to the converter’s
switching loss.
The grid neutral is connected directly to the PV nega-
tive terminal, commonly referred to as a doubly grounded
or common ground structure, thus inherently eliminating the
common-mode, high-frequency ground currents through the
PV module capacitance, which is a common problem in most
of the transformer-less inverters. A dynamic dc-link approach
provides the 120 Hz power decoupling as discussed in a later
section. For grid connected implementation LCL (Linv , Cg, Lg)
filters are considered. In Fig. 1 iinv is the current through Linv ,
and ig is the current through Lg, which is also the grid current.
A. OPERATING PRINCIPLES
The boost stage steps up the input PV voltage vin to a higher
nominal dc voltage vlink of around 400 V. It is particularly
designed to have a large 120 Hz swing of around 140 V peak-
peak. The combination of higher nominal voltage of vlink and
a very large swing is used to address the power decoupling
with a greatly minimized dc-link capacitance.
The input voltage vin and the difference voltage vlink − vin
constitute two asymmetric voltage levels of the HB. db (gen-
erates gate signals for Q1 and Q2 ) and dinv (generates gate
signals for the rest of the switches) are respectively the boost
and inverter stage duty ratio. It is to be noted that being a HB
derived topology, compared to the traditional full bridge (FB)
inverter, all the switches Q1 , Q2 , Q3 , Q4 need to be rated at
higher voltage vlink . However, w.r.t. the conventional HB in-
verter the switch voltage rating of this topology is comparable.
In every grid cycle the T-type asymmetric HB inverter has
three operating states - POS, ZERO, and NEG as shown in
Table I. The pole voltage VMN with respect to a neutral-point
voltage N can be one of vin , 0, or vin − vlink according to
the operating state. The first operating state POS is generated
with Q3 being ON and Q4 and T-branch being OFF with pole
voltage being vin . The operating state ZERO corresponds to
both Q3 and Q4 being OFF and T-branch being ON with pole
voltage being 0. Essentially, ZERO state is generated with
VOLUME 1, 2020
TABLE I Gate Signal & Operating States of Inverter Stage∗
*ON state of T-branch correspond to one of three switching patterns de-
pending on the current direction - both Q5 and Q6 ON, Q5 ON and Q6
OFF, or Q5 OFF and Q6 ON.
both Q3 and Q4 being OFF and either or both of Q5 and Q6
being ON, depending on the voltage polarity. NEG state has
a pole voltage of vin − vlink with Q4 being ON and Q3 and
T-branch being OFF.
Different combinations of these three operating states gen-
erate the output grid voltage at different operating pf. The
corresponding modulation strategy is discussed in the next
section. The operating states of the presented T-Type inverter
stage is shown in Fig. 2 for UPF operation where the unhigh-
lighted part in gray color denotes the devices with OFF gate
signal. When switching, the switch voltage stress on Q3 and
Q4 is around half of the dc-link (vin for Q3 and vlink − vin
for Q4 ). But when they are not switching, the voltage across
them changes between vlink and vin for Q3 and between vlink
and vlink − vin for Q4 . This is shown in Fig. 3 for both the
switching transition between POS and ZERO states (Fig. 3(a)
and between NEG and ZERO states (Fig. 3(b).
Thus though the commutation voltage and hence the
switching loss are reduced for Q3 and Q4 , the absolute stress
on them is still the full dc-link voltage. On the other hand,
the commutation voltage and the absolute switch stress on
Q5 and Q6 are both half the dc-link voltage. However, the
main disadvantage of T-type implementation with the conven-
tional modulation scheme (i.e., the T-branch switching at line
frequency) is the additional conduction loss in the T-branch
body diode, as any one of the two diodes of Q5 or Q6 always
conducts.
B. MODULATION SCHEME
The modulation of the boost stage is straightforward with top
switch Q1 complementary to the bottom one Q2 irrespective
of the operating pf. However, the scheme is complex for the
inverter stage. Table II gives the modulation strategy for the
HB inverter stage with the T-branch for different pf opera-
tions. Scheme I and II respectively correspond to the T-branch
switching at line and carrier frequency.
For UPF operation, the modulation scheme is simple.
The T-branch switches at line frequency, while the effective
switching frequency of Q3 and Q4 is half of the carrier signal
frequency as they are OFF for half the grid cycle as shown in
Fig. 4(a). During the positive half cycle (dinv > 0), operating
states POS and ZERO (Q4 and Q6 being always OFF, Q5 being
always ON, and only Q3 switching) are used to modulate the
output (interval A in Fig. 4(a). And in the negative half cycle
(dinv < 0), operating states NEG and ZERO (Q3 and Q5 being
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FIGURE 2. Operating states of the T-Type half-bridge inverter stage for the topology at UPF condition showing the current path while it switches between
(a) POS and (b) ZERO in positive half cycle and between (c) NEG and (d) ZERO in negative half cycle corresponding to modulation Scheme I.

TABLE II Modulation Scheme of the T-Type Inverter Stage for the Converter ∗

*The gate drives for Q1 and Q2 are similar to a standard boost converter regulating its average output voltage, and hence is not elaborated here. The gate drive is not synchronized
to that of the inverter stage and is independent.

to generate NEG or ZERO states (interval D in Fig. 4(b).

FIGURE 3. Switch voltage stress for all the switches in the inverter stage
when switching between (a) POS and ZERO states, (b) NEG and ZERO
states.
always OFF, Q6 being always ON, and only Q4 switching) are
used to modulate the output waveform (interval C in Fig. 4(a).
On the contrary for non-UPF operation, the modulation is
more involved as it is dependent on the switch pole current
iinv direction [see Fig. 4(b)]. For iinv > 0, modulation scheme
is same as with p f = 1 in the positive half cycle (interval A
in Fig. 4(b), and for iinv < 0 modulation scheme is same as
with p f = 1 in the negative half cycle (interval C in Fig. 4(b).
But in the positive half cycle, for iinv < 0, Q4 and Q5 are OFF,
Q6 is ON, and Q3 switches to generate POS or ZERO states
(interval B in Fig. 4(b). And in the negative half cycle, for
iinv > 0, Q3 and Q6 are OFF, Q5 is ON, and Q4 switches
Here, the T-branch switches at the line frequency as shown in
Scheme I of Table II. The effective switching frequency of Q3
and Q4 is remains same as before. But this approach is very
sensitive to iinv detection, and if not properly implemented,
can lead to shoot-through of the HB inverter leg.
Further for non-UPF operation, this disadvantage can be
addressed by switching the T-branch throughout at the carrier
frequency as shown in scheme II of Table II with the T-branch
(Q5 and Q6 ) having the same gate signal. For dinv > 0, Q3
switches complementary to the T-branch, while for dinv < 0,
Q4 switches complementary to the T-branch as shown in
Fig. 4(c). This results in increased turn-on loss of only one
of the T-branch switches, since depending on the current di-
rection either Q5 or Q6 will have soft turn-ON. Also in this
scheme the conduction loss associated with the T-branch body
diode occurs only during dead-time transition, and thus car-
rier frequency switching of T-branch would not significantly
impact the overall converter efficiency. Table III compares
the converter’s performance in terms of the inductor current
ripple, diode conduction, control complexity, and power loss
for both the switching schemes.
III. TOPOLOGY COMPARISON
A. COMPARISON WITH CONVENTIONAL BOOST
CASCADED T-TYPE INVERTER
The presented topology is very different from the conventional
boost cascaded T-type inverter topology shown in Fig. 5. In
this topology, the boost stage is an integral part of the power

230 VOLUME 1, 2020

FIGURE 4. Switching signals for the T-branch and the half-bridge inverter stage for (a) UPF operation, (b) non-UPF operation in scheme I, (c) non-UPF
operation in scheme II.
TABLE III Modulation Scheme Comparison
FIGURE 5. Conventional boost cascaded T-type inverter topology.
decoupling which operates in parallel to the HB inverter. The
basic differences between the presented and conventional in-
verter shown in Fig. 5 are:
r Topology in Fig. 5 is not common ground, M and N are
not connected. M is the negative terminal of the grid,
while N is the negative terminal of the PV panel.
r Topology in Fig. 5 needs additional two capacitors C1
and C2 . It also has voltage balancing challenge and the
one of the modulation freedom of the T-type stage is
lost as it needs to be used to maintain voltage balancing
between VC1 and VC2 .
r Topology in Fig. 5 conventionally has no dynamic power
decoupling, Vlink is dc with very small ripple and Clink
is very large. However, Clink can be made smaller by
accommodating larger ripple on dc-link, but it entails
additional considerations such as the minimum of the dc-
link to be higher than the twice of the output ac voltage,
VOLUME 1, 2020
TABLE IV Converter Specification
higher peak of Vlink requiring switching devices with
higher voltage rating, and voltage balancing between VC1
and VC2 will be more complex.
r In the topology of Fig. 5 the boost stage processes the
complete, rated power, whereas in this topology part
of the power flows directly from the PV panels to the
grid through the HB dc-ac stage, without having to go
through the boost stage.
r However, one advantage that the topology of Fig. 5 has
over the T-type voltage swing inverter is wider range
allowable in the input voltage due to the front end boost
stage.
B. PERFORMANCE COMPARATIVE SUMMARY
Table IV shows the specification of the converter. In Table V
this topology is compared with the state-of-the-art inverters
implemented for PV application in terms of the number of
active components, power decoupling metric, output filter re-
quirement, peak efficiency, and common grounding capabil-
ity. The average
 device voltage stress normalized by the input
voltage [ ni=1 Vi /(nVin ), where Vi is the voltage stress of the
ith device and n is the total number of devices in converter] is
also compared.
Similar to the conventional FB inverter and its derivatives
such as H5, H6 and HERIC, the presented topology with
the integrated power decoupling also has the constraint that
the input voltage should be higher than the peak of the grid
voltage to avoid over-modulation. An additional boost stage,
or a partial power processing stage that adds a series voltage
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XIA ET AL.: SINGLE STAGE COMMON GROUND THREE-LEVEL PV INVERTER WITH INTEGRATED POWER DECOUPLING
TABLE V Performance Comparisons With Various Other Topologies
NR∗ : not reported
to the input will be needed for applications where the above
constraint cannot be met. Moreover, unlike the conventional
topologies, the T-type voltage swing inverter has an upper
limit on vin for a given vlink given by the instantaneous re-
quirement vlink − vin > |vg|, which can also be met by the use
of the boost or the partial power processing stage mentioned
above.
From Table V it can be further seen that the T-type voltage
swing inverter offers a competitive efficiency and common
grounding capability while using decoupling capacitor of only
55 μF with peak voltage of 500 V leading to a μF*kV/kW
metric [13] of 27.5. The number of active and passive compo-
nents is also comparable to the other topologies considered.
IV. DESIGN PRINCIPLE
A. COMPONENT SELECTION
Clink is designed based on the requirement to support the
120 Hz power pulsation under the worst case operating condi-
tion at leading pf as given by (1). where, Vg and Ig are the grid
voltage and current peak, Vavg is the dc-link average voltage,
2Vr is the peak-peak dc-link ripple voltage varying at double
line frequency, and Sg is the grid VA.
VgIg Sg
Clink = = (1)
4ωVavgVr 2ωVavgVr
232
Finally the capacitance is optimized for the range of operating
condition as given in Table IV with an objective of minimizing
the capacitance volume as outlined in [13].
As the 120 Hz ripple is controlled to be present only in
the dc-link capacitor, Cin is designed based on the maximum
allowable high-frequency voltage ripple at the input. The
boost inductor (Lb ) is designed based on the allowed current
ripple of 20% the nominal value. Conventional LCL design
approach [31] is used to design the values of inverter output
filter (Linv , Cg, Lg).
B. COMMON MODE BEHAVIOR
Fig. 6 shows the equivalent circuit of the T-type common
ground voltage swing inverter for analyzing common-mode
voltage and leakage current. In this model the parasitic ca-
pacitance CPV is equally distributed at the positive and the
negative terminal of the PV module. It can be seen that at
the negative terminal it is short-circuited by the common ac
and dc ground leading to (2). This ideally eliminates the
common-mode current icm1 . Further, the positive terminal is
connected to the grid neutral through the parallel combination
of the parasitic capacitance and the input capacitance Cin . The
typical value of CPV is 60-110 nF/kW in standard PV modules
and 100-160 nF/kW in thin-film PV modules, which is much
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FIGURE 6. Equivalent circuit of the T-type common ground voltage swing
inverter for analyzing common-mode voltage and leakage current.
less than Cin . Thus icm2 is negligibly small as iripple is mostly
bypassed through Cin . In practice due to the non-idealities
of the components, both icm1 and icm2 are non-zero but very
small.
vcm1 = 0; vcm2 = vin
V. ADAPTIVE DC-LINK VOLTAGE CONTROL
The instantaneous values of each of the HB voltage levels (vin
and vlink − vin ) needs to satisfy the constraint in (3) at any
operating pf, where vg = Vg sin(ωt ). These two constraints
place a limit on the minimum value of the PV voltage and the
maximum voltage swing allowed at the dc-link. This ensures
that the HB inverter stage does not operate at modulation
index more than 1, which would otherwise distort the output
waveforms and impact the total harmonic distortion (THD).
 different minimum Vavg is required to satisfy (5). However,
vin > vg if vg ≥ 0
(3)
vlink − vin > |vg| if vg < 0
As vin has no double line frequency ripple, the constraint in (3)
is instantaneously satisfied by ensuring the voltage margin, Vm
[given in (4)] is greater than 0 only in the negative half of the
grid cycle.
Vm = vlink − vin − |vg| > 0
It is worth noting that to have an optimal dc-link capacitance
value, it is enough to satisfy (4) instantaneously, rather than
keeping the Vm always higher than 0 [13]. Again Vm is a
function of the input voltage, operating pf, and VA of the
inverter, which leaves room for improving converter efficiency
by the adaptive dc-link voltage control, as discussed shortly.
A. DEPENDENCE OF THE VOLTAGE MARGIN ON
OPERATING PARAMETERS
The dependence of Vm on the operating kVA is clear from
(1) and (4), where with a fixed dc-link capacitance Clink , Vavg
and Vr , and thus Vm are dependent on Sg. Also its dependence
on vin is obvious from its definition in (4). Finally, the de-
pendence of Vm on operating pf can be studied from (5). As
discussed already, with ideally no ripple on vin , (3) can be
modified for only the negative grid cycle, and by substituting
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for Vr from (1), (5) is obtained.
Sg sin(2ωt + θ )
Vavg + − vin > |Vg sin(ωt )| (5)
2ωVavgClink
Further, pf dependence can be analysed from the steady state
simulation results given in Fig. 7. It gives the dc-link voltage,
input voltage, the difference of dc-link and input voltages
along with grid current and grid voltage waveforms corre-
sponding to different operating pf - unity, 0.7 lagging, and 0.7
leading. Fig. 7(c) shows that the leading pf gives the worst
voltage margin [13] and thus needs a higher dc-link mean,
whereas, lagging pf [see Fig. 7(b)] gives the best margin
requiring minimum dc-link mean. It has been accomplished
by the adaptive dc-link scheme with the voltage margin Vm
always being barely around 20 V at the critical point (Fig. 7).
It can be further seen that the constraints given in (3) have
been satisfied in all three cases.
B. ADAPTIVE DC-LINK SCHEME
(2)
With the dynamic dc-link approach, once the passive compo-
nents are designed for the worst operating condition (leading
pf at full rated VA), the dc-link average Vavg can be adjusted
at other operating conditions instead of a fixed value. As over
a grid cycle, the semiconductor switching loss is dependent
on Vavg, it is beneficial to operate the inverter at the minimum
dc-link average (implying lower switch voltage stress), which
can be decided based on the constraint in (4). Also with lower
Vavg, the inductor current ripple can be decreased accounting
for lower high frequency copper and core loss.
It can be seen that for different values of Sg, vin , and p f ,
deriving the analytical solutions of the optimal Vavg for differ-
ent Sg, vin , and p f values is a complex assignment. Therefore,
numerical method is used to find the minimum Vavg in MAT-
LAB by sweeping the dc-link voltage average value over the
specified operating range. 3-D plots showing the dependence
of minimum Vavg required are given in Fig. 8 for various
combination of Sg (swept from 0 to 1000 VA), vin (swept
(4) from 180 to 260 V), and p f angle (swept from −45◦ to 45◦
corresponding to 0.7 lagging and 0.7 leading pf respectively).
Implementation of the adaptive dc-link scheme does not
interfere with the basic inverter control design. Instead of
providing a constant dc-link average as conventionally done,
the Vavg is decided based on the converter’s operating point
and provided as an input to the dc-link controller. To save the
computational time and resource, for different combinations
of Sg, vin , and p f , Vavg is computed off-line apriori, and is
saved in an LUT for controller implementation.
VI. CONTROLLER IMPLEMENTATION
For the PV inverter operation in grid connected mode, the
objective of the controller is to control the input voltage ac-
cording to the MPPT voltage reference which fixes the input
power, control the grid current depending on the input power
(with the fixed grid voltage), and control the average of the
dc-link voltage. Without the input PV panel, the input of the
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FIGURE 7. Steady state waveforms at 1 kVA showing dc-link voltage, input voltage, grid voltage, grid current, and the difference of the dc-link voltage and
input voltage at (a) unity pf, (b) 0.7 lagging pf, (c) 0.7 leading pf operations highlighting the voltage margin of 20 V fixed for each operating point by
implementation of adaptive dc-link voltage control scheme.

FIGURE 8. Relationship between the minimum Vavg required to satisfy (5) for various combinations of Sg , vin , and pf (a) for different Sg and pf at
vin = 190 V, (b) for different vin and Sg at pf angle = 0◦ (UPF), (c) for different vin and pf at Sg = 1000 VA.

FIGURE 9. Controller block diagram of T-type common ground voltage

swing inverter.

FIGURE 10. 1 kVA experimental prototype of T-type common ground

converter comes from a dc source in series with a resistor
to closely mimic the PV characteristic, and the input voltage
reference is manually provided.
Fig. 9 shows the overall controller block diagram with the
MPPT control block. The objective of the dc-dc stage con-
troller is to regulate the input voltage such that vin is free
of any double line frequency ripple, which would otherwise
disrupt the MPPT efficiency when connected across the PV
source. To ensure this, input voltage controller has a high
bandwidth to generate the boost stage duty db as shown.
voltage swing inverter for transformer-less PV application.
Both dc-link and inverter control loops in the dc-ac stage
employ simple PI controllers with appropriate feed forward
terms added as shown. The dc-link control loop regulates the
average of the dc-link voltage to a reference value generated
by the adaptive dc-link control scheme. A first-order low-
pass-filter (LPF) with cutoff frequency of 10 Hz is used to
filter out the 120 Hz component in the dc-link voltage before

234 VOLUME 1, 2020

FIGURE 11. Steady state waveforms at 1 kVA, UPF operation with 180 V input, 410 V DC-link average, and 120 V/60 Hz output (time : 5 ms/div). (a) Input
and output voltage and current (voltage: 100 V/div, ig : 20 A/div), (b) Magnified input voltage and converter currents (vin : 10 V/div, iin : 2 A/div, ib , iinv :
20 A/div), (c) Cycle-by-cycle averaged duty ratios of the boost and inverter stages (ig : 10 A/div).
TABLE VI Component Details
comparing it with the reference. It is to be noted that due to a
lower bandwidth of the dc-link controller, the response of the
dc-link to the transients is slower.
The output current controller is designed to control the
grid current with the current peak reference derived from the
dc-link voltage control loop and the phase and frequency of
the sinusoidal waveform determined by a phase-locked loop
(PLL) and an external p f command. The output of the con-
troller decides the inverter stage duty dinv , which further gen-
erates the gate signals for Q3 to Q6 with appropriate dead-time
based on the algorithm discussed in Section II.
VII. HARDWARE PROTOTYPE AND EXPERIMENTAL
RESULTS
A hardware prototype rated at 1 kVA has been built to vali-
date the performance features of the T-type common ground
voltage swing inverter for transformer-less PV application as
shown in Fig. 10 (the overall converter size is 10.93 inch x
5.52 inch x 1.38 inch including the heat-sink). The input is
derived from a dc source of 210 V in series with a 6.5 
resistor to mimic a PV panel input. LeCroy 6200 A oscillo-
scope is used to capture the relevant waveforms and power
analyzer YOKOGAWA WT3000 is used to measure the effi-
ciency. Table VI gives the detail of all the active and passive
components. CREE C2M0040120D wide bandgap SiC MOS-
FETs are used for all the switches including the T-branch. The
controller is implemented in a customized DSP board built
with TMS320F28335.
A. STEADY STATE EXPERIMENTAL RESULTS
The results represented in this section correspond to 1 kVA,
UPF operation at steady state with specifications given in
VOLUME 1, 2020
FIGURE 12. Steady state device drain-to-source voltage for T-type HB
inverter stage at 1 kVA, UPF operation (voltage: 200 V/div, time : 5 ms/div).
Table IV. Fig. 11(a) shows the experimental results of input
voltage vin , grid voltage vg, output current ig, dc-link voltage
vlink , and the difference voltage vlink − vin . The grid current
has a THD of 2.3% calculated by using fast Fourier transform
(FFT) in MATLAB on the measured ig data. Fig. 11(b) shows
the magnified input voltage and different converter currents -
input, boost stage inductor, and inverter stage inductor (iin , ib ,
and iinv respectively).
Fig. 11(c) shows the duty ratios of the boost stage and
the HB inverter stage. The T-branch stage switches at line
frequency, and hence, is not shown here. The duty ratio is ob-
tained by cycle-by-cycle averaging of measured gate voltage
Vgs of the two stages. As Vgs is 20 V when turned ON and
-6 V when turned OFF, the 0 and 1 of the duty ratio can be
established from Fig. 11(c) accordingly. It is to be noted that,
dQ3 is purely sinusoidal as it modulates the input voltage vin
with no ripple component to generate positive half of vg. On
the contrary, dQ4 which modulates vlink − vin , has double line
frequency component to mitigate the influence of large 120 Hz
dc-link ripple on the grid output. Also in order to regulate the
input voltage to be a pure dc, the boost duty ratio (dQ1 = db )
should contain 120 Hz component as shown.
Fig. 12 shows the drain-to-source voltage of the MOSFETs
in the HB inverter stage with the T-branch (Vds_Q3 , Vds_Q4 ,
Vds_Q5 , and Vds_Q6 ). As Q3 modulates the input voltage vin
(which has negligibly small ripple component) to generate
positive half of vg, Vds_Q3 profile is a constant while it is
235
XIA ET AL.: SINGLE STAGE COMMON GROUND THREE-LEVEL PV INVERTER WITH INTEGRATED POWER DECOUPLING
FIGURE 13. Dynamic response of the converter with the adaptive dc-link control implementation, (a) 500 W to 1 kW step-up load, (b) step change from
0.7 pf leading to 0.7 pf lagging at 1 kVA, (c) ramp change of input voltage from 205 V to 190 V (voltage: 100 V/div, current: 20 A/div, time : 20 ms/div).
switching (interval A). On the contrary, as Q4 modulates
vlink − vin which has double line frequency component to
mitigate the influence of dc-link ripple on the grid output,
Vds_Q3 profile also contains 120 Hz ripple while it is switching
(interval B). Profiles of Vds_Q5 and Vds_Q6 can be similarly
explained.
B. ADAPTIVE DC-LINK WAVEFORMS
Fig. 13(a) shows the transient waveforms of the inverter in
the grid-connected configuration when the active-power com-
mand is given a step change from 500 W to 1 kW with
vin = 190 V, at UPF operation, i.e., p f = 0◦ . As can be
seen, average value of vlink changes from 389 V to 409 V
dynamically, as calculated from the adaptive dc-link control
block. Fig. 13(b) shows the transient waveforms of the inverter
when the pf command has a step change from 0.7 leading to
0.7 lagging, i.e., p f angle changing from 45◦ to −45◦ with
vin = 190 V at 1 kVA. With the implementation of the adap-
tive dc-link scheme, Vavg is noticed to change from 431 V to
377 V dynamically. It is also seen that vlink − vin waveform is
just above the instantaneous vg at the critical point as expected
with adaptive dc-link implementation.
Finally, Fig. 13(c) gives the transient waveforms of the
inverter when the input voltage has a ramp change from 205 V
to 190 V at 1 kVA UPF operation. With the the adaptive
dc-link scheme, Vavg is noticed to change from 435 V to 420 V
dynamically. Further, no change in the grid current waveforms
is noticed proving good performance of the controller.
C. EFFICIENCY
Fig. 14 shows the efficiency measured at UPF for different
power levels based on California Energy Commission (CEC)
requirement for PV inverters. The weighted CEC efficiency
at switching frequency of 50 kHz is obtained to be 98.03%
and a peak of 98.22%, without considering the controller and
auxiliary power consumption including the power for gate
drivers, DSP controller, and other ICs which is around 2.7 W.
It is to be noted that for UPF operation the efficiency is
measured while switching the T-branch (Q5 and Q6 ) at line
frequency as suggested in Table II. However, for non-UPF
operations, Q5 and Q6 will switch at carrier frequency as given
in Table II. In order to study the impact of this additional
236
FIGURE 14. Efficiency of T-type common ground voltage swing inverter
with adaptive dc-link implemented.
switching specifically, the converter was operated with Q5
and Q6 operating at switching frequency at UPF and the peak
efficiency obtained under this scenario was 97.83% at 50 kHz
switching frequency. The converter efficiency for 0.7 lagging
pf at 1 kVA is 96.82%, while that for 0.7 leading pf at 1 kVA
is 96.35%.
VIII. CONCLUSION
This paper proposes a high-efficiency novel T-type common
ground transformer-less single phase inverter with dynamic
swing of the dc-link voltage which addresses the main chal-
lenges of transformer-less inverters. The presented converter
topology is a combination of a bi-directional boost and an
asymmetric HB stage coupled with a bi-directional T-branch
to reduce the switching loss and minimize the inductor current
ripple of the HB inverter stage. The capacitance required for
power decoupling is significantly reduced to 55 μF/kW at a
peak of 500 V dc-link through an active power decoupling
scheme with a large swing of the dc-link voltage. Extensive
experimental results from the 1 kVA SiC MOSFETs-based
laboratory prototype are presented to validate the concept,
design, and superior performance of the topology. Moreover,
the adaptive dc-link voltage control is implemented leading to
a better utilization of the passive components and switching
scheme under different operating (load and pf) conditions
which finally results in a peak efficiency of 98.22% and a
CEC efficiency of 98.03% at 50 kHz switching frequency in
the experimental prototype.
VOLUME 1, 2020
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