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ZZZ
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PCB
Part Number = DAZ0K400100

Compal Confidential
2 2

K73TA Schematics Document


AMD Sabine
APU Llano / Hudson M3 / Whistler
DIS only

3 3

2011-03-08
LA-7553P REV: 0.2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 1 of 51
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A B C D E

Compal Confidential
Model Name : QBL70

1
VRAM 512M/1G/2G
64M16/128M16 x 8
page 23, 24
Sabine 1

DDR3
Thermal Sensor ATI Vancuver Whistler GFX x 8 Gen2
ADM1032
page 19
uFCBGA-962 GFX x 4
AMD FS1 APU Memory BUS(DDR3)
Page 18~22 204pin DDRIII-SO-DIMM X2
APU HDMI Dual Channel
(UMA / Muxless) Llano BANK 0, 1, 2, 3 Page 11,12
1.5V DDRIII 800~1333MHz
DP x1 (DP0 TXP/N0)
uPGA-722 Package
HDMI Conn.
page 28
Travis LVDS Page 6~10
LVDS
2 LVDS Conn. Translator DP x 4 2

page 26 P_GPP x 2
Reserve eDP GEN1 (DP1 TXP/N 0~4) UMI
page 27 USB2 USB2 USB2 x 2 CMOS Mini Card Card Reader
(LS-7323P) Camera RTS5137
(with BT)
page 30 page 30 page 33 page 27 page 35 page 34

CRT Conn. FCH CRT (VGA DAC) Port 0 Port 1 Port 5 Port2 Port 3 Port 4
page 27 FCH USB
3.3V 48MHz
GPP0 Hudson-M2/M3
HD Audio 3.3V 24.576MHz/48Mhz
LAN(GbE) uFCBGA-656
RTL8111E GPP0
Page 13~17 S-ATA Gen2
page 31
MINI Card 1 LPC BUS port 0 port 2 port 1
3
WLAN 3

page 35 SATA HDD1 SATA HDD2


RJ45 ODD HDA Codec
page 31
Conn. Conn. ALC269 page
page 29 page 29 page 29 33

ENE KB930
page 32

Touch Pad Int.KBD


LED External board page 37 page 37
page 35
LS-7324P
page 36
RTC CKT. HDD/B
4
page 13 4

LS-7325P BIOS ROM


page 36
DC/DC Power/B
Interface CKT.page SYS BIOS (2M)
38 page 15 Security Classification Compal Secret Data Compal Electronics, Inc.
2010/08/04 2010/08/04 Title
LS-7323P Issued Date Deciphered Date
Block Diagrams
Power Circuit Audio BD EC BIOS (128K) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
page 39~48 page 33 page 32 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
QBL70 LA-7553P 0.22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 2 of 51
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5 4 3 2 1

CLOCK DISTRIBUTION DISPLAY DISTRIBUTION


: LVDS PATH

: APU HDMI PATH


LVDS CONN
B_SODIMM

D A_SODIMM D

TXOUT[0:2]+/-
TXCLK+/-
TZOUT[0:2]+/-
TZCLK+/-
I2CC_SCL/DA
AMD R
ATI VGA
MEM_MB_CLK7_P/N
MEM_MB_CLK1_P/N

MEM_MA_CLK7_P/N
MEM_MA_CLK1_P/N
1066~1600MHz

1066~1600MHz

Whistler

APU_TXOUT[0:2]+/-
APU_TXOUT_CLK+/-
CLK_PEG_VGAP/N APU_TZOUT[0:2]+/-
APU_TZOUT_CLK+/-
100MHz APU_LVDS_CLK/DATA

APU_DISP_CLKP/N
C
AMD 100MHz AMD LVDS_OUT C

RTD2132
CPU FS1 SOCKET
FCH DP_IN
APU_CLKP/N Hudson-M2/M3
100MHz Internal CLK GEN

DP0_AUX GPP_CLK
100MHz

LVDS Transtator 32.768KHz 25MHz

DP0_TXP/N[0:1]
DP0_AUXP/N

B B
GPP1 GPP0 DP0
WLAN GbE LAN APU VGA
Mini PCI Socket PCIE_GFX[0:7] C PCIE_GFX[0:7]
DP1 PCIE_GFX[12:15] C

25MHz

FCH

LS
R
A A

CRT CONN HDMI CONN

Security Classification Compal Secret Data


Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
CLOCK / DISPLAY DISTRIBUTION
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom QBL70 LA-7553P 0.22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 3 of 51
5 4 3 2 1
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Voltage Rails
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF

1
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 1

+CPU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF


S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.0VSG 1.0V switched power rail for VGA ON OFF OFF
+1.1ALW 1.1V switched power rail for FCH ON ON ON* Board ID / SKU ID Table for AD channel
+1.1VS 1.1V switched power rail for FCH ON OFF OFF Vcc 3.3V +/- 5%
+1.2VS 1.2V switched power rail for APU ON OFF OFF Ra/Rc/Re 100K +/- 5% BOARD ID Table
+1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max Board ID PCB Revision
+1.5VS 1.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V 0 NA
+1.8VSG 1.8V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 1 P5WS5
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V 2 P5WH5
+3VALW 3.3V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V 3 P7YE5
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V 4 P7YS5
+3VS 3.3V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V 5 NA
+5VALW 5V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V 6 NA
2
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V 7 NA 2

+VSB VSB always on power rail ON ON ON*


+RTCVCC RTC power ON ON ON
M3@ U25
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BTO Option Table
BOM Structure BTO Item FCH M3
TL@ Translator Part Number = SA000043ID0

VGA@ Use VGA (Mux) BOM Config


128@ Use VRAM channel A&B
X76@ VRAM ID Table
M2@ Use Hudson-M2
M3@ Use Hudson-M3
x = 1 is read cmd, x= 0 is writee cmd.
USB30@ USB30 on M/B
External PCI Devices USB20@ USB20 on M/B

Device IDSEL# REQ#/GNT# Interrupts

3 3

EC SM Bus1 address EC SM Bus2 address


Device Address HEX Device Address HEX
Smart Battery 0001 011X b 16H ADI ADM1032 (VGA) 1001 101X b 9AH

FCH FCH
4 SM Bus 0 address SM Bus 1 address 4

Device Address HEX Device Address HEX


DDR DIMM1 1101 000X b D0
DDR DIMM2 1101 001X b D2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 4 of 51
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5 4 3 2 1

AMD APU FS1


BATTERY BATT+ PU3 PU13
+CPU_CORE +CPU_CORE 0.7~1.475V VDD CORE 54A
12.6V CHARGER ISL6267HRZ-T
ISL6251AHAZ-T +CPU_CORE_NB +CPU_CORE_NB 0.7~1.475V VDDNB 27.5A
+2.5VS +2.5VS +2.5VS VDDA 500mA
+1.5V
+1.5V +1.5V VDDIO 4.6A
PU6
AC ADAPTOR VIN +1.2VS +1.2VS VDDR 6.7A
D G5603RU1U D
19V 90W PU9
APL5508
RAM DDRIII SODIMMX2
PU10 +1.2VS +1.5V VDD_MEM 4A
G5603RU1U VTT_MEM 0.5A
B+ +0.75VS
PU2 +0.75VS +0.75VS
UP7711U8
VGA ATI
Whistler/Seymour/Granville
PU11 +VGA_CORE +VGA_CORE
TPS51218DSCR 0.85~1.1V VDDC 47A

+VDDCI 0.9~1.0V VDDCI 4.6A

DPLL_VDDC: 125 mA
PU12 PU8 +1.0VSG +1.0VSG SPV10: 120 mA
+VDDCI +1.0VSG
G5603RU1U G9731G11U PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
VRAM 512/1GB/2GB
U34 +1.5VSG +1.5VSG
+1.5VSG VDDR1: 3400 mA 64M / 128Mx16 * 4 / 8
AO4430L
PU5 +1.1VALW
G5603RU1U PLL_PVDD: 75 mA +1.5VSG 2.4 A
TSVDD: 20 mA
AVDD: 70 mA
C VDD1DI: 100 mA C
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
PU4 +3VALW
PU7 +1.8VSG +1.8VSG VDD_CT: 110 mA
RT8205EGQW U33 +1.8VSG VDDR4: 170 mA
+5VALW SY8033BDBC
SI4800 PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
+INVPWR_B+

+3VS
Q61 +3VSG +3VSG A2VDD: 130 mA
SI2301 +3VSG VDDR3: 60 mA
U33
SI4800

LCD panel
FCH AMD Hudson M2/M3
15.6"
VDDPL_11_DAC: 7 mA
U34 VDDAN_11_ML: 226 mA
B+ 300mA AO4430L VDDCR_11: 1007 mA
+1.1VS +1.1VS +1.1VS
+3.3 350mA VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA

VDDAN_11_USB_S: 140 mA
FAN Control VDDCR_11_USB_S: 197 mA
+1.1VALW
B
APL5607 VDDAN_11_SSUSB_S: 282 mA B
+1.1VALW
VDDCR_11_SSUSB_S: 424 mA
+5VS

VDDCR_11_S: 187 mA
+5VS 500mA VDDPL_11_SYS: 70 mA
Q57
SI2301
+5VALW VDDIO_33_PCIGP: 131 mA
U22/U23 VDDPL_33_SYS: 47 mA
TPA2301DRG4 +USB_VCCA VDDPL_33_DAC: 20 mA
+USB_VCCB
+3VS VDDPL_33_ML: 20 mA
+3VS +3VS VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
USB X3 VDDPL_33_SATA: 93 mA
+1.5VS

VDDIO_AZ_S: 26 mA
+5V
Dual+1
2.5A +3VALW VDDPL_33_SSUSB_S: 20 mA
+3VALW VDDPL_33_USB_S: 17 mA
+3VALW VDDAN_33_USB_S: 658 mA
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
SATA Audio Codec Realtek EC LAN VDDAN_33_HWM_S: 12 mA
HDD*2 ALC271X RTS5138 ENE KB930 Atheros AR8151 Mini Card*2
ODD*1
VDDIO_33_GBE_S
+5V 3A +5V 45mA +3.3VALW 30mA +3.3VALW 201mA +1.5VS 500mA VDDCR_11_GBE_S
+3.3VS 300mA +3.3VS 3mA +3.3VS 1A GND VDDIO_GBE_S
+3.3V +3.3VS 25mA +3.3VALW 330mA

RTC
A RTC BAT VDDBT_RTC_G A
Bettary

Security Classification Compal Secret Data


Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
POWER DELIVERY CHART
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom QBL70 LA-7553P 0.22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 5 of 51
5 4 3 2 1
A B C D E

18 PCIE_GTX_C_FRX_P[0..7] PCIE_FTX_C_GRX_P[0..7] 18 APU To HDMI


18 PCIE_GTX_C_FRX_N[0..7] PCIE_FTX_C_GRX_N[0..7] 18

PCIE_FTX_GRX_P[12..15] 28
JCPU1A CONN@

PCI EXPRESS PCIE_FTX_GRX_N[12..15] 28


PCIE_GTX_C_FRX_P0 AA8 AA2 PCIE_FTX_GRX_P0 C917 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P0
P_GFX_RXP0 P_GFX_TXP0
PCIE_GTX_C_FRX_N0 AA9 AA3 PCIE_FTX_GRX_N0 C918 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N0
P_GFX_RXN0 P_GFX_TXN0
PCIE_GTX_C_FRX_P1 Y7 Y2 PCIE_FTX_GRX_P1 C919 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P1
P_GFX_RXP1 P_GFX_TXP1
1 PCIE_GTX_C_FRX_N1 PCIE_FTX_GRX_N1 C920 PCIE_FTX_C_GRX_N1 1
Y8
P_GFX_RXN1 P_GFX_TXN1
Y1 1 2 0.1U_0402_16V7K
PCIE_GTX_C_FRX_P2 W5 Y4 PCIE_FTX_GRX_P2 C921 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P2
P_GFX_RXP2 P_GFX_TXP2
PCIE_GTX_C_FRX_N2 W6 Y5 PCIE_FTX_GRX_N2 C922 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N2
P_GFX_RXN2 P_GFX_TXN2
PCIE_GTX_C_FRX_P3 W8 W2 PCIE_FTX_GRX_P3 C923 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P3
P_GFX_RXP3 P_GFX_TXP3
For UMA Mux.
PCIE_GTX_C_FRX_N3 W9 W3 PCIE_FTX_GRX_N3 C924 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N3
P_GFX_RXN3 P_GFX_TXN3
PCIE_GTX_C_FRX_P4 V7 V2 PCIE_FTX_GRX_P4 C925 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P4
P_GFX_RXP4 P_GFX_TXP4
PCIE_GTX_C_FRX_N4 V8 V1 PCIE_FTX_GRX_N4 C926 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N4
P_GFX_RXN4 P_GFX_TXN4
PCIE_GTX_C_FRX_P5 U5 V4 PCIE_FTX_GRX_P5 C927 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P5
P_GFX_RXP5 P_GFX_TXP5
PCIE_GTX_C_FRX_N5 U6 V5 PCIE_FTX_GRX_N5 C928 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N5
P_GFX_RXN5 P_GFX_TXN5
PCIE_GTX_C_FRX_P6 U8 U2 PCIE_FTX_GRX_P6 C929 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P6
P_GFX_RXP6 P_GFX_TXP6

GRAPHICS
PCIE_GTX_C_FRX_N6 U9 U3 PCIE_FTX_GRX_N6 C930 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N6
P_GFX_RXN6 P_GFX_TXN6
PCIE_GTX_C_FRX_P7 T7 T2 PCIE_FTX_GRX_P7 C931 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P7
P_GFX_RXP7 P_GFX_TXP7
PCIE_GTX_C_FRX_N7 T8 T1 PCIE_FTX_GRX_N7 C932 1 2 0.1U_0402_16V7K PCIE_FTX_C_GRX_N7
P_GFX_RXN7 P_GFX_TXN7
R5 P_GFX_RXP8 P_GFX_TXP8 T4

R6 P_GFX_RXN8 P_GFX_TXN8 T5
CPU TSI interface level shift
R8 P_GFX_RXP9 P_GFX_TXP9 R2 BSH111, the Vgs is:
2 min = 0.4V 2
R9 R3 C935 1 2 0.1U_0402_16V4Z
P_GFX_RXN9 P_GFX_TXN9 Max = 1.3V
P7 P_GFX_RXP10 P_GFX_TXP10 P2
+3VS 1 R1798 2 1 R1799 2
P8 P_GFX_RXN10 P_GFX_TXN10 P1
31.6K_0402_1% 30K_0402_1%
N5 P_GFX_RXP11 P_GFX_TXP11 P4

N6 P5
P_GFX_RXN11 P_GFX_TXN11

2
G
Q9
N8 N2 PCIE_FTX_GRX_P12
P_GFX_RXP12 P_GFX_TXP12 APU_SID 3 EC_SMB_DA 1
PCIE_FTX_GRX_N12
2 8,14 APU_SID 1 2 EC_SMB_DA2 19,32
R1800 0_0402_5%

D
N9 N3
P_GFX_RXN12 P_GFX_TXN12
M7 M2 PCIE_FTX_GRX_P13 BSH111 1N_SOT23-3
P_GFX_RXP13 P_GFX_TXP13
1
M8
P_GFX_RXN13 P_GFX_TXN13
M1 PCIE_FTX_GRX_N13 To EC
To HDMI

2
G
L5 M4 PCIE_FTX_GRX_P14 Q10
P_GFX_RXP14 P_GFX_TXP14
PCIE_FTX_GRX_N14
0 APU_SIC 3 EC_SMB_CK 1
L6 M5 8,14 APU_SIC 1 2 EC_SMB_CK2 19,32
P_GFX_RXN14 P_GFX_TXN14 R1801 0_0402_5%

D
L8 L2 PCIE_FTX_GRX_P15
P_GFX_RXP15 P_GFX_TXP15 BSH111 1N_SOT23-3
PCIE_FTX_GRX_N15
CK
L9 L3
P_GFX_RXN15 P_GFX_TXN15

AC5 AD4 PCIE_FTX_DRX_P0 C950 1 2 0.1U_0402_16V7K


31 PCIE_DTX_C_FRX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_FTX_C_DRX_P0 31
GLAN
AC6 AD5 PCIE_FTX_DRX_N0 C951 1 2 0.1U_0402_16V7K
31 PCIE_DTX_C_FRX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_FTX_C_DRX_N0 31
3 3
AC8 AC2
P_GPP_RXP1 P_GPP_TXP1
GPP

AC9 AC3
P_GPP_RXN1 P_GPP_TXN1
AB7 AB2
P_GPP_RXP2 P_GPP_TXP2
AB8 AB1
P_GPP_RXN2 P_GPP_TXN2
AA5 AB4
P_GPP_RXP3 P_GPP_TXP3
AA6 AB5
P_GPP_RXN3 P_GPP_TXN3 Power Sequence of APU
AF8 AF1 UMI_FTX_MRX_P0 C956 1 2 0.1U_0402_16V7K
+1.5V
13 UMI_MTX_C_FRX_P0 P_UMI_RXP0 P_UMI_TXP0 UMI_FTX_C_MRX_P0 13
AF7 AF2 UMI_FTX_MRX_N0 C957 1 2 0.1U_0402_16V7K
13 UMI_MTX_C_FRX_N0 P_UMI_RXN0 P_UMI_TXN0 UMI_FTX_C_MRX_N0 13
+2.5VS Group A
UMI-LINK

AE6 AF5 UMI_FTX_MRX_P1 C958 1 2 0.1U_0402_16V7K


13 UMI_MTX_C_FRX_P1 P_UMI_RXP1 P_UMI_TXP1 UMI_FTX_C_MRX_P1 13
AE5 AF4 UMI_FTX_MRX_N1 C959 1 2 0.1U_0402_16V7K
13 UMI_MTX_C_FRX_N1 P_UMI_RXN1 P_UMI_TXN1 UMI_FTX_C_MRX_N1 13
AE9 AE3 UMI_FTX_MRX_P2 C960 1 2 0.1U_0402_16V7K
+1.5VS
13 UMI_MTX_C_FRX_P2 P_UMI_RXP2 P_UMI_TXP2 UMI_FTX_C_MRX_P2 13
AE8 AE2 UMI_FTX_MRX_N2 C961 1 2 0.1U_0402_16V7K
13 UMI_MTX_C_FRX_N2 P_UMI_RXN2 P_UMI_TXN2 UMI_FTX_C_MRX_N2 13
AD8 AD1 UMI_FTX_MRX_P3 C962 1 2 0.1U_0402_16V7K
+CPU_CORE
13 UMI_MTX_C_FRX_P3 P_UMI_RXP3 P_UMI_TXP3 UMI_FTX_C_MRX_P3 13
AD7 AD2 UMI_FTX_MRX_N3 C963 1 2 0.1U_0402_16V7K
13 UMI_MTX_C_FRX_N3 P_UMI_RXN3 P_UMI_TXN3 UMI_FTX_C_MRX_N3 13
Group B
+1.2VS 1 2 P_ZVDDP K5 K4 P_ZVSS 1 2
+CPU_CORE_NB
4 R1802 196_0402_1% P_ZVDDP P_ZVSS R1803 196_0402_1% 4

AMD_TOPEDO_FS-1
+1.2VS

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD FS1 PCIE / UMI / TSI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 6 of 51
A B C D E
A B C D E

1 1

JCPU1B CONN@ JCPU1C CONN@

11 DDRA_SMA[15..0] MEMORY CHANNEL A DDRA_SDQ[63..0] 11 12 DDRB_SMA[15..0] MEMORY CHANNEL B DDRB_SDQ[63..0] 12


DDRA_SMA0 U20 E13 DDRA_SDQ0 DDRB_SMA0 T27 A14 DDRB_SDQ0
DDRA_SMA1 MA_ADD0 MA_DATA0 DDRA_SDQ1 DDRB_SMA1 MB_ADD0 MB_DATA0 DDRB_SDQ1
R20 J13 P24 B14
DDRA_SMA2 MA_ADD1 MA_DATA1 DDRA_SDQ2 DDRB_SMA2 MB_ADD1 MB_DATA1 DDRB_SDQ2
R21 H15 P25 D16
DDRA_SMA3 MA_ADD2 MA_DATA2 DDRA_SDQ3 DDRB_SMA3 MB_ADD2 MB_DATA2 DDRB_SDQ3
P22 J15 N27 E16
DDRA_SMA4 MA_ADD3 MA_DATA3 DDRA_SDQ4 DDRB_SMA4 MB_ADD3 MB_DATA3 DDRB_SDQ4
P21 H13 N26 B13
DDRA_SMA5 MA_ADD4 MA_DATA4 DDRA_SDQ5 DDRB_SMA5 MB_ADD4 MB_DATA4 DDRB_SDQ5
N24 F13 M28 C13
DDRA_SMA6 MA_ADD5 MA_DATA5 DDRA_SDQ6 DDRB_SMA6 MB_ADD5 MB_DATA5 DDRB_SDQ6
N23 MA_ADD6 MA_DATA6 F15 M27 MB_ADD6 MB_DATA6 B16
DDRA_SMA7 N20 E15 DDRA_SDQ7 DDRB_SMA7 M24 A16 DDRB_SDQ7
DDRA_SMA8 MA_ADD7 MA_DATA7 DDRB_SMA8 MB_ADD7 MB_DATA7
N21 MA_ADD8 M25 MB_ADD8
DDRA_SMA9 M21 H17 DDRA_SDQ8 DDRB_SMA9 L26 C17 DDRB_SDQ8
DDRA_SMA10 MA_ADD9 MA_DATA8 DDRA_SDQ9 DDRB_SMA10 MB_ADD9 MB_DATA8 DDRB_SDQ9
U23 MA_ADD10 MA_DATA9 F17 U26 MB_ADD10 MB_DATA9 B18
DDRA_SMA11 M22 E19 DDRA_SDQ10 DDRB_SMA11 L27 B20 DDRB_SDQ10
DDRA_SMA12 MA_ADD11 MA_DATA10 DDRA_SDQ11 DDRB_SMA12 MB_ADD11 MB_DATA10 DDRB_SDQ11
L24 MA_ADD12 MA_DATA11 J19 K27 MB_ADD12 MB_DATA11 A20
DDRA_SMA13 AA25 G16 DDRA_SDQ12 DDRB_SMA13 W26 E17 DDRB_SDQ12
DDRA_SMA14 MA_ADD13 MA_DATA12 DDRA_SDQ13 DDRB_SMA14 MB_ADD13 MB_DATA12 DDRB_SDQ13
L21 MA_ADD14 MA_DATA13 H16 K25 MB_ADD14 MB_DATA13 B17
DDRA_SMA15 L20 H19 DDRA_SDQ14 DDRB_SMA15 K24 B19 DDRB_SDQ14
MA_ADD15 MA_DATA14 DDRA_SDQ15 MB_ADD15 MB_DATA14 DDRB_SDQ15
MA_DATA15 F19 MB_DATA15 C19
DDRA_SBS0# U24 DDRB_SBS0# U27
11 DDRA_SBS0# DDRA_SBS1# MA_BANK0 DDRA_SDQ16 12 DDRB_SBS0# DDRB_SBS1# MB_BANK0 DDRB_SDQ16
11 DDRA_SBS1# U21 MA_BANK1 MA_DATA16 H20 12 DDRB_SBS1# T28 MB_BANK1 MB_DATA16 C21
DDRA_SBS2# L23 F21 DDRA_SDQ17 DDRB_SBS2# K28 B22 DDRB_SDQ17
11 DDRA_SBS2# MA_BANK2 MA_DATA17 DDRA_SDQ18 12 DDRB_SBS2# MB_BANK2 MB_DATA17 DDRB_SDQ18
11 DDRA_SDM[7..0] MA_DATA18 J23 12 DDRB_SDM[7..0] MB_DATA18 C23
DDRA_SDM0 E14 H23 DDRA_SDQ19 DDRB_SDM0 D14 A24 DDRB_SDQ19
DDRA_SDM1 MA_DM0 MA_DATA19 DDRA_SDQ20 DDRB_SDM1 MB_DM0 MB_DATA19 DDRB_SDQ20
J17 MA_DM1 MA_DATA20 G20 A18 MB_DM1 MB_DATA20 D20
DDRA_SDM2 E21 E20 DDRA_SDQ21 DDRB_SDM2 A22 B21 DDRB_SDQ21
DDRA_SDM3 MA_DM2 MA_DATA21 DDRA_SDQ22 DDRB_SDM3 MB_DM2 MB_DATA21 DDRB_SDQ22
F25 MA_DM3 MA_DATA22 G22 C25 MB_DM3 MB_DATA22 E23
DDRA_SDM4 AD27 H22 DDRA_SDQ23 DDRB_SDM4 AF25 B23 DDRB_SDQ23
DDRA_SDM5 MA_DM4 MA_DATA23 DDRB_SDM5 MB_DM4 MB_DATA23
AC23 MA_DM5 AG22 MB_DM5
2 DDRA_SDM6 DDRA_SDQ24 DDRB_SDM6 DDRB_SDQ24 2
AD19 MA_DM6 MA_DATA24 G24 AH18 MB_DM6 MB_DATA24 E24
DDRA_SDM7 AC15 E25 DDRA_SDQ25 DDRB_SDM7 AD14 B25 DDRB_SDQ25
MA_DM7 MA_DATA25 DDRA_SDQ26 MB_DM7 MB_DATA25 DDRB_SDQ26
MA_DATA26 G27 MB_DATA26 B27
DDRA_SDQS0 G14 G26 DDRA_SDQ27 DDRB_SDQS0 C15 D28 DDRB_SDQ27
11 DDRA_SDQS0 DDRA_SDQS0# MA_DQS_H0 MA_DATA27 DDRA_SDQ28 12 DDRB_SDQS0 DDRB_SDQS0# MB_DQS_H0 MB_DATA27 DDRB_SDQ28
11 DDRA_SDQS0# H14 MA_DQS_L0 MA_DATA28 F23 12 DDRB_SDQS0# B15 MB_DQS_L0 MB_DATA28 B24
DDRA_SDQS1 G18 H24 DDRA_SDQ29 DDRB_SDQS1 E18 D24 DDRB_SDQ29
11 DDRA_SDQS1 MA_DQS_H1 MA_DATA29 12 DDRB_SDQS1 MB_DQS_H1 MB_DATA29
DDRA_SDQS1# H18 E28 DDRA_SDQ30 DDRB_SDQS1# D18 D26 DDRB_SDQ30
11 DDRA_SDQS1# MA_DQS_L1 MA_DATA30 12 DDRB_SDQS1# MB_DQS_L1 MB_DATA30
DDRA_SDQS2 J21 F27 DDRA_SDQ31 DDRB_SDQS2 E22 C27 DDRB_SDQ31
11 DDRA_SDQS2 DDRA_SDQS2# MA_DQS_H2 MA_DATA31 12 DDRB_SDQS2 DDRB_SDQS2# MB_DQS_H2 MB_DATA31
11 DDRA_SDQS2# H21 12 DDRB_SDQS2# D22
DDRA_SDQS3 MA_DQS_L2 DDRA_SDQ32 DDRB_SDQS3 MB_DQS_L2 DDRB_SDQ32
11 DDRA_SDQS3 E27 AB28 12 DDRB_SDQS3 B26 AG26
DDRA_SDQS3# MA_DQS_H3 MA_DATA32 DDRA_SDQ33 DDRB_SDQS3# MB_DQS_H3 MB_DATA32 DDRB_SDQ33
11 DDRA_SDQS3# E26 AC27 12 DDRB_SDQS3# A26 AH26
DDRA_SDQS4 MA_DQS_L3 MA_DATA33 DDRA_SDQ34 DDRB_SDQS4 MB_DQS_L3 MB_DATA33 DDRB_SDQ34
11 DDRA_SDQS4 AE26 AD25 12 DDRB_SDQS4 AG24 AF23
DDRA_SDQS4# MA_DQS_H4 MA_DATA34 DDRA_SDQ35 DDRB_SDQS4# MB_DQS_H4 MB_DATA34 DDRB_SDQ35
11 DDRA_SDQS4# AD26 AA24 12 DDRB_SDQS4# AG25 AG23
DDRA_SDQS5 MA_DQS_L4 MA_DATA35 DDRA_SDQ36 DDRB_SDQS5 MB_DQS_L4 MB_DATA35 DDRB_SDQ36
11 DDRA_SDQS5 AB22 AE28 12 DDRB_SDQS5 AG21 AG27
DDRA_SDQS5# MA_DQS_H5 MA_DATA36 DDRA_SDQ37 DDRB_SDQS5# MB_DQS_H5 MB_DATA36 DDRB_SDQ37
11 DDRA_SDQS5# AA22 AD28 12 DDRB_SDQS5# AF21 AF27
DDRA_SDQS6 MA_DQS_L5 MA_DATA37 DDRA_SDQ38 DDRB_SDQS6 MB_DQS_L5 MB_DATA37 DDRB_SDQ38
11 DDRA_SDQS6 AB18 AB26 12 DDRB_SDQS6 AG17 AH24
DDRA_SDQS6# MA_DQS_H6 MA_DATA38 DDRA_SDQ39 DDRB_SDQS6# MB_DQS_H6 MB_DATA38 DDRB_SDQ39
11 DDRA_SDQS6# AA18 AC25 12 DDRB_SDQS6# AG18 AE24
DDRA_SDQS7 MA_DQS_L6 MA_DATA39 DDRB_SDQS7 MB_DQS_L6 MB_DATA39
11 DDRA_SDQS7 AA14 12 DDRB_SDQS7 AH14
DDRA_SDQS7# MA_DQS_H7 DDRA_SDQ40 DDRB_SDQS7# MB_DQS_H7 DDRB_SDQ40
11 DDRA_SDQS7# AA15 Y23 12 DDRB_SDQS7# AG14 AE22
MA_DQS_L7 MA_DATA40 DDRA_SDQ41 MB_DQS_L7 MB_DATA40 DDRB_SDQ41
AA23 AH22
DDRA_CLK0 MA_DATA41 DDRA_SDQ42 DDRB_CLK0 MB_DATA41 DDRB_SDQ42
11 DDRA_CLK0 T21 Y21 12 DDRB_CLK0 R26 AE20
DDRA_CLK0# MA_CLK_H0 MA_DATA42 DDRA_SDQ43 DDRB_CLK0# MB_CLK_H0 MB_DATA42 DDRB_SDQ43
11 DDRA_CLK0# T22 AA20 12 DDRB_CLK0# R27 AH20
DDRA_CLK1 MA_CLK_L0 MA_DATA43 DDRA_SDQ44 DDRB_CLK1 MB_CLK_L0 MB_DATA43 DDRB_SDQ44
11 DDRA_CLK1 R23 AB24 12 DDRB_CLK1 P27 AD23
DDRA_CLK1# MA_CLK_H1 MA_DATA44 DDRA_SDQ45 DDRB_CLK1# MB_CLK_H1 MB_DATA44 DDRB_SDQ45
11 DDRA_CLK1# R24 AD24 12 DDRB_CLK1# P28 AD22
MA_CLK_L1 MA_DATA45 DDRA_SDQ46 MB_CLK_L1 MB_DATA45 DDRB_SDQ46
AA21 AD21
DDRA_CKE0 MA_DATA46 DDRA_SDQ47 DDRB_CKE0 MB_DATA46 DDRB_SDQ47
11 DDRA_CKE0 H28 AC21 12 DDRB_CKE0 J26 AD20
DDRA_CKE1 MA_CKE0 MA_DATA47 DDRB_CKE1 MB_CKE0 MB_DATA47
11 DDRA_CKE1 H27 12 DDRB_CKE1 J27
MA_CKE1 DDRA_SDQ48 MB_CKE1 DDRB_SDQ48
AA19 AF19
DDRA_ODT0 MA_DATA48 DDRA_SDQ49 DDRB_ODT0 MB_DATA48 DDRB_SDQ49
11 DDRA_ODT0 Y25 AC19 12 DDRB_ODT0 W27 AE18
DDRA_ODT1 MA_ODT0 MA_DATA49 DDRA_SDQ50 DDRB_ODT1 MB_ODT0 MB_DATA49 DDRB_SDQ50
11 DDRA_ODT1 AA27 AC17 12 DDRB_ODT1 Y28 AE16
MA_ODT1 MA_DATA50 DDRA_SDQ51 MB_ODT1 MB_DATA50 DDRB_SDQ51
AA17 AH16
DDRA_SCS0# MA_DATA51 DDRA_SDQ52 DDRB_SCS0# MB_DATA51 DDRB_SDQ52
11 DDRA_SCS0# V22 AB20 12 DDRB_SCS0# V25 AG20
3 DDRA_SCS1# MA_CS_L0 MA_DATA52 DDRA_SDQ53 DDRB_SCS1# MB_CS_L0 MB_DATA52 DDRB_SDQ53 3
11 DDRA_SCS1# AA26 Y19 12 DDRB_SCS1# Y27 AG19
MA_CS_L1 MA_DATA53 DDRA_SDQ54 MB_CS_L1 MB_DATA53 DDRB_SDQ54
AD18 AF17
DDRA_SRAS# MA_DATA54 DDRA_SDQ55 DDRB_SRAS# MB_DATA54 DDRB_SDQ55
11 DDRA_SRAS# V21 AD17 12 DDRB_SRAS# V24 AD16
DDRA_SCAS# MA_RAS_L MA_DATA55 DDRB_SCAS# MB_RAS_L MB_DATA55
11 DDRA_SCAS# W24 12 DDRB_SCAS# V27
DDRA_SWE# MA_CAS_L DDRA_SDQ56 DDRB_SWE# MB_CAS_L DDRB_SDQ56
11 DDRA_SWE# W23 AA16 12 DDRB_SWE# V28 AG15
MA_WE_L MA_DATA56 DDRA_SDQ57 MB_WE_L MB_DATA56 DDRB_SDQ57
Y15 AD15
MEM_MA_RST# MA_DATA57 DDRA_SDQ58 MEM_MB_RST# MB_DATA57 DDRB_SDQ58
11 MEM_MA_RST# H25 AA13 12 MEM_MB_RST# J25 AG13
MEM_MA_EVENT# MA_RESET_L MA_DATA58 DDRA_SDQ59 MEM_MB_EVENT# MB_RESET_L MB_DATA58 DDRB_SDQ59
11 MEM_MA_EVENT# T24 AC13 12 MEM_MB_EVENT# T25 AD13
MA_EVENT_L MA_DATA59 DDRA_SDQ60 MB_EVENT_L MB_DATA59 DDRB_SDQ60
Y17 AG16
MA_DATA60 DDRA_SDQ61 MB_DATA60 DDRB_SDQ61
15mil MA_DATA61
AB16
DDRA_SDQ62 MB_DATA61
AF15
DDRB_SDQ62
+MEM_VREF W20 AB14 AE14
M_VREF MA_DATA62 DDRA_SDQ63 MB_DATA62 DDRB_SDQ63
Y13 AF13
MA_DATA63 MB_DATA63
1 2 M_ZVDDIO W21
+1.5V M_ZVDDIO
R1804 39.2_0402_1%
AMD_TOPEDO_FS-1
Place them close to APU within 1"
AMD_TOPEDO_FS-1

EVENT# pull high 0.75V reference voltage +1.5V

+1.5V
2

4 R1805 4
1K_0402_1%
R1806 1 2 1K_0402_5% MEM_MA_EVENT# 15mil
1

R1807 1 2 1K_0402_5% MEM_MB_EVENT# +MEM_VREF


2

1 2
R1808 C964
1K_0402_1% C965 Security Classification Compal Secret Data Compal Electronics, Inc.
1000P_0402_50V7K 0.1U_0402_16V7K Issued Date 2010/08/04 2010/08/04 Title
2 1 Deciphered Date
AMD FS1 DDRIII I/F
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 7 of 51
A B C D E
A B C D E

Place near APU JCPU1D CONN@ Place near APU


If not used, pins are left unconnected (DG ref.)
C971 1 2 0.1U_0402_16V7K DP0_TXP0 F2 D4 DP0_AUXP C972 1 2 0.1U_0402_16V7K To LVDS 20101111
26 DP0_TXP0_C DP0_TXP0 DP0_AUXP DP0_AUXP_C 26

26 DP0_TXN0_C
C973 1 2 0.1U_0402_16V7K DP0_TXN0 F1 D5 DP0_AUXN C974 1 2 0.1U_0402_16V7K DP0_AUXN_C 26
Translator
DP0_TXN0 DP0_AUXN DP0_AUXP R554
To LVDS 2 1 1.8K_0402_5%
Translator 26 DP0_TXP1_C
C1016 1 2 0.1U_0402_16V7K DP0_TXP1 E3 E5 ML_VGA_AUXP C975 1 2 0.1U_0402_16V7K ML_VGA_AUXP_C 15
DP0_AUXN R555 2 1 1.8K_0402_5%
DP0_TXP1 DP1_AUXP
To FCH

DISPLAY PORT 0
C1017 1 2 0.1U_0402_16V7K DP0_TXN1 E2 E6 ML_VGA_AUXN C976 1 2 0.1U_0402_16V7K ML_VGA_AUXP R1809 2 1 1.8K_0402_5%
26 DP0_TXN1_C DP0_TXN1 DP1_AUXN ML_VGA_AUXN_C 15
ML_VGA_AUXN R556 2 1 1.8K_0402_5%
DP0_TXP2 D2 J5
T35 DP0_TXP2 DP2_AUXP
AUX 2~5 are for GFX interface

DISPLAY PORT MISC.


DP0_TXN2 D1 J6
1 T20 DP0_TXN2 DP2_AUXN use, they could be selected to I2C 1
or AUX logic +1.2VS
DP0_TXP3 C2 H4
T21 DP0_TXP3 DP3_AUXP
VDDIO level TEST25_L R548 1 2 510_0402_1%
DP0_TXN3 C3 H5
T22 DP0_TXN3 DP3_AUXN Need Level shift TEST25_H R557 1 2 510_0402_1%
Place near APU
G5
C977 1 DP1_TXP0 DP4_AUXP +1.5V
15 ML_VGA_TXP0 2 0.1U_0402_16V7K K2
DP1_TXP0
G6
C968 1 DP1_TXN0 DP4_AUXN TEST35
15 ML_VGA_TXN0 2 0.1U_0402_16V7K K1
DP1_TXN0
R558 1 2 300_0402_5%

F4 APU_HDMI_CLK R559 1 2 300_0402_5%


DP5_AUXP APU_HDMI_CLK 28
C969 1 2 0.1U_0402_16V7K DP1_TXP1 J3 TEST35 PD 300ohm (DG ref.) @
15 ML_VGA_TXP1 DP1_TXP1 APU_HDMI_DATA
F5 20101111

DISPLAY PORT 1
DP5_AUXN APU_HDMI_DATA 28 +1.5V
C970 1 2 0.1U_0402_16V7K DP1_TXN1 J2
15 ML_VGA_TXN1 DP1_TXN1
To FCH VGA ML D7 DP0_HPD LVDS VDDIO level M_TEST R564 1 @ 2 39.2_0402_1%
DP1_TXP2 DP0_HPD DP0_HPD 10
C978 1 2 0.1U_0402_16V7K H2 Need Level shift
15 ML_VGA_TXP2 DP1_TXP2 DP1_HPD
E7 CRT R567 1 2 39.2_0402_1%
DP1_HPD DP1_HPD 10
C979 1 2 0.1U_0402_16V7K DP1_TXN2 H1
15 ML_VGA_TXN2 DP1_TXN2
DP2_HPD J7
+3VALW
DP1_TXP3
System DP
C980 1 2 0.1U_0402_16V7K G2 H7
15 ML_VGA_TXP3 DP1_TXP3 DP3_HPD FS1R1 R571 1 2 10K_0402_5%
C981 1 2 0.1U_0402_16V7K DP1_TXN3 G3 G7
15 ML_VGA_TXN3 DP1_TXN3 DP4_HPD FS1R1 : Control S5 Dual PWR plane
F7 DP5_HPD In laptop, seems no use
DP5_HPD DP5_HPD 10 +1.5V
HDMI
APU_CLKP AH7
13 APU_CLKP CLKIN_H DP_ENBKL +1.5VS
100MHz C6 VDDIO level R1812 1 2 1K_0402_5%
APU_CLKN DP_BLON DP_ENBKL 10
13 APU_CLKN AH6 CLKIN_L Need Level shift
2 DP_ENVDD ALLOW_STOP R577 1 2
DP_DIGON C5 DP_ENVDD 10 2 1K_0402_5%
@

CLK
APU_DISP_CLKP AH4 C7 DP_INT_PWM MISC APU_RST# R578 1 2 300_0402_5%
13 APU_DISP_CLKP DISP_CLKIN_H DP_VARY_BL DP_INT_PWM 10
100MHz_NSS APU_DISP_CLKN APU_PWRGD
AH3 R580 1 2 300_0402_5%
13 APU_DISP_CLKN DISP_CLKIN_L DP_AUX_ZVSS
D8 R569 1 2 150_0402_1%
DP_AUX_ZVSS +1.5V +3VS
Asserted as an input to force the
APU_SVC B8 Chang to unpop (DG ref.) processor into the HTC-active state
47 APU_SVC SVC
AA10 20101111
TEST6

1
APU_SVD A8
47 APU_SVD SVD

2
R573 1 @ 2 0_0402_5% R587 R588

SER.
G10
TEST9 R586 10K_0402_5% 10K_0402_5%
APU_SIC AH11 H10 1K_0402_5%
6,14 APU_SIC SIC TEST10
TSI

2 2

2
APU_SID AG11 H12 R574 1 2 1K_0402_5%
6,14 APU_SID

1
SID TEST12

B
D9 T6 Q11
TEST14 APU_PROCHOT#

E
1 2 1 3 EC_THERM# 13,32,47
APU_RST# R591 0_0402_5%

C
13 APU_RST# AF10 E9 T7
RESET_L TEST15 MMBT3904_NL_SOT23-3
Chang to PU +1.5VS (DG ref.) APU_PWRGD AE10 G9 +1.5V
+1.5V 13 APU_PWRGD PWROK TEST16 T8
20101111
H9 T9
APU_PROCHOT# TEST17 THERMTRIP shutdown Indicates to the FCH that a thermal trip
AD10
PROCHOT_L

1
R575 1 2 1K_0402_5% APU_SVC H11 APU_TEST18 R582 1 2 1K_0402_5% temperature: 125 degree has occurred. Its assertion will cause the FCH to
CTRL

APU_THERMTRIP# TEST18
Serial VID AG12
THERMTRIP_L
transition the system to S5 immediately

2
R576 1 2 1K_0402_5% APU_SVD G11 APU_TEST19 R583 1 2 1K_0402_5%
ALERT_L TEST19 R610
AH12
ALERT_L APU_TEST20 R584 1
F12 2 1K_0402_5% R609

2 2
+1.5V TEST20 1K_0402_5% 10K_0402_5%

B
E11 APU_TEST21 R585 1 2 1K_0402_5%

1
3 R579 1 APU_SIC APU_TDI TEST21 3
2 1K_0402_5% Q12
TEST

C12
TDI

E
D11 APU_TEST22 R589 1 2 1K_0402_5% APU_THERMTRIP# 3 11 2
TEST22 H_THERMTRIP# 14

C
R581 1 2 1K_0402_5% APU_SID APU_TDO A12 R611 0_0402_5%
TDO MMBT3904_NL_SOT23-3
F10 T10
R791 1 ALERT_L APU_TCK TEST23
2 1K_0402_5% A11
TCK APU_TEST24 R590 1
G12 2 1K_0402_5%
APU_TMS TEST24
D12
JTAG

+1.5V TMS TEST25_H


Close to Header APU_TRST# TEST25_H
AH10
B12
TRST_L TEST25_L
AH9
R592 1 APU_TDI APU_DBRDY TEST25_L
2 1K_0402_5% B11
DBRDY
K7
R593 1 APU_TCK APU_DBREQ# TEST28_H
2 1K_0402_5% C11
DBREQ_L +1.5V
R594 1 2 1K_0402_5% APU_TMS TEST28_L
K8
HDT Debug conn JHDT1
AA12 1 2 APU_TCK
TEST30_H T11 1 2
R595 1 2 1K_0402_5% APU_TRST# E8
RSVD_1 APU_TMS
AB12 T12 3 4
R596 1 APU_DBREQ# TEST30_L 3 4
2 300_0402_5% K21
RSVD

RSVD_2 M_TEST APU_TDI


K22 5 6
TEST31 5 6
AC11
RSVD_3 APU_TDO
TEST32_H
AB11 T13 7
7 8
8 Cut on CPU side, Debug mount
R597 1 2 0_0402_5%
47 APU_VDDNB_RUN_FB_L APU_TRST# R598 1 APU_PWRGD
Route as differential TEST32_L
AA11 T14 2 0_0402_5% 9
9 10
10 R5991 @ 2 0_0402_5%
R600 1 2 0_0402_5% B9
with VSS_SENSE 47 APU_VDD_RUN_FB_L VSS_SENSE TEST35 APU_RST#
D10 R601 1 2 10K_0402_5% 11 12 R6021 @ 2 0_0402_5%
TEST35 11 12
C8
VDDP_SENSE R603 1 APU_DBRDY
2 10K_0402_5% 13 14
APU_VDDNB_SEN 13 14
47 APU_VDDNB_SEN A9
VDDNB_SENSE FS1R1 R605 1 APU_DBREQ#
Y11 2 10K_0402_5% 15 16
SENSE

FS1R1 15 16
B10
VDDIO_SENSE ALLOW_STOP
DMAACTIVE_L AB10 ALLOW_STOP 13 17 17 18 18 R606 1 2 0_0402_5% APU_TEST19
4 APU_VDD_SEN 4
47 APU_VDD_SEN C9 VDD_SENSE C639 1 2 0.1U_0402_16V4Z 19 19 20 20 R608 1 2 0_0402_5% APU_TEST18
A10 AE12 T15 @
VDDR_SENSE THERMDA

THERMDC AD12 T16


Llano do not support this thermal die SAMTE_ASP-136446-07-B
CONN@
AMD_TOPEDO_FS-1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD FS1 Display / MISC / HDT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 8 of 51
A B C D E
A B C D E

Power Name Consumption


VDD
+CPU_CORE 50A CPU BOTTOM SIDE DECOUPLING
VDDNB JCPU1F CONN@
+CPU_CORE
+CPU_CORE_NB 22.5A
VDDIO A7 VSS VSS T11
+1.5V 4A A13 VSS VSS T19

C982

22U_0805_6.3V6M

C996

22U_0805_6.3V6M

C983

22U_0805_6.3V6M

C984

22U_0805_6.3V6M

C997

22U_0805_6.3V6M

C985

22U_0805_6.3V6M

C986

22U_0805_6.3V6M

C987

0.22U_0603_16V4Z

C988

0.22U_0603_16V4Z

C989

0.01U_0402_16V7K

C998

0.01U_0402_16V7K

C990

0.01U_0402_16V7K

C991

180P_0402_50V8J

C992

180P_0402_50V8J
C993

390U_2.5V_10M
C994

390U_2.5V_10M
C999

390U_2.5V_10M
C995

330U_D2_2V_Y
2000mil 2000mil 1 1 1 1 A15 VSS VSS U4
VDDP / VDDR JCPU1E CONN@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A17 U7
+CPU_CORE +CPU_CORE + + + + VSS VSS
+1.2VS 3A / 3.5A A19
A21
VSS VSS
U10
U18
@ VSS VSS
VDDA C1
VDD VDD
T6
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A23
VSS VSS
V9
1 1
+2.5VS 0.75A D3
D6
VDD VDD
T10
T18
A25
B7
VSS VSS
V11
V19
VDD VDD VSS VSS
E1 U1 C4 W4
VDD VDD VSS VSS
CORE_NB CPU_CORE F3
VDD VDD
U11 C10
VSS VSS
W7
F6 U19 C14 W10
330uF X 2 330uF X 4 F8
VDD VDD
V3 C16
VSS VSS
W12
VDD VDD +CPU_CORE_NB +CPU_CORE VSS VSS
22uF X 4 22uF X 11 G1
VDD VDD
V6 C18
VSS VSS
W14
H3 V10 C20 W16
VDD VDD VSS VSS
H6 V18 C22 W18
VDD VDD VSS VSS
H8 W1 C24 Y9
VDD VDD VSS VSS

C1000

22U_0805_6.3V6M

C1001

22U_0805_6.3V6M

C1002

22U_0805_6.3V6M

C1003

22U_0805_6.3V6M

C1004

0.22U_0603_16V4Z

C1005

0.22U_0603_16V4Z

C1006

180P_0402_50V8J

C1007

180P_0402_50V8J

C1008

180P_0402_50V8J
C1009

390U_2.5V_10M
C1010

390U_2.5V_10M
C1011

390U_2.5V_10M

C1014

390U_2.5V_10M

C1015

390U_2.5V_10M
J1 W11 1 1 1 1 1 C26 Y22
VDD VDD VSS VSS
K3 VDD VDD W13 1 1 1 1 1 1 1 1 1 C28 VSS VSS AA4
K6 W15 + + + + + D13 AA7
VDD VDD VSS VSS
L1 VDD VDD W17 D15 VSS VSS AB9
L11 VDD VDD W19 D17 VSS VSS AB13
2 2 2 2 2 2 2 2 2 2 2 2 2 2
L19 VDD VDD Y3 D19 VSS VSS AB15
M3 VDD VDD Y6 D21 VSS VSS AB17
M6 VDD VDD Y10 D23 VSS VSS AB19
M10 VDD VDD Y12 D25 VSS VSS AB21
M18 VDD VDD Y14 D27 VSS VSS AB23
N1 VDD VDD Y16 E4 VSS VSS AB25
N11 Y18 +1.5V E10 AB27
VDD VDD VSS VSS
N19 VDD VDD Y20 E12 VSS VSS AC4
P3 VDD VDD AA1 F9 VSS VSS AC7
P6 VDD VDD AB3 F11 VSS VSS AC10

C1012

22U_0805_6.3V6M

C1013

22U_0805_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

C1018

0.22U_0603_16V4Z

C1019

0.22U_0603_16V4Z

C1020

0.22U_0603_16V4Z

C1021

0.22U_0603_16V4Z

C1022

0.22U_0603_16V4Z

C1023

0.22U_0603_16V4Z

C1024

180P_0402_50V8J

C1025

180P_0402_50V8J

330U_D2_2V_Y
P10 VDD VDD AB6 1 F14 VSS VSS AC12

C14

C15

C16

C17

C5
P18 VDD VDD AC1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F16 VSS VSS AC14
R1 AD3 + F18 AC16
VDD VDD VSS VSS
R11 VDD VDD AD6 F20 VSS VSS AC18
R19 VDD VDD AE1 F22 VSS VSS AC20
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
T3 VDD F24 VSS VSS AC22
F26 VSS VSS AC24
2 2
900mil 900mil F28 VSS VSS AC26
+CPU_CORE_NB J9 VDDNB VDDNB K11 +CPU_CORE_NB G4 VSS VSS AC28
J10 VDDNB VDDNB K12 G8 VSS VSS AD9
J11 VDDNB VDDNB K13 G13 VSS VSS AD11
J12 VDDNB VDDNB K14 G15 VSS VSS AE4
J14 VDDNB VDDNB K16 G17 VSS VSS AE7
J16 VDDNB VDDNB K17 G19 VSS VSS AE13
K9 K18 G21 AE15
VDDNB VDDNB +1.5V VSS VSS
K10 L18 G23 AE17
VDDNB VDDNB VSS VSS
G25 AE19
VSS VSS
160mil 160mil J4
VSS VSS
AE21
+1.5V G28 R22 +1.5V J8 AE23
VDDIO VDDIO VSS VSS

C1027

0.22U_0603_16V4Z

C1028

0.22U_0603_16V4Z

C1029

180P_0402_50V8J

C1030

180P_0402_50V8J
H26 R25 J18 AE25
VDDIO VDDIO VSS VSS
J28 R28 1 1 1 1 J20 AE27
VDDIO VDDIO VSS VSS
K20 T20 J22 AF3
VDDIO VDDIO VSS VSS
K23 T23 J24 AF6
VDDIO VDDIO VSS VSS
K26 T26 K19 AF9
VDDIO VDDIO 2 2 2 2 VSS VSS
L22 U22 L4 AF12
VDDIO VDDIO VSS VSS
L25 U25 L7 AF14
VDDIO VDDIO VSS VSS
L28 U28 L10 AF16
VDDIO VDDIO VSS VSS
M20
VDDIO VDDIO
V20 Decoupling between CPU and DIMMs M9
VSS VSS
AF18
M23 V23 across VDDIO and VSS split M11 AF20
VDDIO VDDIO VSS VSS
M26 V26 M19 AF22
VDDIO VDDIO VSS VSS
N22 W22 N4 AF24
VDDIO VDDIO VSS VSS
N25 W25 N7 AF26
VDDIO VDDIO VSS VSS
N28 W28 N10 AF28
VDDIO VDDIO VSS VSS
P20 Y24 N18 AG10
VDDIO VDDIO VSS VSS
P23
VDDIO VDDIO
Y26 VDDP decoupling P9
VSS VSS
AH5
P26 AA28 P11 AH8
VDDIO VDDIO +1.2VS VSS VSS
P19 AH13
+1.2VS VSS VSS
120mil 120mil R4
VSS VSS
AH15
+1.2VS AG2 A3 R7 AH17
VDDP_A_1 VDDP_B_1 VSS VSS
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

180P_0402_50V8J

180P_0402_50V8J

0.22U_0603_16V4Z

0.22U_0603_16V4Z
3 3
AG3 A4 R10 AH19
VDDP_A_2 VDDP_B_2 VSS VSS
C1034

C1035

C1036

C1037
AG4 B3 1 R18 AH21
VDDP_A_3 VDDP_B_3 VSS VSS
C8

C7

C6

AG5 B4 1 1 1 1 1 1 1 T9 AH23
VDDP_A_4 VDDP_B_4 + C1038 VSS VSS
AH25
220U_6.3V_M VSS
160mil 160mil
+1.2VS AG6 A5
VDDR VDDR 2 2 2 2 2 2 2 2
AG7 A6
VDDR VDDR AMD_TOPEDO_FS-1
AG8 B5
VDDR VDDR
AG9 B6
+2.5VS VDDR VDDR C1038 change to SF000002Y00
L1 20101228
40mil
FBMA-L11-201209-221LMA30T_0805 AE11
VDDA VDDA
2 1 AF11
VDDA VDDR decoupling
+1.2VS
C1040

3300P_0402_50V7K

C1041

0.22U_0603_16V4Z
C18

4.7U_0805_10V4Z

C1043

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
C1044

C1045

C1046

C1047

C1048

C1049

C1050

C1051

1 1 1
1

@ AMD_TOPEDO_FS-1 1 1 1 1 1 1 1 1
Keep trace from resistor to APU
within 0.6"
2

2 2 2
Keep trace from Caps to APU 2 2 2 2 2 2 2 2
within 1.2"
Del C1039
201012061900
Demo Board Capacitor (include PWM side)
CPU_CORE CORE_NB VDDIO_SUS VDDIO_SUS VDDP/R_PWM VDDP VDDR
470uF x 6 470uF x 4 (CPU side) (DIMM x2) 470uF x 2 10uF x 3 4.7uF x 4
C1052

0.22U_0603_16V4Z

C1053

0.22U_0603_16V4Z

C1054

0.22U_0603_16V4Z

C1055

0.22U_0603_16V4Z

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
C10

C11

C12

1 1 1 1 1 1 1 2 22uF x 9 22uF x 6 680uF x 1 100uF x 4 10uF x 1 0.22uF x 2 0.22uF x 4


0.22uF x 2 0.22uF x 2 330uF x 1 0.1uF 180pF x 2 1nF x 4
C13

4 2 2 2 2 2 2 2 1 180pF x 2 180uF x 3 22uF x 3 180pF x 4 4


10nF x 3 4.7uF x 4
0.22uF x 6
180pF x 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD FS1 PWR / GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 9 of 51
A B C D E
5 4 3 2 1

HPD +3VS
Panel ENBKL +3VS

+1.5VS

1
1
@

2
R614

2
R613 @ 4.7K_0402_5%
@ 10K_0402_5% R616 R617

2
D R615 1K_0402_5% 100K_0402_5% ENBKL D
Translator HPD

2 2
1K_0402_5%

1
From Translator

G
1

1
D
LVDS_HPD 1 3 2 @
26 LVDS_HPD DP0_HPD 8
G Q14

MMBT3904_NL_SOT23-3
@ S 2N7002_SOT23

3
1
2 @ 1 @ Q15 C
R618 100K_0402_5% Q13 DP_ENBKL
8 DP_ENBKL 1 2 2
2N7002_SOT23 R619 2.2K_0402_5% B

2
E

3
@
R620
+3VS 100K_0402_5%

1
+1.5VS

1
2

R621 1K_0402_5%
@ 10K_0402_5% R623
CRT HPD R622
1K_0402_5% 2 2 DP_ENBKL R624 1 2 0_0402_5% ENBKL
ENBKL 32

2
From FCH G
1

FCH_CRT_HPD 1 3
15 FCH_CRT_HPD DP1_HPD 8
D

2 @ 1
Q16

Panel ENVDD
R627 100K_0402_5%
2N7002_SOT23

C +3VS C

+1.5VS
1

1
2
@ @
R630 @ R632
HDMI HPD 4.7K_0402_5% R1810 4.7K_0402_5%
100K_0402_5%
2

2
From HDMI Conn APU_ENVDD 27

1
APU_HDMI_HPD R677 1 2 0_0402_5%
28 APU_HDMI_HPD DP5_HPD 8

1
D
2 Q18
2 @ 1 G @

MMBT3904_NL_SOT23-3
R659 100K_0402_5% @ S 2N7002_SOT23

3
1
@ Q19 C
8 DP_ENVDD 1 2 2
R633 2.2K_0402_5% B
E

3
2
@
R634
100K_0402_5%

1
Panel PWM
B B
+3VS

1
R635 R636
47K_0402_5% 4.7K_0402_5%

2
APU_INVT_PWM 26,27

1
D
2
G Q20

MMBT3904_NL_SOT23-3
S 2N7002_SOT23

3
1
Q21 C
8 DP_INT_PWM 1 2 2
R637 2.2K_0402_5% B
E

3
1

R638
4.7K_0402_5%
Q15 / Q19 / Q21 change to SB000006A00
2

20101228

A A

Security Classification Compal Secret Data


Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
AMD FS1 Singal Level Shifter
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 10 of 51
5 4 3 2 1
A B C D E

+VREF_DQ +1.5V +1.5V

15mil JDIMM2
1 VREF_DQ VSS1 2
3 4 DDRA_SDQ4 DDRA_SDQ[0..63]
DDRA_SDQ0 VSS2 DQ4 DDRA_SDQ5 DDRA_SDQ[0..63] 7
5 DQ0 DQ5 6
DDRA_SDQ1 7 8 DDRA_SDM[0..7]
DQ1 VSS3 DDRA_SDM[0..7] 7
9 10 DDRA_SDQS0#
DDRA_SDM0 VSS4 DQS#0 DDRA_SDQS0 DDRA_SDQS0# 7 DDRA_SMA[0..15]
11 DM0 DQS0 12 DDRA_SDQS0 7 DDRA_SMA[0..15] 7
13 VSS5 VSS6 14
DDRA_SDQ2 15 16 DDRA_SDQ6
DDRA_SDQ3 DQ2 DQ6 DDRA_SDQ7
17 18
DQ3 DQ7
19 20
1 DDRA_SDQ8 VSS7 VSS8 DDRA_SDQ12 1
21 22
DDRA_SDQ9 DQ8 DQ12 DDRA_SDQ13
23 24
DQ9 DQ13
25 26
DDRA_SDQS1# VSS9 VSS10 DDRA_SDM1
7 DDRA_SDQS1# 27 28
DDRA_SDQS1 DQS#1 DM1 MEM_MA_RST#
7 DDRA_SDQS1 29
DQS1 RESET#
30 MEM_MA_RST# 7 Place near DIMM1
31 32
DDRA_SDQ10 VSS11 VSS12 DDRA_SDQ14
33 34
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15 +1.5V
35 36
DQ11 DQ15
37 38
DDRA_SDQ16 VSS13 VSS14 DDRA_SDQ20 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
39 40
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21
41 42 2 2 2 2 2 2 2 2 2 2
DQ17 DQ21
43 VSS15 VSS16 44
DDRA_SDQS2# 45 46 DDRA_SDM2 C1067 C1068 C1069 C1070 C1071 C1072 C1073 C1074 C1075 C1076
7 DDRA_SDQS2# DQS#2 DM2
DDRA_SDQS2 47 48
7 DDRA_SDQS2 DQS2 VSS17 DDRA_SDQ22 1 1 1 1 1 1 1 1 1 1
49 VSS18 DQ22 50
DDRA_SDQ18 51 52 DDRA_SDQ23 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDRA_SDQ28
DDRA_SDQ24 VSS20 DQ28 DDRA_SDQ29
57 DQ24 DQ29 58
DDRA_SDQ25 59 60
DQ25 VSS21 DDRA_SDQS3#
61 VSS22 DQS#3 62 DDRA_SDQS3# 7
DDRA_SDM3 63 64 DDRA_SDQS3 +0.75VS +1.5V
DM3 DQS3 DDRA_SDQS3 7
65 66 @
DDRA_SDQ26 VSS23 VSS24 DDRA_SDQ30 0.1U_0402_16V4Z
67 DQ26 DQ30 68 1 2
DDRA_SDQ27 69 70 DDRA_SDQ31 2 2 1 C1106 0.1U_0402_16V4Z
DQ27 DQ31
71 VSS25 VSS26 72
C1077 C1078 C1079 Add C1106
20101101
1 1 2
DDRA_CKE0 73 74 DDRA_CKE1 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
7 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 7
75 VDD1 VDD2 76
77 78 DDRA_SMA15
2 DDRA_SBS2# NC1 A15 DDRA_SMA14 2
7 DDRA_SBS2# 79 BA2 A14 80
81 VDD3 VDD4 82
DDRA_SMA12 83 84 DDRA_SMA11
DDRA_SMA9 A12/BC# A11 DDRA_SMA7
85 A9 A7 86
87 VDD5 VDD6 88
DDRA_SMA8 89 90 DDRA_SMA6
DDRA_SMA5 A8 A6 DDRA_SMA4
91 A5 A4 92
93 94
DDRA_SMA3 VDD7 VDD8 DDRA_SMA2 +VREF_CA +1.5V
95 96
DDRA_SMA1 A3 A2 DDRA_SMA0 +VREF_DQ +1.5V
97 98
A1 A0
99 100
VDD9 VDD10

2
DDRA_CLK0 101 102 DDRA_CLK1
7 DDRA_CLK0 CK0 CK1 DDRA_CLK1 7

2
DDRA_CLK0# 103 104 DDRA_CLK1# R640
7 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 7
105 106 R639 1K_0402_1%
DDRA_SMA10 VDD11 VDD12 DDRA_SBS1# 1K_0402_1%
107 108 DDRA_SBS1# 7
DDRA_SBS0# A10/AP BA1 DDRA_SRAS#
7 DDRA_SBS0# 109 110 DDRA_SRAS# 7 15mil

1
BA0 RAS# +VREF_CA
111 112 15mil

1
DDRA_SWE# VDD13 VDD14 DDRA_SCS0# +VREF_DQ
113 114 DDRA_SCS0# 7
7 DDRA_SWE# WE# S0#

1000P_0402_50V7K
0.1U_0402_16V4Z
DDRA_SCAS# 115 116 DDRA_ODT0
7 DDRA_SCAS# CAS# ODT0 DDRA_ODT0 7

4.7U_0603_6.3V6K
0.1U_0402_16V4Z
117 118
VDD15 VDD16

1000P_0402_50V7K
4.7U_0603_6.3V6K
DDRA_SMA13 119 120 DDRA_ODT1 1 1 1
A13 ODT1 DDRA_ODT1 7

2
DDRA_SCS1# 121 122 1 1 1 @ C1064 C1065
7 DDRA_SCS1# S1# NC2

C1063
123 124 15mil @ C1061 C1062 R642
VDD17 VDD18

C1060
125 126 +VREF_CA R641 1K_0402_1%
NCTEST VREF_CA 1K_0402_1% 2 2 2
127 128
DDRA_SDQ32 VSS27 VSS28 DDRA_SDQ36 2 2 2
129 130

1
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
131 132 1

1
DQ33 DQ37 C1066
133 134
DDRA_SDQS4# VSS29 VSS30 DDRA_SDM4
7 DDRA_SDQS4# 135 136
DDRA_SDQS4 DQS#4 DM4 1000P_0402_50V7K
7 DDRA_SDQS4 137 138
DQS4 VSS31 DDRA_SDQ38 2
139 140
DDRA_SDQ34 VSS32 DQ38 DDRA_SDQ39
141 142
3 DDRA_SDQ35 DQ34 DQ39 3
143 144
DQ35 VSS33 DDRA_SDQ44
145 146
DDRA_SDQ40 VSS34 DQ44 DDRA_SDQ45
147 148
DDRA_SDQ41 DQ40 DQ45
149 150
DQ41 VSS35 DDRA_SDQS5#
151 152 DDRA_SDQS5# 7
DDRA_SDM5 VSS36 DQS#5 DDRA_SDQS5
153 154 DDRA_SDQS5 7
DM5 DQS5
155 156
DDRA_SDQ42 VSS37 VSS38 DDRA_SDQ46
157 158
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
159 160
DQ43 DQ47
161 162
DDRA_SDQ48 VSS39 VSS40 DDRA_SDQ52
163 164
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53
165 166
DQ49 DQ53
167 168
DDRA_SDQS6# VSS41 VSS42 DDRA_SDM6
7 DDRA_SDQS6# 169 170
DDRA_SDQS6 DQS#6 DM6
7 DDRA_SDQS6 171 172
DQS6 VSS43 DDRA_SDQ54
173 174
DDRA_SDQ50 VSS44 DQ54 DDRA_SDQ55
175 176
DDRA_SDQ51 DQ50 DQ55
177 178
DQ51 VSS45 DDRA_SDQ60
179 180
DDRA_SDQ56 VSS46 DQ60 DDRA_SDQ61
181 182
DDRA_SDQ57 DQ56 DQ61
183 184
DQ57 VSS47 DDRA_SDQS7#
185 186 DDRA_SDQS7# 7
DDRA_SDM7 VSS48 DQS#7 DDRA_SDQS7
187 188 DDRA_SDQS7 7
DM7 DQS7
189 190
DDRA_SDQ58 VSS49 VSS50 DDRA_SDQ62
191 192
DDRA_SDQ59 DQ58 DQ62 DDRA_SDQ63
193 194
R643 10K_0402_5% DQ59 DQ63
195 196
VSS51 VSS52 MEM_MA_EVENT#
1 2 197 198 MEM_MA_EVENT# 7
+3VS SA0 EVENT#
+3VS 199 200 FCH_SDATA0 12,14,35
VDDSPD SDA
201 202 FCH_SCLK0 12,14,35
SA1 SCL
203 204 +0.75VS
VTT1 VTT2
1

4 R645 4
1 1 205 G1 G2 206
C1080 C1081
10K_0402_5% TYCO_2-2013310-1
2.2U_0603_6.3V4Z 0.1U_0402_16V4Z CONN@
2

2 2

Security Classification Compal Secret Data Compal Electronics, Inc.


2010/08/04 2010/08/04 Title
DIMM_A STD H:9.2mm Issued Date Deciphered Date
DDRIII SO-DIMM 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
<Address: 00> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 11 of 51
A B C D E
A B C D E

+VREF_DQ +1.5V +1.5V

15mil JDIMM1
1 VREF_DQ VSS1 2
3 4 DDRB_SDQ4 DDRB_SDQ[0..63]
DDRB_SDQ0 VSS2 DQ4 DDRB_SDQ5 DDRB_SDQ[0..63] 7
5 DQ0 DQ5 6
DDRB_SDQ1 7 8 DDRB_SDM[0..7]
DQ1 VSS3 DDRB_SDM[0..7] 7
9 10 DDRB_SDQS0#
DDRB_SDM0 VSS4 DQS#0 DDRB_SDQS0 DDRB_SDQS0# 7 DDRB_SMA[0..15]
11 DM0 DQS0 12 DDRB_SDQS0 7 DDRB_SMA[0..15] 7
13 VSS5 VSS6 14
DDRB_SDQ2 15 16 DDRB_SDQ6
DDRB_SDQ3 DQ2 DQ6 DDRB_SDQ7
17 18
DQ3 DQ7
19 20
1 DDRB_SDQ8 VSS7 VSS8 DDRB_SDQ12 1
21 22
DDRB_SDQ9 DQ8 DQ12 DDRB_SDQ13
23 24
DQ9 DQ13
25 26
DDRB_SDQS1# VSS9 VSS10 DDRB_SDM1
7 DDRB_SDQS1# 27 28
DDRB_SDQS1 DQS#1 DM1 MEM_MB_RST#
7 DDRB_SDQS1 29 30 MEM_MB_RST# 7
DQS1 RESET#
31 32
DDRB_SDQ10 VSS11 VSS12 DDRB_SDQ14
33 34
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
35 36
DQ11 DQ15
37 38
DDRB_SDQ16 VSS13 VSS14 DDRB_SDQ20
39 40
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
41 42
DQ17 DQ21
DDRB_SDQS2#
43 VSS15 VSS16 44
DDRB_SDM2
Place near DIMM2
7 DDRB_SDQS2# 45 DQS#2 DM2 46
DDRB_SDQS2 47 48
7 DDRB_SDQS2 DQS2 VSS17 DDRB_SDQ22
49 50 +1.5V
DDRB_SDQ18 VSS18 DQ22 DDRB_SDQ23
51 DQ18 DQ23 52
DDRB_SDQ19 53 54 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DQ19 VSS19 DDRB_SDQ28
55 VSS20 DQ28 56 2 2 2 2 2 2 2 2 2 2
DDRB_SDQ24 57 58 DDRB_SDQ29
DDRB_SDQ25 DQ24 DQ29 C1089 C1090 C1091 C1092 C1093 C1094 C1095 C1096 C1097 C1098
59 DQ25 VSS21 60
61 62 DDRB_SDQS3#
DDRB_SDM3 VSS22 DQS#3 DDRB_SDQS3 DDRB_SDQS3# 7 1 1 1 1 1 1 1 1 1 1
63 DM3 DQS3 64 DDRB_SDQS3 7
65 66 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ26 VSS23 VSS24 DDRB_SDQ30
67 DQ26 DQ30 68
DDRB_SDQ27 69 70 DDRB_SDQ31
DQ27 DQ31
71 VSS25 VSS26 72

+0.75VS +1.5V +1.5V


DDRB_CKE0 73 74 DDRB_CKE1 @
7 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 7
75 76 0.1U_0402_16V4Z 1 2
VDD1 VDD2 DDRB_SMA15 C1107 0.1U_0402_16V4Z
77 NC1 A15 78 2 2 1

1
2 DDRB_SBS2# DDRB_SMA14 2
7 DDRB_SBS2# 79 BA2 A14 80
81 82 C1099 C1100 C1101 Add C1107 +@
DDRB_SMA12 VDD3 VDD4 DDRB_SMA11 20101101 C1668
83 A12/BC# A11 84
DDRB_SMA9 DDRB_SMA7 1 1 2 330U_2.5V_M_R15
85 86

2
A9 A7 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
87 VDD5 VDD6 88
DDRB_SMA8 89 90 DDRB_SMA6 C1102 change to OSCON
DDRB_SMA5 A8 A6 DDRB_SMA4 20101101
91 A5 A4 92
93 94
DDRB_SMA3 VDD7 VDD8 DDRB_SMA2
95 96
DDRB_SMA1 A3 A2 DDRB_SMA0
97 98
A1 A0
99 100
DDRB_CLK0 VDD9 VDD10 DDRB_CLK1
101 102 DDRB_CLK1 7
7 DDRB_CLK0 DDRB_CLK0# CK0 CK1 DDRB_CLK1#
103 104 DDRB_CLK1# 7
7 DDRB_CLK0# CK0# CK1#
105 106
DDRB_SMA10 VDD11 VDD12 DDRB_SBS1#
107 108 DDRB_SBS1# 7
DDRB_SBS0# A10/AP BA1 DDRB_SRAS#
7 DDRB_SBS0# 109 110 DDRB_SRAS# 7
BA0 RAS#
111 112
DDRB_SWE# VDD13 VDD14 DDRB_SCS0#
113 114 DDRB_SCS0# 7
7 DDRB_SWE# DDRB_SCAS# WE# S0# DDRB_ODT0
7 DDRB_SCAS# 115 116 DDRB_ODT0 7
CAS# ODT0
117 118
DDRB_SMA13 VDD15 VDD16 DDRB_ODT1
119 120 DDRB_ODT1 7
DDRB_SCS1# A13 ODT1 +VREF_DQ +VREF_CA
121 122
7 DDRB_SCS1# S1# NC2
123
VDD17 VDD18
124 15mil
125
NCTEST VREF_CA
126 +VREF_CA 15mil +VREF_DQ
15mil +VREF_CA
127 128
DDRB_SDQ32 VSS27 VSS28 DDRB_SDQ36
129 130
DQ32 DQ36

1000P_0402_50V7K

1000P_0402_50V7K
DDRB_SDQ33 131 132 DDRB_SDQ37 1
DQ33 DQ37

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

0.1U_0402_16V4Z
133 134 C1088
DDRB_SDQS4# VSS29 VSS30 DDRB_SDM4 1000P_0402_50V7K
7 DDRB_SDQS4# 135 136 1 1 1 1 1 1
DDRB_SDQS4 DQS#4 DM4 @ C1083 C1084 @ C1086 C1087
7 DDRB_SDQS4 137 138
DQS4 VSS31 2

C1082

C1085
139 140 DDRB_SDQ38
DDRB_SDQ34 VSS32 DQ38 DDRB_SDQ39
141 142
3 DDRB_SDQ35 DQ34 DQ39 2 2 2 2 2 2 3
143 144
DQ35 VSS33 DDRB_SDQ44
145 146
DDRB_SDQ40 VSS34 DQ44 DDRB_SDQ45
147 148
DDRB_SDQ41 DQ40 DQ45
149 150
DQ41 VSS35 DDRB_SDQS5#
151 152 DDRB_SDQS5# 7
DDRB_SDM5 VSS36 DQS#5 DDRB_SDQS5
153 154 DDRB_SDQS5 7
DM5 DQS5
155 156
DDRB_SDQ42 VSS37 VSS38 DDRB_SDQ46
157 158
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
159 160
DQ43 DQ47
161 162
DDRB_SDQ48 VSS39 VSS40 DDRB_SDQ52
163 164
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
165 166
DQ49 DQ53
167 168
DDRB_SDQS6# VSS41 VSS42 DDRB_SDM6
7 DDRB_SDQS6# 169 170
DDRB_SDQS6 DQS#6 DM6
7 DDRB_SDQS6 171 172
DQS6 VSS43 DDRB_SDQ54
173 174
DDRB_SDQ50 VSS44 DQ54 DDRB_SDQ55
175 176
DDRB_SDQ51 DQ50 DQ55
177 178
DQ51 VSS45 DDRB_SDQ60
179 180
DDRB_SDQ56 VSS46 DQ60 DDRB_SDQ61
181 182
DDRB_SDQ57 DQ56 DQ61
183 184
DQ57 VSS47 DDRB_SDQS7#
185 186 DDRB_SDQS7# 7
DDRB_SDM7 VSS48 DQS#7 DDRB_SDQS7
187 188 DDRB_SDQS7 7
DM7 DQS7
189 190
DDRB_SDQ58 VSS49 VSS50 DDRB_SDQ62
191 192
DDRB_SDQ59 DQ58 DQ62 DDRB_SDQ63
193 194
R646 10K_0402_5% DQ59 DQ63
195 196
VSS51 VSS52 MEM_MB_EVENT#
1 2 197 198 MEM_MB_EVENT# 7
SA0 EVENT#
+3VS 199 200 FCH_SDATA0 11,14,35
VDDSPD SDA
201 202 FCH_SCLK0 11,14,35
SA1 SCL
203 204 +0.75VS
VTT1 VTT2
1

<BOM Structure>
4 <BOM Structure>
R648 4
205 G1 G2 206

10K_0402_5% TYCO_2-2013289-1
CONN@
2

Security Classification Compal Secret Data Compal Electronics, Inc.


2010/08/04 2010/08/04 Title
DIMM_B STD H:5.2mm Issued Date Deciphered Date
DDRIII SO-DIMM 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
<Address: 01> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 12 of 51
A B C D E
A B C D E

U25A
C1195 150P_0402_50V8J
2 1 HUDSON-2
APU_PCIE_RST#_CAE2 AF3
PCIE_RST# PCICLK0
R829 1 2 33_0402_5%A_RST#_R AD5 AF1

PCI CLKS
32 A_RST# A_RST# PCICLK1/GPO36 PCI_CLK1 16
PCI Host Bus Reset (To EC) PCICLK2/GPO37 AF5
C1189 1 2 0.1U_0402_16V7K UMI_MTX_FRX_P0 AE30 AG2
6 UMI_MTX_C_FRX_P0 UMI_MTX_FRX_N0 UMI_TX0P PCICLK3/GPO38 PCI_CLK3 16
C1190 1 2 0.1U_0402_16V7K AE32 AF6 @
6 UMI_MTX_C_FRX_N0 UMI_MTX_FRX_P1 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 16 +3VALW
C1191 1 2 0.1U_0402_16V7K AD33
6 UMI_MTX_C_FRX_P1 UMI_MTX_FRX_N1 UMI_TX1P
C1192 1 2 0.1U_0402_16V7K AD31 AB5 For PCIE device reset on FS1 C1193
6 UMI_MTX_C_FRX_N1 UMI_MTX_FRX_P2 UMI_TX1N PCIRST#
C1196 1 2 0.1U_0402_16V7K AD28 (GFX,GLAN,WLAN,LVDS Travis) 1 2
6 UMI_MTX_C_FRX_P2 UMI_MTX_FRX_N2 UMI_TX2P
C1197 1 2 0.1U_0402_16V7K AD29
6 UMI_MTX_C_FRX_N2 UMI_MTX_FRX_P3 UMI_TX2N
C1198 1 2 0.1U_0402_16V7K AC30 AJ3 0.1U_0402_16V4Z
6 UMI_MTX_C_FRX_P3 UMI_TX3P AD0/GPIO0

5
C1194 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N3 AC32 AL5
6 UMI_MTX_C_FRX_N3 UMI_TX3N AD1/GPIO1
AG4 2 @

P
1 UMI_FTX_C_MRX_P0 AD2/GPIO2 APU_PCIE_RST#_C R825 1 B 1
6 UMI_FTX_C_MRX_P0 AB33
UMI_RX0P AD3/GPIO3
AL6 2 33_0402_5% Y
4 PLT_RST# 18,26,31,35
UMI_FTX_C_MRX_N0 AB31 AH3 1
6 UMI_FTX_C_MRX_N0

PCI EXPRESS INTERFACES


UMI_RX0N AD4/GPIO4 A

G
2
UMI_FTX_C_MRX_P1 AB28 AJ5 2 U26
6 UMI_FTX_C_MRX_P1 UMI_RX1P AD5/GPIO5
UMI_FTX_C_MRX_N1 AB29 AL1 R826 NC7SZ08P5X_NL_SC70-5
6 UMI_FTX_C_MRX_N1

3
UMI_FTX_C_MRX_P2 UMI_RX1N AD6/GPIO6 C1188 @ 8.2K_0402_5%
6 UMI_FTX_C_MRX_P2 Y33 AN5
UMI_FTX_C_MRX_N2 UMI_RX2P AD7/GPIO7 150P_0402_50V8J
6 UMI_FTX_C_MRX_N2 Y31 AN6
UMI_FTX_C_MRX_P3 UMI_RX2N AD8/GPIO8 1
6 UMI_FTX_C_MRX_P3 Y28 AJ1

1
UMI_FTX_C_MRX_N3 UMI_RX3P AD9/GPIO9
6 UMI_FTX_C_MRX_N3 Y29 AL8 1 2
UMI_RX3N AD10/GPIO10 R835 0_0402_5%
AL3
AD11/GPIO11 +3VALW
R827 1 2 590_0402_1% PCIE_CALRP AF29 AM7
PCIE_CALRP AD12/GPIO12
+PCIE_VDDR_FCH R828 1 2 2K_0402_1% PCIE_CALRN AF31
PCIE_CALRN AD13/GPIO13
AJ6 @ C1199
AD14/GPIO14 AK7 1 2
PCIE_W_FTX_DRX_P0 V33 AN8
35 PCIE_W_FTX_DRX_P0 PCIE_W_FTX_DRX_N0 GPP_TX0P AD15/GPIO15 0.1U_0402_16V4Z
V31 GPP_TX0N AD16/GPIO16 AG9

5
35 PCIE_W_FTX_DRX_N0 W30 AM11 @ U27
GPP_TX1P AD17/GPIO17
W32 AJ10 2 B

P
GPP_TX1N AD18/GPIO18 VGA_PWRGD VGA_PWRGD_R
AB26 GPP_TX2P AD19/GPIO19 AL12 25,48 VGA_PWRGD Y 4 1 2
R830 @ 0_0402_5%
WLAN AB27 GPP_TX2N AD20/GPIO20 AK11 1 A

G
AA24 GPP_TX3P AD21/GPIO21 AN12
AA23 AG12 NC7SZ08P5X_NL_SC70-5

3
GPP_TX3N AD22/GPIO22
AD23/GPIO23 AE12 PCI_AD23 16 1 2
PCIE_W_DTX_C_FRX_P0 AA27 AC12 R831 @ 100K_0402_5%
35 PCIE_W_DTX_C_FRX_P0 PCIE_W_DTX_C_FRX_N0 AA26 GPP_RX0P AD24/GPIO24 PCI_AD24 16
35 PCIE_W_DTX_C_FRX_N0 GPP_RX0N AD25/GPIO25 AE13 PCI_AD25 16
W27 AF13 1 2

PCI INTERFACE
GPP_RX1P AD26/GPIO26 PCI_AD26 16
V27 AH13 R832 0_0402_5%
GPP_RX1N AD27/GPIO27 VGA_PWRGD_R PCI_AD27 16
V26 GPP_RX2P AD28/GPIO28 AH14
W26 GPP_RX2N AD29/GPIO29 AD15
W24 AC15
GPP Port0 For USB30 on SUS/B
W23
GPP_RX3P
GPP_RX3N
AD30/GPIO30
AD31/GPIO31 AE16
AN3
Level shift to ISL6267
GPP Port1 For USB30 on M/B 20101103 CBE0#
AJ8
CBE1# +1.5VS +3VS
CBE2# AN10
2 2
+1.1VS_CKVDD R833 1 2 2K_0402_1% CLK_CALRN F27 CLK_CALRN CBE3# AD12
FRAME# AG10

1
DEVSEL# AK9
AL10 Q38 change to SB000006A00
IRDY# R834
G30 AF10 20101228
PCIE_RCLKP TRDY#

2
For "EXT" CLK mode, input to PCIE, 10K_0402_5%
SS G28 PCIE_RCLKN PAR AE10
AH1 R836

2 2
APU_DISP_CLKP R566 1 APU_DISP_CLKP_R R26 STOP#
8 APU_DISP_CLKP 20_0402_5% AM9 4.7K_0402_5%
DISP_CLKP PERR#

B
APU_DISP_CLKN R565 1 APU_DISP_CLKN_R T26
20_0402_5%
APU DISP8 APU_DISP_CLKN DISP_CLKN SERR#
AH8
AG15

1
REQ0#

E
TRAVIS_CLKP R612 1 TRAVIS_CLKP_R
20_0402_5% APU_PWRGD
NSS Translator 26 TRAVIS_CLKP H33
DISP2_CLKP REQ1#/GPIO40
AG13 3 1 APU_PWRGD_L 47

C
TRAVIS_CLKN R568 1 TRAVIS_CLKN_R
20_0402_5% H31 AF15 Q38
26 TRAVIS_CLKN DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41
AM17 T23 MMBT3904_NL_SOT23-3
APU_CLKP R162 1 APU_CLKP_R REQ3#/CLK_REQ5#/GPIO42
8 APU_CLKP 20_0402_5% T24 AD16
APU_CLKN R163 1 APU_CLKN_R APU_CLKP GNT0#
20_0402_5% T23 AD13 1 2
APU 8 APU_CLKN APU_CLKN GNT1#/GPO44
AD21 R842 0_0402_5%
PE_GPIO0 18

RTC BATT Conn.


GNT2#/SD_LED/GPO45 PE_GPIO1 25,32
CLK_PEG_VGA R607 1 CLK_PEG_VGA_R
20_0402_5% J30 AK17 T24
18 CLK_PEG_VGA SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46
VGA CLK_PEG_VGA# R570 1 CLK_PEG_VGA#_R
20_0402_5% K29 AD19
18 CLK_PEG_VGA# SLT_GFX_CLKN CLKRUN#
AH9 +RTCBATT
CLK_PCIE_LAN R604 1 0_0402_5% CLK_PCIE_LAN_R LOCK#
31 CLK_PCIE_LAN 2 H27
GPP_CLK0P

1
GLAN CLK_PCIE_LAN# R625 1 0_0402_5%
2 CLK_PCIE_LAN#_R H28 AF18
31 CLK_PCIE_LAN# GPP_CLK0N INTE#/GPIO32
AE18 PE_GPIO1 1 2 JRTC1

+
CLK_PCIE_MINI1 R644 1 0_0402_5% CLK_PCIE_MINI1_R J27 INTF#/GPIO33 R1811 10K_0402_5%
35 CLK_PCIE_MINI1 2 AC16 SUYIN_060003HA002G202ZL
CLK_PCIE_MINI1#R572 1 0_0402_5% CLK_PCIE_MINI1#_R K26 GPP_CLK1P INTG#/GPIO34
WLAN 35 CLK_PCIE_MINI1# 2
GPP_CLK1N INTH#/GPIO35
AD18 @
F33
CLOCK GENERATOR

GPP_CLK2P R843 22_0402_5%


F31
GPP_CLK2N LPC_CLK0_EC_R 2 LPC_CLK0_EC
SS E33
LPCCLK0
B25
R671
1
1 2 0_0402_5%
LPC_CLK0_EC 16,32
GPP_CLK3P LPC_CLK1_R R844 1 CLK_PCI_DB 35
E31 D25 2 LPC_CLK1 16
GPP_CLK3N LPCCLK1 LPC_AD0 0_0402_5%
D27 LPC_AD0 32,35
LAD0 LPC_AD1
M23 C28 LPC_AD1 32,35
3 GPP_CLK4P LAD1 LPC_AD2 3

-
M24 A26 LPC_AD2 32,35
GPP_CLK4N LAD2 LPC_AD3
LPC

A29 LPC_AD3 32,35

2
LAD3
M27 A31 LPC_FRAME# 32,35
GPP_CLK5P LFRAME#
M26 B27
GPP_CLK5N LDRQ0# CONN@
AE27
LDRQ1#/CLK_REQ6#/GPIO49
N25 AE19 SERIRQ 32
GPP_CLK6P SERIRQ/GPIO48
N26
GPP_CLK6N
R23
GPP_CLK7P APU_PG/APU_RST#/LDT_STP# : OD pin
R24
GPP_CLK7N DMA_ACTIVE#
G25 ALLOW_STOP 8 DMA_ACTIVE# : IN/OD, 0.8V threshold
E28 R853 1 @ 2 0_0402_5% PROCHOT# : IN, 0.8V threshold
PROCHOT# EC_THERM# 8,32,47
N27 E26 APU_PWRGD LDT_STP : No use, NC
GPP_CLK8P APU_PG APU_PWRGD 8
APU

R27 G26
GPP_CLK8N LDT_STP#
APU_RST#
F26 APU_RST# 8 DMA active. The FCH drives the DMA_ACTIVE# to
R657 1
EMI2 22_0402_5% CLK_SD_48M_R J26
APU to notify DMA activity. This will cause the APU
34 CLK_SD_48M 14M_25M_48M_OSC to reestablish the UMI link quicker.
H7 +RTCBATT
S5_CORE_EN R855 1
F1 2 22_0402_5% RTC_CLK 16,32
RTCCLK
F3
INTRUDER_ALERT#

1
1 2 1 2 25M_X1 C31 E6
C1200 R856 0_0402_5% 25M_X1 VDDBT_RTC_G R857
S5 PLUS
1

12P_0402_50V8J G2 32K_X1 1K_0402_5%


R858 32K_X1
X1 1M_0402_5% 25M_X2 C33 D23

2
25M_X2 +RTCVCC
25MHZ_20PF_7A25000012
2

G4 32K_X2 2
32K_X2 RTCVCC_R
1 2 1 2 1
C1201 R859 510_0402_5% 3 +CHGRTC

0.1U_0402_16V4Z
10P_0402_50V8J C1202 1 1 C1203 W=20mils

1
0.1U_0402_16V4Z

1U_0402_6.3V4Z
HUDSON-M2_FCBGA656 1
M2@ CLRP1 C1204 DAN202UT106_SC70-3
SHORT PADS

2
4 2 2 4
for Clear CMOS 2
C1205 1 2 32K_X1
@
10P_0402_50V8J Y4
1

4 OSC NC 3

R861 1 2
20M_0402_5% OSC NC
32.768KHZ 7PF Q13MC1461000100 Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title


C1206 1 32K_X2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-UMI/PCI/CLOCK/LPC/RTC
8P_0402_50V Close to HUDSON-M2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 13 of 51
A B C D E
A B C D E

PCIE_RST2 : Reset PCIE device on Hudson2


U25D

HUDSON-2
AB6 G8

USB MISC
EC_LID_OUT# PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
32 EC_LID_OUT# R2 RI#/GEVENT22#
W7 B9 USB_RCOMP R863 1 2 11.8K_0402_1%
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
32 SLP_S3# T3 SLP_S3#
32 SLP_S5# W2 SLP_S5# USB_FSD1P/GPIO186 H1
32 PBTN_OUT# J4 PWR_BTN# USB_FSD1N H3
32 FCH_PWRGD N7 PWR_GOOD

USB 1.1
H6
USB_FSD0P/GPIO185

ACPI / WAKE UP EVENTS


TEST0 T9 H5
TEST1 TEST0 USB_FSD0N
T10
1 TEST2 TEST1/TMS 1
V9 H10
TEST2 USB_HSD13P
G10
USB_HSD13N
32 EC_GA20 AE22
GA20IN/GEVENT0#
USB_HSD12P
K10 Hudson-M2 Hudson-M3
32 EC_KBRST# AG19
KBRST#/GEVENT1# USB_HSD12N
J12 EHCI CTL xHCI CTL
32 EC_SCI# R9
LPC_PME#/GEVENT3# DEV 22, Fn 2 DEV 16, Fn 1
USB20_P11 <Disable CTL of M2> xHCI CTL
32 EC_SMI# C26
T5
LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
USB_HSD11P
USB_HSD11N
G12
F12 USB20_N11 USB20_P11 33
USB20_N11 33
USB4 DEV 16, Fn 0
+3VALW 1 @ 2 SYS_RESET# U4
SYS_RESET#/GEVENT19#
FCH_PCIE_WAKE# R18 10K_0402_5% USB20_P10
31,32,35 FCH_PCIE_WAKE# K1
V7
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
USB_HSD10P
USB_HSD10N
K12
K13 USB20_N10 USB20_P10 30
USB20_N10 30
USB1
THERMTRIP: R10 For USB 3.0
8 H_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2#
Need level shift from +3VALW to +1.5V +3VS 1 2 AF19 WD_PWRGD USB_HSD9P B11
R862 10K_0402_5% D11 Hudson-M2/M3
USB_HSD9N
32 EC_RSMRST# U2 RSMRST# EHCI CTL
USB_HSD8P E10 DEV 19, Fn 2
AG24 CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N F10
AE24 CLK_REQ3#/SATA_IS1#/GPIO63
AE26 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P C10
R81 1 2 0_0402_5% LAN_CLKREQ#_1 AF22 A10

USB 2.0
31 LAN_CLKREQ# CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N
AH17 SATA_IS4#/FANOUT3/GPIO55
AG18 SATA_IS5#/FANIN3/GPIO59 USB_HSD6P H9
1 2 AF24 SPKR/GPIO66 USB_HSD6N G9
FCH_SCLK0 R1813 10K_0402_5%

GPIO
11,12,35 FCH_SCLK0 AD26 SCL0/GPIO43
SM bus 0-->S0 PWR domain FCH_SDATA0 AD25 A8
11,12,35 FCH_SDATA0 FCH_SCLK1 SDA0/GPIO47 USB_HSD5P
SM bus 1-->S5 PWR domain T7 SCL1/GPIO227 USB_HSD5N C8
FCH_SDATA1 R7 SDA1/GPIO228 USB20_P4
VGA_PD: Support MLDAC power
save if connect 35 MINI1_CLKREQ#
MINI1_CLKREQ#
AG25
AG22
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
USB_HSD4P
USB_HSD4N
F8
E8 USB20_N4 USB20_P4 34
USB20_N4 34
CardReder Hudson-M2/M3
0: MLDAC power on
J2 IR_LED#/LLB#/GPIO184 EHCI CTL
USB20_P3 DEV 18, Fn 2
2
1: MLDAC power off
16 VGA_PD
VGA_PD
AG26
V8
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#/VGA_PD
USB_HSD3P
USB_HSD3N
C6
A6 USB20_N3 USB20_P3 35
USB20_N3 35
WLAN(BT) 2
W8 GBE_LED0/GPIO183 USB20_P2
Y6
V10
SPI_HOLD#/GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
USB_HSD2P
USB_HSD2N
C5
A5 USB20_N2 USB20_P2 27
USB20_N2 27
CMOS
AA8 GBE_STAT0/GEVENT11#
T29 USB20_P1
AF25 CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P
USB_HSD1N
C1
C3 USB20_N1 USB20_P1 33
USB20_N1 33
USB3
USB20_P0
M7
R8
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_HSD0P
USB_HSD0N
E1
E3 USB20_N0 USB20_P0 30
USB20_N0 30
USB2
T1

USB OC
USB_OC5#/IR_TX0/GEVENT17# USBSS_CALRP R864 1 M3@
P6
USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP
C16 2 1K_0402_1%
F5 A16 USBSS_CALRN R865 1 2 1K_0402_1%
USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN +FCH_VDD_11_SSUSB_S
USB_OC2# P5 M3@
30 USB_OC2# USB_OC1# USB_OC2#/TCK/GEVENT14#
33 USB_OC1# J7 A14
USB_OC0# USB_OC1#/TDI/GEVENT13# USB_SS_TX3P
30 USB_OC0# T8
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
C14 Hudson-M3
xHCI CTL
USB_SS_RX3P
C12 DEV 16, Fn 1
USB_SS_RX3N
A12 xHCI CTL
DEV 16, Fn 0
R866 1 2 33_0402_5% HDA_BITCLK AB3 D15
33 HDA_BITCLK_AUDIO HDA_SDOUT AZ_BITCLK USB_SS_TX2P
R867 1 2 33_0402_5% AB1 B15
33 HDA_SDOUT_AUDIO AZ_SDOUT USB_SS_TX2N
HDA_SDIN0 AA2

HD AUDIO
33 HDA_SDIN0 HDA_SDIN1 AZ_SDIN0/GPIO167
Y5 E14

USB 3.0
T36 AZ_SDIN1/GPIO168 USB_SS_RX2P
Y3 F14
T37 AZ_SDIN2/GPIO169 USB_SS_RX2N
Y1
R868 1 HDA_SYNC AZ_SDIN3/GPIO170
33 HDA_SYNC_AUDIO 2 33_0402_5% AD6 F15
+3VALW R869 1 HDA_RST# AZ_SYNC USB_SS_TX1P
33 HDA_RST_AUDIO# 2 33_0402_5% AE4
AZ_RST# USB_SS_TX1N
G15

H13
USB_OC2# USB_SS_RX1P
1 2 G13
R56 100K_0402_5% USB_SS_RX1N
1 2 USB_OC0# K19 J16 USB30_MTX_DRX_P0 C39 1 2 0.1U_0402_16V7K
3 PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB30_MTX_C_DRX_P0 30 3
R55 100K_0402_5% T27 J19 H16 USB30_MTX_DRX_N0 C37 1 2 0.1U_0402_16V7K On board
PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB30_MTX_C_DRX_N0 30
1 2 USB_OC1# J21 M3@ M3@
SPI_CS2#/GBE_STAT2/GPIO166 USB30_MRX_DTX_P0
USB Conn
R54 100K_0402_5% J15
H_THERMTRIP# USB_SS_RX0P USB30_MRX_DTX_N0 USB30_MRX_DTX_P0 30
1 2 USB_SS_RX0N
K15 USB30_MRX_DTX_N0 30
R871 10K_0402_5% +3VALW
1 2 FCH_SCLK1 FCH_GPIO189 D21
R874 2.2K_0402_5% FCH_GPIO190 PS2KB_DAT/GPIO189 R870 1
C20 H19 2 10K_0402_5%
FCH_SDATA1 FCH_GPIO191 PS2KB_CLK/GPIO190 SCL2/GPIO193 R872 1
1 2 D23 G19 2 10K_0402_5%
PS2M_DAT/GPIO191 SDA2/GPIO194
8.2K_0402_5%

8.2K_0402_5%
@

8.2K_0402_5%
@

R876 2.2K_0402_5% @ C22 EMBEDDED CTRL G22 APU_SIC


PS2M_CLK/GPIO192 SCL3_LV/GPIO195 APU_SIC 6,8
1

1 2 EC_LID_OUT# G21 APU_SID


SDA3_LV/GPIO196 APU_SID 6,8
R877 10K_0402_5% E22
EC_PWM0/EC_TIMER0/GPIO197
R47

R45

R43

1 2 FCH_PCIE_WAKE# H22
R878 @ 10K_0402_5% EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2
F21 J22 EC_PWM2 16
KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
E20 H21
2

FCH_GPIO189 KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200


F20
FCH_GPIO190 KSO_2/GPIO211
A22 K21
FCH_GPIO191 KSO_3/GPIO212 KSI_0/GPIO201
E18
KSO_4/GPIO213 KSI_1/GPIO202
K22 For PCIE device reset on FS1
A20 F22 (GFX,GLAN,WLAN,LVDS Travis)
KSO_5/GPIO214 KSI_2/GPIO203
1

+3VS
8.2K_0402_5%
R48

8.2K_0402_5%
@

8.2K_0402_5%
@

@ J18 F24
KSO_6/GPIO215 KSI_3/GPIO204
Project SKU ID H18
KSO_7/GPIO216 KSI_4/GPIO205
E24
1 2 FCH_SCLK0 G18 B23
R880 2.2K_0402_5% GPIO189 (use VGA) L(NO) H(YES) KSO_8/GPIO217 KSI_5/GPIO206
B21 C24
KSO_9/GPIO218 KSI_6/GPIO207
R46

R44

1 2 FCH_SDATA0 R44 R43 K18 F18


2

R881 2.2K_0402_5% GPIO190 (use PX) L(NO) H(YES) KSO_10/GPIO219 KSI_7/GPIO208


D19
MINI1_CLKREQ# KSO_11/GPIO220
1 2 R46 R45 A18
R882 8.2K_0402_5% GPIO191 L(15") H(17") KSO_12/GPIO221
C18
@ KSO_13/GPIO222
R48 R47 B19
Add Project ID Table KSO_14/GPIO223
B17
KSO_15/GPIO224
201011301600 A24
KSO_16/GPIO225
D17
KSO_17/GPIO226

4 LAN_CLKREQ#_1 HUDSON-M2_FCBGA656 4
1 2
R940 8.2K_0402_5% M2@
Modify 20101111

1 2 EC_RSMRST# +3VALW For FCH internal debug use


R884 2.2K_0402_5%
1 @ 2 HDA_BITCLK 1 @ 2 TEST0
R885 10K_0402_5% R887 2.2K_0402_5%
1 @ 2 HDA_SDIN0 1 @ 2 TEST1 Security Classification Compal Secret Data Compal Electronics, Inc.
R886 10K_0402_5% R889 2.2K_0402_5% Issued Date 2010/08/04 2010/08/04 Title
@ HDA_SDIN1 @ TEST2 Deciphered Date
1
R888
2
10K_0402_5% R890
1 2
2.2K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-ACPI/USB/EC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 14 of 51
A B C D E
A B C D E

U25B SYS BIOS ROM 0.1U_0402_16V4Z


@
C466
+3VALW

HUDSON-2 2 1
AK19 AL14 +3VALW @
29 SATA_STX_DRX_P0 SATA_TX0P SD_CLK/SCLK_2/GPIO73
AM19 AN14 U28
29 SATA_STX_DRX_N0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74 FCH_SPI_CS1#
HDD1 AJ12 1 @ 2 1 8
SD_CD/GPIO75 R626 1 @ FCH_SPI_WP# CS# VCC FCH_SPI_CLK
29 SATA_DTX_C_SRX_N0 AL20 SATA_RX0N SD_WP/GPIO76 AH12 2 1K_0402_5% 3 WP# SCLK 6

SD CARD
AN20 AK13 R934 1 @ 2 10K_0402_5% FCH_SPI_HOLD# 7 5 FCH_SPI_MOSI
29 SATA_DTX_C_SRX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77 HOLD# SI FCH_SPI_MISO
AM13 R935 10K_0402_5% 4 2
SD_DATA1/SDATO_2/GPIO78 GND SO
29 SATA_STX_DRX_P1 AN22 SATA_TX1P SD_DATA2/GPIO79 AH15
AL22 AJ14 MX25L1606EM2I-12G SOP 8P
29 SATA_STX_DRX_N1 SATA_TX1N SD_DATA3/GPIO80
ODD SA000041N00
AH20 AC4 GBE_COL
29 SATA_DTX_C_SRX_N1 SATA_RX1N GBE_COL
AJ20 AD3 GBE_CRS @ R36 @ C23
1 29 SATA_DTX_C_SRX_P1 SATA_RX1P GBE_CRS FCH_SPI_CLK 1
AD9 1 2 1 2
GBE_MDCK GBE_MDIO 10_0402_5%
29 SATA_STX_DRX_P2 AJ22 W10
SATA_TX2P GBE_MDIO 10P_0402_50V8J
29 SATA_STX_DRX_N2 AH22 AB8
SATA_TX2N GBE_RXCLK Add for EMI 201011291330
HDD2 GBE_RXD3
AH7
29 SATA_DTX_C_SRX_N2 AM23 AF7
SATA_RX2N GBE_RXD2
29 SATA_DTX_C_SRX_P2 AK23 AE7
SATA_RX2P GBE_RXD1 +3VALW
AD7
GBE_RXD0
AH24 AG8
SATA_TX3P GBE_RXCTL/RXDV GBE_RXERR GBE_MDIO
AJ24 AD1 1 2
SATA_TX3N GBE_RXERR R891 10K_0402_5%
AB7

GBE LAN
GBE_TXCLK
AN24 AF9
SATA_RX3N GBE_TXD3 Change to PD 20101112
AL24 SATA_RX3P GBE_TXD2 AG6
GBE_TXD1 AE8
AL26 AD8 GBE_PHY_INTR 1 2
SATA_TX4P GBE_TXD0 R892 10K_0402_5%
AN26 SATA_TX4N GBE_TXCTL/TXEN AB9
AC2 GBE_COL 1 2

SERIAL ATA
GBE_PHY_PD R893 10K_0402_5%
AJ26 SATA_RX4N GBE_PHY_RST# AA7
AH26 W9 GBE_PHY_INTR GBE_CRS 1 2
SATA_RX4P GBE_PHY_INTR R894 10K_0402_5%
AN29 GBE_RXERR 1 2
SATA_TX5P FCH_SPI_MISO R895 10K_0402_5%
AL28 SATA_TX5N SPI_DI/GPIO164 V6
V5 FCH_SPI_MOSI
SPI_DO/GPIO163

SPI ROM
AK27 V3 FCH_SPI_CLK_R R35 1 @ 2 0_0402_5% FCH_SPI_CLK
SATA_RX5N SPI_CLK/GPIO162 FCH_SPI_CS1#
AM27 SATA_RX5P SPI_CS1#/GPIO165 T6 Add SYS BIOS ROM
V1 FCH_SPI_WP#
ROM_RST#/SPI_WP#/GPIO161 20101111
AL29 NC6
AN31 NC7
VGA_RED L30 FCH_CRT_R 27
AL31 R896 1 2 150_0402_1%
NC8
AL33 NC9
VGA_GREEN L32 FCH_CRT_G 27
AH33 R897 1 2 150_0402_1%
2 NC10 2
AH31 NC11
VGA_BLUE M29 FCH_CRT_B 27
AJ33 R898 1 2 150_0402_1%

VGA DAC
NC12
AJ31 NC13
VGA_HSYNC/GPO68 M28 FCH_CRT_HSYNC 27
VGA_VSYNC/GPO69 N30 FCH_CRT_VSYNC 27
M33 FCH_CRT_DDC_SDA 27
1K_0402_1% 2 SATA_CALRP VGA_DDC_SDA/GPO70
1 R899 AF28
SATA_CALRP VGA_DDC_SCL/GPO71
N32 FCH_CRT_DDC_SCL 27
1K_0402_1% 2 1 R900 SATA_CALRN AF27
+AVDD_SATA SATA_CALRN
K31 R901 1 2 715_0402_1%
VGA_DAC_RSET
SATA_LED# AD22
35 SATA_LED# SATA_ACT#/GPIO67
V28 ML_VGA_AUXP_C 8
R902 1 AUX_VGA_CH_P
+3VS 2 10K_0402_5% V29 ML_VGA_AUXN_C 8
AUX_VGA_CH_N
AF21

VGA MAINLINK
SATA_X1
U28 AUXCAL 1 2 +VDDAN_11_ML
AUXCAL R903 100_0402_1%
T31 ML_VGA_TXP0 8
ML_VGA_L0P
T33 ML_VGA_TXN0 8
ML_VGA_L0N
AG21 T29 ML_VGA_TXP1 8
SATA_X2 ML_VGA_L1P
T28 ML_VGA_TXN1 8
ML_VGA_L1N
R32 ML_VGA_TXP2 8
ML_VGA_L2P
R30 ML_VGA_TXN2 8
ML_VGA_L2N
P29 ML_VGA_TXP3 8
ML_VGA_L3P
P28 ML_VGA_TXN3 8
ML_VGA_L3N +FCH_VDDAN_33_DAC_R

C29 FCH_CRT_HPD FCH_CRT_HPD 2 1


ML_VGA_HPD/GPIO229 FCH_CRT_HPD 10
10K_0402_5% R904
3 T28 3
AH16 N2 1 2
FANOUT0/GPIO52 VIN0/GPIO175 R5 10K_0402_5%
AM15
BT_ON FANOUT1/GPIO53 HW MONITOR
35 BT_ON AJ16 M3 1 2
FANOUT2/GPIO54 VIN1/GPIO176 R6 10K_0402_5%
AK15 L2 1 2
WL_OFF# FANIN0/GPIO56 VIN2/SDATI_1/GPIO177 R7 10K_0402_5%
35 WL_OFF# AN16
FANIN1/GPIO57
AL16 N4 1 2
FANIN2/GPIO58 VIN3/SDATO_1/GPIO178 R8 10K_0402_5%
P1 1 2
VIN4/SLOAD_1/GPIO179 R9 10K_0402_5%
1 2 K6
TEMPIN0/GPIO171
R13 10K_0402_5% P3 1 2
VIN5/SCLK_1/GPIO180 R10 10K_0402_5%
1 2 K5
TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181
M1 1 2
R14 10K_0402_5% R11 @ 10K_0402_5%
M5 1 2
VIN7/GBE_LED3/GPIO182 R12 10K_0402_5%
1 2 K3
R15 10K_0402_5% TEMPIN2/GPIO173
AG16
NC1
1 2 M6 AH10
R16 10K_0402_5% TEMPIN3/TALERT#/GPIO174 NC2
A28
NC3
G27
NC4
L4
NC5

HUDSON-M2_FCBGA656
M2@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-SATA/GBE/HWM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 15 of 51
A B C D E
A B C D E

STRAP PINS
PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 RTC_CLK

1 1
PULL ALLOW USE NON_FUSION EC CLKGEN LPC ROM S5 PLUS If support ML DAC power down when no VGA plug
HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE
STRAPS DISABLED
DEFAULT DEFAULT DEFAULT DEFAULT
L47 30mil
1 2
PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS FBMA-L11-201209-221LMA30T_0805
LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE 220 ohm
STRAP MODE ENABLED +3VS +FCH_VDDAN_33_DAC +FCH_VDDAN_33_DAC_R
DEFAULT DEFAULT DEFAULT
@ L48
@ Q39 3 1 1 2

2.2U_0603_6.3V4Z
AP2301GN-HF_SOT23-3 FBMA-L11-201209-221LMA30T_0805

0.1U_0402_16V4Z
C1209

C1210
220 ohm
1 1

2
+3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW

2 2
R905

R906 10K_0402_5%

R907 10K_0402_5%

R908 10K_0402_5%

R909 10K_0402_5%

R910 10K_0402_5%

R911 10K_0402_5%
VGA_PD# AO3413 Vgs(max)=1V
1

1
1 2
10K_0402_5%

@ @ @ R912 0_0402_5%
+1.1VS +FCH_VDDAN_11_MLDAC
2

2
30mil
@ Q40 3 1 1 @ 2
13 PCI_CLK1
AP2301GN-HF_SOT23-3 R913 0_0402_5%
2 13 PCI_CLK3 2

13 PCI_CLK4

2
13,32 LPC_CLK0_EC VGA_PD#
+3VS
13 LPC_CLK1

14 EC_PWM2

13,32 RTC_CLK

1
100K_0402_5%
R916

100K_0402_5%
R914
1
R915 10K_0402_5%

R917 10K_0402_5%

R918 10K_0402_5%

R919 10K_0402_5%

R920 10K_0402_5%

R921 2.2K_0402_5%

R922 2.2K_0402_5%
1

2
@ @ @ @

2
VGA_PD#
2

6
1K_0402_5%
R923

0_0402_5%

DMN66D0LDW-7_SOT363-6
Q41A
VGA_PD: Support MLDAC power

R924
save if not connect
@ @
0: MLDAC power on 2
1: MLDAC power off

3
DMN66D0LDW-7_SOT363-6
Q41B

1U_0402_6.3V4Z
1

1
C1211
@
Check VGA_PD states
DEBUG STRAPS 14 VGA_PD
1
5
2

4
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23] R925 C1212
2.2K_0402_5%
2
3 1U_0402_6.3V4Z 3

1
PCI_AD26 PCI_AD27 PCI_AD25 PCI_AD24 PCI_AD23

USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI


PULL PLL ILA PLL PCIE STRAPS MEM BOOT
HIGH AUTORUN
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI


LOW PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
AUTORUN

13 PCI_AD27

13 PCI_AD26

13 PCI_AD25

13 PCI_AD24

13 PCI_AD23
R926 2.2K_0402_5%

R927 2.2K_0402_5%

R928 2.2K_0402_5%

R929 2.2K_0402_5%

R930 2.2K_0402_5%

4 4
1

@ @ @ @ @
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-STRAP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 16 of 51
A B C D E
A B C D E

C1218 / C1219 / C1247 Change to SE00000I10


20101228 +VCC_FCH_R +1.1VS
U25C 1007mA
131mA 10mils R9371 2 0_0805_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z

22U_0805_6.3V6M
HUDSON-2
50mils

C1213

C1214

C1215

C1216

C1217

C1219
+3VS R20 1 2 0_0603_5% +VDDIO_33_PCIGP AB17 T14
+3VS VDDIO_33_PCIGP_1 VDDCR_11_1

22U_0805_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
AB18 VDDIO_33_PCIGP_2 VDDCR_11_2 T17 1 1 1 1 1 1

C1218

C1228

C1220

C1221
L3 AE9 T20 U25E

PCI/GPIO I/O
+VDDPL_3.3V VDDIO_33_PCIGP_3 VDDCR_11_3
1 2 1 1 1 1 AD10
VDDIO_33_PCIGP_4 VDDCR_11_4
U16

2.2U_0603_6.3V4Z
MBK1608221YZF_2P AG7 U18 HUDSON-2

.1U_0402_16V7K
VDDIO_33_PCIGP_5 VDDCR_11_5 2 2 2 2 2 2

C1222

C1229

CORE S0
220 ohm AC13
VDDIO_33_PCIGP_6 VDDCR_11_6
V14 A3
VSS VSS
T25
1 1
1 1 AB12 V17 A33 T27
2 2 2 2 VDDIO_33_PCIGP_7 VDDCR_11_7 VSS VSS
AB13 V20 B7 U6
VDDIO_33_PCIGP_8 VDDCR_11_8 VSS VSS
AB14 Y17 B13 U14
VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1VS_CKVDD +1.1VS VSS VSS
AB16 D9 U17
2 2 VDDIO_33_PCIGP_10 VSS VSS
47mA 10mils 20mils 340mA D13
VSS VSS
U20
+VDDPL_3.3V H24 H26 +1.1VS_CKVDD 1 2 E5 U21
VDDPL_33_SYS VDDAN_11_CLK_1 VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
20mA 10mils J25 R25 0_0603_5% E12 U30
+FCH_VDDAN_33_DAC_R VDDAN_11_CLK_2 VSS VSS

C1223

C1224

C1225

C1226

C1230
2 +VDDPL_33_DAC
1 V22 K24 E16 U32

CLKGEN I/O
+FCH_VDDPL_33_MLDAC VDDPL_33_DAC VDDAN_11_CLK_3 VSS VSS
20mA R22 0_0402_5% 10mils VDDAN_11_CLK_4
L22 1 1 1 1 1 E29
VSS VSS
V11
1 2 +FCH_VDDPL_33_MLDAC 2 +VDDPL_33_ML
1 U22 M22 F7 V16
R19 0_0603_5% VDDPL_33_ML VDDAN_11_CLK_5 VSS VSS
200mA R23 0_0402_5% 10mils VDDAN_11_CLK_6
N21 F9
VSS VSS
V18
+3VS
2.2U_0603_6.3V4Z

+FCH_VDDAN_33_DAC_R T22 N22 F11 W4


.1U_0402_16V7K

VDDAN_33_DAC VDDAN_11_CLK_7 2 2 2 2 2 VSS VSS


C1227

C1231

@ L4 VDDPL_33_SSUSB_S 20mA 10mils P22 F13 W6


R936 2 M2@ 10_0402_5% +FCH_VDDPL_33_SSUSB_S VDDAN_11_CLK_8 VSS VSS
1 2 1 1 For Hudson3 USB3.0 only L18 VDDPL_33_SSUSB_S F16 VSS VSS W25
MBK1608221YZF_2P 17mA 10mils F17 W28
220 ohm For Hudson2, connect to GND +FCH_VDDPL_33_USB_S +PCIE_VDDR_FCH +1.1VS VSS VSS
D7 VDDPL_33_USB_S 50mils F19 VSS VSS Y14
2 2
43mA 10mils VDDAN_11_PCIE_1 AB24 1088mA F23 VSS VSS Y16
+VDDPL_33_PCIE AH29 Y21 +PCIE_VDDR_FCH 1 2 F25 Y18
VDDPL_33_PCIE VDDAN_11_PCIE_2 VSS VSS

PCI EXPRESS

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
93mA 10mils AE25 R938 0_0805_5% F29 AA6
VDDAN_11_PCIE_3 VSS VSS

C1233

C1234

C1235

C1236

C1237
LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA AG28 VDDPL_33_SATA VDDAN_11_PCIE_4 AD24 G6 VSS VSS AA12
supply for the RGB outputs VDDAN_11_PCIE_5 AB23 1 1 1 1 1 G16 VSS VSS AA13
For A11: Cap = 1nF @ AA22 G32 AA14
+3VALW VDDAN_11_PCIE_6 VSS VSS
For A12, Cap = DNI 1 2 M31 LDO_CAP VDDAN_11_PCIE_7 AF26 H12 VSS VSS AA16
M3@L6 +FCH_VDDAN_11_MLDAC C1232 2.2U_0603_6.3V4Z AG27 H15 AA17
VDDAN_11_PCIE_8 2 2 2 2 2 VSS VSS
1 2 +FCH_VDDPL_33_SSUSB_S L24 7mA 10mils H29 AA25

GROUND
VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

MBK1608221YZF_2P 1 2 +VDDPL_11_DAC_L
1 2 +VDDPL_11_DAC V21 VDDPL_11_DAC J6 VSS VSS AA28
+1.1VS
C1238

C1239

MBK1608221YZF_2P R24 0_0402_5% 60mils J9 AA30


+VDDAN_11_ML VSS VSS
220 ohm 1 1 220 ohm/2A 226mA VDDAN_11_SATA_1 AA21 1337mA+AVDD_SATA J10 VSS VSS AA32
1 2 20mils Y20 +AVDD_SATA 1 2 J13 AB25
VDDAN_11_SATA_4 VSS VSS

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

22U_0805_6.3V6M
M3@ M3@ R1148 0_0603_5% Y22 AB21 R941 0_0805_5% J28 AC6
VDDAN_11_ML_1 VDDAN_11_SATA_2 VSS VSS

MAIN LINK
C1240

4.7U_0603_6.3V6K
C1241

C1242

C1243

C1244

C1245

C1246

C1247
V23 AB22 J32 AC18

SERIAL ATA
2 2 VDDAN_11_ML_2 VDDAN_11_SATA_3 VSS VSS
1 1 1 V24 VDDAN_11_ML_3 VDDAN_11_SATA_5 AC22 1 1 1 1 1 K7 VSS VSS AC28
2 2
V25 VDDAN_11_ML_4 VDDAN_11_SATA_6 AC21 K16 VSS VSS AD27
VDDAN_11_SATA_7 AA20 K27 VSS VSS AE6
VDDAN_11_SATA_8 AA18 K28 VSS VSS AE15
+VDDAN_33_USB 2 2 2 2 2 2 2 2
VDDAN_11_SATA_9 AB20 L6 VSS VSS AE21
L7 AC19 L12 AE28
VDDAN_11_SATA_10 +3VALW VSS VSS
1 2 +FCH_VDDPL_33_USB_S AB10 VDDIO_33_GBE_S L13 VSS VSS AF8
2.2U_0603_6.3V4Z

.1U_0402_16V7K

0_0603_5% 10mils 59mA L15 AF12


VSS VSS
C1248

C1249

220 ohm AB11 N18 +VDDIO_33_S 1 2 L16 AF16


VDDCR_11_GBE_S_1 VDDIO_33_S_1 VSS VSS

GBE LAN

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
1 1 AA11 L19 R26 0_0402_5% L21 AF33
VDDCR_11_GBE_S_2 VDDIO_33_S_2 VSS VSS

C1250

C1251

C1252
change to 0ohm-AMD request M18 M13 AG30
VDDIO_33_S_3 VSS VSS

3.3V_S5 I/O
20110212 1 2 AA9 V12 1 1 1 M16 AG32
R945 0_0402_5% VDDIO_GBE_S_1 VDDIO_33_S_4 VSS VSS
AA10 V13 M21 AH5
2 2 +3VALW VDDIO_GBE_S_2 VDDIO_33_S_5 VSS VSS
Y12 M25 AH11
L54 VDDIO_33_S_6 VSS VSS
658mA 30mils VDDIO_33_S_7
Y13
2 2 2
N6
VSS VSS
AH18
1 2 +VDDAN_33_USB G7 W11 N11 AH19
VDDAN_33_USB_S_1 VDDIO_33_S_8 VSS VSS
1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_16V7K
FBMA-L11-201209-221LMA30T_0805 H8 N13 AH21
+3VS VDDAN_33_USB_S_2 +3VALW VSS VSS
C1253

C1254

C1255

C1256

C1257
220 ohm/2A J8
VDDAN_33_USB_S_3
N23
VSS VSS
AH23
L15 1 1 1 1 1 K8 10mils 5mA L28 N24 AH25
+VDDPL_33_PCIE VDDAN_33_USB_S_4 +VDDXL_3.3V VSS VSS
1 2 K9 G24 1 2 P12 AH27
VDDAN_33_USB_S_5 VDDXL_33_S VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
MBK1608221YZF_2P M9 MBK1608221YZF_2P P18 AJ18
VDDAN_33_USB_S_6 VSS VSS
C1258

C1259

C1260

C1261
220 ohm 2 2 2 2 2
M10
VDDAN_33_USB_S_7 220 ohm P20
VSS VSS
AJ28
1 1 N9 1 1 P21 AJ29
VDDAN_33_USB_S_8 VSS VSS
N10 P31 AK21
VDDAN_33_USB_S_9 VSS VSS
M12 P33 AK25
VDDAN_33_USB_S_10 VSS VSS
N12 R4 AL18
2 2 VDDAN_33_USB_S_11 2 2 VSS VSS
M11 R11 AM21
+1.1VALW VDDAN_33_USB_S_12 VSS VSS
R25 AM25
L57 +1.1VALW VSS VSS
140mA 10mils R28
VSS VSS
AN1

USB
1 2 +VDDAN_11_USB_S U12 10mils 187mA T11 AN18
VDDAN_11_USB_S_1 VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

MBK1608221YZF_2P U13 N20 +VDDCR_1.1V 1 2 T16 AN28


+3VS VDDAN_11_USB_S_2 VDDCR_11_S_1 VSS VSS
C1262

C1263

1U_0402_6.3V6K

2.2U_0603_6.3V4Z
220 ohm M20 R1145 0_0603_5% T18 AN33
VDDCR_11_S_2 VSS VSS

C1264

C1265
L22 1 1
3 +VDDPL_33_SATA 3
1 2 1 1 N8
VSSAN_HWM VSSPL_DAC
T21
2.2U_0603_6.3V4Z

.1U_0402_16V7K

MBK1608221YZF_2P L28
VSSAN_DAC
C1266

C1267

220 ohm 2 2
K25
VSSXL VSSANQ_DAC
K33
1 1 N28
2 2 VSSIO_DAC
H25
VSSPL_SYS
R6
+1.1VALW EFUSE
2 2 L59 +1.1VALW
197mA 10mils
1 2 +VDDCR_1.1V_USB T12 10mils 70mA L29
VDDCR_11_USB_S_1
2.2U_0603_6.3V4Z

.1U_0402_16V7K

.1U_0402_16V7K

MBK1608221YZF_2P T13 J24 +VDDPL_1.1V 1 2 HUDSON-M2_FCBGA656


VDDCR_11_USB_S_2 VDDPL_11_SYS_S
C1268

C1269

C1270

2.2U_0603_6.3V4Z
220 ohm MBK1608221YZF_2P M2@

.1U_0402_16V7K
C1271

C1272
1 1 1 220 ohm Connected to VSS through a dedicated via.
1 1

2 2 2
2 2

+3VALW
+FCH_VDD_11_SSUSB_S 12mA
20mils 10mils +VDDAN_33_HWM
282mA P16
VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S
M8 1 2

2.2U_0603_6.3V4Z
M3@ 2 +VDDAN_SSUSB R27 0_0402_5% AMD reply:

.1U_0402_16V7K
1 M14
VDDAN_11_SSUSB_S_2
1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

C1472

C1665
R1149 0_0603_5% N14 VDDAN_33_HWM_S: Please connect
VDDAN_11_SSUSB_S_3
C1273

C1274

C1275

For FCH M2 - BOM option 40mils P13 1 1 it to +3.3V_S5 directly if HWM is not used.
+FCH_VDD_11_SSUSB_S

VDDAN_11_SSUSB_S_4
VDDAN_11_SSUSB_S / VDDAN_11_SSUSB_S 1 1 1 P14
VDDAN_11_SSUSB_S_5
Connected to VSS.
USB SS

M3@ M3@ M3@ 2 2


2 2 2 30mils
N16
1

M2@ M2@ VDDCR_11_SSUSB_S_1 +3VS


N17
C1275 C1281 VDDCR_11_SSUSB_S_2
P17
VDDCR_11_SSUSB_S_3 10mils 26mA
0_0402_5% 0_0402_5% M17 AA4 +VDDIO_AZ 1 2
4 VDDCR_11_SSUSB_S_4 VDDIO_AZ_S R28 0_0402_5% VDDIO_AZ_S should be tied to 4
2

POWER 1 2 +3.3/1.5V_S5 rail if Wake on Ring


424mA C1276 2.2U_0603_6.3V4Z is supported
+1.1VALW 2 L61 M3@ 1 1 M3@ 2 +VDDCR_11_SSUSB HUDSON-M2_FCBGA656 1 2
10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

R1150 0_0603_5% M2@ C1277 .1U_0402_16V7K


C1278

C1279

C1280

C1281

FBMA-L11-201209-221LMA30T_0805
42 ohm/4A 1 1 1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
M3@ M3@ M3@ M3@ Issued Date 2010/08/04 2010/08/04 Title
2 2 2 2 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-POWER/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 17 of 51
A B C D E
A B C D E

<DIGON> <VARY_BL>
Controls panel digital power on/off. LCD PWM (pulse width modulated)
GFX PCIE LANE REVERSAL Active High ,external PD need output to adjust LCD brightness
Active High ,external PD need
PCIE_FTX_C_GRX_P[0..7] U8A U8G
6 PCIE_FTX_C_GRX_P[0..7] PCIE_GTX_C_FRX_P[0..7]
PCIE_FTX_C_GRX_N[0..7] PCIE_GTX_C_FRX_P[0..7] 6
6 PCIE_FTX_C_GRX_N[0..7] PCIE_GTX_C_FRX_N[0..7]
PCIE_GTX_C_FRX_N[0..7] 6 LVDS CONTROL R386 1
VARY_BL AK27 2 10K_0402_5%
AJ27 R387 1 2 10K_0402_5%
DIGON
PCIE_FTX_C_GRX_P0 AA38 Y33 PCIE_GTX_FRX_P0 C580 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P0
1
PCIE_FTX_C_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_GTX_FRX_N0 C291 0.1U_0402_16V7K PCIE_GTX_C_FRX_N0 1
Y37 PCIE_RX0N PCIE_TX0N Y32 1 2

TXCLK_UP_DPF3P AK35
PCIE_FTX_C_GRX_P1 Y35 W 33 PCIE_GTX_FRX_P1 C247 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P1 AL36
PCIE_FTX_C_GRX_N1 PCIE_RX1P PCIE_TX1P PCIE_GTX_FRX_N1 C473 0.1U_0402_16V7K PCIE_GTX_C_FRX_N1 TXCLK_UN_DPF3N
W 36 PCIE_RX1N PCIE_TX1N W 32 1 2
TXOUT_U0P_DPF2P AJ38
TXOUT_U0N_DPF2N AK37
PCIE_FTX_C_GRX_P2 W 38 U33 PCIE_GTX_FRX_P2 C572 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P2
PCIE_FTX_C_GRX_N2 PCIE_RX2P PCIE_TX2P PCIE_GTX_FRX_N2 C288 0.1U_0402_16V7K PCIE_GTX_C_FRX_N2
V37 PCIE_RX2N PCIE_TX2N U32 1 2 TXOUT_U1P_DPF1P AH35
TXOUT_U1N_DPF1N AJ36

PCIE_FTX_C_GRX_P3 V35 U30 PCIE_GTX_FRX_P3 C579 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P3 For UMA Mux. AG38
PCIE_FTX_C_GRX_N3 PCIE_RX3P PCIE_TX3P PCIE_GTX_FRX_N3 C316 0.1U_0402_16V7K PCIE_GTX_C_FRX_N3 TXOUT_U2P_DPF0P
U36 PCIE_RX3N PCIE_TX3N U29 1 2 TXOUT_U2N_DPF0N AH37

TXOUT_U3P AF35
PCIE_FTX_C_GRX_P4 U38 T33 PCIE_GTX_FRX_P4 C287 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P4 AG36
PCIE_FTX_C_GRX_N4 PCIE_RX4P PCIE_TX4P PCIE_GTX_FRX_N4 C228 0.1U_0402_16V7K PCIE_GTX_C_FRX_N4 TXOUT_U3N
T37 PCIE_RX4N PCIE_TX4N T32 1 2

PCI EXPRESS INTERFACE


LVTMDP
PCIE_FTX_C_GRX_P5 T35 T30 PCIE_GTX_FRX_P5 C224 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P5
PCIE_FTX_C_GRX_N5 PCIE_RX5P PCIE_TX5P PCIE_GTX_FRX_N5 C576 0.1U_0402_16V7K PCIE_GTX_C_FRX_N5
R36 PCIE_RX5N PCIE_TX5N T29 1 2 TXCLK_LP_DPE3P AP34
TXCLK_LN_DPE3N AR34

PCIE_FTX_C_GRX_P6 R38 P33 PCIE_GTX_FRX_P6 C295 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P6 AW 37


PCIE_FTX_C_GRX_N6 PCIE_RX6P PCIE_TX6P PCIE_GTX_FRX_N6 C472 0.1U_0402_16V7K PCIE_GTX_C_FRX_N6 TXOUT_L0P_DPE2P
P37 PCIE_RX6N PCIE_TX6N P32 1 2 TXOUT_L0N_DPE2N AU35

TXOUT_L1P_DPE1P AR37
PCIE_FTX_C_GRX_P7 P35 P30 PCIE_GTX_FRX_P7 C242 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P7 AU39
PCIE_FTX_C_GRX_N7 PCIE_RX7P PCIE_TX7P PCIE_GTX_FRX_N7 C468 0.1U_0402_16V7K PCIE_GTX_C_FRX_N7 TXOUT_L1N_DPE1N
N36 PCIE_RX7N PCIE_TX7N P29 1 2
2
TXOUT_L2P_DPE0P AP35 2

TXOUT_L2N_DPE0N AR35
N38 PCIE_RX8P PCIE_TX8P N33
M37 PCIE_RX8N PCIE_TX8N N32 TXOUT_L3P AN36
TXOUT_L3N AP37

M35 PCIE_RX9P PCIE_TX9P N30


L36 PCIE_RX9N PCIE_TX9N N29
2160809000A11SEYMOU_FCBGA962
L38 PCIE_RX10P PCIE_TX10P L33
K37 PCIE_RX10N PCIE_TX10N L32

K35 PCIE_RX11P PCIE_TX11P L30


J36 PCIE_RX11N PCIE_TX11N L29

J38 PCIE_RX12P PCIE_TX12P K33


H37 K32 +3VSG
PCIE_RX12N PCIE_TX12N

H35 PCIE_RX13P PCIE_TX13P J33


G36 PCIE_RX13N PCIE_TX13N J32

1
@
R394
G38 K30 2.2K_0402_5%
PCIE_RX14P PCIE_TX14P U21
F37 PCIE_RX14N PCIE_TX14N K29

5
2
2

P
3 13 PE_GPIO0 B 3
F35 H33 4 VGA_RST#
PCIE_RX15P PCIE_TX15P Y
E37 PCIE_RX15N PCIE_TX15N H32 13,26,31,35 PLT_RST# 1 A

G
Change to APU_PCIE_RST# (SCH ref.)

3
20101111 NC7SZ08P5X_NL_SC70-5
CLOCK
13 CLK_PEG_VGA AB35 PCIE_REFCLKP
13 CLK_PEG_VGA# AA36 PCIE_REFCLKN 1 @ 2
R159 0_0402_5%

CALIBRATION
Y30 VGA_PCIE_CALRP R388 1 2 1.27K_0402_1%
PCIE_CALRP
2 1 AH16 Y29 VGA_PCIE_CALRN R390 1 2 2K_0402_1% +1.0VSG
R389 10K_0402_5% PW RGOOD PCIE_CALRN

VGA_RST# AA30 PERSTB

2160809000A11SEYMOU_FCBGA962

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/12 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Vancouver_ PCIE / LVDS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 18 of 51
A B C D E
A B C D E

U8B
Strap Name Pin Straps description <all internal PD> Setting +3VSG External VGA Thermal Sensor
VIP Device Strap Enable indicates to the software driver (Internal PD) Don't have this strap on U9 @
VIP_DEVICE_EN V2SYNC 0: Driver would ignore the value sampled on VHAD_0 during reset 0 AU24 1 8 VGA_SMB_CK2
(GENLK_VSYNC) 1: VHAD_0 to determine whether or not a VIP slave device Whistler and Seymour TXCAP_DPA3P
AV23 1 @
VDD SCLK
TXCAM_DPA3N

0.1U_0402_16V4Z
C324
GPU_THERM_D+ 2 7 VGA_SMB_DA2
2200P_0402_50V7K D+ SDATA
VGA Disable determines (Internal PD) TX0P_DPA2P AT25
VGA_DIS GPIO9 0: VGA Controller capacity enabled 0 MUTI GFX AR24 1 2 3 6 THM_ALERT#
DPA TX0M_DPA2N 2 C325 @ D- ALERT#
1: The device will not be recognized as the system’s VGA controller
AU26 GPU_THERM_D- 4 5 1 2
TX1P_DPA1P THERM# GND +3VSG
Transmitter Power Saving Enable (Internal PD) AV25 R391 @ 4.7K_0402_5%
TX1M_DPA1N
TX_PWRS_ENB GPIO0 0: 50% Tx output swing 1
1: full Tx output swing AR8 AT27 ADM1032ARMZ-2REEL_MSOP8
NC_DVPCNTL_MVP_0 TX2P_DPA0P
NC on Park, AU8 NC_DVPCNTL_MVP_1 TX2M_DPA0N AR26
PCI Express Transmitter De-emphasis Enable (Internal PD) AP8
TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled 1 Robson and Seymour AW8
NC_DVPCNTL_0
AR30 +3VSG
NC_DVPCNTL_1 TXCBP_DPB3P
1: Tx de-emphasis enabled NC on Park, Robson AR3
NC_DVPCNTL_2 TXCBM_DPB3N
AT29
AR1 +3VSG
1
VRAM_ID0 NC_DVPCLK 1
GPIO13,12,11 (config 2,1,0) : (Internal PD) memory apertures AU1
DVPDATA_0 TX3P_DPB2P
AV31

2
CONFIG[2] GPIO13 a) If BIOS_ROM_EN = 1, then Config[2:0] defines VRAM_ID1 AU3 AU30
CONFIG[3:0] VRAM_ID2 DVPDATA_1 DPB TX3M_DPB2N 04/19
AW3 R392 R393
the ROM type. 128 MB 000 VRAM_ID3 DVPDATA_2
CONFIG[1] GPIO12 001 AP6 AR32 4.7K_0402_5% 4.7K_0402_5%
DVPDATA_3 TX4P_DPB1P

2
b) If BIOS_ROM_EN = 0, then Config[2:0] defines 256 MB 001 * AW5 AT31
DVPDATA_4 TX4M_DPB1N @
CONFIG[0] GPIO11 the primary memory aperture size. 64 MB 010 AU5

1
DVPDATA_5 VGA_SMB_CK2 SM_CK2 EC_SMB_CK2
AR6 AT33 2 1 1 6 EC_SMB_CK2 6,32
DVPDATA_6 TX5P_DPB0P R1814 0_0402_5%
BIOS_ROM_EN GPIO22 Enable external BIOS ROM device (Internal PD) AW6
DVPDATA_7 TX5M_DPB0N
AU32
0: Diable, 1: Enable 0 AU6 Q8A DMN66D0LDW-7_SOT363-6
DVPDATA_8

5
AT7 AU14
DVPDATA_9 TXCCP_DPC3P @
AUD[1] HSYNC 00: No audio function; 10: Audio for DisplayPort only; AV7
DVPDATA_10 TXCCM_DPC3N
AV13
00 AN7 VGA_SMB_DA2 2 1 SM_DA2 4 3 EC_SMB_DA2
01: Audio for DisplayPort and HDMI if adapter is detected; DVPDATA_11 EC_SMB_DA2 6,32
AUD(0) VSYNC AV9 AT15 R1815 0_0402_5%
11: Audio for both DisplayPort and HDMI DVPDATA_12 TX0P_DPC2P Q8B DMN66D0LDW-7_SOT363-6
AT9 DVPDATA_13 TX0M_DPC2N AR14
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on AR10 DVPDATA_14
BIF_GEN2_EN GPIO2 1= Advertises the PCI-E device as 5.0 GT/s capable at power-on 1 AW10 DPC AU16
DVPDATA_15 TX1P_DPC1P
5.0 GT/s capability will be controlled by software AU10 DVPDATA_16 TX1M_DPC1N AV15
AP10 NC_DVPDATA_17
H2SYNC Internal use only. THIS PAD HAS AN INTERNAL AV11 NC_DVPDATA_18 TX2P_DPC0P AT17
RESERVED (GENLK_CLK) NC on Park, AT11 AR16
PULL-DOWN AND MUST BE 0 V AT RESET. The NC_DVPDATA_19 TX2M_DPC0N
GPIO8 Robson and Seymour
AR12 NC_DVPDATA_20
pad may be left unconnected DNI AW12 NC_DVPDATA_21 NC_TXCDP_DPD3P AU20
GPIO21 AU12 AT19 SM_DA2 R1816 2 1 0_0402_5% VGA_GPIO3
NC_DVPDATA_22 NC_TXCDM_DPD3N
AP12 NC_DVPDATA_23
AT21 SM_CK2 R1817 2 1 0_0402_5% VGA_GPIO4
NC_TX3P_DPD2P
Global Swap Lock on AJ21 SWAPLOCKA NC_TX3M_DPD2N AR20
Multiple GPUs
AK21 SWAPLOCKB NC on Park,
VRAM ID
DPD AU22
+1.8VSG NC_TX4P_DPD1P
AV21 Robson and Seymour 04/19
NC_TX4M_DPD1N
GPIO5 fast-power reduction: I2C AT23
@ @ @ @ NC_TX5P_DPD0P
HW control will casue display disturb Move to NC_TX5M_DPD0N AR22
1

1
10K_0402_5%
R426

10K_0402_5%
R427

10K_0402_5%
R428

10K_0402_5%
R429

AK26
should use SW method control DDCCLK_AUX3P,DDCDATA_AUX3N, SCL
AJ26 SDA Not share via for other GND
GPIO6 voltage control signal ,No use can NC
R AD39
GENERAL PURPOSE I/O AD37
2

VRAM_ID0 VGA_GPIO0 RB
AH20 GPIO_0
VRAM_ID1 VGA_GPIO1 AH18 AE36
VRAM_ID2 VGA_GPIO2 GPIO_1 G
2 AN16 GPIO_2 GB AD35 2
VRAM_ID3 VGA_GPIO3 AH23
@ @ @ @ VGA_GPIO4 GPIO_3_SMBDATA
AJ23 GPIO_4_SMBCLK B AF37
1

1
10K_0402_5%
R432

10K_0402_5%
R433

10K_0402_5%
R434

10K_0402_5%
R435

AH17 GPIO_5_AC_BATT BB AE38


AJ17 DAC1
VGA_ENBKL GPIO_6
GPIO7 Controls backlight on/off. 2 1 AK17 GPIO_7_BLON HSYNC AC36 HSYNC
Active High ,need external PD R413 10K_0402_5% AJ13 GPIO_8_ROMSO VSYNC AC38 VSYNC
ROM AH15 HSYNC:VSYNC
2

GPIO_9_ROMSI
if GPIO22 High ,GPIO 11-13->CFG[0:2] AJ16
Config ROM type ,GPU has internal PD VGA_GPIO11 AK16
GPIO_10_ROMSCK
AB34 R414 1 2 499_0402_1% L8 11: Audio for both DisplayPort and HDMI
VGA_GPIO12 GPIO_11 RSET BLM18AG121SN1D_0603 +3VSG
AL16 GPIO_12 10mil
GPIO6,15,16,20 VGA_GPIO13 AM16 70mA AVDD AD34 +AVDD 2 1 +1.8VSG
GPIO_13 VSYNC R417 1 @
Voltage control signal AM14 AE34 AUD Strap 2 10K_0402_5%
GPIO_14_HPD2 AVSSQ

22U_0805_6.3V6M
C331
GPU_VID0 AM13 10mil 1 1 1 HSYNC R418 1 @ 2 10K_0402_5%
GPIO6,15 no use can NC 48 GPU_VID0 GPIO_15_PWRCNTL_0

1U_0402_6.3V6K
C329

0.1U_0402_16V4Z
C330
AK14 100mA VDD1DI AC33 +VDD1DI AMD ref:120ohm/0.3A
THM_ALERT# GPIO_16
Thermal monitor interrupt AG30 GPIO_17_THERMAL_INT VSS1DI AC34
AN14 GPIO_18_HPD3
+3VSG 2 2 2
Critical temperature fault AM17 GPIO_19_CTF
GPU_VID1 AL13 AC30 L9
VGA_GPIO0 48 GPU_VID1 GPIO_20_PWRCNTL_1 R2/NC
R395 1 2 10K_0402_5% Reserved AJ14 AC31 NC on Whistler
R396 10K_0402_5% VGA_GPIO1 GPIO_22_ROMCSB GPIO_21_BB_EN R2B/NC
1 2 AK13 2 1 +1.8VSG
R397 1 2 10K_0402_5% VGA_GPIO2 External BIOS device T30 AN13
GPIO_22_ROMCSB
AD30 and Seymour
R398 @ 10K_0402_5% VGA_GPIO3 T32 GPIO_23_CLKREQB G2/NC BLM18AG121SN1D_0603
1 2 ON(1)/OFF(0) inter PD AM23 AD31 1 1 1
JTAG_TRSTB G2B/NC

1U_0402_6.3V6K
C332

0.1U_0402_16V4Z
C333

10U_0603_6.3V6M
C334
R401 1 @ 2 10K_0402_5% VGA_GPIO4 T18 AN23 AMD ref:120ohm/0.3A
T33 JTAG_TDI
Internal Debug AK23 JTAG_TCK B2/NC AF30 SM010030010
T34 AL24 AF31
VGA_GPIO11
no use can floating JTAG_TMS B2B/NC 2 2 2 200ma 120ohm@100mhz DCR 0.2
R405 1 2 10K_0402_5% T17 AM24
R406 @ 10K_0402_5% VGA_GPIO12 ON(1)/OFF(0) JTAG_TDO
1 2 AJ19 GENERICA
R408 1 @ 2 10K_0402_5% VGA_GPIO13 Stereo Sync AK19 AC32
R409 @ 3K_0402_5% GPIO_22_ROMCSB GENERICB C/NC
1 2 no use can NC AJ20 AD32
GENERICC Y/NC
AK20 GENERICD COMP/NC AF32
For ATI Cross fire AJ24 GENERICE_HPD4
AH26 DAC2
no use can NC NC_GENERICF_HPD5
AH24 NC_GENERICG_HPD6 H2SYNC/GENLK_CLK AD29 T2
V2SYNC/GENLK_VSYNC AC29 T3 Back compatibility(Manhattan)
AK24 HPD1 10mil +VDD2DI +VDD1DI
AG31 R77 1 @ 2 0_0402_5%
VDD2DI/NC VSS2DI R209 1 @
100mA AG32 2 0_0402_5% Whistler and Seymour
VSS2DI/NC
3
+1.8VSG R430 1 2 499_0402_1% 10mil Except A2VSSQ change to TSVSSQ, 3

20mil 100mA AG33 +A2VDD R70 1 @ 2 0_0402_5% +3VSG others are NC


R431 1 A2VDD/NC
2 249_0402_1% 10mil
2mA AD33 +A2VDDQ R256 1 @ 2 0_0402_5% +1.8VSG
C335 +VGA_VREF AH13 A2VDDQ/NC
SM010030010 1 2 0.1U_0402_16V4Z 1 @ 1 @ 1 @
VREFG

1U_0402_6.3V6K
C342

0.1U_0402_16V4Z
C343

10U_0603_6.3V6M
C344
200ma 120ohm@100mhz DCR 0.2 A2VSSQ/TSVSSQ AF33
+1.8VSG
20mil 2 2 2
L10 AA29 1 2
+DPLL_PVDD R2SET/NC R436 715_0402_1%
2 1 AM32 DPLL_PVDD
BLM18AG121SN1D_0603 1 1 1 AN32 DPLL_PVSS 75mA
0.1U_0402_16V4Z
C340

1U_0402_6.3V6K
C341

AMD ref:470ohm/1A
C339 20mil DDC/AUX AM26
10U_0603_6.3V6M PLL/CLOCK DDC1CLK
AN31 DPLL_VDDC DDC1DATA AN26
2 2 2
125mA
AUX1P AM27
+1.0VSG 27MCLK AV33 AL27
L126 XTALOUT AU34 XTALIN AUX1N
+DPLL_VDDC XTALOUT
2 1 AM19
XTALOUT 27MCLK BLM18AG121SN1D_0603 DDC2CLK
2 1 1 1 1 DDC2DATA AL19 GPIO8 Serial-ROM output from ROM. if GPIO22 High ,GPIO 11-13->CFG[0:2]
10U_0603_6.3V6M
C345

0.1U_0402_16V4Z
C346

1U_0402_6.3V6K
C347

R445 1M_0402_5% AMD ref:470ohm/1A XO_IN AW34 XO_IN


AN20 GPIO9 Serial-ROM input to ROM. Config ROM type ,GPU has internal PD
AUX2P
Y3
2 2 2
XO_IN2 AW35 XO_IN2 AUX2N AM20 GPIO10 Serial-ROM clock to ROM. if GPIO22 Low ,GPIO 11-13->CFG[0:2]
2 1 GPIO22 erternal BIOS-ROM enable Config Primary memory-aperture size
1

DDCCLK_AUX3P AL30
27MHZ_16PF_X5H027000FG1H R443 R444
DDCDATA_AUX3N AM30 CFG[3:0]
@ @ GPIO8,GPIO9,GPIO10 no use can NC
C353 C354 0_0402_5% 0_0402_5% 128MB 000
NC_DDCCLK_AUX4P AL29 NC on Park, GPIO22
12P_0402_50V8J 12P_0402_50V8J AF29 AM29 256MB 001 *
2

AG29
DPLUS THERMAL NC_DDCDATA_AUX4N Robson and Seymour Enable need 3K PH ,no use must NC 64MB 010
DMINUS
DDCCLK_AUX5P AN21
DDCDATA_AUX5N AM21
GPU_THERM_D+ AK32
GPU_THERM_D- TS_FDO
Seymour(XT) DDC6CLK AJ30
AL31 TS_A/NC DDC6DATA AJ31

Location VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0 Future ASIC call MLPS NC_DDCCLK_AUX7P AK30 NC on Park,
VRAM AJ32 AK29
OLD ASIC is Fan PWM AJ33
TSVDD
20mA
NC_DDCDATA_AUX7N Robson and Seymour
TSVSS
4 Samsung 4
SA00004GS30 64M16 0 0 0 0
K4W1G1646G-BC11 +1.8VSG L127
BLM18AG121SN1D_0603 10mil 2160809000A11SEYMOU_FCBGA962
Samsung 2 1 +TSVDD
SA000047QA0 128M16 0 0 0 1 1 1 1
K4W2G1646C-HC11
10U_0603_6.3V6M
C350

1U_0402_6.3V6K
C351

0.1U_0402_16V4Z
C352

120ohm/0.3A
Hynix 2 2 2
SA000041S60 64M16 0 1 0 0
H5TQ1G63DFR-11C
Hynix
Security Classification Compal Secret Data Compal Electronics, Inc.
SA00003YO30 128M16 0 1 0 1 Issued Date 2010/07/12 Deciphered Date 2012/07/12 Title
H5TQ2G63BFR-11C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Vancouver_Strape/DP/HDMI//CRT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 19 of 51
A B C D E
A B C D E

U8C U8D
DDR2 DDR2 DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 MAA[0..12] GDDR3/GDDR5 GDDR5/GDDR3 MAB[0..12]
MDA[0..63] DDR3 DDR3 MAA[0..12] 23 MDB[0..63] DDR3 DDR3 MAB[0..12] 24
23 MDA[0..63] 24 MDB[0..63]
MDA0 C37 G24 MAA0 MDB0 C5 P8 MAB0
MDA1 NC_DQA0_0/DQA_0 NC_MAA0_0/MAA_0 MAA1 MDB1 DQB0_0/DQB_0 MAB0_0/MAB_0 MAB1
C35 J23 C3 T9
MDA2 NC_DQA0_1/DQA_1 NC_MAA0_1/MAA_1 MAA2 MDB2 DQB0_1/DQB_1 MAB0_1/MAB_1 MAB2
A35 H24 E3 P9
MDA3 NC_DQA0_2/DQA_2 NC_MAA0_2/MAA_2 MAA3 MDB3 DQB0_2/DQB_2 MAB0_2/MAB_2 MAB3
E34 J24 E1 N7
NC_DQA0_3/DQA_3 NC_MAA0_3/MAA_3 DQB0_3/DQB_3 MAB0_3/MAB_3

MEMORY INTERFACE A
MDA4 G32 H26 MAA4 MDB4 F1 N8 MAB4
NC_DQA0_4/DQA_4 NC_MAA0_4/MAA_4 DQB0_4/DQB_4 MAB0_4/MAB_4

MEMORY INTERFACE B
MDA5 D33 J26 MAA5 MDB5 F3 N9 MAB5
MDA6 NC_DQA0_5/DQA_5 NC_MAA0_5/MAA_5 MAA6 MDB6 DQB0_5/DQB_5 MAB0_5/MAB_5 MAB6
F32 H21 F5 U9
MDA7 NC_DQA0_6/DQA_6 NC_MAA0_6/MAA_6 MAA7 MDB7 DQB0_6/DQB_6 MAB0_6/MAB_6 MAB7
E32 G21 G4 U8
MDA8 NC_DQA0_7/DQA_7 NC_MAA0_7/MAA_7 MAA8 MDB8 DQB0_7/DQB_7 MAB0_7/MAB_7 MAB8
D31 H19 H5 Y9
MDA9 NC_DQA0_8/DQA_8 NC_MAA1_0/MAA_8 MAA9 MDB9 DQB0_8/DQB_8 MAB1_0/MAB_8 MAB9
F30 H20 H6 W9
1 MDA10 NC_DQA0_9/DQA_9 NC_MAA1_1/MAA_9 MAA10 MDB10 DQB0_9/DQB_9 MAB1_1/MAB_9 MAB10 1
C30 L13 J4 AC8
MDA11 NC_DQA0_10/DQA_10 NC_MAA1_2/MAA_10 MAA11 MDB11 DQB0_10/DQB_10 MAB1_2/MAB_10 MAB11
A30 G16 K6 AC9
MDA12 NC_DQA0_11/DQA_11 NC_MAA1_3/MAA_11 MAA12 A_BA[0..2] MDB12 DQB0_11/DQB_11 MAB1_3/MAB_11 MAB12 B_BA[0..2]
F28 J16 A_BA[0..2] 23 K5 AA7 B_BA[0..2] 24
MDA13 NC_DQA0_12/DQA_12 NC_MAA1_4/MAA_12 A_BA2 MDB13 DQB0_12/DQB_12 MAB1_4/MAB_12 B_BA2
C28 H16 L4 AA8
+1.5VSG MDA14 NC_DQA0_13/DQA_13 NC_MAA1_5/MAA_13_BA2 A_BA0 MDB14 DQB0_13/DQB_13 MAB1_5/BA2 B_BA0
A28 J17 M6 Y8
MDA15 NC_DQA0_14/DQA_14 NC_MAA1_6/MAA_14_BA0 A_BA1 +1.5VSG MDB15 DQB0_14/DQB_14 MAB1_6/BA0 B_BA1
E28 H17 M1 AA9
MDA16 NC_DQA0_15/DQA_15 NC_MAA1_7/MAA_A15_BA1 DQMA#[0..7] MDB16 DQB0_15/DQB_15 MAB1_7/BA1 DQMB#[0..7]
D27 DQMA#[0..7] 23 M3 DQMB#[0..7] 24
MDA17 NC_DQA0_16/DQA_16 DQMA#0 MDB17 DQB0_16/DQB_16 DQMB#0
F26 A32 M5 H3
NC_DQA0_17/DQA_17 NC_WCKA0_0/DQMA_0 DQB0_17/DQB_17 WCKB0_0/DQMB_0
1

MDA18 C26 C32 DQMA#1 MDB18 N4 H1 DQMB#1


NC_DQA0_18/DQA_18 NC_WCKA0B_0/DQMA_1 DQB0_18/DQB_18 WCKB0B_0/DQMB_1

1
R446 MDA19 A26 D23 DQMA#2 MDB19 P6 T3 DQMB#2
MDA20 NC_DQA0_19/DQA_19 NC_WCKA0_1/DQMA_2 DQMA#3 R447 MDB20 DQB0_19/DQB_19 WCKB0_1/DQMB_2 DQMB#3
F24 E22 P5 T5
40.2_0402_1% MDA21 NC_DQA0_20/DQA_20 NC_WCKA0B_1/DQMA_3 DQMA#4 MDB21 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 DQMB#4
15mil MDA22
C24
NC_DQA0_21/DQA_21 NC_WCKA1_0/DQMA_4
C14
DQMA#5 40.2_0402_1% MDB22
R4
DQB0_21/DQB_21 WCKB1_0/DQMB_4
AE4
DQMB#5
A24 A14 15mil T6 AF5
2

MVREFDA MDA23 NC_DQA0_22/DQA_22 NC_WCKA1B_0/DQMA_5 DQMA#6 MDB23 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 DQMB#6


E24 E10 T1 AK6

2
MDA24 NC_DQA0_23/DQA_23 NC_WCKA1_1/DQMA_6 DQMA#7 MVREFDB MDB24 DQB0_23/DQB_23 WCKB1_1/DQMB_6 DQMB#7
C22 NC_DQA0_24/DQA_24 NC_WCKA1B_1/DQMA_7 D9 U4 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 AK5
1

1 MDA25 A22 QSA[0..7] MDB25 V6 QSB[0..7]


NC_DQA0_25/DQA_25 QSA[0..7] 23 DQB0_25/DQB_25 QSB[0..7] 24

1
GDDR5/DDR2/GDDR3 GDDR5/DDR2/GDDR3
0.1U_0402_16V4Z
C355

R448 MDA26 F22 C34 QSA0 MDB26 V1 F6 QSB0


MDA27 NC_DQA0_26/DQA_26 NC_EDCA0_0/QSA_0/RDQSA_0 QSA1 MDB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 QSB1
D21 NC_DQA0_27/DQA_27 NC_EDCA0_1/QSA_1/RDQSA_1 D29 1 V3 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 K3

0.1U_0402_16V4Z
C356
100_0402_1% MDA28 A20 D25 QSA2 R449 MDB28 Y6 P3 QSB2
2 MDA29 NC_DQA0_28/DQA_28 NC_EDCA0_2/QSA_2/RDQSA_2 QSA3 100_0402_1% MDB29 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 QSB3
F20 E20 Y1 V5
2

MDA30 NC_DQA0_29/DQA_29 NC_EDCA0_3/QSA_3/RDQSA_3 QSA4 MDB30 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 QSB4


D19 E16 Y3 AB5

2
MDA31 NC_DQA0_30/DQA_30 NC_EDCA1_0/QSA_4/RDQSA_4 QSA5 2 MDB31 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 QSB5
E18 NC_DQA0_31/DQA_31 NC_EDCA1_1/QSA_5/RDQSA_5 E12 Y5 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AH1
MDA32 C18 J10 QSA6 MDB32 AA4 AJ9 QSB6
MDA33 NC_DQA1_0/DQA_32 NC_EDCA1_2/QSA_6/RDQSA_6 QSA7 MDB33 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 QSB7
A18 NC_DQA1_1/DQA_33 NC_EDCA1_3/QSA_7/RDQSA_7 D7 AB6 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 AM5
MDA34 F18 QSA#[0..7] MDB34 AB1 QSB#[0..7]
+1.5VSG NC_DQA1_2/DQA_34 QSA#[0..7] 23 DQB1_2/DQB_34 QSB#[0..7] 24
MDA35 D17 A34 QSA#0 MDB35 AB3 G7 QSB#0
MDA36 NC_DQA1_3/DQA_35 NC_DDBIA0_0/QSA_0B/WDQSA_0 QSA#1 +1.5VSG MDB36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 QSB#1
A16 NC_DQA1_4/DQA_36 NC_DDBIA0_1/QSA_1B/WDQSA_1 E30 AD6 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 K1
MDA37 F16 E26 QSA#2 MDB37 AD1 P1 QSB#2
MDA38 NC_DQA1_5/DQA_37 NC_DDBIA0_2/QSA_2B/WDQSA_2 QSA#3 MDB38 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 QSB#3
D15 NC_DQA1_6/DQA_38 NC_DDBIA0_3/QSA_3B/WDQSA_3 C20 AD3 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 W4
1

MDA39 E14 C16 QSA#4 MDB39 AD5 AC4 QSB#4


NC_DQA1_7/DQA_39 NC_DDBIA1_0/QSA_4B/WDQSA_4 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4

1
R450 MDA40 F14 C12 QSA#5 MDB40 AF1 AH3 QSB#5
MDA41 NC_DQA1_8/DQA_40 NC_DDBIA1_1/QSA_5B/WDQSA_5 QSA#6 R451 MDB41 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 QSB#6
D13 NC_DQA1_9/DQA_41 NC_DDBIA1_2/QSA_6B/WDQSA_6 J11 AF3 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AJ8
40.2_0402_1% 15mil MDA42 F12 F8 QSA#7 MDB42 AF6 AM3 QSB#7
MDA43 NC_DQA1_10/DQA_42NC_DDBIA1_3/QSA_7B/WDQSA_7 40.2_0402_1% MDB43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
A12 15mil AG4
2

MVREFSA MDA44 NC_DQA1_11/DQA_43 ODTA0 MDB44 DQB1_11/DQB_43 ODTB0


2 D11 J21 ODTA0 23 AH5 T7 ODTB0 24 2

2
MDA45 NC_DQA1_12/DQA_44 NC_ADBIA0/ODTA0 ODTA1 MVREFSB MDB45 DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB1
F10 NC_DQA1_13/DQA_45 NC_ADBIA1/ODTA1 G19 ODTA1 23 AH6 DQB1_13/DQB_45 ADBIB1/ODTB1 W7 ODTB1 24
1

1 MDA46 A10 MDB46 AJ4


NC_DQA1_14/DQA_46 DQB1_14/DQB_46

1
0.1U_0402_16V4Z
C357

R452 MDA47 C10 H27 CLKA0 1 MDB47 AK3 L9 CLKB0


NC_DQA1_15/DQA_47 NC_CLKA0 CLKA0 23 DQB1_15/DQB_47 CLKB0 CLKB0 24

0.1U_0402_16V4Z
C358
MDA48 G13 G27 CLKA0# R453 MDB48 AF8 L8 CLKB0#
NC_DQA1_16/DQA_48 NC_CLKA0B CLKA0# 23 DQB1_16/DQB_48 CLKB0B CLKB0# 24
100_0402_1% MDA49 H13 MDB49 AF9
2 MDA50 NC_DQA1_17/DQA_49 CLKA1 100_0402_1% MDB50 DQB1_17/DQB_49 CLKB1
J13 J14 CLKA1 23 AG8 AD8 CLKB1 24
2

MDA51 NC_DQA1_18/DQA_50 NC_CLKA1 CLKA1# 2 MDB51 DQB1_18/DQB_50 CLKB1 CLKB1#


H11 H14 CLKA1# 23 AG7 AD7 CLKB1# 24

2
MDA52 NC_DQA1_19/DQA_51 NC_CLKA1B MDB52 DQB1_19/DQB_51 CLKB1B
G10 AK9
MDA53 NC_DQA1_20/DQA_52 RASA0# MDB53 DQB1_20/DQB_52 RASB0#
G8 K23 RASA0# 23 AL7 T10 RASB0# 24
MDA54 NC_DQA1_21/DQA_53 NC_RASA0B RASA1# MDB54 DQB1_21/DQB_53 RASB0B RASB1#
K9 K19 RASA1# 23 AM8 Y10 RASB1# 24
MDA55 NC_DQA1_22/DQA_54 NC_RASA1B MDB55 DQB1_22/DQB_54 RASB1B
K10 AM7
MDA56 NC_DQA1_23/DQA_55 CASA0# MDB56 DQB1_23/DQB_55 CASB0#
G9 K20 CASA0# 23 AK1 W10 CASB0# 24
MDA57 NC_DQA1_24/DQA_56 NC_CASA0B CASA1# MDB57 DQB1_24/DQB_56 CASB0B CASB1#
A8 K17 CASA1# 23 AL4 AA10 CASB1# 24
MDA58 NC_DQA1_25/DQA_57 NC_CASA1B MDB58 DQB1_25/DQB_57 CASB1B
C8 AM6
MDA59 NC_DQA1_26/DQA_58 CSA0#_0 MDB59 DQB1_26/DQB_58 CSB0#_0
E8 K24 CSA0#_0 23 AM1 P10 CSB0#_0 24
MDA60 NC_DQA1_27/DQA_59 NC_CSA0B_0 MDB60 DQB1_27/DQB_59 CSB0B_0
A6 K27 AN4 L10
MDA61 NC_DQA1_28/DQA_60 NC_CSA0B_1 MDB61 DQB1_28/DQB_60 CSB0B_1
C6 AP3
MDA62 NC_DQA1_29/DQA_61 CSA1#_0 MDB62 DQB1_29/DQB_61 CSB1#_0
E6 M13 CSA1#_0 23 AP1 AD10 CSB1#_0 24
MDA63 NC_DQA1_30/DQA_62 NC_CSA1B_0 MDB63 DQB1_30/DQB_62 CSB1B_0
A5 K16 AP5 AC10
NC_DQA1_31/DQA_63 NC_CSA1B_1 DQB1_31/DQB_63 CSB1B_1
MVREFDA L18 K21 CKEA0 U10 CKEB0
+1.5VSG NC_MVREFDA NC_CKEA0 CKEA0 23 CKEB0 CKEB0 24
MVREFSA L20 J20 CKEA1 MVREFDB Y12 AA11 CKEB1
NC_MVREFSA NC_CKEA1 CKEA1 23 MVREFDB CKEB1 CKEB1 24
MVREFSB AA12
WEA0# MVREFSB WEB0#
1 2 L27 K26 WEA0# 23 N10 WEB0# 24
R454 NC_MEM_CALRN0 NC_WEA0B WEB0B
1 2 243_0402_1% N12 L15 WEA1#
WEA1# 23 AB11 WEB1#
WEB1# 24
R455 MEM_CALRN1 NC_WEA1B WEB1B
1 2 243_0402_1% AG12 R459
R456 243_0402_1% NC_MEM_CALRN2 5.11K_0402_1%
1 2 M12 H23 2 1 TESTEN AD28 T8
MEM_CALRP1 NC_MAA0_8 MAA13 23 TESTEN MAB0_8 MAB13 24
R457 1 2 243_0402_1% M27 J19 W8
R458 NC_MEM_CALRP0 NC_MAA1_8 MAB1_8
1 2 243_0402_1% AH12 TEST_MCLK AK10 R461 10_0402_5%

GDDR5
NC_MEM_CALRP2 CLKTESTA
GDDR5

R460 243_0402_1% TEST_YCLK AL10 AH11 1 2 1 2


CLKTESTB DRAM_RST VRAM_RST# 23,24
R462 51.1_0402_1%

0.1U_0402_16V4Z

0.1U_0402_16V4Z
3 2 2 3

2
C360

C361
1
@ @ R463 C359
1 1 2160809000A11SEYMOU_FCBGA962 5.11K_0402_1% 120P_0402_50V8
2160809000A11SEYMOU_FCBGA962 2

1
1

1
R464 R465
@ @ Place all these components very close
51.1_0402_1% 51.1_0402_1%
to GPU (Within 25mm) and

2
keep all component close to
each Other (within5mm) except Rser2
Note:
route 50ohms single-ended
and 100ohms diff
and keep short
REF137-03 suggest Park&Seymour is single channel for
memory (channel B only)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/12 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Vancouver_Memory
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom QBL70 LA-7553P 0.22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 20 of 51
A B C D E
A B C D E

Seymour/Whistler :
U8E PCIE_VDDR,PCIE_PVDD can combian to PCIE_VDDR
+1.5VSG
MEM I/O
1 SM010014520 3000ma 220ohm@100mhz DCR 0.04

1U_0402_6.3V6K
C363
PCIE
1 1 1 1 1 1 1 1 40mil

1U_0402_6.3V6K
C375

1U_0402_6.3V6K
C376

1U_0402_6.3V6K
C362

1U_0402_6.3V6K
C377

1U_0402_6.3V6K
C378

1U_0402_6.3V6K
C379

1U_0402_6.3V6K
C380
+ AC7 AA31 +PCIE_VDDR 2 1
VDDR1#1 PCIE_VDDR#1 +1.8VSG
C374 AD11 AA32 L128
330U_2.5V_M VDDR1#2 PCIE_VDDR#2 FBMA-L11-201209-221LMA30T_0805
AF7 VDDR1#3 PCIE_VDDR#3 AA33 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2

0.1U_0402_16V4Z
C381

0.1U_0402_16V4Z
C382

1U_0402_6.3V6K
C364

1U_0402_6.3V6K
C383

1U_0402_6.3V6K
C365

10U_0603_6.3V6M
C384
AG10 VDDR1#4 PCIE_VDDR#4 AA34 220ohm/2A
AJ7 VDDR1#5 440mA PCIE_VDDR#5 V28
AK8 VDDR1#6 PCIE_VDDR#6 W29
C374 change to SF000002Z00 2 2 2 2 2 2
AL9 VDDR1#7 PCIE_VDDR#7 W30
20101228 G11 Y31
VDDR1#8 PCIE_VDDR#8

1U_0402_6.3V6K
C390
1 1 1 1 1 1 1 1 G14 VDDR1#9 PCIE_VDDR/PCIE_PVDD AB37

1U_0402_6.3V6K
C385

1U_0402_6.3V6K
C366

1U_0402_6.3V6K
C386

1U_0402_6.3V6K
C387

1U_0402_6.3V6K
C388

1U_0402_6.3V6K
C367

1U_0402_6.3V6K
C389
1 G17 VDDR1#10
1
G20 VDDR1#11 PCIE_VDDC#1 G30 +1.0VSG
G23 VDDR1#12 PCIE_VDDC#2 G31
2 2 2 2 2 2 2 2
G26 VDDR1#13 PCIE_VDDC#3 H29 1 1 1 1 1 1 1 1

1U_0402_6.3V6K
C391

1U_0402_6.3V6K
C392

1U_0402_6.3V6K
C368

1U_0402_6.3V6K
C393

1U_0402_6.3V6K
C369

1U_0402_6.3V6K
C370

1U_0402_6.3V6K
C394

10U_0603_6.3V6M
C395
G29 VDDR1#14 PCIE_VDDC#4 H30
H10 VDDR1#15 PCIE_VDDC#5 J29
J7 VDDR1#16 3400mA 2A PCIE_VDDC#6 J30
2 2 2 2 2 2 2 2

1U_0402_6.3V6K
C401
1 1 1 1 1 1 1 1 1 J9 VDDR1#17 PCIE_VDDC#7 L28

10U_0603_6.3V6M
C396

10U_0603_6.3V6M
C371

10U_0603_6.3V6M
C372

10U_0603_6.3V6M
C373

10U_0603_6.3V6M
C397

1U_0402_6.3V6K
C398

1U_0402_6.3V6K
C399

1U_0402_6.3V6K
C400
K11 VDDR1#18 PCIE_VDDC#8 M28
K13 VDDR1#19 PCIE_VDDC#9 N28
K8 VDDR1#20 PCIE_VDDC#10 R28
2 2 2 2 2 2 2 2 2
L12 VDDR1#21 PCIE_VDDC#11 T28
L16 VDDR1#22 PCIE_VDDC#12 U28
L21 VDDR1#23
L23 VDDR1#24 Granville VDDC:47A
L26 VDDR1#25 VDDC#1 AA15 +VGA_CORE

1U_0402_6.3V6K
C405

1U_0402_6.3V6K
C406

1U_0402_6.3V6K
C407

1U_0402_6.3V6K
C408

1U_0402_6.3V6K
C409

1U_0402_6.3V6K
C410

1U_0402_6.3V6K
C411

1U_0402_6.3V6K
C412

1U_0402_6.3V6K
C413

1U_0402_6.3V6K
C414
L7 CORE AA17 1 1 1 1 1 1 1 1 1 1
VDDR1#26 VDDC#2
M11 VDDR1#27 VDDC#3 AA20
N11 VDDR1#28 VDDC#4 AA22
P7 VDDR1#29 VDDC#5 AA24
2 2 2 2 2 2 2 2 2 2 Granville PRO VDDC:47A
SM010030010 R11 VDDR1#30 VDDC#6 AA27
Madison PRO VDDC+VDDCI=31.3A
+1.8VSG 12 U11 VDDR1#31 VDDC#7 AB16
300ma 120ohm@100mhz DCR 0.3 120ohm/0.3A L129 U7 VDDR1#32 VDDC#8 AB18 Whistler PRO VDDC+VDDCI=24A
BLM18AG121SN1D_0603 1 1 1 Y11 AB21
VDDR1#33 VDDC#9
SeymourXT VDDC+VDDCI=14.2A

0.1U_0402_16V4Z
C404
Y7 VDDR1#34 VDDC#10 AB23

10U_0603_6.3V6M
C402

1U_0402_6.3V6K
C403

1U_0402_6.3V6K
C416

1U_0402_6.3V6K
C417

1U_0402_6.3V6K
C418

1U_0402_6.3V6K
C419

1U_0402_6.3V6K
C420

1U_0402_6.3V6K
C421

1U_0402_6.3V6K
C422

1U_0402_6.3V6K
C423

1U_0402_6.3V6K
C424

1U_0402_6.3V6K
C425
AB26 1 1 1 1 1 1 1 1 1 1
VDDC#11
AB28
RobsonXT VDDC+VDDCI=12.9A
2 2 2 VDDC#12
VDDC#13 AC17
VDDC#14 AC20
LEVEL 2 2 2 2 2 2 2 2 2 2
20mil TRANSLATION VDDC#15 AC22
VDDC#16 AC24

POWER
Ref137-12~ remove Bead +VDD_CT AF26 AC27
VDD_CT#1 VDDC#17
AF27 VDD_CT#2 VDDC#18 AD18

10U_0603_6.3V6M
C428

10U_0603_6.3V6M
C429

10U_0603_6.3V6M
C430

10U_0603_6.3V6M
C431

10U_0603_6.3V6M
C432

10U_0603_6.3V6M
C433

10U_0603_6.3V6M
C434
+3VSG AG26 VDD_CT#3 219mA VDDC#19 AD21 1 1 1 1 1 1 1 1 1 1 1
2
AG27 VDD_CT#4 VDDC#20 AD23 2
1 1 1 AD26 C435 + C436 + C474 + C560 +
VDDC#21

0.1U_0402_16V4Z
C427
VDDC#22 AF17
2 2 2 2 2 2 2

10U_0603_6.3V6M
C415

1U_0402_6.3V6K
C426
I/O AF20 330U_D2_2V_Y330U_D2_2V_Y 390U_2.5V_10M
VDDC#23 2 2 2
390U_2.5V_10M2
AF23 VDDR3#1 VDDC#24 AF22
2 2 2
10mil AF24 VDDR3#2 VDDC#25 AG16
AG23 VDDR3#3 60mA VDDC#26 AG18
AG24 VDDR3#4 VDDC#27 AG21
SM010030010 20mil 47A VDDC#28 AH22
VDDC#29 AH27
300ma 120ohm@100mhz DCR 0.3 +1.8VSG 2 1 +VDDR4_5 AF13 AH28
L16 VDDR4#4 VDDC#30
AF15 VDDR4#5 VDDC#31 M26 BIF_VDDC
120ohm/0.3ABLM18AG121SN1D_0603 1 1 1 AG13 VDDR4#7 VDDC#32 N24 Park/Madison:Connect to VDDC
10U_0603_6.3V6M
C437

1U_0402_6.3V6K
C438

0.1U_0402_16V4Z
C439 AG15 N27 +BIF_VDDC +BIF_VDDC
VDDR4#8 VDDC/BIF_VDDC#33 Seymour/Whisler:
170mA VDDC#34 R18
2 2 2 VDDC#35 R21 dGPU operating:VDDC
AD12 VDDR4#1 VDDC#36 R23 BACO mode:+1.0V
AF11 VDDR4#2 55mA VDDC#37 R26
AF12 VDDR4#3 VDDC#38 T17
AG11 VDDR4#6 VDDC#39 T20 2010/04/27
VDDC#40 T22 non-BACO design,N27,T27
VDDC#41 T24
470ohm/1A T27 connect BIF_VDDC to VDDC
VDDC/BIF_VDDC#42
VDDC#43 U16 For BACO design
SM010030010 M20 NC_VDDRHA VDDC#44 U18
M21 NC_VSSRHA VDDC#45 U21
200ma 120ohm@100mhz DCR 0.2 VDDC#46 U23
VDDC#47 U26
L17 V12 V17
NC_VDDRHB VDDC#48
+1.8VSG 2 1 U12 NC_VSSRHB VDDC#49 V20
BLM18AG121SN1D_0603 V22
VDDC#50
1 1 1 1 1 VDDC#51 V24
10U_0603_6.3V6M
C440

1U_0402_6.3V6K
C441

0.1U_0402_16V4Z
C442

1U_0402_6.3V6K
C443

0.1U_0402_16V4Z
C444

VDDC#52 V27 VDDCI and VDDC should have seperate regulators with a merge option on PCB
VDDC#53 Y16
PLL Y18 For Madison and Park, VDDCI and VDDC can share one common regulator
2 2 2 2 2 VDDC#54
3
VDDC#55 Y21 3

VDDC#56 Y23 (GDDR3/DDR3 1.12V@4A VDDCI)


SM010030010 20mil +MPV_18
H7 MPV18#1 VDDC#57 Y26
(GDDR5 1.12V@16A VDDCI)
200ma 120ohm@100mhz DCR 0.2
H8 MPV18#2 150mA VDDC#58 Y28 SM01000BY00 5000ma 120ohm@100mhz DCR 0.02
L20 10mil Granville VDDCI:4.6A
+1.8VSG 2 1 +SPV_18 AM10 75mA 160mil
BLM18AG121SN1D_0603 L18 SPV18 +VDDCI
20mil +SPV10 VDDCI#1 AA13 2 1 +VGA_CORE
1 1 1 +1.0VSG 2 1 AN9 SPV10 120mA VDDCI#2 AB13
10U_0603_6.3V6M
C458

1U_0402_6.3V6K
C459

0.1U_0402_16V4Z
C460

AC12 1 1 1 1 1 1 1 1 1 1 L19 Seymour/Whistler


VDDCI#3
10U_0603_6.3V6M
C445

1U_0402_6.3V6K
C446

0.1U_0402_16V4Z
C447

1U_0402_6.3V6K
C448

1U_0402_6.3V6K
C449

1U_0402_6.3V6K
C450

1U_0402_6.3V6K
C451

1U_0402_6.3V6K
C452

1U_0402_6.3V6K
C453

1U_0402_6.3V6K
C454

1U_0402_6.3V6K
C455

1U_0402_6.3V6K
C456

1U_0402_6.3V6K
C457
BLM18AG121SN1D_0603 1 1 1 AN10 AC15 FBMA-L11-201209-121LMA50T_0805
SPVSS VDDCI#4
VDDCI#5 AD13 2 1
2 2 2
470ohm/1A VDDCI#6 AD16
2 2 2 2 2 2 2 2 2 2 L21
SM010030010 2 2 2 VDDCI#7 M15
M16 FBMA-L11-201209-121LMA50T_0805
200ma 120ohm@100mhz DCR 0.2 VOLTAGE VDDCI#8
SENESE
5A VDDCI#9 M18
VDDCI#10 M23

GCORE_SEN
10mil VDDCI#11 N13
48 GCORE_SEN AF28 FB_VDDC VDDCI#12 N15
VDDCI#13 N17
VDDCI#14 N20
AG28 FB_VDDCI N22
ISOLATED VDDCI#15

1U_0402_6.3V6K
C461

0.1U_0402_16V4Z
C462

10U_0603_6.3V6M
C463

10U_0603_6.3V6M
C464

10U_0603_6.3V6M
C465
NC 20101116 R12
CORE I/O VDDCI#16 R13
VDDCI#17 1 1 1 1 1
FB_GND AH29 R16
FB_GND VDDCI#18
VDDCI#19 T12
1

VDDCI#20 T15
@ 2 2 2 2 2
VDDCI#21 V15
R466 Y13
0_0402_5% VDDCI#22
2

2160809000A11SEYMOU_FCBGA962

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/12 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Vancouver_Power/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 21 of 51
A B C D E
A B C D E

U8F
DPA_VDD18,DPA_PVDD,DPB_VDD18,DPB_PVDD Seymour/Whistler :
can combian to DPAB_VDD18 DPA_VDD10,DPB_VDD10
DPC_VDD18,DPC_PVDD,DPD_VDD18,DPD_PVDD can combian to DPAB_VDD10
AB39 PCIE_VSS#1 GND#1 A3 can combian to DPCD_VDD18 DPC_VDD10,DPD_VDD10
E39 PCIE_VSS#2 GND#2 A37 (DPD_VDD18,DPD_PVDD not applicable on Robson/Park) can combian to DPCD_VDD10
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18 DPE_VDD18,DPE_PVDD,DPF_VDD18,DPF_PVDD DPE_VDD10,DPD_VDD10
G33 PCIE_VSS#5 GND#5 AA2 can combian to DPEF_VDD18 can combian to DPEF_VDD10
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
H34 AA26
H39
PCIE_VSS#8 GND#8
AA28
DPx-VSSR,DPx_PVSS can combian to DP_VSSR
PCIE_VSS#9 GND#9
1
J31
PCIE_VSS#10 GND#10
AA6 (Manhatann should have individual GND) 1
J34 AB12
K31
PCIE_VSS#11 GND#11
AB15 where x is A,B,C,D,E,F
PCIE_VSS#12 GND#12
K34 AB17
PCIE_VSS#13 GND#13 U8H
K39
PCIE_VSS#14 GND#14
AB20 SM01000BL00
L31 AB22 1000ma 470ohm@100mhz DCR 0.2
PCIE_VSS#15 GND#15 DP C/D POWER DP A/B POWER
L34 AB24
PCIE_VSS#16 GND#16 L23
M34
PCIE_VSS#17 GND#17
AB27 Manhatann:300mA 20mil 20mil MBK1608221YZF_2P
M39
PCIE_VSS#18 GND#18
AC11
Seymour:150mA +DPABCD_VDD18
AP20
DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1
AN24
+DPABCD_VDD18
300mA
N31 AC13 AP21 AP24 2 1 +1.8VSG
PCIE_VSS#19 GND#19 DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2
N34 AC16
PCIE_VSS#20 GND#20
P31 AC18 1 1 1
PCIE_VSS#21 GND#21
P34 PCIE_VSS#22 GND#22 AC2 20mil 20mil FootPrint

10U_0603_6.3V6M
C469

0.1U_0402_16V4Z
C470

1U_0402_6.3V6K
C471
P39 PCIE_VSS#23 GND#23 AC21 AP13 DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 AP31
R34 AC23 +DPABCD_VDD10 AT13 AP32 +DPABCD_VDD10
PCIE_VSS#24 GND#24 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2 2 2 2
T31 PCIE_VSS#25 GND#25 AC26
T34 PCIE_VSS#26 GND#26 AC28
T39 PCIE_VSS#27 GND#27 AC6 AN17 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AN27
U31 PCIE_VSS#28 GND#28 AD15 AP16 DP/DPC_VSSR#2 DP/DPA_VSSR#2 AP27
U34 PCIE_VSS#29 GND#29 AD17 AP17 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AP28
V34 PCIE_VSS#30 GND#30 AD20 AW14 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW24
V39 PCIE_VSS#31 GND#31 AD22 AW16 DP/DPC_VSSR#5 DP/DPA_VSSR#5 AW26
W31 PCIE_VSS#32 GND#32 AD24
W34 PCIE_VSS#33 GND#33 AD27
Y34 PCIE_VSS#34 GND#34 AD9 20mil 20mil
Y39 PCIE_VSS#35 GND#35 AE2 AP22 DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1 AP25
AE6 +DPABCD_VDD18 AP23 AP26 +DPABCD_VDD18 SM01000BL00
GND#36 DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2
GND#37 AF10 1000ma 470ohm@100mhz DCR 0.2
GND#38 AF16 20mil
AF18 20mil L25
GND#39 +DPABCD_VDD10 MBK1608221YZF_2P
AF21 Manhatann:220mA AP14 AN33 220mA
F15 GND#100
GND GND#40
GND#41
GND#42
AG17
AG2 Seymour:110mA
AP15
DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2
DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2 AP33 +DPABCD_VDD10 2 1 +1.0VSG
2 2
F17 GND#101 GND#43 AG20
F19 GND#102 GND#44 AG22 1 1 1 FootPrint

0.1U_0402_16V4Z
C475

1U_0402_6.3V6K
C476

10U_0603_6.3V6M
C477
F21 GND#103 GND#45 AG6 AN19 DP/DPD_VSSR#1 DP/DPB_VSSR#1 AN29
F23 GND#104 GND#46 AG9 AP18 DP/DPD_VSSR#2 DP/DPB_VSSR#2 AP29
F25 GND#105 GND#47 AH21 AP19 DP/DPD_VSSR#3 DP/DPB_VSSR#3 AP30
F27 AJ10 AW20 AW30 2 2 2
GND#106 GND#48 DP/DPD_VSSR#4 DP/DPB_VSSR#4
F29 GND#107 GND#49 AJ11 AW22 DP/DPD_VSSR#5 DP/DPB_VSSR#5 AW32
F31 AJ2
GND#108 GND#50 R467 R468
F33 AJ28
GND#109 GND#51 150_0402_1% 150_0402_1%
F7
GND#110 GND#52
AJ6 SM01000BL00 DP mode:300mA
F9 AK11 1000ma 470ohm@100mhz DCR 0.2 2 1 AW18 AW28 1 2
GND#111 GND#53 LVDS mode:440mA DPCD_CALR DPAB_CALR
G2 AK31
GND#112 GND#54 L26
G6
GND#113 GND#55
AK7 20mil 20mA
H9 AL11 MBK1608221YZF_2P DP E/F POWER DP PLL POWER 10mil
GND#114 GND#56 +DPEF_VDD18 +DPABCD_VDD18
J2 AL14 +1.8VSG 2 1 AH34 AU28
GND#115 GND#57 DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD
J27 AL17 AJ34 AV27
GND#116 GND#58 DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS
J6 AL2 1 1 1
GND#117 GND#59

10U_0603_6.3V6M
C478

1U_0402_6.3V6K
C479

0.1U_0402_16V4Z
C480
J8
GND#118 GND#60
AL20 FootPrint 20mil 20mA
K14 AL21 PX_EN 10mil
GND#119 GND/PX_EN#61 PX_EN 25,32 +DPEF_VDD10 +DPABCD_VDD18
K7 AL23 AL33 AV29
GND#120 GND#62 2 2 2 DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD
L11
GND#121 GND#63
AL26 PX_EN: PU at P.20 AM33
DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS
AR28
L17 AL32
L2
GND#122 GND#64
AL6 SBIOS will control VGA power on/off. 20mA
GND#123 GND#65
L22
GND#124 GND#66
AL8 High :BACO mode enable +DPABCD_VDD18
10mil
L24 AM11 AN34 AU18
GND#125 GND#67 LOW:BACO disable DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD
L6 AM31 AP39 AV17
GND#126 GND#68 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS
M17 AM9 AR39
GND#127 GND#69 DP/DPE_VSSR#3
M22
GND#128 GND#70
AN11 AU37
DP/DPE_VSSR#4 20mA
M24
GND#129 GND#71
AN2
+DPABCD_VDD18
10mil
N16 AN30 AV19
GND#130 GND#72 DPCD_VDD18/DPD_PVDD
N18 AN6 AR18
GND#131 GND#73 DP_VSSR/DPD_PVSS
3
N2
GND#132 GND#74
AN8 20mil 3
N21
GND#133 GND#75
AP11
+DPEF_VDD18
AF34
DPEF/DPF_VDD18#1 20mA
N23
GND#134 GND#76
AP7 SM01000BL00 AG34
DPEF/DPF_VDD18#2 10mil
N26 AP9 AM37 +DPEF_VDD18
GND#135 GND#77 1000ma 470ohm@100mhz DCR 0.2 DPEF_VDD18/DPE_PVDD
N6
GND#136 GND#78
AR5 DP mode:220mA 20mil DP_VSSR/DPE_PVSS
AN38
R15 B11 L27
R17
GND#137 GND#79
B13 MBK1608221YZF_2P LVDS mode:240mA AK33 20mA
GND#138 GND#80 +DPEF_VDD10 DPEF/DPF_VDD10#1
R2
GND#139 GND#81
B15 +1.0VSG 2 1 AK34
DPEF/DPF_VDD10#2 +DPEF_VDD18
10mil
R20 B17 AL38
GND#140 GND#82 DPEF_VDD18/DPF_PVDD
R22 B19 1 1 1 AM35
GND#141 GND#83 DP_VSSR/DPF_PVSS
10U_0603_6.3V6M
C481

1U_0402_6.3V6K
C482

0.1U_0402_16V4Z
C483
R24
GND#142 GND#84
B21 FootPrint
R27 B23 AF39
GND#143 GND#85 DP/DPF_VSSR#1
R6 B25 AH39
GND#144 GND#86 2 2 2 DP/DPF_VSSR#2
T11 B27 AK39
GND#145 GND#87 DP/DPF_VSSR#3
T13 B29 AL34
GND#146 GND#88 DP/DPF_VSSR#4
T16 B31 AM34
GND#147 GND#89 DP/DPF_VSSR#5
T18 B33
GND#148 GND#90
T21 B7
GND#149 GND#91 R470
T23 B9
GND#150 GND#92
T26 C1 2 1 AM39
GND#151 GND#93 DPEF_CALR
U15 C39
GND#153 GND#94 150_0402_1%
U17 E35
GND#154 GND#95 2160809000A11SEYMOU_FCBGA962
U2 E5
GND#155 GND#96
U20 F11
GND#156 GND#97
U22 F13
GND#157 GND#98
U24
GND#158
U27
GND#159
U6
GND#160
V11
GND#161
V16
GND#163 Park/Madison :AL21left NC
V18
GND#164
V21
GND#165
4
V23 GND#166 Seymour/Whistler: 4
V26 GND#167
W2 GND#168
AL21:PX_EN
W6 GND#169 use to control discreate GPU regulators
Y15 GND#170
Y17 GND#171
for power express BACO mode
Y20 GND#172 Support BACO:
Y22 GND#173 VSS_MECH#1 A39
Y24 AW1 output High3.3V:turn off regulators (BACO mode on)
Y27
GND#174 VSS_MECH#2
AW39
Security Classification Compal Secret Data Compal Electronics, Inc.
U13
GND#175 VSS_MECH#3 output Low0V:turn on regulators (BACO mode off) 2010/07/12 2012/07/12 Title
GND#152 Issued Date Deciphered Date
V13 GND#162 need PD resistor Vancouver_Power/GND
2160809000A11SEYMOU_FCBGA962 No support BACO: THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
left NC DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
QBL70 LA-7553P 0.22
REF137-13 update MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 22 of 51
A B C D E
A B C D E

U11 U12 U13 U14

ZZZ X76L02@ VREFCA_A1 M8 E3 MDA22 VREFCA_A2 M8 E3 MDA25 VREFCA_A3 M8 E3 MDA35 VREFCA_A4 M8 E3 MDA48
ZZZ X76L01@ VREFDA_Q1 H1 VREFCA DQL0 MDA19 VREFDA_Q2 VREFCA DQL0 MDA30 VREFDA_Q3 VREFCA DQL0 MDA32 VREFDA_Q4 VREFCA DQL0 MDA51
VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDA21 F2 MDA24 F2 MDA38 F2 MDA55
MAA0 DQL2 MDA18 MAA0 DQL2 MDA29 MAA0 DQL2 MDA34 MAA0 DQL2 MDA54
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAA1 P7 H3 MDA23 MAA1 P7 H3 MDA26 MAA1 P7 H3 MDA37 MAA1 P7 H3 MDA50
MAA2 A1 DQL4 MDA16 MAA2 A1 DQL4 MDA31 MAA2 A1 DQL4 MDA36 MAA2 A1 DQL4 MDA52
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAA3 N2 G2 MDA20 MAA3 N2 G2 MDA27 MAA3 N2 G2 MDA39 MAA3 N2 G2 MDA49
MAA4 A3 DQL6 MDA17 MAA4 A3 DQL6 MDA28 MAA4 A3 DQL6 MDA33 MAA4 A3 DQL6 MDA53
1G SAM 2G SAM P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAA5 P2 MAA5 P2 MAA5 P2 MAA5 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAA7 R2 D7 MDA0 MAA7 R2 D7 MDA15 MAA7 R2 D7 MDA43 MAA7 R2 D7 MDA63
ZZZ X76L03@ ZZZ X76L04@ MAA8 A7 DQU0 MDA5 MAA8 A7 DQU0 MDA11 MAA8 A7 DQU0 MDA44 MAA8 A7 DQU0 MDA58
T8 C3 T8 C3 T8 C3 T8 C3
MAA9 A8 DQU1 MDA1 MAA9 A8 DQU1 MDA14 MAA9 A8 DQU1 MDA40 MAA9 A8 DQU1 MDA60
R3 C8 R3 C8 R3 C8 R3 C8
1 MAA10 A9 DQU2 MDA7 MAA10 A9 DQU2 MDA10 MAA10 A9 DQU2 MDA45 MAA10 A9 DQU2 MDA59 1
L7 C2 L7 C2 L7 C2 L7 C2
MAA11 A10/AP DQU3 MDA3 MAA11 A10/AP DQU3 MDA13 MAA11 A10/AP DQU3 MDA42 MAA11 A10/AP DQU3 MDA61
R7 A7 R7 A7 R7 A7 R7 A7
MAA12 A11 DQU4 MDA4 MAA12 A11 DQU4 MDA9 MAA12 A11 DQU4 MDA46 MAA12 A11 DQU4 MDA56
N7 A2 N7 A2 N7 A2 N7 A2
MAA13 A12 DQU5 MDA2 MAA13 A12 DQU5 MDA12 MAA13 A12 DQU5 MDA41 MAA13 A12 DQU5 MDA62
T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 MDA6 A13 DQU6 MDA8 A13 DQU6 MDA47 A13 DQU6 MDA57
1G HYNIX T7
A14 DQU7
A3 T7
A14 DQU7
A3 T7
A14 DQU7
A3 T7
A14 DQU7
A3
2G HYNIX M7
A15/BA3
M7
A15/BA3
M7
A15/BA3
M7
A15/BA3
+1.5VSG +1.5VSG +1.5VSG +1.5VSG

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2


20 A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9
20 A_BA1 BA1 VDD A_BA2 BA1 VDD A_BA2 BA1 VDD A_BA2 BA1 VDD
20 A_BA2 M3 G7 M3 G7 M3 G7 M3 G7
BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
MDA[0..63] N1 N1 N1 N1
20 MDA[0..63] CLKA0 VDD CLKA0 VDD CLKA1 VDD CLKA1 VDD
J7 CK VDD N9 J7 CK VDD N9 J7 CK VDD N9 J7 CK VDD N9
CLKA0# K7 R1 CLKA0# K7 R1 CLKA1# K7 R1 CLKA1# K7 R1
CK VDD CKEA0 CK VDD CK VDD CKEA1 CK VDD
20 CKEA0 K9 CKE/CKE0 VDD R9 K9 CKE/CKE0 VDD R9 20 CKEA1 K9 CKE/CKE0 VDD R9 K9 CKE/CKE0 VDD R9
+1.5VSG +1.5VSG +1.5VSG +1.5VSG

ODTA0_1 K1 A1 ODTA0_1 K1 A1 ODTA1_1 K1 A1 ODTA1_1 K1 A1


20 MAA[13..0] ODT/ODT0 VDDQ ODT/ODT0 VDDQ ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSA0#_0 L2 A8 L2 A8 CSA1#_0 L2 A8
20 CSA0#_0 CS/CS0 VDDQ RASA0# CS/CS0 VDDQ 20 CSA1#_0 CS/CS0 VDDQ RASA1# CS/CS0 VDDQ
20 RASA0# J3 C1 J3 C1 20 RASA1# J3 C1 J3 C1
RAS VDDQ CASA0# RAS VDDQ RAS VDDQ CASA1# RAS VDDQ
20 CASA0# K3 CAS VDDQ C9 K3 CAS VDDQ C9 20 CASA1# K3 CAS VDDQ C9 K3 CAS VDDQ C9
L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
20 WEA0# WE VDDQ WE VDDQ 20 WEA1# WE VDDQ WE VDDQ
20 DQMA#[7..0] VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA2 F3 H2 QSA3 F3 H2 QSA4 F3 H2 QSA6 F3 H2
QSA0 DQSL VDDQ QSA1 DQSL VDDQ QSA5 DQSL VDDQ QSA7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

20 QSA[7..0] DQMA#2 DQMA#3 DQMA#4 DQMA#6


E7 DML VSS A9 E7 DML VSS A9 E7 DML VSS A9 E7 DML VSS A9
DQMA#0 D3 B3 DQMA#1 D3 B3 DQMA#5 D3 B3 DQMA#7 D3 B3
2 DMU VSS DMU VSS DMU VSS DMU VSS 2
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#2 G3 J2 QSA#3 G3 J2 QSA#4 G3 J2 QSA#6 G3 J2
20 QSA#[7..0] QSA#0 DQSL VSS QSA#1 DQSL VSS QSA#5 DQSL VSS QSA#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9
20,24 VRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
R471 NC/ODT1 VSSQ R472 NC/ODT1 VSSQ R473 NC/ODT1 VSSQ R474 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J9 D1 J9 D1 J9 D1 J9 D1
NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
G1 G1 G1 G1
VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
+1.5VSG @ @ @ @
+1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG
Pull high for Madison and Park...
ODTA0_1
1

1
R484 R475 R476 R477 R478 R479 R480 R481 R482
56_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
3 ODTA0 2 3
20 ODTA0 1 1 2
R483 0_0402_5% 15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
2

2
R486 VREFCA_A1 VREFDA_Q1 VREFCA_A2 VREFDA_Q2 VREFCA_A3 VREFDA_Q3 VREFCA_A4 VREFDA_Q4
56_0402_1%
1

1
ODTA1 2 1 1 2 1 1 1 1 1 1 1 1
20 ODTA1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R485 0_0402_5% R487 C484 R488 R489 C486 R490 C487 R491 C488 R492 C489 R493 C490 R494 C491
4.99K_0402_1% 4.99K_0402_1% C485 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
ODTA1_1
2 2 2 2 2 2 2 2
2

2
+1.5VSG +1.5VSG +1.5VSG
+1.5VSG

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
C492

1U_0402_6.3V6K
C493

1U_0402_6.3V6K
C494

1U_0402_6.3V6K
C495

1U_0402_6.3V6K
C496

1U_0402_6.3V6K
C497

1U_0402_6.3V6K
C498

1U_0402_6.3V6K
C499

1U_0402_6.3V6K
C500

1U_0402_6.3V6K
C501

1U_0402_6.3V6K
C502

1U_0402_6.3V6K
C503

1U_0402_6.3V6K
C504

1U_0402_6.3V6K
C505

1U_0402_6.3V6K
C506
1 1 1 1 1

1U_0402_6.3V6K
C507

1U_0402_6.3V6K
C508

1U_0402_6.3V6K
C509

1U_0402_6.3V6K
C510

1U_0402_6.3V6K
C511
20 CLKA0 1 2
R495 56_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2
20 CLKA0# 1 2
R1794 56_0402_1%
+1.5VSG
1
+1.5VSG
C512
0.01U_0402_16V7K
2
1 10U_0603_6.3V6M 1 1 1
C519

10U_0603_6.3V6M
C520

10U_0603_6.3V6M
C517

10U_0603_6.3V6M
C518
4
1 1 1 1 4
10U_0603_6.3V6M
C513

10U_0603_6.3V6M
C514

10U_0603_6.3V6M
C515

10U_0603_6.3V6M
C516

20 CLKA1 1 2
R497 56_0402_1% 2 2 2 2
2 2 2 2

20 CLKA1# 1 2
R498 56_0402_1%
1
C521 Security Classification Compal Secret Data Compal Electronics, Inc.
0.01U_0402_16V7K Issued Date 2010/07/12 Deciphered Date 2012/07/12 Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel A
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 23 of 51
A B C D E
A B C D E

U15 U16 U17 U18

VREFCB_A1 M8 E3 MDB26 VREFCB_A2 M8 E3 MDB22 VREFCB_A3 M8 E3 MDB35 VREFCB_A4 M8 E3 MDB55


VREFDB_Q1 H1 VREFCA DQL0 MDB28 VREFDB_Q2 H1 VREFCA DQL0 MDB20 VREFDB_Q3 H1 VREFCA DQL0 MDB37 VREFDB_Q4 H1 VREFCA DQL0 MDB49
VREFDQ DQL1 F7 VREFDQ DQL1 F7 VREFDQ DQL1 F7 VREFDQ DQL1 F7
F2 MDB27 F2 MDB21 F2 MDB34 F2 MDB52
MAB0 DQL2 MDB31 MAB0 DQL2 MDB18 MAB0 DQL2 MDB39 MAB0 DQL2 MDB50
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAB1 P7 H3 MDB25 MAB1 P7 H3 MDB19 MAB1 P7 H3 MDB33 MAB1 P7 H3 MDB53
MAB2 A1 DQL4 MDB30 MAB2 A1 DQL4 MDB17 MAB2 A1 DQL4 MDB38 MAB2 A1 DQL4 MDB48
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAB3 N2 G2 MDB24 MAB3 N2 G2 MDB23 MAB3 N2 G2 MDB32 MAB3 N2 G2 MDB54
MAB4 A3 DQL6 MDB29 MAB4 A3 DQL6 MDB16 MAB4 A3 DQL6 MDB36 MAB4 A3 DQL6 MDB51
P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAB5 P2 MAB5 P2 MAB5 P2 MAB5 P2
MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAB7 R2 D7 MDB15 MAB7 R2 D7 MDB1 MAB7 R2 D7 MDB44 MAB7 R2 D7 MDB56
MAB8 A7 DQU0 MDB10 MAB8 A7 DQU0 MDB6 MAB8 A7 DQU0 MDB43 MAB8 A7 DQU0 MDB59
T8 C3 T8 C3 T8 C3 T8 C3
MAB9 A8 DQU1 MDB12 MAB9 A8 DQU1 MDB0 MAB9 A8 DQU1 MDB47 MAB9 A8 DQU1 MDB63
R3 C8 R3 C8 R3 C8 R3 C8
1 MAB10 A9 DQU2 MDB11 MAB10 A9 DQU2 MDB4 MAB10 A9 DQU2 MDB41 MAB10 A9 DQU2 MDB62 1
L7 C2 L7 C2 L7 C2 L7 C2
MAB11 A10/AP DQU3 MDB13 MAB11 A10/AP DQU3 MDB3 MAB11 A10/AP DQU3 MDB45 MAB11 A10/AP DQU3 MDB57
R7 A7 R7 A7 R7 A7 R7 A7
MAB12 A11 DQU4 MDB9 MAB12 A11 DQU4 MDB7 MAB12 A11 DQU4 MDB40 MAB12 A11 DQU4 MDB61
N7 A2 N7 A2 N7 A2 N7 A2
MAB13 A12 DQU5 MDB14 MAB13 A12 DQU5 MDB2 MAB13 A12 DQU5 MDB46 MAB13 A12 DQU5 MDB58
T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 MDB8 A13 DQU6 MDB5 A13 DQU6 MDB42 A13 DQU6 MDB60
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15/BA3 +1.5VSG A15/BA3 +1.5VSG A15/BA3 +1.5VSG A15/BA3 +1.5VSG

M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2


20 B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
20 B_BA1 BA1 VDD B_BA2 BA1 VDD B_BA2 BA1 VDD B_BA2 BA1 VDD
20 B_BA2 M3 G7 M3 G7 M3 G7 M3 G7
BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
MDB[0..63] K8 K8 K8 K8
20 MDB[0..63] VDD VDD VDD VDD
VDD N1 VDD N1 VDD N1 VDD N1
CLKB0 J7 N9 CLKB0 J7 N9 CLKB1 J7 N9 CLKB1 J7 N9
CLKB0# CK VDD CLKB0# CK VDD CLKB1# CK VDD CLKB1# CK VDD
K7 R1 K7 R1 K7 R1 K7 R1
CK VDD CKEB0 CK VDD CK VDD CKEB1 CK VDD
20 CKEB0 K9 CKE/CKE0 VDD R9 K9 CKE/CKE0 VDD R9 20 CKEB1 K9 CKE/CKE0 VDD R9 K9 CKE/CKE0 VDD R9
+1.5VSG +1.5VSG +1.5VSG +1.5VSG
20 MAB[13..0] ODTB0_1 ODTB0_1 ODTB1_1 ODTB1_1
K1 ODT/ODT0 VDDQ A1 K1 ODT/ODT0 VDDQ A1 K1 ODT/ODT0 VDDQ A1 K1 ODT/ODT0 VDDQ A1
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
20 CSB0#_0 CS/CS0 VDDQ RASB0# CS/CS0 VDDQ 20 CSB1#_0 CS/CS0 VDDQ RASB1# CS/CS0 VDDQ
20 RASB0# J3 C1 J3 C1 20 RASB1# J3 C1 J3 C1
RAS VDDQ CASB0# RAS VDDQ RAS VDDQ CASB1# RAS VDDQ
20 CASB0# K3 CAS VDDQ C9 K3 CAS VDDQ C9 20 CASB1# K3 CAS VDDQ C9 K3 CAS VDDQ C9
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
20 DQMB#[7..0] 20 WEB0# WE VDDQ WE VDDQ 20 WEB1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 H2 QSB2 F3 H2 QSB4 F3 H2 QSB6 F3 H2
QSB1 DQSL VDDQ QSB0 DQSL VDDQ QSB5 DQSL VDDQ QSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
20 QSB[7..0]
DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9
DQMB#1 DML VSS DQMB#0 DML VSS DQMB#5 DML VSS DQMB#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
2 2
VSS E1 VSS E1 VSS E1 VSS E1
20 QSB#[7..0] VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 J2 QSB#2 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2
QSB#1 DQSL VSS QSB#0 DQSL VSS QSB#5 DQSL VSS QSB#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9
20,23 VRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
R499 NC/ODT1 VSSQ R500 NC/ODT1 VSSQ R501 NC/ODT1 VSSQ R502 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 D1 243_0402_1% J9 D1 243_0402_1% J9 D1 243_0402_1% J9 D1
NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
G1 G1 G1 G1
VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
Pull high for Madison and Park... K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
@ @ @ @
+1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG
+1.5VSG +1.5VSG +1.5VSG +1.5VSG
1

1
ODTB0_1

1
R503 R504 R505 R506
R512 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% R507 R508 R509 R510
3 R511 56_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 3
ODTB02 1 1 2
20 ODTB0
2

2
0_0402_5%

2
VREFCB_A1 VREFDB_Q1 VREFCB_A2 VREFDB_Q2
R514 VREFCB_A3 VREFDB_Q3 VREFCB_A4 VREFDB_Q4
1

1
R513 56_0402_1% 1 1 1 1

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
ODTB12 1 1 2 R515 C522 R516 C523 R517 C524 R518 C525 1 1 1 1
20 ODTB1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% R519 C526 R520 C527 R521 C528 R522 C529
0_0402_5% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
ODTB1_1 2 2 2 2
2

2
2 2 2 2

2
R523 56_0402_1%
1 2 +1.5VSG +1.5VSG
20 CLKB0
+1.5VSG +1.5VSG

R524 56_0402_1%
20 CLKB0# 1 2 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
C531

1U_0402_6.3V6K
C532

1U_0402_6.3V6K
C533

1U_0402_6.3V6K
C534

1U_0402_6.3V6K
C535

1U_0402_6.3V6K
C536

1U_0402_6.3V6K
C537

1U_0402_6.3V6K
C538

1U_0402_6.3V6K
C539

1U_0402_6.3V6K
C540

1 1 1 1 1 1 1 1 1 1

1U_0402_6.3V6K
C541

1U_0402_6.3V6K
C542

1U_0402_6.3V6K
C543

1U_0402_6.3V6K
C544

1U_0402_6.3V6K
C545

1U_0402_6.3V6K
C546

1U_0402_6.3V6K
C547

1U_0402_6.3V6K
C548

1U_0402_6.3V6K
C549

1U_0402_6.3V6K
C550
1
C530 2 2 2 2 2 2 2 2 2 2
+1.5VSG 2 2 2 2 2 2 2 2 2 2
0.01U_0402_16V7K
2 +1.5VSG
R525
56_0402_1%
20 CLKB1 1 2 1 1 1 1
10U_0603_6.3V6M
C551

10U_0603_6.3V6M
C552

10U_0603_6.3V6M
C554

10U_0603_6.3V6M
C553

1 1 1 1
R526

10U_0603_6.3V6M
C555

10U_0603_6.3V6M
C556

10U_0603_6.3V6M
C557

10U_0603_6.3V6M
C558
56_0402_1%
2 2 2 2
20 CLKB1# 1 2
4 2 2 2 2 4

1
C559
0.01U_0402_16V7K
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/12 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 24 of 51
A B C D E
5 4 3 2 1

Power Sequence of Whistler and Seymour


VGA Muxless with BACO Status Mapping table
Normal mode BACO mode
SUSP#
PX_EN 0 1
+3VSG
1.5_VDDC_PWREN 1 0 VGA Power Enable Signal Mapping table
(JUMP form +3VS)
VDDC_EN 1 0 Whislter
VGA_ON 10ms
1.0_EN 0 1 VGA_PWR_ON source signal VGA_ON
D VGA_PWR_ON +3.3VSG ON ON +3.3VSG SUSP# D

+1.8VSG ON ON +1.8VSG VGA_PWR_ON


1.5_VDDC_PWREN
+1.0VSG ON ON +1.0VSG VGA_PWR_ON
+VGA_CORE +VGA_CORE ON OFF +VDDCI Combine with +VGA_CORE
+1.5VSG ON OFF +VGA_CORE 1.5_VDDC_PWREN
+1.5VSG
+BIF_VDDC +VGA_CORE +1.0VSG +1.5VSG 1.5_VDDC_PWREN
+1.0VSG
+1.8VSG 20ms

For PX sequence, >2mS delay is required between


PE_GPIO1 and VGA_PWR_ON

@
R649 1 2 0_0402_5%
+3VS C1103
PE_GPIO1
0.1U_0402_16V4Z
1 2
C C
VGA_PWR_ON >2ms

5
U19
VGA_PWR_ON 2

P
B 1.5_VDD_PWREN
Y 4 1.5_VDD_PWREN 38,48
+3VS R650 1 2 10K_0402_5% 1 A

G
NC7SZ08P5X_NL_SC70-5

3
1
D

22,32 PX_EN 1 2 2
R651 0_0402_5% G

1
S Q22

3
2N7002_SOT23
R1792
5.11K_0402_1% +5VS +5VS

2
Delay SUSP# 10ms
For VGA Power on control

2
32 VGA_ON 1 2 VGA_PWR_ON 38,42,45
R1793 0_0402_5%
R1795 R1796
1K_0402_5% 1K_0402_5%
@

1
R119 VDDC_EN
1 2 C1104 +3VS
13,32 PE_GPIO1
10K_0402_1% 0.1U_0402_16V4Z 1.0_EN
2 1

3
DMN66D0LDW-7_SOT363-6
Q23A

DMN66D0LDW-7_SOT363-6
Q23B
5
U20
B 1.5_VDD_PWREN B
1 2 2

P
R1797 0_0402_5% B
4 2 5
Y
13,48 VGA_PWRGD 1
A

4
From +VGA_CORE regulator NC7SZ08P5X_NL_SC70-5

3
+BIF_VDDC +VGA_CORE
+1.0VSG Q24 Q25
20mil 30mil @

D
3 1 1 3 1 2

S
R656 0_0805_5%
AO3416_SOT23-3 AO3416_SOT23-3 1

G
2

2
1.0_EN C1105
2 22U_0805_6.3V6M

C1105 Change to SE00000I10


VDDC_EN
20101228

2
G

G
30mil AO3416 NMOS
3 1 1 3 Vgs(th)(Max)= 1V

S
A Q26 Q114 Rds(on)(Max)= 22m ohm @Vgs=4.5V A
+VGA_CORE AO3416_SOT23-3 AO3416_SOT23-3

Q24 / Q25 / Q26 / Q27 change to SB00000FG10


20101228

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA power sequence and BACO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 25 of 51
5 4 3 2 1
5 4 3 2 1

+3VS +3VS_ANX
40mil +DVDD12 +DVDD33

D 1 2 D
R529 0_0805_5%

32
46
59

13
53
9
U3
+1.2VS +1.2VS_ANX +AVDD12 +AVDD33
40mil

DVDD12
DVDD12
DVDD12
DVDD12

DVDD33
DVDD33
1 AVDD12 AVDD33 8
AVDD33 25
1 2 AVDD33 33
R527 0_0805_5% 39
AVDD33
AVDD33 63

DP0_AUXN_C 60
8 DP0_AUXN_C DPRX_AUX_N
DP0_AUXP_C 61
8 DP0_AUXP_C DPRX_AUX_P
10 LVDS_HPD R1291 1 2 0_0402_5% 58 26 APU_TXOUT_CLK- APU_TXOUT_CLK- 27
+1.2VS_ANX +DVDD12 DP0_TXN0_C DPPX_HPD LVDS_CLKL_N APU_TXOUT_CLK+
L31
20mil 8 DP0_TXN0_C
DP0_TXP0_C
4 DPRX_LN0_N LVDS_CLKL_P 27
APU_TXOUT0-
APU_TXOUT_CLK+ 27
8 DP0_TXP0_C 3 DPRX_LN0_P LVDS_L0_N 19 APU_TXOUT0- 27
FBMA-L11-201209-221LMA30T_0805 DP0_TXN1_C 7 20 APU_TXOUT0+ APU_TXOUT0+ 27
8 DP0_TXN1_C DPRX_LN1_N LVDS_L0_P
2 1 0.1U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K DP0_TXP1_C 6 21 APU_TXOUT1- APU_TXOUT1- 27
8 DP0_TXP1_C DPRX_LN1_P LVDS_L1_N
2 2 2 2 1 1 1 22 APU_TXOUT1+ APU_TXOUT1+ 27
C286 C289 C292 C296 C317 C326 C327 LVDS_L1_P APU_TXOUT2-
LVDS_L2_N 23 APU_TXOUT2- 27
+3VS_ANX 1 2 CLK_SEL 10 CLK_SEL LVDS_L2_P 24 APU_TXOUT2+ APU_TXOUT2+ 27
R399 10K_0402_5% 12 28
1 1 1 1 2 2 2 13,18,31,35 PLT_RST# RESET_L LVDS_L3_N
27 TL_ENVDD TL_ENVDD 14 29
0.1U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K 2.2U_0603_6.3V6K DIGON LVDS_L3_P

+3VS_ANX 1 2
R404 1M_0402_5% 42 APU_TZOUT_CLK- APU_TZOUT_CLK- 27
LVDS_CLKU_N APU_TZOUT_CLK+
2 1 34 POR LVDS_CLKU_P 43 APU_TZOUT_CLK+ 27
C223 0.1U_0402_16V7K 35 APU_TZOUT0- APU_TZOUT0- 27
C LVDS_U0_N APU_TZOUT0+ C
LVDS_U0_P 36 APU_TZOUT0+ 27
+1.2VS_ANX +AVDD12 APU_TZOUT1-
L30
20mil T25 51 CFG_SCL LVDS_U1_N 37
APU_TZOUT1+
APU_TZOUT1- 27
T31 52 CFG_SDA LVDS_U1_P 38 APU_TZOUT1+ 27
FBMA-L11-201209-221LMA30T_0805 40 APU_TZOUT2- APU_TZOUT2- 27
0.1U_0402_16V7K 0.01U_0402_16V7K R403 1 LVDS_U2_N
2 1 2 10K_0402_5% 16 GPIO_0 LVDS_U2_P 41 APU_TZOUT2+ APU_TZOUT2+ 27
2 2 1 1 1 T26 17 GPIO_1 LVDS_U3_N 44
C337 C564 C336 C562 C349 T38 18 45
GPIO_2 LVDS_U3_P
2 1
R400 12K_0402_1%
1 1 2 2 2 R_BIAS APU_LVDS_CLK
1 2 64 R_BIAS DDC_CLK 49 APU_LVDS_CLK 27
0.1U_0402_16V7K 0.01U_0402_16V7K 2.2U_0603_6.3V6K C225 100P_0402_50V8J 50 APU_LVDS_DAT APU_LVDS_DAT 27
DDC_DATA

T39 55 TDI
20mil +DVDD33 T50 57 15 TL_BKOFF# TL_BKOFF# 27,32
+3VS_ANX TMS BL_EN TL_INVT_PW M
T51 56 TCK VARY_BL 47 TL_INVT_PW M 27
L32 T52 54 48 APU_INVT_PW M
TDO CPU_VARY_BL APU_INVT_PW M 10,27
FBMA-L11-201209-221LMA30T_0805 1 2 11 31 TRAVIS_CLKN
TEST_EN OSC_OUT TRAVIS_CLKN 13
2 1 0.1U_0402_16V7K R402 10K_0402_5%
OSC_IN 30 TRAVIS_CLKP
TRAVIS_CLKP 13
2 1 65 PAD

AVSS
AVSS
AVSS
C338 C565

1 2 ANX3110_QFN64_9X9

2
5
62
2.2U_0603_6.3V6K

+3VS_ANX +AVDD33
L33
20mil
B FBMA-L11-201209-221LMA30T_0805 +3VS_ANX B

2 1 0.1U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K


+3VS_ANX
2 2 2 1 1 1
C563 C348 C561 C567 C467 C566 APU_LVDS_CLK 1 2
R530 4.7K_0402_5%
DP0_AUXP_C 2 @ 1 APU_LVDS_DAT 1 2
1 1 1 2 2 2 R531 1M_0402_5% R469 4.7K_0402_5%
0.1U_0402_16V7K 0.01U_0402_16V7K 2.2U_0603_6.3V6K
DP0_AUXN_C 2 @ 1
R528 1M_0402_5%

Place via on each trace bus and let resistor very close the via

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/11 Deciphered Date 2011/11/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Translator-ANX3110
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEQAE LA-7291P M/B
Date: Friday, April 29, 2011 Sheet 26 of 51
5 4 3 2 1
5 4 3 2 1

D1
BLUE 2 Q92
1
GREEN 3 1 3

GND
VIN VOUT

YSDA0502C 3P C/A SOT-23 @

2
AP2230_SOT23-3

CRT RED 2
D2

+5VS W=40mils
+CRT_VCC
1
+CRT_VCC 3 L115 W=40mils
2 1+5VS_CRTVCC 1 2
YSDA0502C 3P C/A SOT-23 D4 SMD1812P075TF .75A 13.2V

0.1U_0402_16V4Z
RB491D_SOT23-3 1 1

0.1U_0402_16V4Z
D D
C1570 C1571
D15
@
R1634
HSYNC_L 2
FCH_CRT_R 1 2 CRT_R_R L116 1 2 FCM2012CF-800T06_2P RED 1 2 2
15 FCH_CRT_R
0_0402_5% VSYNC_L 3
R1635
FCH_CRT_G 1 2 CRT_G_R L117 1 2 FCM2012CF-800T06_2P GREEN
15 FCH_CRT_G YSDA0502C 3P C/A SOT-23
0_0402_5%
R1636
FCH_CRT_B 1 2 CRT_B_R L118 1 2 FCM2012CF-800T06_2P BLUE
15 FCH_CRT_B D16
0_0402_5%
1 1 1 VGA_DDC_DATA_C 2
For EMI C1575 C1576 C1577 1

150_0402_1%

150_0402_1%

150_0402_1%
1 1 1

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
1

1
R1637 R1638 R1639 C1572 C1573 C1574 VGA_DDC_CLK_C 3

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
2 2 2
2 2 2 YSDA0502C 3P C/A SOT-23
+CRT_VCC

ESD
2

2
JCRT1
6
T19 CRTTEST 11
RED 1
7
+3VS +CRT_VCC 12
GREEN 2
+CRT_VCC 8 16
G
C1578 HSYNC_L 13 17
G

1
1 2 R1640 1 2 BLUE 3

1
0.1U_0402_16V4Z 1K_0402_5% 9

2.2K_0402_5%
R1642 VSYNC_L

R1644
14
5
1

1
4.7K_0402_5% 4

2.2K_0402_5%
R1645
10
OE#
P

2
2 1 2 4 CRT_HSYNC_D 1 2 HSYNC_L R1646 15
15 FCH_CRT_HSYNC

2
A Y

2
R1641 0_0402_5% R1643 0_0603_5% 4.7K_0402_5% 5
G

U87

2
74AHCT1G125GW_SOT353-5 FCH_CRT_DDC_SDA 1 2CRT_DATA 1 6 VGA_DDC_DATA_C SUYIN_070546FR015S297ZR
15 FCH_CRT_DDC_SDA
3

R1647 0_0402_5% CONN@


C Q2A DMN66D0LDW-7_SOT363-6 C

100P_0402_50V8J
1 VGA_DDC_DATA_C
C1579 +CRT_VCC C1580
1 2 R1648 1 2

100P_0402_50V8J
0.1U_0402_16V4Z 1K_0402_5%
2
1
5
1

5
C1581 VGA_DDC_CLK_C
@
OE#
P

2 1 2 4 CRT_VSYNC_D 1 2 VSYNC_L FCH_CRT_DDC_SCL 1 2 CRT_CLK 4 3 VGA_DDC_CLK_C 1

100P_0402_50V8J
15 FCH_CRT_VSYNC A Y 15 FCH_CRT_DDC_SCL 2
R1651 0_0402_5% R1650 0_0603_5% R1649 0_0402_5% C1582
G

U88 1 Q2B @
74AHCT1G125GW_SOT353-5 C1583 C1584 1 DMN66D0LDW-7_SOT363-6

15P_0402_50V8J

15P_0402_50V8J
3

2
FCH_CRT_DDC_SDA R17 1 @ 2 VGA_DDC_DATA_C
2 0_0402_5%
Close to APU 2 FCH_CRT_DDC_SCL R31 1 @ 2 VGA_DDC_CLK_C
0_0402_5%
For AMD DG-47520-1-10

680P_0402_50V7K
LCD POWER CIRCUIT

C131
+LCDVDD +LCDVDD +3VS

2
+5VALW Q93 @
SI2301BDS-T1-E3_SOT23-3
1

+LCDVDD JLVDS1 DMIC_CLK


S

1 3
D

R1653 1 W=80mils 41 42 W=80mils


4.7U_0805_10V4Z

R1652 L123 1 GMD GND


100_0805_5%
47K_0402_5%
C1585
W=60mils B+ 2
FBMA-L11-201209-221LMA30T_0805
39
39 40
40 +LCDVDD
1 37 38
G
2

4.7U_0805_10V4Z 37 38
35 36

22P_0402_50V8J
6 2

2 C1586 35 36 @
1 1 33 34 2
C1587 C1588 33 34
+3VS 31 32
2 31 32 APU_TZOUT0+

C132
29 30 APU_TZOUT0+ 26
0.1U_0402_16V4Z

B
0.1U_0402_16V4Z 0.1U_0402_16V4Z R1656 @ 1 APU_TXOUT0+ 29 30 APU_TZOUT0- B
26 APU_TXOUT0+ 27 28 APU_TZOUT0- 26
2 2 0.047U_0402_16V7K C1590 APU_TXOUT0- 27 28 1
2 2 1 26 APU_TXOUT0- 25 26
220K_0402_1% 25 26 APU_TZOUT1-
23 24 APU_TZOUT1- 26
2N7002DW-7-F_SOT363-6 C1589 APU_TXOUT1- 23 24 APU_TZOUT1+
26 APU_TXOUT1- 21 22 APU_TZOUT1+ 26
1

21 22
3

2 APU_TXOUT1+ 19 20
Q99A 26 APU_TXOUT1+ 19 20
17 18 APU_TZOUT2+ APU_TZOUT2+ 26
Q99B APU_TXOUT2+ 17 18 APU_TZOUT2-
26 APU_TXOUT2+ 15 16 APU_TZOUT2- 26
2N7002DW-7-F_SOT363-6 APU_TXOUT2- 15 16
10 APU_ENVDD 1 2 5 26 APU_TXOUT2- 13 14
R1659 @ 0_0402_5% 13 14 APU_TZOUT_CLK-
11 12 APU_TZOUT_CLK- 26
APU_TXOUT_CLK+ 11 12 APU_TZOUT_CLK+
9 10
26 APU_TXOUT_CLK+ APU_TZOUT_CLK+ 26
EMI
4

R712 1 APU_TXOUT_CLK- 9 10
26 TL_ENVDD 20_0402_5% 26 APU_TXOUT_CLK- 7 8
7 8 APU_LVDS_CLK
5 6 APU_LVDS_CLK 26
INVTPWM 5 6 APU_LVDS_DAT
3 4 APU_LVDS_DAT 26
3 4
1

DISPOFF# 1 2
R1660 1 2
ACES_87242-4001-09 Camera
100K_0402_5% CONN@
JCM1
2

+3VS 1
USB20_N2 1
14 USB20_N2 2
USB20_P2 2
14 USB20_P2 3
DMIC_CLK 3
33 DMIC_CLK 4
DMIC_DATA 4
5 7
Panel PWM Control 33 DMIC_DATA
6
5 G1
6 G2
8

ACES_87213-0600G
+3VS CONN@
TL_INVT_PWM 1 2 D28
Panel Backlight Control 26 TL_INVT_PWM
R722 0_0402_5% 6
I/O4 I/O2
3
1

10,26 APU_INVT_PWM R1654 1 @ 2


@ R1670 0_0402_5%
10K_0402_5% R1655 1 @ 2 INVTPWM
32 EC_INVT_PWM
@ 0_0402_5% +5VS 5 2
VDD GND
1

D5 RB751V_SOD323
2

1 2 R1657
10K_0402_5%
4 1
I/O3 I/O1
A A
2

TL_BKOFF# R1672 1 @ 2 DISPOFF# AZC099-04S.R7G_SOT23-6


26,32 TL_BKOFF#
0_0402_5% @

32 BKOFF#
BKOFF#
D32
1
@
RB751V_SOD323
2
ESD
1

R1677
R1673 1 2 10K_0402_5%
0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P10-LVDS/CRT CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 27 of 51
5 4 3 2 1
5 4 3 2 1

Q94 +5VS Q95


+1.5VS +1.5VS

D
+HDMI_5V_OUT

S
1 3 6

GND
+5VS VIN VOUT +HDMI_5V_OUT
4 5 F2
+HDMI_5V_OUT @ 2 +HDMI_5V 1 2
1

1
4.7K_0402_5%

4.7K_0402_5%
@ C1591 1 W=40mils0.5A 15VDC_FUSE

1U_0603_10V6K

1U_0603_10V4Z
2
AP2230_SOT23-3

G
1
C1592

3
2 SI3456BDV-T1-E3 1N TSOP6

1
R202

R205

3.9K_0402_1%

3.9K_0402_1%
+VSB

2
2

R200

R201

470K_0402_5%
1
D R1678 D

2
2
G
1 2 HDMICLK 3 1 HDMI_SCLK R200, R201 place near JHDMI connect

2
8 APU_HDMI_CLK R203 0_0402_5% EN_HDMI

D
Q36

1
D

G
BSH111 1N_SOT23-3 R1679 C1601 1

1.5M_0402_5%

0.1U_0402_16V7K
2 Q96
38,45 SUSP
1 2 HDMIDAT 3 1 HDMI_SDATA G SSM3K7002FU_SC70-3
8 APU_HDMI_DATA R206 0_0402_5%

D
S

3
Q33 2

2
BSH111 1N_SOT23-3

5V PULL UP IN CONNECTOR SIDE


+HDMI_5V_OUT

JHDMI1
HDMI_HPD 19 HP_DET
18 +5V
17 DDC/CEC_GND
HDMI_SDATA 16
HDMI_SCLK SDA
15 SCL
14 Reserved
C C
Near the connector HDMI_R_CLK#
13 CEC
12 CK- GND 20
@ 11 21
HDMI_R_CLK CK_shield GND
1 2 10 CK+ GND 22
C1602 1 2 0.1U_0402_16V7K HDMI_CLK HDMI_CLK R1690 1 2 604_0402_1% R208 0_0402_5% HDMI_R_TX0# 9 23
6 PCIE_FTX_GRX_P15 D0- GND
C1603 1 2 0.1U_0402_16V7K HDMI_CLK# 8
6 PCIE_FTX_GRX_N15 D0_shield
HDMI_CLK# R1691 1 2 604_0402_1% L11 HDMI_R_TX0 7
C1604 1 D0+
6 PCIE_FTX_GRX_P14 2 0.1U_0402_16V7K HDMI_TX0 HDMI_CLK 4 4 3 3 HDMI_R_CLK HDMI_R_TX1# 6 D1-
C1605 1 2 0.1U_0402_16V7K HDMI_TX0# HDMI_TX0 R1693 1 2 604_0402_1% 5
6 PCIE_FTX_GRX_N14 D1_shield
HDMI_R_TX1 4
C1606 1 D1+
6 PCIE_FTX_GRX_P13 2 0.1U_0402_16V7K HDMI_TX1 HDMI_TX0# R1695 1 2 604_0402_1% HDMI_CLK# 1 1 2 2 HDMI_R_CLK# HDMI_R_TX2# 3 D2-
C1607 1 2 0.1U_0402_16V7K HDMI_TX1# 2
6 PCIE_FTX_GRX_N13 D2_shield
HDMI_TX1 R1696 1 2 604_0402_1% WCM-2012-670T_4P HDMI_R_TX2 1
C1608 1 D2+
6 PCIE_FTX_GRX_P12 2 0.1U_0402_16V7K HDMI_TX2
C1609 1 2 0.1U_0402_16V7K HDMI_TX2# HDMI_TX1# R1697 1 2 604_0402_1% 1 2 SUYIN_100042GR019M23DZL
6 PCIE_FTX_GRX_N12
R210 @ 0_0402_5% CONN@
HDMI_TX2 R1698 1 2 604_0402_1%
@
HDMI_TX2# R1699 1 604_0402_1%
From APU 2
R211
1 2
0_0402_5%
D7
L12 HDMI_HPD 6 3 HDMI_SDATA
I/O4 I/O2

1
SSM3K7002FU_SC70-3 D Q97 HDMI_TX0# HDMI_R_TX0#
1 1 2 2
+HDMI_5V_OUT 2
G
1

S HDMI_TX0 4 3 HDMI_R_TX0 +5VS 5 2

3
4 3 VDD GND
R1700 WCM-2012-670T_4P
100K_0402_5%
1 2 +HDMI_5V_OUT 4 1 HDMI_SCLK
2

R213 @ 0_0402_5% I/O3 I/O1


AZC099-04S.R7G_SOT23-6
B B
NEAR CONNECTOR 1 @ 2

HDMI_TX1#
R214

L13
0_0402_5%

HDMI_R_TX1#
ESD
1 1 2 2

D3 D6 HDMI_TX1 4 3 HDMI_R_TX1 +1.5VS


HDMI_TX0# HDMI_TX0# HDMI_TX1# HDMI_TX1# 4 3
1 1 10 9 1 1 10 9
WCM-2012-670T_4P

2
HDMI_TX0 2 2 9 8 HDMI_TX0 HDMI_TX1 2 2 9 8 HDMI_TX1
1 @ 2 R755
HDMI_CLK# 4 4 7 7 HDMI_CLK# HDMI_TX2# 4 4 7 7 HDMI_TX2# R220 0_0402_5% 2.2K_0402_5%

HDMI_CLK 5 5 6 6 HDMI_CLK HDMI_TX2 5 5 6 6 HDMI_TX2 1 @ 2

1 1
R223 0_0402_5%
D
3 3 3 3
L14 2 HDMI_HPD

ESD 8 8 HDMI_TX2# 1 1 2 2 HDMI_R_TX2#


S
G

1
10 APU_HDMI_HPD Q35
L15ESDL5V0NA-4 SLP2510P8 L15ESDL5V0NA-4 SLP2510P8 HDMI_TX2 4 3 HDMI_R_TX2 SSM3K7002FU_SC70-3 R768
4 3 100K_0402_5%
WCM-2012-670T_4P

2
1 @ 2
R226 0_0402_5%
BOT SIDE NEAR CONNECTOR
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P11-HDMI CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 28 of 51
5 4 3 2 1
A B C D E F G H

SATA HDD BTB Conn.

JHDD1
15 SATA_STX_DRX_P0 1 2 +5VS
1 1 2 1
15 SATA_STX_DRX_N0 3 4
3 4
5 6
5 6
7 8
15 SATA_DTX_C_SRX_N0 7 8
9 10
15 SATA_DTX_C_SRX_P0 9 10
11 12
11 12
15 SATA_STX_DRX_P2 13 14 +3VS
13 14
15 SATA_STX_DRX_N2 15 16
15 16
17 18
17 18
19 20
15 SATA_DTX_C_SRX_N2 19 20
21 22
15 SATA_DTX_C_SRX_P2 21 22
23 24
23 24
25 25 26 26
27 27 28 28
29 30

GND
GND
GND
GND
GND
GND
29 30

ACES_88018-304G

31
32
33
34
35
36
CONN@

2 2

SATA ODD FFC Conn.

JODD1
1
C1310 1 SATA_STX_C_DRX_P1 GND
15 SATA_STX_DRX_P1 2 0.01U_0402_16V7K 2
A+
15 SATA_STX_DRX_N1 C1311 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_N1 3
A-
4
C1308 1 SATA_DTX_SRX_N1 GND
15 SATA_DTX_C_SRX_N1 2 0.01U_0402_16V7K 5
C1309 1 SATA_DTX_SRX_P1 B-
15 SATA_DTX_C_SRX_P1 2 0.01U_0402_16V7K 6
B+
7
GND
80mils 8
DP
9
+5V
+5VS 10
+5V
+3VS 1 2 11
R4 10K_0402_5% MD
12 14
GND GND1
@ 13 15
GND GND2
SANTA_206001-1
CONN@

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/20 Deciphered Date 2012/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P28-HDD & ODD CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 29 of 51
A B C D E F G H
5 4 3 2 1

+5VALW 2 R652 1 0_0402_5%


@

USB20_N0_CON
L60
USB20_N0_C
Left USB Conn.
1 1 2 2
U54 +USB_VCCA +USB_VCCA
W=80mils JUSB1
0_0402_5%
1 USB20_P0_CON USB20_P0_C
GND OUT 8 4 4 3 3
USB20_N0_C
1 1
2 IN OUT 7 2 2
C707 2 10.1U_0402_16V4Z 3 WCM-2012HS-900T USB20_P0_C
USBAI_PEN#4 IN OUT 6 1 1 3 3
32 USBAI_PEN# EN# OC# 5 1 2
R109
USB_OC0# 14
C711 C712
4 4
2 1
R631@ 0_0402_5% 470P_0402_50V7K 47U_0805_6.3V 5
2 2 GND
AP2301MPG-13 MSOP 8P EMI request 6
GND
1 7
D C710 GND D
Low Active 8
GND
@ 1000P_0402_50V7K
OCTEK_USB-04APEB
2
CONN@
+5VALW
ESD
U55 +USB_VCCB D14
USB20_N0_C 6 3 USB20_N10_C

C708
1
2
GND
IN
OUT
OUT
8
7
I/O4 I/O2
AI CHARGER
2 10.1U_0402_16V4Z 3 IN OUT 6
32,33 USB_ON# USB_ON# 4 5 1 2 +5VALW 5 2 U2 @
EN# OC# USB_OC2# 14 VDD GND CEN#
0_0402_5% R111 32 USBAI_EN R949 1 2 0_0402_5% 8 1 R33 1 2 0_0402_5% AI_CEN# 32
USB20_N0 CB CEN USB20_N0_CON
14 USB20_N0 7 TDM DM 2

1
AP2301MPG-13 MSOP 8P USB20_P0 6 3 USB20_P0_CON
14 USB20_P0 TDP DP
1 USB20_P0_C 4 1 USB20_P10_C 5 4
I/O3 I/O1 +5VALW VCC GND
Low Active C715 R1016 2 9
@ 1000P_0402_50V7K AZC099-04S.R7G_SOT23-6 100K_0402_5% GND
C1669 MAX14566EETA+_TDFN-EP8_2X2~D

2
2
0.1U_0402_16V7K~N
1

CB=0 Auto detection charger identification active


CB=1 Connect DP/DM to TDP/TDM

C C

2 R655 1 0_0402_5%
@
+USB_VCCB
L55 W=80mils JUSB2
USB REDRIVER 14 USB20_N10
USB20_N10 1
1 2
2 USB20_N10_C
USB20_N10_C
USB20_P10_C
1
2
VBUS
D-
1 1 3
USB20_P10 USB20_P10_C D+
14 USB20_P10 4 3 4
+3VS 4 3 C714 C713 U3RXDN_A_R_0 GND
5
U56 WCM-2012HS-900T 470P_0402_50V7K 47U_0805_6.3V U3RXDP_A_R_0 SSRX-
6 10
2 2 SSRX+ GND
1 7 11
VCC U3TXDN_A_R GND GND
13
VCC 2 R654 1 0_0402_5% 8
SSTX- GND
12
EQ1 2 17 EQ2 @ U3TXDP_A_R 9 13
DE1 EQ1 EQ2 DE2 SSTX+ GND
3 16
@ OS1 DE1 DE2 OS2 OCTEK_USB-09EAEB
4 15
R227 1 OS1 OS2
2 4.7K_0402_5% 5 CONN@
EN_RXD

14 USB30_MRX_DTX_P0 USB30_MRX_DTX_P0
M3@C21 2 1 0.1U_0402_16V7KUSB30_MRX_P0 12 19 U3RXDP_A_RM3@C3 2 1 0.1U_0402_16V7K U3RXDP_A_R_C
USB30_MRX_DTX_N0 TX2+ RX2+
14 USB30_MRX_DTX_N0 M3@C22 2 1 0.1U_0402_16V7KUSB30_MRX_N011 20 U3RXDN_A_RM3@C4 2 1 0.1U_0402_16V7K U3RXDN_A_R_C
USB30_MTX_C_DRX_P0 TX2- RX2- U3TXDP_A_CM3@C19 0.1U_0402_16V7K U3TXDP_A
14 USB30_MTX_C_DRX_P0 9 22 2 1
USB30_MTX_C_DRX_N0 RX1+ TX1+ U3TXDN_A_CM3@C20 0.1U_0402_16V7K U3TXDN_A
14 USB30_MTX_C_DRX_N0 8 23 2 1
RX1- TX1-
TEST 7 14 R228 1 2 4.7K_0402_5%
NC CM +3VS
I2C_EN 24 @
NC
18
GND
6 21
B GND GND B
10 25
GND GPAD
For USB3.0 ESD diode
SN65LVPE502RGER_QFN24_4X4
M3@ @ 1 2 D41
R933 0_0402_5% U3TXDP_A_R 1 1 10 9 U3TXDP_A_R

WCM-2012-900T_0805 U3TXDN_A_R 2 2 9 8 U3TXDN_A_R


+3VS U3RXDP_A_R_C 1 2 U3RXDP_A_R_0
1 2 U3RXDP_A_R_0 4 4 U3RXDP_A_R_0
7 7

U3RXDN_A_R_C 4 3 U3RXDN_A_R_0 U3RXDN_A_R_0 5 5 6 6 U3RXDN_A_R_0


4 3
L56 M3@ 3 3
1

1
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

@ 1 2 8
R931 0_0402_5%
@ 1 2 YSCLAMP0524P_SLP2510P8-10-9
R939 0_0402_5% M3@
R204

R207

R212

R215

R216

R217

R1818

R1819
2

WCM-2012-900T_0805
U3TXDP_A 1 2 U3TXDP_A_R
1 2
@ @ @ @ @ @ @ @
EQ1 U3TXDN_A 4 3 U3TXDN_A_R
EQ2 TEST 4 3
L58 M3@
DE1 I2C_EN
DE2 must to close to JUSB2 @ 1 2
R946 0_0402_5%
OS1
OS2
1

1
4.7K_0402_5%

4.7K_0402_5%

A A
1

1
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

R1820

R1821
2

2
R218

R219

R221

R222

R224

R225

Security Classification Compal Secret Data Compal Electronics, Inc.


2

@ @
Issued Date 2010/08/20 Deciphered Date 2012/06/30 Title
@ @ @ @ @ @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P31-USB/BT/USBsub
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 30 of 51
5 4 3 2 1
5 4 3 2 1

J8
2 2 1 1
+LAN_IO +LAN_VDD
W=60mils W=60mils
@ JUMP_43X118

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
+3VALW
+LAN_IO 1.5A R1788 1 1 1 1 1 1 1
Q29 470_0603_5%

D
3 1 W=20mils C1617 C1618 C1619 C1620 C1621 C1622 C1623

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
1

1
C1610 +LAN_IO_DISC 2 2 2 2 2 2 2
1 1 1 1 1 1
1U_0402_6.3V6K AO3419L 1P SOT23-3

G
2

1
C1611 C1612 C1613 C1614 C1615 C1616 D
+5VALW 2 2 EN_WOL#
D 2 2 2 2 2 2 G D
S SSM3K7002FU_SC70-3 These caps close to Pin 3,6,9,13,29,41,45

3
2
Q113
R533
100K_0402_5%

R534 These caps close to Pin 12,27,39,42,47,48


1

1 2 EN_WOL#
220K_0402_5%~N +LAN_IO W=40mils W=20mils
1

D R535 +LAN_VDD
1 R536
2 Q30 C1624 +LAN_IO 1 2 +LAN_VDDREG
32 EN_WOL

0.1U_0402_16V7K
+LAN_EVDD10

4.7U_0603_6.3V6K
G SSM3K7002FU_SC70-3 0.1U_0603_25V7K 1 2

0.1U_0402_16V7K

1U_0402_6.3V6K
S 0_0603_5% 1 1
3
2

2
0_0603_5%

2
R1789 C1625 C1626 1 1
10K_0402_5% R1658
10K_0402_5% 2 2 C1627 C1628
1

2
2 2

1
14,32,35 FCH_PCIE_WAKE# 1 3 LAN_WAKE#

S
U49 SSM3K7002FU_SC70-3
Q98
C1629 1 20.1U_0402_16V7K PCIE_FRX_C_DTX_P0 22 31
6 PCIE_DTX_C_FRX_P0 HSOP LED3/EEDO
LED1/EESK 37
C1630 1 20.1U_0402_16V7K PCIE_FRX_C_DTX_N0 23 40
6 PCIE_DTX_C_FRX_N0 HSON LED0

6 PCIE_FTX_C_DRX_P0 17 HSIP EECS/SCL 30 R537 1 2 10K_0402_5%


6 PCIE_FTX_C_DRX_N0 18 HSIN EEDI/SDA 32 R538 1 2 10K_0402_5% L120
+LAN_VDD
C +LAN_SROUT1.05 C
W=60mils 1 2 W=60mils

0.1U_0402_16V7K
LAN_MDIP0

4.7U_0603_6.3V6K
14 LAN_CLKREQ# 16 CLKREQB MDIP0 1 R539
2 LAN_MDIN0 2.2UH +-5% NLC252018T-2R2J-N 1 1
MDIN0 LAN_MDIP1 12P_0402_50V8J 1 XTLI
13,18,26,35 PLT_RST# 25 PERSTB MDIP1 4 2 C1633 2 1
5 LAN_MDIN1 C1631 C1632
MDIN1

2
19 7 LAN_MDIP2 0_0402_5%
13 CLK_PCIE_LAN REFCLK_P NC/MDIP2 2 2
20 8 LAN_MDIN2 Y6
13 CLK_PCIE_LAN# REFCLK_N NC/MDIN2
10 LAN_MDIP3 25MHZ_12PF_X5H025000FC1H-H
NC/MDIP3 LAN_MDIN3
11

1
XTLO NC/MDIN3 XTLO
43 1 2
CKXTAL1 12P_0402_50V8J C1634
XTLI 44 13 These components close to Pin 36
CKXTAL2 DVDD10 +LAN_VDD
DVDD10
29 ( Should be place within 200 mils )
41
LAN_WAKE# DVDD10
R540 28
LANWAKEB

+3VS 1 2 ISOLATEB 26 27
ISOLATEB DVDD33
39
1K_0402_5% DVDD33
14 12 +LAN_IO
NC/SMBCLK AVDD33
2

R542 1 2 10K_0402_5% 15 42
R541 R543 1 NC/SMBDATA AVDD33
+LAN_IO 2 1K_0402_5% 38 47
15K_0402_5% GPO/SMBALERT AVDD33
48
AVDD33

+LAN_IO 2 1 33
1

R544 0_0402_5% ENSWREG +LAN_EVDD10


21
3.3V : Enable switching regulator EVDD10 JLAN1
34
0V : Disable switching regulator +LAN_VDDREG VDDREG
35 3 +LAN_VDD
VDDREG AVDD10
6 12
AVDD10 RJ45_TX3- SHLD4
9 8
R547 1 AVDD10 PR4-
2 2.49K_0402_1% 46 45 D34 @ LSE-200NX3216TRLF_1206-2 11
RSET AVDD10 RJ45_TX0+ 1 SHLD3
2 RJ45_TX0- RJ45_TX3+ 7
B +LAN_SROUT1.05 PR4+ B
24 36
GND REGOUT D35 @ LSE-200NX3216TRLF_1206-2 RJ45_RX1-
49 6
PGND RJ45_RX1+ 1 PR2-
2 RJ45_RX1-
RJ45_TX2- 5
RTL8111E-VL-GR_QFN48_6X6 D36 @ LSE-200NX3216TRLF_1206-2 PR3-
RJ45_TX2+ 1 2 RJ45_TX2- RJ45_TX2+ 4
TS1 PR3+
D37 @ LSE-200NX3216TRLF_1206-2 RJ45_RX1+ 3
+V_DAC RJ45_TX3+ 1 PR2+
1 24 R549 1 2 75_0402_5% 2 RJ45_TX3-
LAN_MDIP0 TCT1 MCT1 RJ45_TX0+ R1529 1 75_0402_5% RJ45_TX0-
2 23 2 2
LAN_MDIN0 TD1+ MX1+ RJ45_TX0- R1530 1 75_0402_5% PR1-
3 22 2 10
TD1- MX1- R552 1 75_0402_5% RJ45_TX0+ SHLD2
2 1
+V_DAC PR1+
4 21 9
LAN_MDIP1 TCT2 MCT2 RJ45_RX1+ SHLD1
5 20
C1635 1 2

0.01U_0402_16V7K
LAN_MDIN1

+V_DAC
6

7
TD2+
TD2-

TCT3
MX2+
MX2-

MCT3
19

18
RJ45_RX1- 2
C1636
100P_1206_2KV7K
ESD SANTA_130451-Y
CONN@
LAN_MDIP2 8 17 RJ45_TX2+
LAN_MDIN2 TD3+ MX3+ RJ45_TX2- 1
9 16
TD3- MX3- 04/19
+V_DAC
LAN_MDIP3
LAN_MDIN3
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
RJ45_TX3+
RJ45_TX3- LAN_MDIP1 6
D11
I/O4 I/O2
3 LAN_MDIP0
ESD LAN_MDIP3 6
D13
I/O4 I/O2
3 LAN_MDIP2

TAIMAG_IH-160 D18 @ LSE-200NX3216TRLF_1206-2 +LAN_IO 5 2 +LAN_IO 5 2


VDD GND VDD GND
1 2

D19 @ LSE-200NX3216TRLF_1206-2
1 2 LAN_MDIN1 4 1 LAN_MDIN0 LAN_MDIN3 4 1 LAN_MDIN2
I/O3 I/O1 I/O3 I/O1
A LANGAN D29 @ LSE-200NX3216TRLF_1206-2 AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6 A
2 1
R34 0_0603_5% 1 2
@
D31 @ LSE-200NX3216TRLF_1206-2
1 2

2 1 LANGAN
R76 0_0603_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
@
ESD Issued Date 2010/3/31 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2012/06/30 Title
P24-LAN RTL8111E
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom QBL70 LA-7553P 0.22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 31 of 51
5 4 3 2 1
5 4 3 2 1

+3VALW ID BRD ID Ra Rb Vab


L65
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2+EC_VCCA 0 R01 SR 100K 115K 1.6613V
1 1 C1346 1 1 2 2 BLM18AG601SN1D_2P
C1345 1
C1347 C1348 C1349 C1350 1 R02 ER 100K 154K 1.8857V
1000P_0402_50V7K 1000P_0402_50V7K C1351
2 2 2 2 1 1
2

ECAGND
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 R10 PR 100K 215K 2.1261V
+3VS

D D
1 2 EC_SCI#

111
125
R1623 10K_0402_5%

22
33
96

67
9
U31
2 1 ENBKL

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
R1661 100K_0402_5%
@ +3VALW
Ra
EC_GA20 1 21 VGA_DBCLK
14 EC_GA20 EC_KBRST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BRDID R1603
14 EC_KBRST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 EC must program to 500KHZ output 1 2 100K_0402_5%
SERIRQ 3 26
13 SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF Start and stop follow SUP high/Low R1606
13,35 LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF 39 1 2 215K_0402_1%
@ C1352 LPC_AD3 5 1 2 ECAGND
13,35 LPC_AD3 LAD3
22P_0402_50V8J @
13,35 LPC_AD2
LPC_AD2 7 LAD2 PWM Output C2 100P_0402_50V8J Rb
2 1 2 1 LPC_AD1 8 63 BATT_TEMP
13,35 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 40
R1014 33_0402_5% LPC_AD0 +5VS
13,35 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
ADP_I/AD2/GPIO3A 65 ADP_I 39
LPC_CLK0_EC 12 AD Input 66 BRDID TP_CLK 2 1
13,16 LPC_CLK0_EC PCICLK AD3/GPIO3B
A_RST# 13 75 1 2 ENBKL 4.7K_0402_5% R1018
13 A_RST# PCIRST#/GPIO05 AD4/GPIO42
+3VALW 2 1 37 76 R30 0_0402_5% TP_DATA 2 1
R1011 47K_0402_5% EC_SCI# ECRST# SELIO2#/AD5/GPIO43 4.7K_0402_5% R1019
14 EC_SCI# 20 SCI#/GPIO0E
2 1 38 CLKRUN#/GPIO1D
C1353 0.1U_0402_16V4Z 68
DAC_BRIG/DA0/GPIO3C EN_DFAN1
EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1 36
DA Output 71 IREF C1363 100P_0402_50V8J
IREF/DA2/GPIO3E IREF 39
KSI0 55 72 CHGVADJ ACIN 2 1
KSO[0..15] KSI0/GPIO30 DA3/GPIO3F CHGVADJ 39
KSI1 56
KSO[0..15] 37 KSI1/GPIO31
KSI2 57
KSI[0..7] KSI3 KSI2/GPIO32 EC_MUTE#
KSI[0..7] 37 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# 33
C KSI4 59 84 USB_ON# C
KSI4/GPIO34 PSDAT1/GPIO4B USB_ON# 30,33 +3VS
KSI5 60 85 W LAN_LED#
KSI5/GPIO35 PSCLK2/GPIO4C W LAN_LED# 35
KSI6 61 PS2 Interface 86 BT_LED#
KSI6/GPIO36 PSDAT2/GPIO4D BT_LED# 35
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 37
KSO0 39 88 TP_DATA FCH_PW RGD 1 @ 2
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 37
KSO1 40 R1625 10K_0402_5%
KSO2 KSO1/GPIO21
41 KSO2/GPIO22
KSO3 42 97 VGATE
KSO3/GPIO23 SDICS#/GPXOA00 VGATE 47
KSO4 43 98 EN_W OL
KSO4/GPIO24 SDICLK/GPXOA01 EN_W OL 31
KSO5 VLDT_EN
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW #
VLDT_EN 38,46
TL_BKOFF#_R 1
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW # 37 2 TL_BKOFF# 26,27
KSO7 46 SPI Device Interface R1620 0_0402_5%
KSO8 KSO7/GPIO27
+3VALW 1 2 47 KSO8/GPIO28
R1020 @ 2.2K_0402_5% KSO9 48 119 SPI_SO_R
EC_SMB_CK2 KSO10 KSO9/GPIO29 SPIDI/RD# SPI_SI_R
+3VS 1
R1021
2
2.2K_0402_5% KSO11
49 KSO10/GPIO2A SPIDO/WR# 120
L125 1
EMI2 SPI_CLK
50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126
1 2 EC_SMB_DA2 KSO12 51 128 SPI_CS# FBMA-10-100505-101T
R1022 2.2K_0402_5% KSO13 KSO12/GPIO2C SPICS#
52 KSO13/GPIO2D
+3VALW 1 2 KSO14 53
R1023 @ 2.2K_0402_5% KSO15 KSO14/GPIO2E AI_CEN# SPI_CLK_R
54 KSO15/GPIO2F CIR_RX/GPIO40 73 AI_CEN# 30 Delay EC_PWROK 50ms
USBAI_EN 81 74 PX_EN
30 USBAI_EN
USBAI_PEN# KSO16/GPIO48 CIR_RLC_TX/GPIO41 PX_EN 22,25 for VGA criterial
30 USBAI_PEN# 82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89 FSTCHG 39

1
90 CHARGE_LED0#
+3VALW BATT_CHGI_LED#/GPIO52 CHARGE_LED0# 35
91 CAPS_LED# @ R180
CAPS_LED#/GPIO53 CAPS_LED# 35
EC_SMB_CK1 77 GPIO 92 CHARGE_LED1# 33_0402_5%
40 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 CHARGE_LED1# 35
1 2 EC_SMB_CK1 EC_SMB_DA1 78 93 PW R_LED# PW R_LED# 35,36
40 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
R1027 2.2K_0402_5% EC_SMB_CK2 79 SM Bus 95 SYSON
6,19 EC_SMB_CK2 SYSON 38,43

2
EC_SMB_DA1 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 VR_ON
1 2 6,19 EC_SMB_DA2 80 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 121 VR_ON 47
R1028 2.2K_0402_5% 127 ACIN
B AC_IN/GPIO59 ACIN 39 B
1 2 KSO1 1
R1029 47K_0402_5% @
1 2 KSO2 SLP_S3# 6 100 EC_RSMRST# C1535
14 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 14
R1030 47K_0402_5% SLP_S5# 14 101 EC_LID_OUT# 22P_0402_50V8J
14 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 14 2
EC_SMI# 15 102 EC_ON
14 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 36
16 103 EC_PME#
@ EC_PME# LID_SW#/GPIO0A EC_SWI#/GPXO06 FCH_PW RGD
1 2 17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104 FCH_PW RGD 14
R1032 10K_0402_5% 18 GPO 105 BKOFF#
1
R1616
2
10K_0402_5%
EC_MUTE#
EC_INVT_PW M
19
25
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D GPIO
BKOFF#/GPXO08
WL_OFF#/GPXO09 106
107
W L_OFF#_EC
BKOFF# 27
WL_OFF#_EC 35 EMI
27 EC_INVT_PW M EC_THERM#/GPIO11 GPXO10 RF_LED# 35
1 2 USB_ON# FAN_SPEED1 28 108 VGA_ON 25
R1619 10K_0402_5% 36 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
29 FANFB2/GPIO15
EC_TX_P80_DATA 30
35 EC_TX_P80_DATA EC_TX/GPIO16
EC_RX_P80_CLK 31 110 PE_GPIO1 PE_GPIO1 13,25 +3VALW
35 EC_RX_P80_CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1
ON/OFF ENBKL_R 1 @
36 ON/OFF 32
34
ON_OFF/GPIO18
PWR_LED#/GPIO19
ENBKL/GPXID2
GPXID3
112
114 EAPD
2
R32 0_0402_5%
ENBKL 10
EAPD 33
20mils
NUM_LED# 36 GPI 115 EC_THERM# 1
35 NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# 8,13,47

1
116 SUSP#
GPXID5 SUSP# 35,38
117 PBTN_OUT# C1539
GPXID6 TL_BKOFF#_R PBTN_OUT# 14 0.1U_0402_16V4Z R1629
GPXID7 118
EC_CRY1 2 10K_0402_5%
122 XCLK1
13,16 RTC_CLK 1 2 EC_CRY2 123 124

2
EC_CRY1 EC_CRY2 R1036 0_0402_5% XCLK0 V18R U48
1
1

AGND

2 C1359 SPI_CS# 1 8
GND
GND
GND
GND
GND

R1037 C1358 SPI_SO_R CS# VCC


2 2 1 2 SPI_SO 2 SO HOLD# 7 SPI_HOLD#
@ @ 100K_0402_5% 22P_0402_50V8J 4.7U_0603_6.3V6K R1630 15_0402_5% 3 6 SPI_CLK_R1 R1631 2 SPI_CLK
WP# SCLK
1

C1361 @ C1362 KB930QF A1 LQFP 128P 2 15_0402_5%


4 5
11
24
35
94
113

69

15P_0402_50V8J X2 15P_0402_50V8J 1 GND SI


20mil
OSC

OSC

1 1 L114 MX25L1606EM2I-12G SOP 8P SPI_SI 1 R1632 2 SPI_SI_R


A A
ECAGND 1 2 SA000041N00 15_0402_5%
FBM-11-160808-601-T_0603
NC

NC

32.768KHZ_12.5PF_Q13MC14610002
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
EC_PME#
14,31,35 FCH_PCIE_W AKE# 1
R1618
2
0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB930
@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 32 of 51
5 4 3 2 1
A B C D E F G H

+5VS_PVDD
EMI close to JSPK1

SPKOUT_L1 R1532 1 2 0_0603_5% SPK_L1 1 2


R1531
1 C1473 0.22U_0603_16V7K
+5VS 2 1 @

10U_0805_10V6K

0.1U_0402_16V7K

0.1U_0402_16V7K
0_0805_5% @ C1474 1U_0603_10V6K
1 1 1 2
SPKOUT_L2 R1533 1 2 0_0603_5% SPK_L2 1 2
C1475 C1476 C1477 C1478 0.22U_0603_16V7K
@
2 2 2 JSPK1
SPK_R1 1
1 R1534 SPKOUT_R1 SPK_R1 SPK_R2 1 1
R1535 1 2 0_0603_5% 1 2 2
+3VS_DVDD_R SPK_L1 2
+3VS_DVDD 2 1 1 C1480 0.22U_0603_16V7K 3
3 G1
5

10U_0603_6.3V6M
@ SPK_L2 4 6
4 G2

0.1U_0402_16V7K
0_0603_5% 1 1 @ C1483 1U_0603_10V6K
ACES_88266-04001
C1481 C1482 SPKOUT_R2 R1536 1 2 0_0603_5% SPK_R2 2 1 2 CONN@
C1484 0.22U_0603_16V7K
2 2
@
+5VS_PVDD +VDDA
L108
2 1 +5VS

2
+3VS_DVDD

10U_0805_10V6K
0.1U_0402_16V7K

0.1U_0402_16V7K
R1537 1 1 1 MBK1608800YZF 0603
+3VS 2 1 D9 D10
10U_0603_6.3V6M

0.1U_0402_16V7K
0_0603_5% C1485 C1486 C1487
1 1 2 2 2
C1488 C1489

1
YSDA0502C 3P C/A SOT-23 YSDA0502C 3P C/A SOT-23
2 2

10P_0402_50V8J
39

46

25

38
1

9
U50 HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO
2
ESD @ @

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD

0_0402_5%
C1491

1
@ 1 R1538
23 40 SPKOUT_L1 @
LINE1_L SPK_OUT_L+ SPKOUT_L2
24 LINE1_R SPK_OUT_L- 41 EMI

22P_0402_50V8J
14 45 SPKOUT_R1
LINE2_L SPK_OUT_R+

10P_0402_50V8J
15 44 SPKOUT_R2 1
LINE2_R SPK_OUT_R- HDA_SYNC_AUDIO
MIC1 1 R1539 2 MIC1_R 1 2 C1490 4.7U_0603_6.3V6K MIC1_C 21 32 HP_OUTL 2 C1492
2 1K_0402_5% MIC2_C 22 MIC1_L HP_OUT_L HP_OUTR 2
MIC1_R HP_OUT_R 33
MIC2 1 R1540 2 MIC2_R 1 2 C1493 4.7U_0603_6.3V6K C1494 @ 2
1K_0402_5% 16 MIC2_L @ 1
17 MIC2_R
10 HDA_SYNC_AUDIO R1541 1 2.2K_0402_1%
2
SYNC HDA_SYNC_AUDIO 14 +MIC1_VREFO_R
R1542 1 2.2K_0402_1%
2 +MIC1_VREFO_L
DMIC_DATA R1543 1 2 0_0402_5% DMIC_DATA_CODEC 2 6 HDA_BITCLK_AUDIO
27 DMIC_DATA GPIO0/DMIC_DATA BCLK HDA_BITCLK_AUDIO 14
DMIC_CLK 1 2 DMIC_CLK_CODEC 3
27 DMIC_CLK GPIO1/DMIC_CLK
L124 FBMA-L10-160808-301LMT_2P 5 HDA_SDOUT_AUDIO JAU1
SDATA_OUT HDA_SDOUT_AUDIO 14 MIC_JD 1
EC_MUTE# R1545 1 PD# HDA_SDIN_AUDIO1 R1546 2 MIC2 1
32 EC_MUTE# 2 0_0402_5% 4 8 HDA_SDIN0 14 2
PD# SDATA_IN 33_0402_5% 2
3
MIC1 HP_JD 3
4
HDA_RST_AUDIO# HP_OUTR 4
14 HDA_RST_AUDIO# 11
RESET# EAPD
47 1 R1547 2 EAPD 32 5
5
HP_OUTL 6
0_0402_5% 6
48 7
SPDIFO 7
12 8
MIC_JD PCBEEP 8
1 R1548 2 20 9
20K_0402_1% MONO_OUT 9
10
HP_JD SENSE_A 10
2 R1549 1 13 11
39.2K_0402_1% SENSE A 11
29 12
MIC2_VREFO 12
18 14 USB20_N1 13
SENSE B 13
30 +MIC1_VREFO_R 14 USB20_P1 14
MIC1_VREFO_R 14
36 28 15
CBP LDO_CAP 15
16
+5VALW 16

10U_0805_10V6K
1 2 35 27 AC97_VREF 17
CBN VREF 17

10U_0805_10V6K

0.1U_0402_16V7K
C1497 2.2U_0603_16V6K 1 18
AC_JDREF 18
31 19 1 R1552 2 1 1 19
+MIC1_VREFO_L MIC1_VREFO_L JDREF 20K_0402_1% C1501 USB_ON# 19
30,32 USB_ON# 20
C1499 C1500 20
43 34 1 2 1 2 @ 14 USB_OC1# 21
PVSS2 CPVEE C1498 2 21
42 22
3 PVSS1 2.2U_0603_16V6K @ 2 2 C9 0.1U_0402_16V7K USB20_P11 22 3
49 26 14 USB20_P11 23
+1.5VS DVSS2 AVSS1 USB20_N11 23
7 37 14 USB20_N11 24
DVSS1 AVSS2 24
1 2 @ 25
G1
ALC269Q-VB5-GR_QFN48_7X7 26
C123 0.1U_0402_16V7K G2
1

ACES_85202-24051
1 2 @ CONN@
4.7K_0402_5%
R1553 @ C124 0.1U_0402_16V7K
1 2 @
2

HDA_RST_AUDIO# R1556 1 2 0_0402_5% C125 0.1U_0402_16V7K


@
1 R1557 1 2 0_0402_5%
0.1U_0402_16V7K
C1503 R1558 1 2 0_0402_5% For EMI (on MIC and Headphone AGND to connected with
DGND)
2 R1559 1 2 0_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/3/31 Deciphered Date 2012/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P25-HD CODEC ALC259
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom QBL70 LA-7553P 0.22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 33 of 51
A B C D E F G H
5 4 3 2 1

Card Reader RTS5137


(only SD/MMC/MS function)
+3VS +3VS_CR

D
30mil D
R1560 1 2 0_0603_5%

@
2 1 10mil
C1507 100P_0402_50V8J U51
C1508 1 2 +RREF 1
6.2K_0603_1% REFE @
17 1 2 1 2
USB20_N4 GPIO0 R1561 10_0402_5% @ C1509 10P_0402_50V8J
14 USB20_N4 2
USB20_P4 DM CLK_SD_48M
14 USB20_P4 3 24 CLK_SD_48M 13
DP CLK_IN
+3VS_CR 4 23
+CARDPWR 3V3_IN NC
+VREG
30mil 5 CARD_3V3 MS_BS
1 2 6 V18 SP14 22
C1511 1 10mil 21 SDD2_MS_D5
C1510 C1512 EMI SP13 SDD3_MSD1
7 NC SP12 20
4.7U_0805_10V4Z 1U_0402_6.3V6K 0_0402_5% R37 19
2 1 SDWP_MSCLK 1 SP11 SDCMD
2 8 SP1 SP10 18
0.1U_0402_16V4Z 2 MS_INS# 9 16 MSD0
SDD1 SP2 SP9 SDCLK_MSD2
10 SP3 SP8 15 1 2

EPAD
SDD0 11 14 0_0402_5% R74 EMI
MSD3 SP4 SP7 SDCD#
12 SP5 SP6 13

RTS5137-GR_QFN24_4X4

25
+CARDPWR

Card Reader Connector JCR1


SDCD# 1
SDWP_MSCLK SD-CD
2 SD-WP
C SDD1 C
3 SD-DAT1
SDD0 4 SD-DAT0
5 MS-GND
6 SD-GND
+CARDPWR MS_BS 7
SDCLK_MSD2 MS-BS
8 CD-CLK
30mil SDD3_MSD1 9
MSD0 MS-DAT1
10
MS-DAT0
11
SD-VCC
12
MS-DAT2
2

@ 1 1 1 13
MS_INS# SD-GND
14
R1562 C1514 C1515 C1513 MSD3 MS-INS
15
100K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z SDCMD MS-DAT3
16
2 2 2 SD-CMD
17
1

MS-SCLK
Close to connector 18
MS-VCC GND
22
19 23
SD-DAT3 GND
20
SDD2_MS_D5 MS-GND
21
SD-DAT2
TAITW_R009-142-HM_RV
CONN@

SDWP_MSCLK SDCLK_MSD2

B
EMI B

close U51 22P_0402_50V8J

22P_0402_50V8J
1 1
C128 C129

@ 2 @ 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/10/08 Deciphered Date 2012/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P26-RTS5137 Media Card Controller
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom QBL70 LA-7553P 0.22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 34 of 51
5 4 3 2 1
A B C D E

Mini-Express Card for WLAN/WiMAX(Half) W=60mils W=60mils

+3VALW +3VS_WLAN

Q31

D
3 1 R1590 2 1 0_1206_5%
1
C1664
+1.5VS 1U_0402_6.3V6K AO3419L 1P SOT23-3

G
2
+3VS +3VS_WLAN +5VALW 2

Mini-Express Card(WLAN/WiMAX)

2
R1563 2 1 0_1206_5%
R1564 R545
1 1
@ 0_1206_5% 100K_0402_5%

@ JMINI1

1
14,31,32 FCH_PCIE_WAKE# R1565 1 2 0_0402_5% WLAN_WAKE# 1 2 1 2 WLAN_EN#
@ 1 2 R114 20K_0402_5%
3 4
3 4

1
R1587 1 D
15 BT_ON 2 0_0402_5% 5 6 1
MINI1_CLKREQ# 5 6 LPC_FRAME#_R Q32
14 MINI1_CLKREQ# 7 8 32,38 SUSP# 2
7 8 LPC_AD3_R G SSM3K7002FU_SC70-3 C1663
9 10
9 10 LPC_AD2_R 4700P_0603_50V7K
13 CLK_PCIE_MINI1# 11 12 S

3
11 12 LPC_AD1_R 2
13 CLK_PCIE_MINI1 13 14
13 14 LPC_AD0_R
15 16
PCI_RST#_R 15 16 R1567 1 @ 0_0402_5%
17 18 2 WL_OFF# 15
CLK_PCI_DB 17 18 R1568 1 0_0402_5%
19 20 2 WL_OFF#_EC 32
19 20
21 22 PLT_RST# 13,18,26,31
PCIE_W_DTX_C_FRX_N0 21 22 R1569 1
13 PCIE_W_DTX_C_FRX_N0 23 24 2 @ 0_0402_5% +3VALW
PCIE_W_DTX_C_FRX_P0 23 24 R1570 1
13 PCIE_W_DTX_C_FRX_P0 25 26 2 @ 0_0402_5% +3VS
25 26
27 28
PCIE_W_FTX_C_DRX_N0 27 28 FCH_SMCLK0_R R1571 1
13 PCIE_W_FTX_DRX_N0 1 2 29 30 2 @ 0_0402_5% FCH_SCLK0 11,12,14
C952 0.1U_0402_16V7K 29 30 FCH_SMDAT0_R R1572 1
31 32 2 @ 0_0402_5% FCH_SDATA0 11,12,14
PCIE_W_FTX_C_DRX_P0 31 32
13 PCIE_W_FTX_DRX_P0 1 2 33 34
C953 0.1U_0402_16V7K 33 34 CLK_PCI_DB
35 36 USB20_N3 14
+3VS_WLAN 35 36
37 38
39
37 38
40
USB20_P3 14 Reserve for SW mini-pcie debug card.

0_0402_5%
39 40
41
41 42
42 Series resistors closed to KBC side.

1
43 44 WLAN_LED_R# 0_0402_5% 2 1 R1575 WLAN_LED#

EC_TX_P80_DATA 1
100_0402_1%
R1581
2 EC_TX_P80_DATA_R
45
47
49
43
45
47
44
46
48
46
48
50
BT_LED_R# 0_0402_5% 2 1 R1577 BT_LED#
WLAN_LED# 32
BT_LED# 32
LPC_FRAME#_R
LPC_AD3_R
R1573
R1574
1
1
2
2
0_0402_5%
0_0402_5%
LPC_FRAME#
LPC_AD3
LPC_FRAME# 13,32
EMI R93
@
32 EC_TX_P80_DATA 49 50 LPC_AD3 13,32
EC_RX_P80_CLK 1 2 EC_RX_P80_CLK_R 51 52 LPC_AD2_R R1576 1 2 0_0402_5% LPC_AD2
32 EC_RX_P80_CLK LPC_AD2 13,32

2
@ R1582 51 52 LPC_AD1_R R1578 0_0402_5% LPC_AD1
1 2

22P_0402_50V8J
LPC_AD1 13,32
100_0402_1% 53 54 LPC_AD0_R R1579 1 2 0_0402_5% LPC_AD0 1
GND1 GND2 LPC_AD0 13,32
15 BT_ON R1566 1 2 0_0402_5% PCI_RST#_R R1580 1 2 0_0402_5% PLT_RST#
CLK_PCI_DB CLK_PCI_DB 13 C133
ACES_88915-5204 +3VALW +1.5VS
2

2
For EC to detect CONN@ @
R1583
debug card insert. 100K_0402_5% 1 1 1
2 @ 2
C1516 C1517 C1518
1

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


2 2 2

+5VALW 1 2
R110 10K_0402_5%

LED
LED1
Green
32,36 PWR_LED# 1 2 2 1 +3VALW
100_0402_5% R1584
19-21SYGC/S530-E3/TR8 0603 Y/G D22
@
PWR_LED# 2
1
Orange LED2 3
BATT_LOW_LED# 1 2 2 1
32 CHARGE_LED1# +3VALW YSDA0502C 3P C/A SOT-23
O 300_0402_5% R1585
D25
32 CHARGE_LED0# 3 4 2 1 +3VALW @
W 100_0402_5% R1586 CHARGE_LED1#
BATT_CHG_LED# 2
Green HT-297DQ/GQ 0603 AMB/YG CHARGE_LED0#
1
3

D24 LED3 YSDA0502C 3P C/A SOT-23


@ Green
3 D26 3
WLAN_LED_R# 1 2 RF_D_LED# 1 2 2 1 +3VS @
100_0402_5% R1588 RF_D_LED# 2
RB751V_SOD323 1
D30 19-21SYGC/S530-E3/TR8 0603 Y/G
@ SATA_LED# 3
BT_LED_R# 1 2

RB751V_SOD323 YSDA0502C 3P C/A SOT-23

D27
@
NUM_LED# 2
32 RF_LED# R1589 1 2 0_0402_5% 1
CAPS_LED# 3

YSDA0502C 3P C/A SOT-23


LED4
Green
15 SATA_LED# 1 2 2 1 +3VS
100_0402_5% R1591
19-21SYGC/S530-E3/TR8 0603 Y/G
ESD
LED5
Green
32 NUM_LED# 1 2 2 1 +3VS
100_0402_5% R1593
19-21SYGC/S530-E3/TR8 0603 Y/G

LED6
Green
4 32 CAPS_LED# 1 2 2 1 +3VS 4
100_0402_5% R1594
19-21SYGC/S530-E3/TR8 0603 Y/G

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P27-Mini PCIE/LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 35 of 51
A B C D E
ON/OFF switch Power Button
+3VALW

Fan Control Circuit

2
R1791 +3VS +5VS

For SR 100K_0402_5%

2
@ 2

1
SW 3 D12 R653 C701 1
SMT1-05-A_4P 2 10K_0402_5%
ON/OFF 32
1 3 ON/OFFBTN# 1 2.2U_0603_106K C700
Top Side U53 1
3 51_ON# 40 1000P_0402_50V7K

1
2
2 4 8 GND EN 1
DAN202UT106_SC70-3 FAN_SPEED1 JFAN1
7 GND VIN 2
Change to SC600000B00 6 3 +5VS_FAN 1
6
5
GND VOUT FAN_SPEED1 1
2 1 5 GND VSET 4 32 FAN_SPEED1 2 2

1
C773 C702 3
1000P_0402_50V7K APL5607KI-TRG_SO8 C703 3
1000P_0402_50V7K 10U_0603_6.3V6M 4

2
1 2 GND
5 GND

Bottom Side @ D 32 EN_DFAN1 ACES_85204-0300N

1
SW 4
SMT1-05-A_4P EC_ON SSM3K7002FU_SC70-3 CONN@
32 EC_ON 2

2
1 3 G Q27
R496 S

3
2 4
10K_0402_5%
6
5

1
H19
H_3P2

JBTN1
4 ON/OFFBTN# @
3.2

1
4
3 3 PW R_LED# 32,35
2 2 +5VALW
1 1
H18 H17 H16 H15
5 H_4P2 H_4P2 H_4P2 H_4P2
G1
G2
E-T_6905K-Q04N-00R
6

@ @ @ @
4.2

1
2

CONN@

PJSOT24CH_SOT23-3
D21 H7 H6 H5 H4 H3 H2
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
1

@ @ @ @ @ @ @ 3.0

1
H27 H26 H12 H11 H20 H9
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

@ @ @ @ @ @ 3.0

1
H24 H14
H10 H8 H1 H_6P0 H_6P0
H_2P5 H_2P5 H_2P5

2.5 @ @ 6.0

1
@ @ @

1
H28 H25 H22
H_3P8 H_3P8 H_3P8
H23
H_4P5X3P2 3.8
4.5X3.2 @ @ @

1
@

1
FD1 FD2 FD3 FD4

H21
H_3P3
1

FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80


@ 3.3

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/20 Deciphered Date 2012/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P33-Other IO/USB (right)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 36 of 51
5 4 3 2 1

INT_KBD Conn. ACES_85202-24051


26 G2
KSI[0..7] 25
KSI[0..7] 32 G1
KSO7 24
KSO[0..15] KSO0 24
D KSO[0..15] 32 23 23 D
KSI1 22
KSI7 22
21 21
KSO9 20
KSO2 C1543 1 20
2 @ 100P_0402_50V8J KSO1 C1544 1 2 @ 100P_0402_50V8J KSI6 19 19
KSI5 18
KSO15 C1546 1 18
2 @ 100P_0402_50V8J KSO7 C1545 1 2 @ 100P_0402_50V8J KSO3 17 17
KSI4 16
KSO6 C1547 1 16
2 @ 100P_0402_50V8J KSI2 C1548 1 2 @ 100P_0402_50V8J KSI2 15 15
KSO1 14
KSO8 C1549 1 14
2 @ 100P_0402_50V8J KSO5 C1550 1 2 @ 100P_0402_50V8J KSI3 13 13
KSI0 12
KSO13 C1551 1 12
2 @ 100P_0402_50V8J KSI3 C1552 1 2 @ 100P_0402_50V8J KSO13 11 11
KSO5 10
KSO12 C1553 1 10
2 @ 100P_0402_50V8J KSO14 C1554 1 2 @ 100P_0402_50V8J KSO2 9 9
KSO4 8
KSO11 C1555 1 8
2 @ 100P_0402_50V8J KSI7 C1556 1 2 @ 100P_0402_50V8J KSO8 7 7
KSO6 6
KSO10 C1557 1 6
2 @ 100P_0402_50V8J KSI6 C1558 1 2 @ 100P_0402_50V8J KSO11 5 5
KSO10 4
KSO3 C1559 1 4
2 @ 100P_0402_50V8J KSI5 C1560 1 2 @ 100P_0402_50V8J KSO12 3 3
KSO14 2
KSO4 C1561 1 2
2 @ 100P_0402_50V8J KSI4 C1562 1 2 @ 100P_0402_50V8J KSO15 1 1
KSI0 C1563 1 2 @ 100P_0402_50V8J KSO9 C1564 1 2 @ 100P_0402_50V8J JKB1
CONN@
KSO0 C1565 1 2 @ 100P_0402_50V8J KSI1 C1566 1 2 @ 100P_0402_50V8J
REED Switch +3VALW

C C
CONN PIN define need double check +3VALW

1
R140
47K_0402_5%
Q34

To TP/B Conn.

2
2 3 LID_SW #

GND
+5VS VDD VOUT LID_SW # 32

C136 @ APX9131AAI-TRG_SOT23-3

1
0.1U_0402_16V4Z

C1567
JTP1
0.1U_0402_16V4Z 8
GND
GND 7
6 6
TP_CLK 5
32 TP_CLK 5
TP_DATA 4
32 TP_DATA 4
1 1 SW /L 3
@ @ SW /R 3
2 2
C1568 C1569 1
100P_0402_50V8J 100P_0402_50V8J 1
2 2 E-T_6905-E06N-00R
B CONN@ B
3

D17 D20

@ @
1

YSDA0502C 3P C/A SOT-23


YSDA0502C 3P C/A SOT-23

ESD
DTSM-61N-S-V-T-R(756)_4P
DTSM-61N-S-V-T-R(756)_4P
SW /R 3 1
SW /L 3 1
4 2
4 2
A SW 6 A
SW 5

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P30-KB /SW/TP/Lid
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 37 of 51
5 4 3 2 1
A B C D E

+5VALW TO +5VS +5VALW


+1.1VALW TO +1.1VS (1.1A) +5VALW +5VALW

(5A)
+5VS

2
U38 +1.1VALW +1.1VS
SI4178DY-T1-GE3 1N SO8 U39 R1097 R1098
8 1 AO4430L_SO8 100K_0402_5% 100K_0402_5%
7 2 8 1

2
10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V6K
6 3 1 7 2

1
1

2
C1446

C1444

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z
1 1 5 6 3 1 1 VLDT_EN#

1
C1443

C1447

C1449
R1099 1 5 SYSON#

C1445
470_0603_5% R1100 R1101

1
2 D

C1448
1K_0402_5% 470_0603_5%

4
2 2 2 2 2 Q51 SSM3K7002FU_SC70-3
32,46 VLDT_EN

1
2 G 2N7002_SOT23 Q43 D

2
1

1
D Q4 S 32,43 SYSON 2

3
1
1 SUSP D Q6 G 1
2

1
G 2 VLDT_EN# R1102 S

3
1 2 5VS_GATE S G 10K_0402_5% R1104
+VSB

3
R1103 47K_0402_5% SSM3K7002FU_SC70-3 +VSB 1 2 1.1VS_GATE S 100K_0402_5%

2
1 R1105 47K_0402_5% SSM3K7002FU_SC70-3

2
1
C1450 Q5 D +5VALW
1
1

Q3 D 0.1U_0603_25V7K VLDT_EN# 2
SUSP 2 G C1451
2

2
G S 0.1U_0603_25V7K

3
S SSM3K7002FU_SC70-3 2 R1108
3

SSM3K7002FU_SC70-3 100K_0402_5%

1
SUSP

+3VALW TO +3VS (3.3A)


28,45 SUSP

+3VALW +3VS SSM3K7002FU_SC70-3

1
U40 Q44 D
SI4178DY-T1-GE3 1N SO8 32,35 SUSP# 2
8 1 G

1
7 2 S

3
2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z
6 3 1 1

C1455
1 1 5 R1109
C1452

R1110 10K_0402_5%
C1453

C1454

470_0603_5%
4

2
2 2

1
2 2

1
D Q28
2 SUSP
2 1 3VS_GATE G

VGA Power
2 +VSB 2
R1112 200K_0402_5% S
3
SSM3K7002FU_SC70-3
1
1

Q7 D
SUSP 2 C1456 +1.5V to +1.5VSG (1.5A) Current
G 0.1U_0603_25V7K
S 2 +1.5V +1.5VSG
3

SSM3K7002FU_SC70-3 U41
AO4430L_SO8
8 1
7 2
+1.5V TO +1.5VS (1.5A)

2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
6 3 1 1
1 1 5
C1458 R1114
+1.5V +1.5VS

C1459

C1460

C1457
AP2301GN-HF_SOT23-3 1U_0402_6.3V4Z 470_0603_5%

4
Q63 2 2

1
3 1 2 2
2

1
D
10U_0603_6.3V6M

1 Q42
C1461

2 1.5_VDD_PWREN#
R1116 R1117 G
2

100K_0402_5% 470_0603_5% 1 2 1.5VSG_GATE S


+VSB

3
2 R1118 100K_0402_5% SSM3K7002FU_SC70-3
1

1
Q37 D C1462 +5VALW
1

D Q46 1.5_VDD_PWREN# 2 1 2
1

R1122 Q45 D SUSP R1120 47K_0402_5% G 0.1U_0603_25V7K


2

2
SUSP# G 2
2 1 2 S

3
47K_0402_5% 1 G S SSM3K7002FU_SC70-3
1 R1119
3

S SSM3K7002FU_SC70-3 100K_0402_5%
3

C1463
SSM3K7002FU_SC70-3 C1464
3 0.22U_0603_16V4Z 0.1U_0402_16V7K 3

1
2 2 VGA_PWR_ON#

SSM3K7002FU_SC70-3

1
Q68 D
VGA_PWR_ON 2
25,42,45 VGA_PWR_ON
G
S

3
1
R1123
+1.0VSG +VGA_CORE +1.8VSG +1.2VS 100K_0402_5%

2
2

R1125 R1126 R1127 R1128


470_0603_5% 470_0603_5% 470_0603_5%
33_0603_5%
+3VS to +3VSG (3.3A) +5VALW
1

04/19 Change to Jump

2
201012062000
1

D D D D R1131
2 VGA_PWR_ON# 2 1.5_VDD_PWREN# 2 VGA_PWR_ON# 2 VLDT_EN# @ PJ14 100K_0402_5%
G G G G +3VS 1 2 +3VSG
Q71 Q72 Q73 Q74 1 2
S S S S
3

1
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 JUMP_43X118 1.5_VDD_PWREN#

SSM3K7002FU_SC70-3

1
Q77 D

25,48 1.5_VDD_PWREN 2
+1.5V +2.5VS +0.75VS G

1
S

3
2

4 R1134 4
R1135 R1136 R1137 10K_0402_5%
470_0603_5% 470_0603_5% 470_0603_5%

2
1

1
1

D D D
2 SYSON# 2 SUSP 2 SUSP Security Classification Compal Secret Data Compal Electronics, Inc.
G G G Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
Q78 Q79 2N7002_SOT23
S S S
DC Interface
3

2N7002_SOT23 2N7002_SOT23 Q80 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBL70 LA-7553P
Date: Friday, April 29, 2011 Sheet 38 of 51
A B C D E
A B C D

(B+ 6A,240mils ,Via NO.= 12)


B+ B+
PQ101 P2 PQ102 P3 PR101 PL102 CHG_B+ PQ103
AO4435L_SO8 AO4409L_SO8 0.02_1206_1% 1.2UH_1231AS-H-1R2N=P3_2.9A_30% AO4407AL 1P SO8
VIN 8 1 1 8 1 4 2 1 1 8
7 2 2 7 2 7
6 3 3 6 2 3 CSIN 3 6

10U_0805_25V6K
5 5 5

4.7U_0805_25V6-K

2200P_0402_25V7K
0.1U_0402_25V6
CSIP

4
1

1
1 1

PC103

PC104
VIN

PC105

PC106
PQ104 CHG_N_005

3
LTA044EUBFS8TL PNP UMT3F PR107 PR108

@5600P_0402_25V7K

2
2
200K_0402_1% 191K_0402_1% PR110

0.1U_0603_25V7K

PC107
6251VDD 1 2 ACSETIN 200K_0402_1%

2
1

1000P_0402_50V7K
2 1 2

2.2U_0603_6.3V6K
1
VIN
1CHG_N_010

2
PC108

PC109
RB751V-40TE17_SOD323-2

2
PR109

1
PC110
47K_0402_1% PD101 PR112

14.3K_0402_1%
47K_0402_1%
2

PR111
1

CHG_VIN 1

1CHG_N_0081
CHG_N_003

2
CHG_N_001

PR113 PR115
2 PR114 ACSETIN 1 2 100K_0402_1%
1 10K_0402_1% 1 2 CHG_N_001
2 1 PU101 10_1206_5% PC112

DCIN
PQ105 32 FSTCHG 1U_0603_25V6K

1
LTC015EUBFS8TL NPN UMT3F PR116

100K_0402_1%
1 24 1 2
3

VDD DCIN

PR117
150K_0402_1%
6

PQ106 2 CHG_N_006
2

2 23 ACPRN LTC015EUBFS8TL NPN UMT3F


PQ107A ACSET ACPRN PR118

2
2 20_0603_5%
3CHG_N_002

1
SSM6N7002FU_US6 6251_EN CHG_CSON 1 CSON D
2S: Float 3 22 2

3
EN CSON

1
PR130 PC113 PC114 2 ACPRN
3S: GND
1

0_0402_5% 0.047U_0603_16V7K @2200P_0402_25V7K G


1 2 4 21 CHG_CSOP 1 2 CSOP S PQ109

3
CELLS CSOP PR119 @SSM3K7002FU_SC70-3
PQ107B PC116 6800P_0402_25V7K 20_0603_5% PQ108
2
SSM6N7002FU_US6 1 2 CHG_ICOMP 5 20 CHG_CSIN 2 1 4 AON7408L_DFN8-5 2

ICOMP CSIN

2
PC118 PR120
CHG_N_009 5 PC117 PR121 10K_0402_1% 0.1U_0603_25V7K 20_0603_5%
1 2 1 2 CHG_VCOMP 6 19 CHG_CSIP 1 2

1
VCOMP CSIP PL101 PR102
4

3
2
1
0.01U_0402_25V7K PR123 100_0402_1% PR122 10UH +-20% MSCDRI-104A-100M-E 0.02_1206_1% BATT+
PR124 1 2 CHG_ICM 7 ICM PHASE 18 LX_CHG 2.2_0603_1% 1 2 CHG 1 4
22K_0402_5% PR134

5
6
7
8
PACIN PC120 must close EC pin. 0_0402_5%

@4.7_1206_5%
1 2 1 2 2 3

1
PC120 6251VREF DH_CHG PQ110

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
8 VREF UGATE 17 1 2

PR125
0.1U_0402_16V7K PR126 PC121
32 ADP_I 0_0603_5% 0.1U_0603_25V7K

1
PC101

PC102

PC111
2 1 CHG_CHLIM 9 16 BST_CHG 1 2 BST_CHGA 2 1
32 IREF CHLIM BOOT
1

1
4

1CHG_SNUB2
PR103 PR127 PD106
0.01U_0402_25V7K

2
150K_0402_1% 6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1

12.4K_0402_1%
1

1
PC122

ACOFF PR104 Rtop 26251VDD AO4468L_SO8

@680P_0402_50V7K
32 ACOFF 2 1

3
2
1
140K_0402_1% 11 14 DL_CHG
VADJ LGATE

PC124
PR129
2

PQ111 PR128 4.7_0603_5%


2

LTC015EUBFS8TL NPN UMT3F 20K_0402_1% CHG_VADJ 12 13 PC123


3

2
GND PGND 4.7U_0805_6.3V6K

ISL6251AHAZ-T QSOP 24P

PR105
10K_0402_1%
1 2
32 CHGVADJ
2

3
PR106 3

22K_0402_1%
1

6251VDD

PR133

1
10K_0402_1%
PR131 1 2
CP= 85%*Iada; 47K_0402_1% PR132 ACIN 32
10K_0402_1%
Iada=0~4.737A(90W);CP=4.03A;where Racdet=0.020ohm,where Rtop=12.4K PACIN

2
90W for Dis:Rtop:SD00000AJ80

1
Iada=0~3.421A(65W);CP=2.91A;where Racdet=0.020ohm,where Rtop=226K C

1
ACPRN 2 PQ112
65W for UMA:Rtop:SD034226380 B PR136
Astro2010_01_15 need confirm P/N E 20K_0402_1%

3
MMBT3904W H NPN SOT323-3

2
CP mode
Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal))
when 90W Vaclim=2.39*(20K//152K/(20K//152K+12.4K//152K))=1.44966V
when 65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V
Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05))
when 90W,Iinput=(1/0.02)*(0.05*1.44966/2.39+0.05)=4.02A
4 when 65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A 4

CC=0.25A~3A CHGVADJ=(Vcell-4)/0.10627
IREF=1.016*Icharge Vcell CHGVADJ
IREF=0.254V~3.048V 4V 0V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
VCHLIM need over 95mV 4.2V 1.882V CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 39 of 49
A B C D
A B C D

PL1
HCB2012KF-121T50_0805
PH1 under CPU botten side :
1 2
VIN CPU thermal protection at 92 +-3 degree C
PL2
HCB2012KF-121T50_0805
Recovery at 80 +-3 degree C
ADPIN 1 2 VL
PJPDC1

4 4

@4.7U_0805_25V6-K

@4.7U_0805_25V6-K
1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
3 3

22K_0402_1%
1

2
PC4
PC14
1
2 2 1

PC1

PC2

PC3
PC13
PC5

2
0.1U_0603_16V7K

PR1
1

2
1
@CVILU_CI0104P1VRB-NH
X7R type

1
PU1
1 8 OTP_N_001
VCC TMSNS1
2 7 OTP_N_002 2 1
GND RHYST1
3 6 PR2 22.1K_0402_1%
OT1 TMSNS2

1
4 OT2 RHYST2 5

OTP_N_003
G718TM1U_SOT23-8 PH1
100K_0402_1%_NCP15W F104F03RC

2
PL3
HCB2012KF-121T50_0805
1 2
PR4
VMB 2 1
PJP2 VS_ON 41
PL4
1 HCB2012KF-121T50_0805 0_0402_5%
1
2 2 1 2 BATT+
3 3
4 4
EC_SMCA

10U_0805_25V6K
5 5

1
PC15
6 EC_SMDA
6
2

7 TS_A PC6
7 PR27 1000P_0402_50V7K
8

2
8 1K_0402_1% PC7
9
@PJSOT24CW_SOT323-3

2 9 0.01U_0402_25V7K 2

G1 10
1

11 PD1
1

G2

@SUYIN_200275MR009G180ZR
2

PD2 B+ 3 1 +VSBP
2

100K_0402_1%

0.1U_0603_25V7K
1

0.22U_0603_25V7K
1
3

1
PC8

PC9
PR10
PR28
100_0402_1% @PJSOT24CW _SOT323-3
1 2 EC_SMB_CK1 32

2
2

2
1 2 PQ1
EC_SMB_DA1 32 VL
PR31 PR12 TP0610K-T1-GE3_SOT23-3
100_0402_1% 22K_0402_1%
PR29 1 2 VSB_N_001

1VSB_N_003
1 2 +3VALW
PR13
100K_0402_5% 100K_0402_1%
PR30
1 2 PR16
BATT_TEMP 32

1
0_0402_5% D
1K_0402_1%
41,44 SPOK 1 2VSB_N_002 2 PQ2
3
G SSM3K7002FU_SC70-3 3

0.1U_0402_16V7K
S

3
1

PC10
2
VIN
2

PD3
PJ2
RLS4148_LL34-2
2 1
VS_N_001

+VSBP +VSB
1

2 1
@JUMP_43X39

BATT+ 2 1 (120mA,40mils ,Via NO.= 1)


1

PD4
RLS4148_LL34-2 PQ3 PR17 PR18
TP0610K-T1-GE3_SOT23-368_1206_5% 68_1206_5%
2

N1 3 1 VS
1

PC12
PR21 PC11 0.1U_0603_25V7K
100K_0402_1% 0.22U_0603_25V7K
2

2
2

4 4

1 2 VS_N_002
36 51_ON#
PR22
22K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN / BATT CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 40 of 49
A B C D
A B C D E

2VREF_6182

1
1 1
PC308
1U_0603_16V6K

2
PR301 PR305
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR302 PR306
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 FB_3V FB_5V 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
PR303 PR307
@680P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K

10U_0805_25V6K
0.1U_0402_25V6

0.1U_0402_25V6
133K_0402_1% 165K_0402_1%
1

1
4.7U_0805_25V6-K

1 2 1 2
1

1
PC322

PC309

PC310

PC311

PC312
PC304

PC306
PQ303
2

2
6

1
AON7408L_DFN8-5 PU301
2

5
ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
1
PC313 PQ305
4 10U_0805_6.3V6M 25 AON7408L_DFN8-5
P PAD

2
7 VO2 VO1 24 4
2 2

1
2
3
PC314 8 23 PR309 PC315
0.1U_0402_10V7K PR308 VREG3 PGOOD 2.2_0402_5% 0.1U_0402_10V7K
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 1 2

3
2
1
PR311 0_0402_5% BOOT2 BOOT1 PR310
PL303 1 2 UG_3V 10 21 UG_5V 1 2 PL305
4.7UH_FMJ-0630T-4R7 HF_5.5A_20% 0_0402_5% UGATE2 UGATE1 0_0402_5% 4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

8
7
6
5

5
6
7
8

1
@4.7_1206_5%

@4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
PR312

PQ304

SKIPSEL

PR313
VREG5
1
PR314 1

GND

VIN
+

NC
PC303 499K_0402_1%

EN
2

2
220U 6.3V M 6.3X5.9 R15M VL HF 4 1 2 4 + PC305
B++ SPOK 40,44
220U 6.3V M 6.3X5.9 R15M VL HF
1 SNUB_3V

SNUB_5V
13

14

15

16

17

18
2 RT8205LZQW(2) WQFN 24P PWM
EN0 2
AO4468L_SO8 PQ306
1
2
3

3
2
1
@680P_0402_50V7K

@680P_0402_50V7K
VL AO4406AL 1N SO8

1
PC316

PC317
PR315
95.3K_0402_1% PC320
2

1U_0603_10V6K

2
1
PC318
4.7U_0805_10V6K

2
1
B++
PC319

2
3 0.1U_0603_25V7K 3

2VREF_6182
ENTRIP1

ENTRIP2
6

D D
PQ307A 2 N_3_5V_001 5 PQ307B
SSM6N7002FU_US6 G G SSM6N7002FU_US6 +3VLP +CHGRTC
PJP302
S S 2 1
1

PAD-OPEN 2x2m
PJP306

+5VALWP 1 2 +5VALW (5A,200mils ,Via NO.= 10)


1 2
VL PAD-OPEN 4x4m VL
40 VS_ON
1

PR317 PJP305 PJP301


100K_0402_5%
+5VALWP 1 2 +5VALW (5A,200mils ,Via NO.= 10) 2 1

PAD-OPEN 2x2m
PAD-OPEN 4x4m
1 2 2
VS PJP303
42.2K_0402_1%

2.2U_0603_10V6K

PR319 PQ308
+3VALWP 1 2 +3VALW (4A,120mils ,Via NO.= 8)
1

100K_0402_1% LTC015EUBFS8TL NPN UMT3F


1
PR320

PC321

PAD-OPEN 4x4m
3
2
2

4 4

EC:+3VL, reserve PR319, install PR318, PR320 100K


EC:+3VALW, reserve PR318, install PR319, PR320 42.2K Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LAXXXX 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 41 of 49
A B C D E
A B C D

1 1

PL402
PU401 PL401 <Vo=1.8V> VFB=0.6V

4
+5VALW HCB1608KF-121T30_0603 1UH_VLS252012T-1R0N1R7_2.4A_30%
1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V

PG
PVIN LX +1.8VSGP

68P_0402_50V8J
9 PVIN LX 3

1
4.7_1206_5%
1

1
PC404
PC403 8 SVIN

PR403
22U_0805_6.3VAM PR401
6 1.8VSP_FB 20K_0402_1%
2

2
FB

22U_0805_6.3VAM

22U_0805_6.3VAM
5

2
EN

1
NC

NC
TP

PC401

PC402
11

2
SNUB_1.8VSP
2
1 2 EN_1.8VSP 2

25,38,45 VGA_PWR_ON

1
1
PR404 200K_0402_5%

0.1U_0402_10V7K
PC405
RT8061AZQW W DFN 10P PR402

1
1 2 PR405 10K_0402_1%
@47K_0402_5%

2
PD401

680P_0402_50V7K
2

2
1SS355_SOD323-2

1
PC406

2
PJP401

+1.8VSGP 1 2 +1.8VSG (2A, 80mils, Via NO.= 4)


PAD-OPEN 3x3m
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VSGP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 42 of 49
A B C D
5 4 3 2 1

D D

1.5V_B+
PR503 PL502 B+
2 1 EN_1.5V HCB1608KF-121T30_0603
32,38 SYSON 2 1
0_0402_5% PC505

1
@0.1U_0402_10V7K

10U_0805_25V6K

2200P_0402_50V7K
@4.7U_0805_25V6-K

0.1U_0402_25V6
2

PC507
PC503

PC504

PC506
PR504

2
2.2_0402_5%
BST_1.5V 1 2BST1_1.5V 1 2
4
PC508
0.1U_0402_10V7K

15

14
1
PU501 PQ501
PR506 AON7408L_DFN8-5

EN/DEM

NC

BOOT

3
2
1
255K_0402_1% PR505 +1.5VP
1 2TON_1.5V 2 TON UGATE 13 UG_1.5V 2 1 PL501
C 1UH +-20% VMPI0703AR-1R0M-Z01 11A C
LX_1.5V 0_0402_5%
+1.5VP 3 VOUT PHASE 12 1 2

+5VALW 1 V5FILT_1.5V TRIP_1.5V 1 PR508 15K_0402_1%


+5VALW 2 4 VDD CS 11 2

@4.7_1206_5%
PR507 PR501

5
6
7
8

1
+1.5VP 1 2 FB_1.5V 5 10 +5VALW +5VALW 1
100_0402_1% FB VDDP

PR509
1

1
2.21K_0402_1% 6 9 LG_1.5V PQ502 + PC501
PGOOD LGATE

PGND
PC509 PC510 FDS6690AS-G_SO8 220U 6.3V M 6.3X5.9 R15M VL HF
GND
1

4.7U_0603_10V6K 4.7U_0805_10V6K
2

2
PR502 2
4
2.15K_0402_1%

1SNUB_1.5V
7

8
RT8209MGQW _W QFN14_3P5X3P5

@680P_0402_50V7K
2

3
2
1

PC511
2
B PJP502 B

1 2

@PAD-OPEN 4x4m
PJP501

+1.5VP 1 2 +1.5V (8A,320mils ,Via NO.= 16)


@PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LAXXXX 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 43 of 49
5 4 3 2 1
5 4 3 2 1

D D
1.1V_B+
PR703 PL702 B+
2 1 EN_1.1V HCB1608KF-121T30_0603
40,41 SPOK 2 1
0_0402_5% PC704

1
@0.1U_0402_10V7K

10U_0805_25V6K

2200P_0402_50V7K
1

0.1U_0402_25V6
2

1
PC702

PC705

PC706
PR704

2
2.2_0402_5% 2

2
BST_1.1V 1 2 BST1_1.1V 1 2
4
PC707
0.1U_0402_10V7K

15

14
1
PU701 PQ701
PR705 PR710 AON7408L_DFN8-5

EN/DEM

NC

BOOT

3
2
1
255K_0402_1% 0_0402_5% +1.1VALWP
1 2TON_1.1V 2 TON UGATE 13 UG_1.1V 2 1 PL701
2.2UH_PCMC063T-2R2MN_8A_20%
+1.1VALW P 3 12 LX_1.1V 1 2
VOUT PHASE PR708 14K_0402_1%
+5VALW +5VALW 1 2 V5FILT_1.1V 4 11 TRIP_1.1V 1 2
VDD CS

@4.7_1206_5%
PR701

5
6
7
8

1
PR707 1 2 5 10 +5VALW +5VALW 1
FB VDDP

2
PR709
100_0402_1% +1.1VALW P FB_1.1V
1

1
4.75K_0402_1% 6 9 LG_1.1V PQ702 PR706 + PC701
PGOOD LGATE
1

PGND
C PC708 PC709 @100K_0402_5% 220U 6.3V M 6.3X5.9 R15M VL HF C

GND
4.7U_0603_6.3V6M PR702 4.7U_0805_10V6K AO4468L_SO8
2

2
10K_0402_1% 2
4

1
RT8209MGQW _W QFN14_3P5X3P5

1SNUB_1.1V
7

8
2

@680P_0402_50V7K
3
2
1

PC710
2
PJP701

+1.1VALW P 1 2 +1.1VALW (5A,200mils ,Via NO.=20)


PAD-OPEN 4x4m

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR+1.1VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LAXXXX
Date: Friday, April 29, 2011 Sheet 44 of 49
5 4 3 2 1
5 4 3 2 1

+1.5V

PU601
1 VIN NC 8 +3VALW
2 GND NC 7

1
D D

1
PC601 3 6
VREF VCNTL

1
4.7U_0805_6.3V6K

2
PR601 PC603
4 VOUT NC 5
1K_0402_1% 1U_0603_10V6K

2
9

2
TP
APL5336KAI-TRL_SOP8P8
VREF_G2992

+0.75VSP

0.1U_0402_16V7K
1
PQ602
SSM3K7002FU_SC70-3

1
PR604 D
PR602

1
2 10.75VS_N_002 2 1K_0402_1%
28,38 SUSP G PC605

2
10U_0805_6.3V6M

PC604
S

2
0_0402_5%

1
PC606
2 @0.1U_0402_10V7K

C PJP601 C

+0.75VSP 1 2 +0.75VS (2A,80mils ,Via NO.= 4)


PU603
PAD-OPEN 3x3m
APL5508-25DC-TRL_SOT89-3

+3VS 2 3
IN OUT
+2.5VSP

4.7U_0805_6.3V6K

1
GND

1
PC607
1U_0402_6.3V6K 1 PR605

PC608
@150_1206_5%

2
+5VALW

+1.5V
1U_0603_10V6K
1

PC612
2
4.7U_0805_6.3V6K

PJP602
+2.5VSP 1 2 +2.5VS
PU602 APL5930KAI-TRG_SO8
1
PC611

6 VCNTL PAD-OPEN 3x3m


5 VIN VOUT 3 +1.0VSP
9 4
2

VIN VOUT
1

B B
PR610

1
8 1.82K_0402_1%

180P_0402_50V8J

22U_0805_6.3V6M
PR609 EN

PC614

PC615
7 2
GND

15K_0402_1% POK FB 2

2
25,38,42 VGA_PWR_ON 1 2
2
1
1

1 2
1

PC613
PD601 0.1U_0402_16V7K PR611
2

1SS355_SOD323-2 7.32K_0402_1%
2

PJP603

+1.0VSP 1 2 +1.0VSG (2.5A,100mils ,Via NO.= 5)


PAD-OPEN 3x3m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR 0.75VSP/1.0VSP/2.5VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LAXXXX 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 45 of 49
5 4 3 2 1
A B C D

1 1

1.2V_B+
PR803 PL802 B+
2 1 EN_1.2V HCB1608KF-121T30_0603
32,38 VLDT_EN
0_0402_5% 2 1
PC804
1
@0.1U_0402_10V7K

2200P_0402_50V7K
10U_0805_25V6K

0.1U_0402_25V6
2

PC806
PC802

PC805
2 2

PR804

2
2.2_0402_5%
BST_1.2V 1 2BST1_1.2V 1 2
4
PC807
0.1U_0402_10V7K

15

14
1
PU801 PQ801
PR805 AON7408L_DFN8-5

EN/DEM

NC

BOOT

3
2
1
255K_0402_1% +1.2VS
1 2TON_1.2V 2 TON UGATE 13 UG_1.2V PL801
2.2UH_PCMC063T-2R2MN_8A_20%
+1.2VS 3 12 LX_1.2V 1 2
VOUT PHASE

+5VALW +5VALW 1 2 V5FILT_1.2V 4 11 TRIP_1.2V 1 PR808 2


15K_0402_1%
VDD CS
PR801

5
6
7
8

1
PR807 +1.2VS 1 2 FB_1.2V 5 10 +5VALW +5VALW 1
100_0402_1% FB VDDP PR809

220U_D2_2VY_R15M
1

1
+

PC801
3.24K_0402_1% 6 9 LG_1.2V @4.7_1206_5%
PGOOD LGATE

PGND
PC808 PC809 PQ802
GND
1

4.7U_0603_6.3V6M 4.7U_0805_10V6K AO4406AL 1N SO8


2

1SNUB_1.2V 2
PR802 2
4
5.36K_0402_1% RT8209MGQW _W QFN14_3P5X3P5
7

8
2

3
2
1
PC810
@680P_0402_50V7K

2
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.2VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 46 of 49
A B C D
5 4 3 2 1

PL204
HCB2012KF-121T50_0805
1 2
CPU_B+ PL205
HCB2012KF-121T50_0805
1 2 B+

10U_0805_25V6K

2200P_0402_50V7K
0.01U_0402_25V7K
PLACE NEAR NB choke

@68U_25V_M

68U_25V_M
1 1

10U_0805_25V6K
1

1
VSUMG+ + +

PC226

PC225

PC228

PC229

PC230

PC227
PR202 PC231

5
10_0402_5% 0.01U_0402_16V7K

4.02K_0402_1%

2
2 2

PR203
2 1

0.1U_0402_10V7K

0.047U_0402_16V7K
1 2 PR254

11K_0402_1%
2

1
D D
0_0603_5% PQ205
8 APU_VDDNB_RUN_FB_L

1PH203_NB 2
PC232

PC233

PC234

PR201
2 1 4
@330P_0402_50V7K TPCA8065-H_PPAK56-8-5
8 APU_VDDNB_SEN

2
PR204 2 1
+CPU_CORE_NB 10_0402_5%

2
2 1 PL203

3
2
1
PC266 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
@330P_0402_50V7K PH203 PHASE_NB 1 4
+CPU_CORE_NB
PLACE NEAR NB L-MOS 10K_0402_5%_ERTJ0ER103J 2 3

5
PQ206

TPCA8059-H_PPAK56-8-5
2

1
VSUMG-
PR205
PC236 PR207 PR208 4.7_1206_5%

VSUMG+_1

VSUMG-_1
470P_0402_50V7K 143K_0402_1% 2.37K_0402_1% PH204

1
2 1COMP_NB_1
2 1 2 1 470K_0402_5%_TSM0B474J4702RE 4

845_0402_1%

SNUB_NB 2
1 2 PC235

PR206
0.1U_0603_50V7K

2
PR211 PR213
1

27.4K_0402_1% 3.65K_0805_1%

3
2
1
PR209 2 1 2 1FB_NB_12 1 1 2NTC_NB_1 1 2 VSUMG+ 2 1
100K_0402_1% PR212

1
PC238 PR210 PC239 3.83K_0402_1%

BOOT1_NB 6.65K_0402_1%
100P_0402_50V8J 324_0402_1% 1000P_0402_50V7K PC237 PR214
2

UGATE_NB 680P_0402_50V7K 1_0402_1%

2
2
PR215 PC240 VSUMG-

PR217
2 1
+5VS 2.2_0603_5% 0.1U_0603_50V7K CPU_B+
2

2 1BOOST1_NB1 2 1

LGATE_NB
2

ISUMN_NB

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
0.01U_0402_25V7K
PR216 PC241

PROG2 1
8.06K_0402_1% 1000P_0402_50V7K

NTC_NB
1
1

1
PC223

PC224

PC242

PC243
Rfset(Kohm)=(Period(uS))-0.29)*2.65

2
5
48

47

46

45

44

43

42

41

40

39

38

37
PU201 +5VS
C C

PROG2
ISEN1_NB

ISEN2_NB

VSEN_NB

RTN_NB

ISUMP_NB

ISUMN_NB

NTC_NB

BOOT1_NB

UG1_NB

PH1_NB

LG1_NB
PR255
0_0603_5% PQ203
1 36 UGATE2 2 1 4
FB2_NB PWM2_NB

1
PR219 TPCA8065-H_PPAK56-8-5

0_0402_5%
FB_NB 2 35 BOOT2 0_0603_5%
FB_NB BOOT2

PR218
COMP_NB 3 34 UGATE2

3
2
1
+3VS COMP_NB UG2 PL202

6267_VCCP1 2
VW_NB 4 33 PHASE2 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
VW_NB PH2 PHASE2 1 4
5 32 LGATE2 +CPU_CORE
PGOOD_NB LG2
1

PR223 0_0402_5% PR224 PR226 PC244 ISEN2 2 PR220 1 2 3 1 PR222 2 ISEN1

5
8 APU_SVD 2 1 SDA 6 31 6267_VCCP1 2 2.2_0603_5% 0.1U_0603_50V7K PQ204 10K_0402_1% 10K_0402_1%
SVD VCCP
1

VSUM+_2
PR221 PR227 0_0402_5% ISL6267HRZ-T_QFN48_6X6 0_0402_5% BOOT2 2 1BOOT2_12 1 PR228
100K_0402_5% 2 1 ALERT# 7 30 PWM3 4.7_1206_5%

TPCA8059-H_PPAK56-8-5
13 APU_PWRGD_L PWROK PWM3

1
PR229 0_0402_5%

1U_0603_10V6K
2

1 SCLK LGATE1 VSUM+ 2 PR230 1

PC245
8 APU_SVC 2 8 29
PR225 PR253 0_0402_5% SVC LG1 LGATE2 3.65K_0805_1%
4
2

2
@100K_0402_5% 2 1 9 28 PHASE1
32 VR_ON ENABLE PH1 PR231

SNUB_CPU2
10 27 UGATE1 1_0402_1%
32 VGATE PGOOD UG1 VSUM- 2 1 VSUM-_2

3
2
1
11 26 BOOT1
8,13,32 EC_THERM# PROC_HOT BOOT1
PR232 3.83K_0402_1% PR233 27.4K_0402_1%
ISEN3/FB2

2 1PH202_CPU 2 1 NTC_CPU 12 25 PROG1_CPU 1 2


NTC PROG1 PC246
ISUMN

ISUMP
COMP

1
ISEN2

ISEN1

VSEN

PR234 680P_0402_50V7K
VDD
RTN

VIN
VW

6.65K_0402_1% If the layout of each phase to CPU


FB

TP

2 1 is symmetric, the two res. can be

2
PLACE NEAR Phase1 L-MOS
13

14

15

16

17

18

19

20

21

22

23

24

49

PH202 470K_0402_5%_TSM0B474J4702RE removed.


VW_CPU
They are used for phase current
1 VDD_CPU

balance adjustment.
ISEN3_FB2_CPU

VIN_CPU

2 PR2351
1U_0603_10V6K

CPU_B+
1

COMP_CPU 0_0603_5%
ISUMN_CPU
1

2 1 +5VS
PR236 PC247 PR237
B B
8.06K_0402_1% 1000P_0402_50V7K 1_0603_5%
0.22U_0603_25V7K
2

PC248 33P_0402_50V8J CPU_B+


Rfset(Kohm)=(Period(uS))-0.29)*2.65
2

PC250

1 2
2

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
0.01U_0402_25V7K
FB_CPU
PC249

1
PR238 VSUM+

PC222

PC221

PC254

PC253
5
100K_0402_1% PC251 PR239 PC252
1

2 1 2 1 2 1FB_CPU_1
2 1 ISEN2

2
PR240
68P_0402_50V8J 324_0402_1% 1000P_0402_50V7K 2.61K_0402_1%
0.22U_0402_16V7K

0.01U_0402_16V7K

ISEN1 PQ201
11K_0402_1%
1

PC255 PR241 PR242 UGATE1 4


0.22U_0402_10V6K

0.22U_0402_10V6K

1PH201_CPU 2

1COMP_CPU_12
PC258

PC259

PR243

2 1 2 1 TPCA8065-H_PPAK56-8-5
1

470P_0402_50V7K 143K_0402_1% 2.43K_0402_1%


PC256

PC257

PL201
2

3
2
1
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PHASE1 1 4
PR248 VSUM-
10_0402_5% PH201 PR247 PC260 ISEN1 2 PR245 1 2 3 1 PR246 2 ISEN2

5
+CPU_CORE 2 1 10K_0402_5%_ERTJ0ER103J 2.2_0603_5% 0.1U_0603_50V7K 10K_0402_1% 10K_0402_1%

VSUM+_1
PR244 BOOT1 2 1BOOT1_1 2 1 PQ202 PR249
976_0402_1% 4.7_1206_5%
2

2 1 2 1 VSUM-

TPCA8059-H_PPAK56-8-5
VSUM+ 2 PR250 1
PC261 LGATE1 4 3.65K_0805_1%
8 APU_VDD_SEN

2
1

@330P_0402_50V7K
PC263 PC262 PR251

SNUB_CPU1
8 APU_VDD_RUN_FB_L
@330P_0402_50V7K PLACE NEAR Phase1 choke 0.1U_0603_50V7K 1_0402_1%
2

1 2 VSUM- 2 1 VSUM-_1

3
2
1
PR252
10_0402_5% PC264
2 1 0.01U_0402_16V7K
PC265

1
A 680P_0402_50V7K A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/11/11 Deciphered Date 2011/11/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+CPU_CORE/+CPU_CORE_NB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEQAE LA-7291P M/B
Date: Friday, April 29, 2011 Sheet 47 of 49
5 4 3 2 1
A B C D

PL902
HCB2012KF-121T50_0805
1 2 VGA_B+
B+

10U_0805_25V6K

10U_0805_25V6K
1 1

@4.7U_0805_25V6-K
1

0.1U_0402_25V6

2200P_0402_50V7K
PC912

PC911

1
PC914

PC915
PC913
2

5
TPCA8065-H_PPAK56-8-5

@TPCA8065-H_PPAK56-8-5
2

2
+3VS PQ901 PQ906

2
PR905
10K_0402_1% 4 4

1
PU901 PR906 PC916
1 10 BST_VGA 1 2BST1_VGA 1 2
13,25 VGA_PW RGD

3
2
1

3
2
1
PGOOD VBST 2.2_0603_5%
1 PR9072TRIP_VGA 2 9 DH_VGA 2 1 0.1U_0603_25V7K PL901 +VGA_CORE
73.2K_0402_1% TRIP DRVH PR919 0_0603_5% 0.36UH_PDME104T-R36MS0R825_37A_20%
1 PR908 2 EN_VGA 3
EN SW 8 LX_VGA 1 2
25,38 1.5_VDD_PW REN PR909
1

1
0_0402_5% FB_VGA 4 7 V5IN_VGA 1 2

@.1U_0402_16V7K
+5VALW

TPCA8059-H_PPAK56-8-5
VFB V5IN

5
PC917 0_0603_5% PR910

330U_D2_2V_Y
2
5 6 DL_VGA PQ902 PQ903 @4.7_1206_5% 1
2

RF DRVL PC918

PC901
RF_VGA

2
11 +

1
TP 0.1U_0402_10V7K

1SNUB_VGA
RT8237CZQW (2) W DFN 4 4

1
2
2

2 TPCA8059-H_PPAK56-8-5 2

PC919
2.2U_0603_6.3V6K

3
2
1

3
2
1
PR911 PC920
470K_0402_1% @680P_0402_50V7K
1

2
PR912
+VGA_CORE1 2 1 GCORE_SEN 21

@10K_0402_1%
100_0402_1%

6.19K_0402_1%
2

2
PR903

PR904
+3VSG
+3VSG
3.01K_0402_1%

FB1_VGA1

FB0_VGA 1
2

2
PR901 PR913

10K_0402_1%
@10K_0402_1%

2
PR915

PR914
@5.1K_0402_1%
1

1
D

1
19 GPU_VID1 PR917

@SSM3K7002FU_SC70-3
D

1
19 GPU_VID0

PQ904
2GPU_VID1_1 1 2 5.1K_0402_1%

@.1U_0402_16V7K

1
2
G 2 GPU_VID0_1 1 2

1
S PR916 G

0.1U_0402_16V7K
3

2
@10K_0402_5%

PC921
S

1
PQ905 PR918

PC922
2
@10K_0402_5%

1
SSM3K7002FU_SC70-3

2
3 3

1
Rtrip = 73.2K, OCP = 34.42A
Rrf = 470K, FSW = 290KHz
1

PR902
GPU VID1 GPU VID0 Whistler Pro 6.98K_0402_1%
2

X L 1.0V
X H 0.9V
H L
H H

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/05/29 Deciphered Date 200810/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LAXXXX 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 48 of 49
A B C D
5 4 3 2 1

Version change list (P.I.R. List) Power section Page 1 of 1

Item Reason for change PG# Modify List Date Phase


1

2
D D

C C

B B

A A

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Changed-List History
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
QBL70 LA-7553P 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 49 of 51
5 4 3 2 1
5 4 3 2 1

POWER SEQUENCE

ACIN/BATT-IN

+5VALW

D D

+3VALW

+1.1VALW

EC_RSMRST#
T2>10ms

T2A<50ms

T3>16ms
RTC_CLK

PBTN_OUT#

SLP_S5# T13>8ns
SLP_S3#
Delay SLP_S5#
SYSON

+1.5V

Delay SLP_S3#
SUSP#
C C

+5VS

+3VS

+1.8VS

+1.05VS/+0.75VS

VLDT_EN Delay SUSP# 10ms

T13A>80ns
+1.1VS
FCH_PWRGD

VGA_ON Delay SUSP# 10ms

1.5_VDDC_PWREN AND from VGA_ON & PX_EN

+VGA_CORE/+1.5VSG
B B

+1.8VSG/+1.0VSG
T<20ms +3VSG to +1.0VSG power up

VGA_PWRGD

VR_ON VGA_ON Delay 20ms

+APU_CORE/+APU_CORE_NB

VGATE

T7B<1ms
T7A<50ms

FCH_PWRGD

98ms<T7<150ms
APU_PWRGD

A
A_RST# 101ms<T9A<113ms
A

T8A<100ns

PLT_RST#
101ms<T9<113ms

APU_RST# 1ms<T8C<2.3ms

Security Classification Compal Secret Data


Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
Power Sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-7553P 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Friday, April 29, 2011
Date: Sheet 50 of 51
5 4 3 2 1
5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1 for HW

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

For AMD reuqest 0.11 PG#26 Translator change to ANX3110 03/15 ER


1
D D
For AI charge function 0.11 PG#34 Add U2 & U55 03/15 ER
2
For PBL70 MEMO 0.11 PG#32 Change LED1 to Green color. 03/15 ER
3
Change R1584 to 100 ohm.
4 For LED brightness. 0.11 PG#32 Change R1586,R1588,R1591,R1592,R1593 to 100 ohm 03/15 ER

For LED1 brightness. 0.11 PG#32 Change LED1 power to 3VALW 03/15 ER
5
For USB3.0 & AI charger 0.12 PG#30 USBP0 connect to JUSB1 and USBP10 connect to JUSB2 03/22 ER
6
For LED1 0.12 PG#35 LED1 connect to +3VALW 03/22 ER
7
For +5VS rising time 0.2 PG#38 R1103 change to 47K 03/25 ER
8
For AI charger 0.2 PG#30 U2 reserve CEN# to EC 03/25 ER
9
C C
For AMD spec 0.2 PG#27 R1642 & R1646 change to 4.7K ohm 03/25 ER
10
PG#15 Unpop U28,R626,R935,R934,R35,C466
For share ROM request 0.2 PG#16 Pop R910,unpop R921 03/25 ER
11
Add Q101,R1644,R1645
For +3VS leakage from CRT 0.21 PG#27 Delete R17,R31 03/31 PR
12
For Crystal EA 0.21 PG#13 Y4 change to SJ100007N00 03/31 PR
13
For EMI ISN 0.22 PG#31 C1636 change to 100P 04/19 PR
14
For thermal team recommand 0.22 PG#19 Add R1816,R1817 reserve R1814,R1815 04/19 PR
15
For BRD ID 0.22 PG#32 Change R1606 to 215K. 04/19 PR
16
Reserve PX_EN signal 0.22 PG#32 Reserve PX_EN signal to EC pin74 04/19 PR
17
B
PG#11 B
For JDIMM1 and JDIMM2 location definition 0.22 PG#12 Swap JDIMM1 and JDIMM2 location 04/19 PR
18
Prevent the leakage from CRT monitor. 0.23 PG#27 Add R1644, R1645, Q2 and Del R17, R31. 04/22 PR
19
for EMI request 0.23 PG#31 H1 change to connect to GND 04/22 PR
20
Don't use for MP 0.23 PG#13 Unpop C1193 04/22 PR
21
For VGA Sequence. 0.23 PG#38 Change R1127 from 470 ohm to 33 ohm. 04/22 PR
22
for EMI request 1.0 PG#30 modify USB3.0 redriver schemaitc 04/25 PR
23
For de-emphasis USB3.0 signal 1.0 PG#30 reserve TEST and I2C_EN net 04/25 PR
24
For some HDMI device detect error 1.0 PG#28 Change R200,R201 to 3.9K ohm 04/25 PR
25
A A
For WLAN module rising time specification 1.0 PG#35 Change R114 to 20K ohm C1663 change to 4700P 04/25 PR
26

27
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-7322P 0.22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 51 of 51
5 4 3 2 1
5 4 3 2 1

Version change list (P.I.R. List) Page 3 of 3 for HW

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

Reduce the component count for MP. 1.0 Change below the footprints from 0 ohm to R short. 04/25 PR
1
D D
2

3
4

9
C C
10

11

12

13

14

15

16

17
B B
18

19

20

21

22

23

24

25
A A
26

27
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/25 Deciphered Date 2012/04/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR3
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom QBL60 LA-7552P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 29, 2011 Sheet 53 of 53
5 4 3 2 1
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