Microprocessors and Microcontrollers

Unit II
Instruction Set and
Assembly Language Programming of 8086:
Part 3

B.Tech, ETM,
II Year, II Semester
N.Ramakrishna
Dept. of Electronics and Telematics
GNITS, Hyderabad
April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 1
 Syllabus
Unit II
Instruction Set and
Assembly Language Programming of 8086:
• Instruction formats
• Addressing modes
• Instruction set
• Assembler directives
• Macros
• Simple programs involving logical, branch and
call instructions, sorting,
evaluating arithmetic expressions,
string manipulations.

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 2

 Instruction set of
8086 Microprocessor
Prepared By
Manish Singhal
Also from: Microprocessors and Interfacing
by Douglas V. Hall
Microprocessors and Microcontrollers
by Lyla B.Das
Adapted and Modified by
N.Ramakrishna
April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 3
 Logical Instructions
Mnemonic Meaning Format Operation Flags Affected
AND Logical AND AND D, S (S) · (D)  (D) OF, CF = 0
SF, ZF, PF,
AF undefined
OR Logical OR OR D, S (S)+(D)  (D)
OF, SF, ZF, PF, CF
AF undefined
XOR Logical Exclusive XOR D, S (S) + (D)(D)
OR OF, SF, ZF, PF, CF
AF undefined
NOT LOGICAL NOT NOT D (D)  (D)
Destination Source
None

Register Register
Destination
Register Memory
Memory Register Register
Register Immediate Memory
Memory Immediate
Accumulator Immediate
April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 4
 Logical Instructions
AND
• Uses any addressing mode except memory-to-memory and
segment registers
• Especially used in clearing certain bits (masking)
XXXX XXXX
AND 0 0 0 0 1 1 1 1
= 0 0 0 0 XXXX (clear the first four bits)
Examples: AND BL, 0FH;
AND AL, [0345H];
OR
• Used in setting certain bits
XXXX XXXX
OR 0 0 0 0 1 1 1 1
= XXXX 1 1 1 1 (Set the lower four bits)

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 5

 Logical Instructions
XOR
– Used in inverting bits
if AX=FF00H
XOR AX,F000h:
Results:0FOOH

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 6

 Shift and Rotate Instructions

 SHL/SAL: shift logical left/

shift arithmetic left (same)
 SHR: shift logical right
 SAR: shift arithmetic right
 ROL: rotate left
 RCL: rotate left through carry
 ROR: rotate right
 RCR: rotate right through carry

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 7

 Logical vs Arithmetic Shifts
• A logical shift fills the newly created bit position
with zero: SHR

0
CF

• An arithmetic shift fills the newly created bit position

with a copy of the number’s sign bit (MSB):
SAR

CF

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 8

 Shift Instructions
Mnemo Meaning Format Operation Flags
-nic Affected
SAL/ Shift SAL/SHL D, Count Shift the (D) left by the CF,PF,SF,ZF
SHL Arithmetic number of bit positions AF undefined
Left/SHift equal to count and fill the OF undefined
Logical left vacated bits positions on if count ≠1
the right with zeros

Shift the (D) right by the CF,PF,SF,ZF

SHR SHift SHR D, Count number of bit positions AF undefined
logical equal to count and fill the OF undefined
Right vacated bits positions on if count ≠1
the left with zeros

Shift the (D) right by the CF,PF,SF,ZF

Shift SAR D, Count number of bit positions AF undefined
SAR Arithmetic equal to count and fill the OF undefined
Right vacated bits positions on if count ≠1
the left with the original
most significant bit
April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 9
 Shift Instructions
Allowed operands

Destination Count

Register Immediate

Register CL

Memory Immediate

Memory CL

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 10

 Shift Instructions

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 11

 SHL Instruction

• The SHL (shift left) instruction performs a logical left

shift on the destination operand, filling the lowest bit
with 0.

0
CF

• Operand types:
SHL reg,imm8
SHL mem,imm8
SHL reg,CL
SHL mem,CL
April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 12
 Fast Multiplication

Shifting left 1 bit multiplies a number by 2

MOV DL,5 Before: 00000101 =5

SHL DL,1 After: 00001010 = 10

Shifting left n bits multiplies the operand by 2n

For example, 5 * 22 = 20
MOV DL, 5 ;
SHL DL, 2 ; DL = 20

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 13

 Fast Multiplication

Ex.
; Multiply AX by 10
SHL AX,1 ; multiply AX by 2
MOV BX, AX ; copy AX to BX
MOV CL,2 ; copy 2 to CL (count)
SHL AX,CL ; multiply AX by 4
ADD AX, BX ; Add AX and BX to
get 10 AX

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 14

Unit II Part 3 14
 SHR Instruction
• The SHR (shift right) instruction performs a logical right
shift on the destination operand. The highest bit
position is filled with a zero.

0
CF

Shifting right n bits divides the operand by 2n

MOV DL,80
SHR DL,1 ; DL = 40
SHR DL,2 ; DL = 10

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 15

 SAR Instruction
• SAR (shift arithmetic right) performs
a right arithmetic shift on the destination operand.

CF

An arithmetic shift preserves the number's sign.

MOV DL,-80
SAR DL,1 ; DL = -40
SAR DL,2 ; DL = -10

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 16

 Rotate Instructions
Mnem Meaning Format Operation Flags Affected
-onic
ROL Rotate ROL D,Count Rotate the (D) left by the CF
Left number of bit positions equal OF undefined
to Count. Each bit shifted out if count ≠ 1
from the left most bit goes back
into the rightmost bit position.
ROR Rotate ROR D,Count Rotate the (D) right by the CF
Right number of bit positions equal OF undefined
to Count. Each bit shifted out if count ≠ 1
from the rightmost bit goes
back into the leftmost bit
position.
RCL Rotate RCL D,Count Same as ROL except carry is CF
Left attached to (D) for rotation. OF undefined
through if count ≠ 1
Carry
RCR Rotate RCR D,Count Same as ROR except carry is CF
Right attached to (D) for rotation. OF undefined
through if count ≠ 1
Carry
April 16, 2022 MPMC-N.Ramakrishna 17
 ROL Instruction
• ROL (rotate) shifts each bit to the left
• The highest bit is copied into both the Carry flag and
into the lowest bit
• No bits are lost

CF

MOV AL, 11110000b ;

ROL AL, 1 ; AL = 11100001b
MOV DL, 3FH ;
ROL DL, 4 ; DL = F3H
April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 18
 RCL Instruction
• RCL (rotate carry left) shifts each bit to the left
• Copies the Carry flag to the least significant bit
• Copies the most significant bit to the Carry flag
CF

CLC ; CF = 0
MOV BL,88H ; CF,BL = 0 10001000b
RCL BL,1 ; CF,BL = 1 00010000b
RCL BL,1 ; CF,BL = 0 00100001b
April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 19
 ROR Instruction
• ROR (rotate right) shifts each bit to the right
• The lowest bit is copied into both the Carry flag and
into the highest bit
• No bits are lost

CF

MOV AL,11110000b
ROR AL,1 ; AL = 01111000b
MOV DL,3Fh
ROR DL,4 ; DL = F3h
April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 20
 RCR Instruction
• RCR (rotate carry right) shifts each bit to the right
• Copies the Carry flag to the most significant bit
• Copies the least significant bit to the Carry flag
CF

STC ; CF = 1
MOV AH,10H ; AH,CF = 00010000 1
RCR AH,1 ; AH,CF = 10001000 0

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 21

 Rotate Instructions
Allowed operands
Destination Count

Register Immediate

Register CL

Memory Immediate

Memory CL

Similar to Shift instructions

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 22

 Flag control instructions
Mnem- Meaning Operation Flags
onic Affected
CLC Clear Carry Flag (CF)  0 CF
STC Set Carry Flag (CF)  1 CF
CMC Complement CF
Carry Flag (CF)  (CF)
CLD Clear Direction (DF)  0
Flag SI & DI will be auto incremented DF
while string instructions are executed.
STD Set Direction (DF)  1
Flag SI & DI will be auto decremented DF
while string instructions are executed.
CLI Clear Interrupt (IF)  0 IF
Flag
STI Set Interrupt (IF)  1 IF
Flag
April 16, 2022 MPMC-N.Ramakrishna 23
 Compare Instruction, CMP
Mnemo Meaning Format Operation Flags
nic Affected

CMP Compare CMP D,S (D) – (S) is used CF, AF, OF,
in setting or resetting PF, SF, ZF
the flags

Allowed Operands
Destination Source
Condition ZF CF SF
Register Register
(D) = (S) 1 0 0
Register Memory
(D) > (S) 0 0 0
Memory Register
(D) < (S) 0 1 1
Register Immediate
Memory Immediate
Accumulator Immediate
April 16, 2022 MPMC-N.Ramakrishna 24
 String

String : An array of bytes or words

located in memory
Examples : Array of characters A, B, C, D, …
Array of numbers 1, 2, 3, …
• Supported String Operations
• Copy (move, load)
• Search (scan)
• Store
• Compare
April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 25
 String Instruction - Basics

• Source DS:SI, Destination ES:DI

• Ensure DS and ES are correct
• Ensure SI and DI are offsets into DS and ES,
respectively.
• Direction Flag
( 0 = Up, increment pointers SI, DI addresses,
1 = Down, decrement pointers SI, DI addresses)
• CLD - Increment addresses (left to right)
• STD - Decrement addresses (right to left)

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 26

 String Instructions
Instruction prefixes
Prefix Used with Meaning

REP MOVS Repeat while not end of string

STOS CX ≠ 0

REPE/REPZ CMPS Repeat while not end of string

SCAS and strings are equal.
CX ≠ 0 and ZF = 1

REPNE / CMPS Repeat while not end of string

REPNZ and strings are not equal.
SCAS CX ≠ 0 and ZF = 0

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 27

 String Instructions
Mnemo- meaning format Operation Flags
nic affect
-ed
MOVS Move string MOVSB/ [(ES)0+(DI)]  [(DS)0+(SI)] none
DS:SI MOVSW (SI)  (SI) ± 1 or 2*
ES:DI (DI)  (DI) ± 1 or 2*

CMPS Compare CMPSB/ Set flags as per All

string CMPSW [(DS)0+(SI)] – [(ES)0+(DI)] status
(SI)  (SI) ± 1 or 2* flags
(DI)  (DI) ± 1 or 2*

* Note : If DF = 0, SI and DI are incremented after string operation

If DF =1, SI and DI are decremented after string operation
April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 28
 String Instructions

Mnemo- meaning format Operation

nic
SCAS Scan string SCASB/ Set flags as per
AL or AX SCASW (AL or AX) – [(ES)0+(DI)]
– ES:DI (DI)  (DI) ± 1 or 2
LODS Load string LODSB/ (AL or AX)  [(DS)0+(SI)]
DS:SI LODSW (SI)  (SI) ± 1 or 2
 AL or AX
STOS Store string STOSB/ [(ES)0+(DI)]  (AL or AX) ± 1 or 2
ES:DI STOSW (DI)  (DI) ± 1 or 2
 AL or AX

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 29

 Text Books
TEXT BOOKS:
1. Advanced Microprocessors and Peripherals – A. K.
Ray and K.M. Bhurchandi, Tata-McGraw Hill, 2nd
edition 2006.
2. D. V. Hall, Microprocessors and Interfacing, Tata-
McGraw Hill, 2nd edition 2006.
3. Kenneth. J. Ayala, The 8051 microcontroller , 3rd
edition, Cengage learning, 2010
4. Microprocessors and Microcontrollers, Lyla B.Das,
Pearson, 2012

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 30

 References
REFERENCES:
1. The 8051 Microcontrollers, Architecture and programming and
Applications -K.Uma Rao, Andhe Pallavi, , Pearson, 2009.
2. The 8051 Microcontoller and Embedded Systems Using
Assembly and C, Second Edition, Muhammad Ali Mazidi, Janice
Gillispie Mazidi, Rolin D. McKinlay, Prentice Hall
3. Micro Computer System 8086/8088 Family Architecture,
Programming and Design - Liu and GA Gibson,
Prentice Hall India, 2nd Ed.
4. Microcontrollers and application, Ajay. V. Deshmukh,
Tata-McGraw Hill, 2005
5. The 8085 Microprocessor: Architecture, programming and
Interfacing – K. Uday Kumar, B.S. Umashankar, 2008, Pearson

April 16, 2022 MPMC-N.Ramakrishna Unit II Part 3 31