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N

Apple iPhone SE Schematic

Diagram
Schematic
8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
4 0004752417 ENGINEERING RELEASED 2015-08-24

N69 MLB - EVT


D D

LAST_MODIFICATION=Wed Aug 19 11:42:47 2015


PAGE <CSA> CONTENTS SYNC DATE PAGE <CSA> CONTENTS SYNC DATE
1 46
1 TABLE OF CONTENTS 31 I/O:DOCK FLEX B2B
3
2 SYSTEM:BOM TABLES 32 I/O:BUTTON FLEX B2B
4 49
3 SYSTEM:N69 SPECIFIC [4] 33 BASEBAND:RADIO SYMBOL
5 50
4 SYSTEM:MECHANICAL 34 page1
6 51
5 SOC:JTAG,USB,XTAL 35 CELL:ALIASES
7
6 SOC:PCIE 36 AP INTERFACE & DEBUG CONNECTORS
8
7 SOC:CAMERA & DISPLAY 37 BASEBAND PMU (1 0F 2)
9
8 SOC:SERIAL & GPIO 38 BASEBAND PMU (2 OF 2)
10
9 SOC:OWL 39 BASEBAND (1 OF 2)
11
10 SOC:POWER (1/3) 40 BASEBAND (1 OF 2)
C 11
12
SOC:POWER (2/3) 41 MOBILE DATA MODEM (2 OF 2) C
13
12 SOC:POWER (3/3) 42 RF TRANSCEIVER (1 0F 3)
15
13 NAND 43 RF TRANSCEIVER (2 OF 3)
20
14 SYSTEM POWER:PMU (1/3) 44 RF TRANSCEIVER (3 OF 3)
21
15 SYSTEM POWER:PMU (2/3) 45 QFE DCDC
22
16 SYSTEM POWER:PMU (3/3) 46 2G PA
23
17 SYSTEM POWER:CHARGER 47 VERY LOW BAND PAD
24
18 SYSTEM POWER:BATTERY CONN 48 LOW BAND PAD
30
19 SENSORS:MOTION SENSORS 49 MID BAND PAD
31
20 CAMERA:FOREHEAD FLEX B2B 50 HIGH BAND PAD
32
21 CAMERA:REAR CAMERA B2B 51 ANTENNA SWITCH
33
22 CAMERA:STROBE DRIVER 52 HIGH BAND SWITCH
35
23 AUDIO:CALTRA CODEC (1/2) 53 RX DIVERSITY
36
24 AUDIO:CALTRA CODEC (2/2) 54 RX DIVERSITY (2)
37
25 AUDIO:SPEAKER DRIVER 55 GPS
40
26 DISPLAY:POWER 56 ANTENNA FEEDS
41
27 MESA POWER AND IO FILTERS 57 WIFI/BT: MODULE AND FRONT END
42

B 28
43
DISPLAY FLEX 58 STOCKHOLM
B
29 D403 (TOUCH B2B, DRIVER ICS) 59 OMIT_TABLE_RF
45
30 I/O:TRISTAR 2 60 Radio Subdesign Ports

SCH 051-00648
MT Pro Dongle

BRD 820-00282
MCO 056-01352
BOM 639-00931 (N69 BETTER)
BOM 639-01012 (N69H BETTER)
BOM 639-01231 (N69 BEST)
A BOM 639-01232 (N69H BEST) DRAWING TITLE
TABLE OF CONTENTS A
BOM 639-01271 (N69 ULTRA) SCH,MLB,N69
DRAWING NUMBER SIZE

BOM 639-01272 (N69H ULTRA) R


Apple Inc.
051-00648
REVISION

4.0.0
D

NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 1 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SCHEMATIC & PCB BOM CALLOUTS TABLE_5_HEAD


ALTERNATE BOM OPTIONS TABLE_ALT_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_5_ITEM

051-00648 1 SCH,MLB,N69 SCH CRITICAL ? TABLE_ALT_ITEM

NOT ALL REFERENCE DESIGNATORS LISTED.


TABLE_5_ITEM
138S00032 138S0831 ALTERNATE C0610 TY,2.2UF,0201 USED 91 TIMES IN DESIGN.
820-00282 1 PCBF,MLB,N69 PCB CRITICAL ? TABLE_ALT_ITEM

TABLE_5_ITEM
138S00049 138S0831 ALTERNATE C0610 KYOCERA,2.2UF,0201 USED 91 TIMES IN DESIGN.
825-6838 1 EEEE CODE FOR 639-00931 16GB EEEE_GH6K CRITICAL EEEE_16G TABLE_ALT_ITEM

TABLE_5_ITEM
155S0660 155S0513 ALTERNATE FL3100 MURATA,FERR,22-OHM USED 5 TIMES IN DESIGN.
825-6838 1 EEEE CODE FOR 639-01012 16GB EEEE_GJYD CRITICAL EEEE_16GH TABLE_ALT_ITEM

USED 61 TIMES IN DESIGN.


D
138S00005 138S00003 ALTERNATE C1500 TY,15UF,0402

D
TABLE_5_ITEM

825-6838 1 EEEE CODE FOR 639-01231 32GB EEEE_GN7J CRITICAL EEEE_32G TABLE_ALT_ITEM

TABLE_5_ITEM
138S00048 138S00003 ALTERNATE C1500 KYOCERA,15UF,0402 USED 61 TIMES IN DESIGN.
825-6838 1 EEEE CODE FOR 639-01232 32GB EEEE_GN7H CRITICAL EEEE_32GH TABLE_ALT_ITEM

TABLE_5_ITEM
118S0764 118S0717 ALTERNATE R2250 PANASONIC,3.92K-OHM,0201
USED 1 TIME IN DESIGN.
825-6838 1 EEEE CODE FOR 639-01271 64GB EEEE_GP3V CRITICAL EEEE_64G TABLE_ALT_ITEM

TABLE_5_ITEM
138S00006 138S0835 ALTERNATE C1106 TY,4.3UF,0402 USED 20 TIMES IN DESIGN.
825-6838 1 EEEE CODE FOR 639-01272 64GB EEEE_GP3W CRITICAL EEEE_64GH TABLE_ALT_ITEM

152S2052 152S1929 ALTERNATE L2060 CYNTEC,1UH,1608 USED 1 TIME IN DESIGN.


TABLE_ALT_ITEM

155S0773 155S0453 ALTERNATE FL3101 TY,FERR,120-OHM,01005 USED 35 TIMES IN DESIGN.


S3E NAND BOM OPTIONS 377S0168 377S0140 ALTERNATE DZ3150 TDK,VARISTOR,6.8V,100PF,01005
TABLE_ALT_ITEM

USED 9 TIMES IN DESIGN.


TABLE_5_HEAD TABLE_ALT_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 155S00067 155S0581 ALTERNATE FL4200 TDK,FERR,240-OHM,0201
USED 5 TIMES IN DESIGN.
TABLE_5_ITEM TABLE_ALT_ITEM

335S00054 1 NAND,1YNM,16GX8,S3E,64G,T,SLGA70 U1500 CRITICAL NAND_16G 155S00012 155S00009 ALTERNATE L3100 MURATA,CHOKE,65-OHM,0605
USED 10 TIMES IN DESIGN.
TABLE_5_ITEM TABLE_ALT_ITEM

335S00072 1 NAND,1YNM,32GX8,S3E,64G,T,SLGA70 U1500 CRITICAL NAND_32G 138S0706 138S0739 ALTERNATE C5302_RF MURATA,CAP,CER,1UF,20%,10V,X5R,0201 USED 4 TIMES IN DESIGN.
TABLE_5_ITEM TABLE_ALT_ITEM

335S00076 1 NAND,1YNM,64GX8,S3E,TLC,128G,H,ULGA70 U1500 CRITICAL NAND_64G 138S0945 138S0739 ALTERNATE C5302_RF KYOCERA,CAP,CER,1UF,20%,10V,X5R,0201 USED 4 TIMES IN DESIGN.
TABLE_ALT_ITEM

TABLE_ALT_HEAD 155S00095 155S00068 ALTERNATE FL1280 FERR BD,100 OHM,25%,100MA,2 OHM,01005 USED 1 TIME IN DESIGN.
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: TABLE_ALT_ITEM

PART NUMBER
138S0648 138S0652 ALTERNATE C3650 TY,4.7UF,0402 USED 9 TIMES IN DESIGN.
TABLE_ALT_ITEM

TABLE_ALT_ITEM

335S00071 335S00054 NAND_16G U1500 HYNIX 16G SLGA70 132S0400 132S0436 ALTERNATE C1280 CAP,CER,X5R,0.22UF,20%,6.3V,01005 USED 1 TIME IN DESIGN.
TABLE_ALT_ITEM

TABLE_ALT_ITEM

335S00085 335S00072 NAND_32G U1500 TOSHIBA 16G SLGA70 155S0960 155S0941 ALTERNATE FL3151 FERR BD,70 OHM,25%,300MA,0.4 DCR,01005 USED 8 TIMES IN DESIGN.
TABLE_ALT_ITEM

138S00024 138S0986 ALTERNATE C5201_RF CAP,CER,3-TERM,7.5UF,20%,4V,0402 USED 1 TIME IN DESIGN.


TABLE_ALT_ITEM

335S00066 335S0946 ALTERNATE U0900 IC,EEPROM,16KX8,1.8V,I2C,WLCSP4 USED 1 TIME IN DESIGN.


TABLE_ALT_ITEM

CARBON BOM OPTIONS 376S00106 376S00047 ALTERNATE Q2300 DIODES INC. ACT DIODE
TABLE_ALT_ITEM
USED 1 TIME IN DESIGN.

C 343S0688 343S0638 ALTERNATE U4301 CUMULUS 2ND FLOW USED 1 TIME IN DESIGN.
C
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION


TABLE_ALT_ITEM

TABLE_5_ITEM

138S00022 138S0867 ALTERNATE C1100 TY,10UF,0402 USED 51 TIMES IN DESIGN.


338S00017 1 IC,CARBON,MPU-6700-12,LGA16 U3010 INVENSENSE_CARBON TABLE_ALT_ITEM

TABLE_5_ITEM

138S00020 138S0867 ALTERNATE C1100 MURATA,10UF,0402 USED 51 TIMES IN DESIGN.


338S1163 1 IC,ACCEL,3-AXIS,DIG,BMA282,LGA14 U3020 INVENSENSE_CARBON
TABLE_5_ITEM

132S0316 1 CAP,CER,X5R,0.1UF,20%,6.3V,01005 C3020 INVENSENSE_CARBON


TABLE_5_ITEM

138S0692 1 CAP,CER,X5R,1UF,20%,6.3V,0201 C3021 INVENSENSE_CARBON


TABLE_5_ITEM

132S0316 1 CAP,CER,X5R,0.1UF,20%,6.3V,01005 C3022 INVENSENSE_CARBON


TABLE_5_ITEM

117S0202 1 RES,MF,20OHM,5%,1/32W,01005 R3020 INVENSENSE_CARBON


TABLE_5_ITEM

117S0202 1 RES,MF,20OHM,5%,1/32W,01005 R3021 INVENSENSE_CARBON

117S0202 1 RES,MF,20OHM,5%,1/32W,01005 R3022 INVENSENSE_CARBON


TABLE_5_ITEM

TABLE_5_ITEM
PMU/SOC BOM OPTIONS
TABLE_5_HEAD

338S00087 1 IC,CARBON,MPU-6800-00,LGA16 U3010 INVENSENSE_CARBON_1_1 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_ITEM

339S00121 1 POP,MALTA+2GB 25NM DDR,A1,M,DEV U0600 MALTA


TABLE_5_ITEM

118S00009 1 RES,MF,3.01KOHM,1%,1/32W,01005 R0730 MALTA


TABLE_5_ITEM

131S0307 1 CAP,CER,NPO/COG,100PF,5%,16V,01005 C0730 NOSTUFF


TABLE_5_ITEM

118S00025 1 RES,MF,330OHM,1%,1/32W,01005 R0651 MALTA


TABLE_5_ITEM

132S0316 1 CAP,CER,X5R,0.1UF,20%,6.3V,01005 C0731 NOSTUFF


COMPASS PART NUMBER TABLE_5_HEAD
338S00170 1 IC,PMU,ANTIGUA,D2255A1,OTP-BG U2000 MALTA
TABLE_5_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION


TABLE_5_ITEM

338S00084 1 IC,COMPASS,MAGNESIUM,601A-19,FLGA14 U3000 COMMON


B B
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION


TABLE_5_ITEM

339S00096 1 POP,MAUI+2GB 25NM DDR,C0,H,DEV U0600 MAUI

SHIELD PART NUMBERS TABLE_5_HEAD


118S0631 1 RES,MF,100OHM,1%,1/32W,01005 R0730 MAUI
TABLE_5_ITEM

TABLE_5_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION


131S0307 1 CAP,CER,NPO/COG,100PF,5%,16V,01005 C0730 MAUI
TABLE_5_ITEM

TABLE_5_ITEM

806-03629 1 SHIELD,EMI,UPPER FRONT,N69 SH0500 COMMON 117S0161 1 RES,MF,0OHM,1/32W,01005 R0651 MAUI


TABLE_5_ITEM

TABLE_5_ITEM

806-03630 1 SHIELD,EMI,LOWER FRONT,N69 SH0501 COMMON 132S0316 1 CAP,CER,X5R,0.1UF,20%,6.3V,01005 C0731 MAUI


TABLE_5_ITEM

TABLE_5_ITEM

806-03556 1 SHIELD,EMI,BACK,N69 SH0503 COMMON 338S00171 1 IC,PMU,ANTIGUA,D2255A1,OTP-YG U2000 MAUI

POWER INDUCTOR ALTERNATES


TABLE_ALT_HEAD
SOC ALTERNATES  TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
PART NUMBER
TABLE_ALT_ITEM

TABLE_ALT_ITEM

152S00117 152S00074 ? L2000 TAIYO 2016 1.0UH 339S00122 339S00121 ALTERNATE U0600 MALTA DEV, H DRAM
TABLE_ALT_ITEM

152S00121 152S00081 ? L2001 TAIYO 2012 0.47UH 339S00123 339S00121


TABLE_ALT_ITEM

152S00120 152S00077 ? L2070 TAIYO 2016 1.0UH 0.65MM


TABLE_ALT_ITEM

TABLE_ALT_HEAD

152S00118 152S00075 ? L3700 TAIYO 2016 1.2UH PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_ITEM PART NUMBER
152S00123 152S1936 ? L4020 TAIYO 3225 15UH TABLE_ALT_ITEM

339S00097 339S00096 ALTERNATE U0600 MAUI DEV, M DRAM

A A
TABLE_ALT_ITEM

339S00098 339S00096 ALTERNATE U0600 MAUI DEV, S DRAM


SYNC_MASTER=N/A SYNC_DATE=N/A
PAGE TITLE

SYSTEM:BOM TABLES
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 2 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

TESTPOINTS N69 I2C DEVICE MAP


I2C BUS DEVICE BINARY 7-BIT HEX 8-BIT HEX

I2C0 ANTIGUA PMU 1110100X 0X74 0XE8


POWER AMUX CHESTNUT 0100111X 0X27 0X4E

D TP00
1
A POWER GROUND 16 PMU_AMUX_AY TP16
1
A
BACKLIGHT 1100010X 0X62 0XC4 D
TP-P6 TP-P55
ROOM=TEST ROOM=TEST
I2C1 TIGRIS 1110101X 0X75 0XEA
PP5V0_USB TP01
1 PMU_AMUX_BY TP17
1
31 30 17 A VBUS 16 A
TP-P6 TP-P55
ROOM=TEST ROOM=TEST SPEAKER AMP 1000000X 0X40 0X80

33 18 17 PP_BATT_VCC TP02
1
A
MOJAVE TRISTAR 0011010X 0X1A 0X34
TP-P6
ROOM=TEST
VBATT MESA_TO_BOOST_EN TP18
1
TP03
1
27 26 A I2C2 ALS 0101001X 0X29 0X52
A TP-P55
TP-P6 ROOM=TEST
ROOM=TEST

PP11V3_MESA TP19
1
27 26 A
TP-P55
TP 24 FOR USB OWL UNUSED N/A N/A N/A
TP05
1 TP24
1
ROOM=TEST
A A FIXTURE SI
TP-P55
ROOM=TEST
TP-P55
ROOM=TEST LCM ISP I2C0 REAR CAM TBD TBD TBD

PP_LCM_BL_CAT1_CONN TP20
1
LED DRIVER 1100011X 0X63 0XC6
28 A
TP-P55
ROOM=TEST

RESET 28 PP_LCM_BL_CAT2_CONN TP21


1
A
ISP I2C1 FRONT CAM 0110110X 0X36 0X6C

TP-P55
PMU_TO_SYSTEM_COLD_RESET_L TP06
1 SOC & BB RESET ROOM=TEST TOUCH I2C UNUSED N/A N/A N/A
C A
C
16 9 5
TP-P55
ROOM=TEST
PP_LCM_BL_ANODE_CONN TP22
1
28 A
TP-P55
DFU ROOM=TEST

LCD_TO_AP_PIFA_CONN TP23
1 SEP I2C SEP EEPROM 1010001X 0x51 0xA2
FORCE_DFU TP07
1 FORCE DFU PROCEDURE: 28 A
8 A TP-P55
TP-P55 ROOM=TEST
ROOM=TEST 1. FROM OFF MODE SHORT TP07 TO PP07
PP07
P4MM-NSM
2. PLUG IN E75 CABLE TO FORCE DFU
SM
PP1V8 1
28 21 20 14 13 12 9 8 7 6 5 3
29 PP

ROOM=TEST BOOTSTRAPPING:BOARD REV


PP08
8 DFU_STATUS
P4MM-NSM
1
SM
PP
BOARD ID
ROOM=TEST
BOOT CONFIG
E75
TP08 8 OUT BOARD_REV3 R0400 ROOM=SOC
1 2 1.00K PP1V8 3 5 6 7 8 9 12 13 14 20 21 28
90_TRISTAR_DP1_CONN_P 1 01005 MF 1/32W 29
31 30 A 5%
TP-P55
ROOM=TEST
TRISTAR USB 8 OUT BOARD_REV2 R0401 ROOM=SOC
1 2 1.00K
01005 MF 5% 1/32W
90_TRISTAR_DP1_CONN_N TP09
1 NOSTUFF
A
R0402
31 30
ROOM=SOC
BOARD_REV1 1 2 1.00K
B
TP-P55
B ROOM=TEST
8 OUT
01005 MF 5% 1/32W

TP10 NOSTUFF
31 30 90_TRISTAR_DP2_CONN_P 1
TP-P55
A 8 OUT BOARD_REV0 R0403 ROOM=SOC
1 2 1.00K
01005 MF 5% 1/32W
ROOM=TEST TRISTAR DEBUG UART BOARD_REV[3:0]
90_TRISTAR_DP2_CONN_N TP11
1
FLOAT=LOW, PULLUP=HIGH
1111 PROTO0 MLB
31 30 A NOSTUFF
TP-P55
ROOM=TEST 8 OUT BOARD_ID4 R0404 ROOM=SOC
1 2 1.00K
1110
1101
PROTO1
PROTO2
01005 MF 5% 1/32W SELECTED --> 1100 EVT
PP_TRISTAR_ACC1 TP12
1 NOSTUFF XXXX CARRIER
A
R0405
31 30
ROOM=SOC XXXX DVT
TP-P55 8 OUT BOARD_ID3 1 2 1.00K
ROOM=TEST 01005 MF 1/32W
TRISTAR ACCESSORY ID 5%
BOARD_ID[4:0]
TP13 ACCESSORY POWER NOSTUFF FLOAT=LOW, PULLUP=HIGH
31 30 PP_TRISTAR_ACC2 1
TP-P55
A 8 BI
BOARD_ID2 R0406 ROOM=SOC
1 2 1.00K SELECTED --> 00010 N69 MLB
01005 MF 5% 1/32W 00011 N69 DEV
ROOM=TEST
BOOT_CONFIG[2:0]
TP14
1 R0407 ROOM=SOC
1 2 1.00K FLOAT=LOW, PULLUP=HIGH
A 8
TP-P55 01005 MF 5% 1/32W 000 SPI0
ROOM=TEST NOSTUFF 001 SPI0 TEST MODE

8 OUT BOARD_ID0 R0408 ROOM=SOC


1 2 1.00K SELECTED -->
010
011
NVME0 x2 MODE
NVME0 x2 TEST MODE

TRISTAR_CON_DETECT_L TP15
1
01005 MF 5% 1/32W 100
101
NVME0 x1 MODE
NVME0 x1 TEST MODE
31 30 A
TP-P55 110 SLOW SPI0 TEST MODE
ROOM=TEST 111 FAST SPI0 TEST MODE
NOSTUFF
8 OUT BOOT_CONFIG2 R0409 ROOM=SOC
1 2 1.00K
01005 MF 1/32W
A
5%
SYNC_MASTER=N/A SYNC_DATE=N/A A
8 OUT BOOT_CONFIG1 R0410 ROOM=SOC
1 2 1.00K PAGE TITLE
01005 MF 5% 1/32W
SYSTEM:N69 SPECIFIC [4]
DRAWING NUMBER SIZE
BOOT_CONFIG0 R0411 ROOM=SOC
1 2 1.00K 051-00648 D
Apple Inc.
8
01005 MF 5% 1/32W
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
RESISTOR STUFF = HIGH '1' THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
RESISTOR NOSTUFF = LOW '0' THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
4 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 3 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

FIDUCIALS
BOARD STANDOFFS SHIELDS
AND AC COUPLING CAPS FOR FD0501
COMPASS RETURN CURRENTS FID
D 0P5SM1P0SQ-NSP
1
D
TOP-SIDE, EAST UPPER FRONT SHIELD
ROOM=ASSEMBLY
1
EAST_STANDOFF_AC_GND_SCREW 1 SH0500 FD0502
FID
SM 0P5SM1P0SQ-NSP
1
BS0501 ROOM=ASSEMBLY
1 C0510 1 C0511 1 C0512 1 C0513 STDOFF-2.7OD1.4ID-1.04H-SM-1 SHLD-EMI-UPPER-FRONT-N69
OMIT_TABLE
5%
100PF 56PF
5%
3.3PF
+/-0.1PF
56PF
5%
FD0503
FID
16V
2 NP0-C0G
01005
2 16V
NP0-C0G
01005
16V
2 CERM
01005
2 16V
NP0-C0G
01005
LOWER FRONT SHIELD 0P5SM1P0SQ-NSP
1
1
ROOM=ASSEMBLY
SH0501 FD0505
TOP-SIDE, WEST SM FID
0P5SM1P0SQ-NSP
1
SHLD-EMI-LOWER-FRONT-N69
WEST_STANDOFF_AC_GND_SCREW 1 OMIT_TABLE ROOM=ASSEMBLY
FD0510
BS0502 FID
1 C0520 1 C0521 1 C0522 1 C0523 STDOFF-2.7OD1.4ID-1.04H-SM-1 0P5SQ-SMP3SQ-NSP
1
100PF 56PF 3.3PF 56PF
5% 5% +/-0.1PF 5%
ROOM=ASSEMBLY
16V
2 NP0-C0G
01005
2 16V
NP0-C0G
01005
16V
2 CERM
01005
2 16V
NP0-C0G
01005
PLATED SHIELD SLOT
SL0501 FD0511
TH-NSP FID
1 0P5SQ-SMP3SQ-NSP
1
SL-1.20X0.40-1.50X0.70-NSP
ROOM=ASSEMBLY
FD0512
FID
C 0P5SQ-SMP3SQ-NSP
1
C
ROOM=ASSEMBLY
TOP-SIDE, GROUND SPRING FD0514
FID
0P5SQ-SMP3SQ-NSP
SP0502
SPRING-SUPER-COWLING-GROUND-X145
1
1 ROOM=ASSEMBLY
CLIP-SM
FD0515
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
FD0504
FID
0P5SM1P0SQ-NSP
1
ROOM=ASSEMBLY
NORTH WIFI UNDERFILL BLOCKING FD0516
CKPLUS_WAIVE=TERMSHORTED FID
0P5SQ-SMP3SQ-NSP
R0500 1 2 0.00 1
01005 MF 1/32W
0% ROOM=ASSEMBLY
R0501 1 2 0.00
01005 MF 1/32W
0%
CKPLUS_WAIVE=TERMSHORTED

B B

COMPASS AC GROUNDING CAPS


COMPASS_AC_GND_SCREW 1
SM
PP PP0501
P4MM-NSM

1 C0540 1 C0541 1 C0542 1 C0543


0.01UF 100PF 56PF 3.3PF
10% 2% 2% +/-0.1PF
25V
2 X5R-CERM 2 50V 2 50V 25V
2 C0G-CERM
C0G NP0-C0G-CERM
0201 0201 0201 0201
ROOM=ASSEMBLY
ROOM=ASSEMBLYROOM=ASSEMBLYROOM=ASSEMBLY

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SYSTEM:MECHANICAL
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 4 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - USB, JTAG, XTAL

D D
VDD12_PLL_LPDP:1.14-1.26V @2mA MAX
VDD12_PLL_SOC: 1.14-1.26V @12mA MAX
VDD12_PLL_CPU: 1.14-1.26V @2mA MAX
VDD18_USB: 1.71-1.89V @20mA MAX
R0600 VDD18_XTAL:1.62-1.98V @2mA MAX
PP1V2 1
0.00 2 PP1V2_PLL PP1V8
15 7 6 3 6 7 8 9 12 13 14 20 21 28 29

0%
1/32W
MF 1 C0600 1 C0601 1 C0602 1 C0603 1 C0612 FL0610
01005 1KOHM-25%-0.2A
ROOM=SOC 0.1UF 0.1UF 0.01UF 0.01UF 0.1UF
20% 20% 10% 10% 20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V PP1V8_XTAL 1 2
X5R-CERM X5R-CERM X5R X5R X5R-CERM
01005 0201
01005
ROOM=SOC
01005
ROOM=SOC
01005
ROOM=SOC
01005
ROOM=SOC ROOM=SOC 1 C0611 1 C0610 ROOM=SOC

0.1UF 2.2UF
20% 20%
2 6.3V 2 6.3V
X5R-CERM
X5R-CERM 0201
01005 ROOM=SOC
ROOM=SOC

PP3V3_USB 15

1 C0604 1 C0620 VDD33_USB:3.14-3.46V @5mA MAX

VDD33_USB AN20
VDD12_UH1_HSIC0 AP21

VDD12_PLL_CPU AF13
0.22UF 0.1UF

VDD18_USB AL21

VDD18_XTAL AL34
W19
VDD12_UH2_HSIC1 C15

U20
VDD12_PLL_LPDP F22

T19
20% 20%
2 6.3V
X5R
6.3V
2 X5R-CERM
0201 01005

VDD12_PLL_SOC
ROOM=PMU ROOM=SOC

C C
PP0620
P2MM-NSM OMIT_TABLE
SM
1 CRITICAL
PP
ROOM=SOC
U0600
MAUI-2GB-25NM-DDR-H
33 50_AP_BI_BB_HSIC0_DATA AN22 UH1_HSIC0_DATA FCMSP ANALOGMUX_OUT AP24 AP_TO_PMU_AMUX_OUT 16
BI OUT
AN21
33 BI
50_AP_BI_BB_HSIC0_STB UH1_HSIC0_STB SC58980X0B-A040
L0602
SYM 1 OF 14 15NH-250MA
C16
PP0621
P2MM-NSM
NC
D15
UH2_HSIC1_DATA ROOM=SOC 1 2
SM NC UH2_HSIC1_STB 0201
1
PP USB_D_P AT20 90_USB_AP_DATA_AP_P ROOM=TRISTAR 90_USB_AP_DATA_P BI 30
ROOM=SOC Y32 JTAG_SEL USB_D_N AT19 90_USB_AP_DATA_AP_N L0601 90_USB_AP_DATA_N BI 30
15NH-250MA
AC32 JTAG_TRST* 1 2
NC
AB31 JTAG_TDO 0201 ROOM=TRISTAR
NC
AA32 JTAG_TDI USB_VBUS AP19 USB_VBUS_DETECT
NC IN 17

30 SWD_DOCK_BI_AP_SWDIO AB32 JTAG_TMS


BI
30 SWD_DOCK_TO_AP_SWCLK AA31 JTAG_TCK USB_ID AR19NC
IN

16 9 3 PMU_TO_SYSTEM_COLD_RESET_L AC31 COLD_RESET*


IN

H33 USB_REXT AP18 USB_REXT


30 26 16 9 IN
PMU_TO_OWL_ACTIVE_READY CFSB
ROOM=SOC
P3MM-NSM 16 OUT
AP_TO_PMU_TEST_CLKOUT AR23 TST_CLKOUT
1
R0640
SM 200
PP0610 PP
1 1%
1/32W
MF
AP_TO_NAND_RESET_L AN23
B 13 OUT S3E_RESET* 2 01005
ROOM=SOC B
H32 HOLD_RESET WDOG Y33 AP_TO_PMU_WDOG_RESET 16
OUT

AF6 TESTMODE
AL22 FUSE1_FSRC XI0 AK35 45_XTAL_AP_24M_IN
AG25 FUSE2_FSRC XO0 AL35 45_XTAL_AP_24M_OUT 1
R0650 CRITICAL
511K ROOM=SOC
1%
1/32W Y0600
2
MF
01005 R0651 1.60X1.20MM-SM
24.000MHZ-30PPM-9.5PF-60OHM
ROOM=SOC
1
0.00 2 45_SOC_24M_O 1 3
0%
1/32W 2 4
MF
01005
1 C0650 1 C0651
ROOM=SOC 12PF 12PF
OMIT_TABLE 5% 5%
2 16V 2 16V
CERM
01005
ROOM=SOC
CERM
01005 XW0650
SHORT-10L-0.1MM-SM
ROOM=SOC 1 2
45_AP_XTAL_GND
ROOM=SOC

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC:JTAG,USB,XTAL
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 5 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - PCIE INTERFACES


VDD12_PCIE_REFBUF:1.08-1.26V @50mA MAX
VDD12_PCIE_TXPLL: 1.08-1.32V @10mA MAX XW0740
SHORT-10L-0.1MM-SM
VDD12_PCIE: 1.14-1.26V @115mA MAX 1 2 PP1V2_PCIE_TXPLL VDD085_PCIE:0.802-TBDV @TBDmA MAX
D 15 7 5 PP1V2 ROOM=SOC PP_FIXED 7 11 14
D
1 C0740 1 C0741 1 C0742 1 C0752 1 C0751 1 C0750
2.2UF
20%
1.0UF
20%
0.1UF
20%
1 C0744 1 C0743 1 C0731 0.1UF 1.0UF 2.2UF
0.1UF 0.1UF 0.1UF 20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R 2 6.3V
X5R-CERM 20% 20% 20% 2 6.3V 2 6.3V 2 6.3V
0201 0201-1 01005 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
X5R-CERM
01005
X5R
0201-1
X5R-CERM
0201
ROOM=SOC ROOM=SOC ROOM=SOC 01005 01005 01005

AH28
AK28
AK25

AK27
AL24
AL27

VDD12_PCIE_TXPLL AL26

AL23

AL29
ROOM=SOC ROOM=SOC ROOM=SOC

VDD12_PCIE_REFBUF AJ26

AJ25

AJ29

AJ24

AJ27
ROOM=SOC ROOM=SOC ROOM=SOC
OMIT_TABLE

VDD12_PCIE

VDD085_PCIE
PCIE_EXT_C AP29 PCIE_EXT_C
C0701 1 2 0.1UF OMIT_TABLE
90_PCIE_NAND_TO_AP_RXD0_P ROOM=SOC 20% X5R-CERM 90_PCIE_NAND_TO_AP_RXD0_C_P AM30 PCIE_RX0_P PCIE_REF_CLK0_P AN35 90_PCIE_AP_TO_NAND_REFCLK_P
13 IN 6.3V 01005
AN30
CRITICAL AP35
OUT 13

90_PCIE_NAND_TO_AP_RXD0_N 90_PCIE_NAND_TO_AP_RXD0_C_N PCIE_RX0_N U0600 PCIE_REF_CLK0_N 90_PCIE_AP_TO_NAND_REFCLK_N


13 IN
C0702 1 2 0.1UF OUT 13 P2MM-NSM
SM
ROOM=SOC 20% X5R-CERM MAUI-2GB-25NM-DDR-H
1
PP PP0700
6.3V 01005
FCMSP PCIE_REF_CLK1_P AN34 90_PCIE_AP_TO_WLAN_REFCLK_P OUT 33

SC58980X0B-A040 PCIE_REF_CLK1_N AP34 90_PCIE_AP_TO_WLAN_REFCLK_N OUT 33 P2MM-NSM


C0703 1 2 0.1UF SYM 2 OF 14
1
SM
PP PP0701
13 90_PCIE_AP_TO_NAND_TXD0_P ROOM=SOC 20% X5R-CERM 90_PCIE_AP_TO_NAND_TXD0_C_P AT32 PCIE_TX0_P ROOM=SOC PCIE_REF_CLK2_P AM32NC
OUT 6.3V 01005
90_PCIE_AP_TO_NAND_TXD0_N 90_PCIE_AP_TO_NAND_TXD0_C_N AR32 PCIE_TX0_N PCIE_REF_CLK2_N AN32NC
13 OUT
C0704 1 2 0.1UF
PCIE LINK 0

ROOM=SOC 20% X5R-CERM PP1V8 3 5 7 8 9 12 13 14 20 21 28 29


6.3V 01005 PCIE_REF_CLK3_P AM31NC
C PCIE_REF_CLK3_N AN31NC
1
R0720 1
R0721 C
C0705 1 2 0.1UF 100K
5%
100K
5%
13 90_PCIE_NAND_TO_AP_RXD1_P ROOM=SOC 20% X5R-CERM 90_PCIE_NAND_TO_AP_RXD1_C_P AM28 PCIE_RX1_P 1/32W 1/32W
IN 6.3V 01005 MF MF
90_PCIE_NAND_TO_AP_RXD1_N 90_PCIE_NAND_TO_AP_RXD1_C_N AN28 PCIE_RX1_N 2 01005 2 01005
13 IN
C0706 1 2 0.1UF ROOM=SOC ROOM=SOC
ROOM=SOC 20% X5R-CERM
6.3V 01005 PCIE_CLKREQ0* AT11 PCIE_NAND_TO_AP_CLKREQ_L 13
BI
PCIE_CLKREQ1* AP12 PCIE_WLAN_TO_AP_CLKREQ_L 33
BI
C0707 1 2 0.1UF PCIE_CLKREQ2* AR12
NC
90_PCIE_AP_TO_NAND_TXD1_P ROOM=SOC 20% X5R-CERM 90_PCIE_AP_TO_NAND_TXD1_C_P AT31 PCIE_TX1_P PCIE_CLKREQ3* AT12
13 OUT 6.3V 01005 NC
90_PCIE_AP_TO_NAND_TXD1_N 90_PCIE_AP_TO_NAND_TXD1_C_N AR31 PCIE_TX1_N
13 OUT
C0708 1 2 0.1UF
ROOM=SOC 20% X5R-CERM
6.3V 01005

C0709 1 2 0.1UF PCIE_PERST0* AR10 PCIE_AP_TO_NAND_RESET_L OUT 13

33 90_PCIE_WLAN_TO_AP_RXD_P ROOM=SOC 20% X5R-CERM 90_PCIE_WLAN_TO_AP_RXD_C_P AM27 PCIE_RX2_P PCIE_PERST1* AT10 PCIE_AP_TO_WLAN_RESET_L 33
IN 6.3V 01005 OUT
90_PCIE_WLAN_TO_AP_RXD_N 90_PCIE_WLAN_TO_AP_RXD_C_N AN27 PCIE_RX2_N PCIE_PERST2* AP11
33 IN
C0710 NC
PCIE LINK 1

1 2 0.1UF AR11
ROOM=SOC 20% X5R-CERM PCIE_PERST3* NC
6.3V 01005

C0711 1 2 0.1UF
33 OUT
90_PCIE_AP_TO_WLAN_TXD_P ROOM=SOC 20% X5R-CERM 90_PCIE_AP_TO_WLAN_TXD_C_P AT28 PCIE_TX2_P PCIE_EXT_REF_CLK_P AR33
1
R0700 1
R0701
6.3V 01005
AR28 100K 100K
90_PCIE_AP_TO_WLAN_TXD_N 90_PCIE_AP_TO_WLAN_TXD_C_N PCIE_TX2_N PCIE_EXT_REF_CLK_N AT33
33 OUT
C0712 1 2 0.1UF
5%
1/32W
MF
5%
1/32W
MF
ROOM=SOC 20% X5R-CERM 01005 01005
6.3V 01005 2 ROOM=SOC 2 ROOM=SOC

B NC
AM26 PCIE_RX3_P PCIE_RX_TX_BYPASS_CLK_P AT29 B
NC
AN26 PCIE_RX3_N PCIE_RX_TX_BYPASS_CLK_N AR29

AT26 PCIE_TX3_P
NC
AR26 PCIE_TX3_N
NC

AM25 PCIE_RX4_P
NC
AN25 PCIE_RX4_N
NC

AR24 PCIE_TX4_P PCIE_RCAL_P AT30


1
R0730 1 C0730
NC 3.01K 100PF
AT24 PCIE_TX4_N PCIE_RCAL_N AR30 1% 5%
NC 1/32W 2 16V
MF NP0-C0G
2 01005 01005
ROOM=SOC ROOM=SOC
45_PCIE_RCAL_N OMIT_TABLE OMIT_TABLE

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC:PCIE
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
7 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - CAMERA & DISPLAY INTERFACES

D D

0.756-0.893V @11mA MAX 1.62-1.98V @23mA MAX


14 11 6 PP_FIXED PP1V8 3 5 6 7 8 9 12 13 14 20 21 28
29

1 C0814 1 C0801 1 C0802 1 C0815


0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% NOTE:VDD12_LPDP SHOULD BE POWERED
2 6.3V 2 6.3V 2 6.3V 2 6.3V

D13

D10
E10
E13

E11
E14
X5R-CERM X5R-CERM X5R-CERM X5R-CERM

E8

E7
D8
01005 01005 01005 01005 EVEN WHEN LPDP IS NOT USED
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC

VDD085_MIPI

VDD18_MIPI
15 6 5 PP1V2

PP1V8 3 5 6 7 8 9 12 13 14 20 21 28

E25
E27
F24
E23
29
OMIT_TABLE
1
U0600 R0804 1
R0805 1
R0806 1
R0807

VDD12_LPDP
MAUI-2GB-25NM-DDR-H 1.00K 1.00K 1.00K 1.00K
5% 5% 5% 5%
FCMSP 1/32W 1/32W 1/32W 1/32W
MF MF MF MF
SC58980X0B-A040 2 01005 2 01005 2 01005 2 01005
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC

C 21 IN
90_MIPI_RCAM_TO_AP_DATA0_CONN_P B8
A8
MIPI0C_DATA0_P
SYM 3 OF 14
ROOM=SOC ISP_I2C0_SCL G31 I2C_ISP_TO_RCAM_SCL OUT 21 22
OMIT_TABLE
C
21 IN
90_MIPI_RCAM_TO_AP_DATA0_CONN_N MIPI0C_DATA0_N ISP_I2C0_SDA G32 I2C_ISP_BI_RCAM_SDA BI 21 22
CRITICAL U0600
21 IN
90_MIPI_RCAM_TO_AP_DATA1_CONN_P A9 MIPI0C_DATA1_P ISP_I2C1_SCL F35 I2C_ISP_TO_FCAM_SCL OUT 20
MAUI-2GB-25NM-DDR-H
90_MIPI_RCAM_TO_AP_DATA1_CONN_N B9 MIPI0C_DATA1_N ISP_I2C1_SDA G34 I2C_ISP_BI_FCAM_SDA A29 LPDP_AUX_P FCMSP
21 IN BI 20
NC
B29 LPDP_AUX_N SC58980X0B-A040
NC
90_MIPI_RCAM_TO_AP_DATA2_CONN_P A13 MIPI0C_DATA2_P SYM 4 OF 14
R0808
21 IN A33 LPDP_TX0_P
21 90_MIPI_RCAM_TO_AP_DATA2_CONN_N B13 MIPI0C_DATA2_N NC ROOM=SOC
IN
33.2 B33 LPDP_TX0_N
SENSOR0_CLK D33 45_AP_TO_RCAM_CLK_R 1 2 45_AP_TO_RCAM_CLK 21
NC CRITICAL
OUT
1% MF 1/32W
90_MIPI_RCAM_TO_AP_DATA3_CONN_P B14 MIPI0C_DATA3_P SENSOR0_RST D32 AP_TO_RCAM_SHUTDOWN_L 01005
NC
A32 LPDP_TX1_P
R0809
21 IN OUT 21
ROOM=SOC
90_MIPI_RCAM_TO_AP_DATA3_CONN_N A14 MIPI0C_DATA3_N B32 LPDP_TX1_N
21 IN
33.2 NC
SENSOR1_CLK F33 45_AP_TO_FCAM_CLK_R 1 2 45_AP_TO_FCAM_CLK OUT 20
A31
1% MF 1/32W
NC LPDP_TX2_P
21 IN
90_MIPI_RCAM_TO_AP_CLK_CONN_P A12 MIPI0C_CLK_P SENSOR1_RST E34 AP_TO_FCAM_SHUTDOWN_L OUT 20 01005
ROOM=SOC B31
B12 NC LPDP_TX2_N
21 IN
90_MIPI_RCAM_TO_AP_CLK_CONN_N MIPI0C_CLK_N
A30 LPDP_TX3_P
45_RCAM_REXT D12 MIPI0C_REXT NC
SENSOR0_ISTRB D34 NC NC
B30 LPDP_TX3_N
28 OUT
90_MIPI_AP_TO_LCM_DATA0_P A3 MIPID_DATA0_P SENSOR0_XSHUTDOWN F32 AP_TO_STOCKHOLM_DWLD_REQUEST OUT 33
D24
B3 NC LPDP_CAL_DRV_OUT
90_MIPI_AP_TO_LCM_DATA0_N MIPID_DATA0_N
SENSOR1_ISTRB C35 NC
28 OUT
D25 LPDP_CAL_VSS_EXT
B4 SENSOR1_XSHUTDOWN C34 AP_TO_MUON_BL_STROBE_EN 26
NC
28 OUT
90_MIPI_AP_TO_LCM_DATA1_P MIPID_DATA1_P
OUT
AL4
A4 NC EDP_HPD
28 OUT
90_MIPI_AP_TO_LCM_DATA1_N MIPID_DATA1_N MIPICSI_MUXSEL G35 NC
H35 DP_WAKEUP
MIPI1C_REXT D14 45_FCAM_REXT NC
B6 MIPID_DATA2_P
NC
A6 MIPID_DATA2_N MIPI1C_DATA0_P B17 90_MIPI_FCAM_TO_AP_DATA0_P
NC IN 20

MIPI1C_DATA0_N A17 90_MIPI_FCAM_TO_AP_DATA0_N IN 20


A7 MIPID_DATA3_P
NC
B NC
B7 MIPID_DATA3_N MIPI1C_DATA1_P B19 NC
MIPI1C_DATA1_N A19 NC
B
28 90_MIPI_AP_TO_LCM_CLK_P A5 MIPID_CLK_P
OUT
28 90_MIPI_AP_TO_LCM_CLK_N B5 MIPID_CLK_N MIPI1C_CLK_P A18 90_MIPI_FCAM_TO_AP_CLK_P 20
OUT IN

D9 MIPI1C_CLK_N B18 90_MIPI_FCAM_TO_AP_CLK_N 20


45_LCM_REXT MIPID_REXT IN

1
R0801
1
R0802
1 R0803
4.02K
4.02K 4.02K 1%
1% 1% 1/32W
1/32W 1/32W MF
MF MF 2 01005
01005 2 01005 2 ROOM=SOC
ROOM=SOC ROOM=SOC

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC:CAMERA & DISPLAY


DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
8 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 7 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - GPIO & SERIAL INTERFACES


PP1V8 3 5 6 7 8 9 12 13 14 20 21 28
29
1 1 1 1 1
R0900 1 R0901 R0902 R0903 R0904 R0905
D
2.2K
5%
1/32W
2.2K
5%
1/32W
2.2K
5%
1/32W
2.2K
5%
1/32W
1.33K
1%
1/32W
1.33K
1%
1/32W
D
MF MF MF MF MF MF
01005 2 01005 01005 01005 01005 01005
ROOM=SOC ROOM=SOC 2 ROOM=SOC 2 ROOM=SOC 2 ROOM=SOC 2 ROOM=SOC 2

R0920
33.2
24 OUT
45_I2S_AP_TO_CODEC_MCLK 1 2 45_I2S_AP_TO_CODEC_MCLK_R P34 I2S0_MCK OMIT_TABLE I2C0_SCL E31 I2C0_AP_SCL OUT 8 16 26

1% 45_I2S_AP_OWL_TO_CODEC_XSP_BCLK R34 I2S0_BCLK I2C0_SDA D35 I2C0_AP_SDA


OMIT_TABLE 25 45_I2S_AP_TO_SPEAKERAMP_MCLK
1/32W
MF
24 9

24 9
OUT
I2S_AP_OWL_TO_CODEC_XSP_LRCLK N34 I2S0_LRCK
U0600 BI 8 16 26

OUT OUT
C1 01005 FCMSP
GPIO_0 I2S_CODEC_TO_AP_OWL_XSP_DIN N35 I2C1_SCL AH1 I2C1_AP_SCL
NC
D2 GPIO_1
U0600 ROOM=SOC 24 9 IN I2S0_DIN
SC58980X0B-A040 OUT 8 17 25 30

NC I2S_AP_TO_CODEC_XSP_DOUT M33 I2S0_DOUT I2C1_SDA AG4 I2C1_AP_SDA


BUTTON_VOL_UP_L D1 MAUI-2GB-25NM-DDR-H 24 OUT
SYM 6 OF 14
BI 8 17 25 30
32 16 IN GPIO_2
F1 FCMSP MAUI-2GB-25NM-DDR-H
32 16 IN
BUTTON_VOL_DOWN_L GPIO_3 M4 I2S1_MCK I2C2_SCL L31 I2C2_AP_SCL
E2 SC58980X0B-A040 NC ROOM=SOC OUT 8 20
25 IN
SPEAKERAMP_TO_AP_INT_L GPIO_4 45_I2S_AP_TO_BT_BCLK M3 I2S1_BCLK I2C2_SDA M32 I2C2_AP_SDA
F3 SYM 5 OF 14 33 OUT CRITICAL BI 8 20

NC GPIO_5 ROOM=SOC TMR32_PWM0 AE1 NC 33 I2S_AP_TO_BT_LRCLK P1 I2S1_LRCK


OUT
AP_TO_SPEAKERAMP_RESET_L F2 GPIO_6 TMR32_PWM1 AF2 AP_TO_VIBE_TRIG I2S_BT_TO_AP_DIN N3 PP1V8
25 OUT CRITICAL OUT 32
33 IN I2S1_DIN 3 5 6 7 8 9 12 13 14 20 21 28
29
AP_TO_BT_WAKE H3 GPIO_7 TMR32_PWM2 AF3 NC I2S_AP_TO_BT_DOUT L4
33 OUT I2S1_DOUT 1
R0922
33 OUT
33 OUT
AP_TO_BB_RESET_L G3
J1
GPIO_8
33.2
R0906 1
R0907
33 OUT
PCIE_AP_TO_WLAN_DEV_WAKE GPIO_9 UART0_RXD AE3 UART_AP_DEBUG_RXD IN 30 1 2 45_I2S_AP_TO_SPEAKERAMP_MCLK_R U32 I2S2_MCK 2.2K 2.2K
H4 5% 5%
22 OUT
AP_TO_LED_DRIVER_EN GPIO_10 UART0_TXD AE4 UART_AP_DEBUG_TXD OUT 30 1% 25 24 45_I2S_AP_TO_CODEC_ASP_BCLK V33 I2S2_BCLK SEP_SPI0_SCLK W3 NC 1/32W 1/32W
OUT MF MF
AP_TO_TOUCH_RESET_L K1 1/32W
29 OUT GPIO_11 MF I2S_AP_TO_CODEC_ASP_LRCLK U33 I2S2_LRCK SEP_SPI0_MISO AA4 NC 01005 01005 2
J3 K31 01005
25 24 OUT ROOM=SOC 2 ROOM=SOC
28 OUT
AP_TO_LCM_RESET_L GPIO_12 UART1_CTS* UART_BT_TO_AP_CTS_L IN 33
ROOM=SOC 25 24 I2S_CODEC_TO_AP_ASP_DIN T33 I2S2_DIN SEP_SPI0_MOSI U2 NC
IN
PMU_TO_AP_IRQ_L K2 GPIO_13 UART1_RTS* K32 UART_AP_TO_BT_RTS_L I2S_AP_TO_CODEC_ASP_DOUT V34
16 IN OUT 33
25 24 OUT I2S2_DOUT
J4 GPIO_14 UART1_RXD L33 UART_BT_TO_AP_RXD
NC IN 33

AP_TO_STOCKHOLM_DEV_WAKE L2 GPIO_15 UART1_TXD L32 UART_AP_TO_BT_TXD AM3


33 OUT OUT 33
20 IN
ALS_TO_AP_INT_L I2S3_MCK SEP_I2C_SCL V3 I2C_SEP_TO_EEPROM_SCL OUT 8
BOARD_ID3 K3 GPIO_16 AM4
3 IN 33 OUT
45_I2S_AP_TO_BB_BCLK I2S3_BCLK SEP_I2C_SDA Y4 I2C_SEP_BI_EEPROM_SDA BI 8
L3 GPIO_17 UART2_CTS* AT23 UART_STOCKHOLM_TO_AP_CTS_L I2S_AP_TO_BB_LRCLK AN2
NC IN 33
33 OUT I2S3_LRCK
C 3 IN
BOOT_CONFIG0
AP_TO_BB_WAKE_MODEM
N1
AH2
GPIO_18
GPIO_19
UART2_RTS*
UART2_RXD
AR20
AP23
UART_AP_TO_STOCKHOLM_RTS_L
UART_STOCKHOLM_TO_AP_RXD
OUT 33
33 IN
I2S_BB_TO_AP_DIN AP1
AN1
I2S3_DIN C
33 OUT IN 33
33 OUT
I2S_AP_TO_BB_DOUT I2S3_DOUT SEP_GPIO0 Y3 NC
LCM_TO_AP_HIFA_BSYNC AH3 GPIO_20 UART2_TXD AP22 UART_AP_TO_STOCKHOLM_TXD
33 29 28 9 IN OUT 33
SEP_GPIO1 AB4 NC
BB_TO_AP_HSIC_DEVICE_RDY AH4 GPIO_21 TRISTAR_TO_AP_INT R32
33 IN 30 16 IN I2S4_MCK
BB_TO_AP_GPS_TIME_MARK AJ1 GPIO_22 UART3_CTS* N4 UART_BB_TO_AP_CTS_L 45_I2S_AP_TO_CODEC_MSP_BCLK R31
33 IN IN 33
24 OUT I2S4_BCLK
AP_TO_BB_HSIC_HOST_RDY AJ2 GPIO_23 UART3_RTS* P3 UART_AP_TO_BB_RTS_L I2S_AP_TO_CODEC_MSP_LRCLK V32
33 OUT OUT 33
24 OUT I2S4_LRCK
BB_TO_AP_RESET_DETECT_L AJ3 GPIO_24 UART3_RXD R3 UART_BB_TO_AP_RXD I2S_CODEC_TO_AP_MSP_DIN P31 PP1V8_ALWAYS
33 IN IN 33
24 IN I2S4_DIN 8 12 15 17

BOOT_CONFIG1 AJ4 GPIO_25 UART3_TXD R2 UART_AP_TO_BB_TXD I2S_AP_TO_CODEC_MSP_DOUT P32


3 IN OUT 33
24 I2S4_DOUT
3 FORCE_DFU AK1 GPIO_26
OUT
PP1V8 3 5 6 7 8 9 12 13 14 20 21 28
IN 29

3 OUT
DFU_STATUS AP3 GPIO_27 UART4_CTS* J33 UART_WLAN_TO_AP_CTS_L IN 33 NOSTUFF
3 IN
BOOT_CONFIG2 AN4 GPIO_28 UART4_RTS* J34 UART_AP_TO_WLAN_RTS_L OUT 33 R0941 1 R0910 1 1
R0909
BOARD_ID4 AP4 GPIO_29 UART4_RXD J35 UART_WLAN_TO_AP_RXD BOARD_ID2 AD4
10K 10K 10K
3 IN IN 33
3 IN SPI0_MISO 5% 5% 5%
CODEC_TO_AP_PMU_INT_L AP5 GPIO_30 UART4_TXD K33 UART_AP_TO_WLAN_TXD BOARD_ID1 AC3 1/32W 1/32W 1/32W
24 16 IN OUT 33
3 IN SPI0_MOSI MF MF MF
AP_TO_BB_RADIO_ON_L AR2 GPIO_31 BOARD_ID0 AB2 01005 2 01005 2 2 01005
33 OUT 3 IN SPI0_SCLK ROOM=SOC ROOM=SOC ROOM=SOC
AP_TO_NAND_FW_STRAP AR3 GPIO_32 UART5_RTXD T32 SWI_AP_BI_TIGRIS AD3 ROOM=SOC
13 OUT BI 9 17
NC SPI0_SSIN
29 IN
TOUCH_TO_AP_INT_L AR4 GPIO_33 R0940
BOARD_REV3 AP6 GPIO_34 0.00
3 IN 24 8 IN
SPI_CODEC_TO_AP_MISO P33 SPI1_MISO SOCHOT0 AM1 PMU_TO_AP_SOCHOT0_R_L 1 2 PMU_TO_AP_SOCHOT0_L IN 16
BOARD_REV2 AT3 0% MF 1/32W
3 IN GPIO_35 24 8 SPI_AP_TO_CODEC_MOSI V35 SPI1_MOSI 01005
OUT
BOARD_REV1 AT4 GPIO_36 SPI_AP_TO_CODEC_SCLK N32
3 IN 24 8 OUT SPI1_SCLK
BOARD_REV0 AR6 GPIO_37 UART6_RXD AF1 UART_ACCESSORY_TO_AP_RXD
3 IN IN 30
24 OUT
SPI_AP_TO_CODEC_CS_L M31 SPI1_SSIN SOCHOT1 AM2 AP_TO_PMU_SOCHOT1_L OUT 16
33 OUT
AP_TO_BB_COREDUMP AP7 GPIO_38 UART6_TXD AE2 UART_AP_TO_ACCESSORY_TXD OUT 30

BB_TO_AP_IPC_GPIO AT5 GPIO_39 ROOM=SOC SPI_TOUCH_TO_AP_MISO E33


33 IN SPI2_MISO
R0960
29 8 IN
BUTTON_RINGER_A AP8 GPIO_40 UART7_RXD J31 NC SPI_AP_TO_TOUCH_MOSI E35
32 16 8 IN 29 8 OUT SPI2_MOSI
AP_TO_BB_MESA_ON AP9 GPIO_41 UART7_TXD J32 NC SPI_AP_TO_TOUCH_SCLK 1
0.00 2 SPI_AP_TO_TOUCH_SCLK_R F34
33 OUT 29 OUT SPI2_SCLK
CAM_EXT_LDO_EN AP10 GPIO_42 F31 CPU_ACTIVE_STATUS H31 NC
01005 1/32W MF SPI_AP_TO_TOUCH_CS_L
21 OUT 0% 29 OUT SPI2_SSIN
ROOM=SOC SPI_MESA_TO_AP_MISO AA2 SPI3_MISO
B R0930 B
27 IN
27 OUT
SPI_AP_TO_MESA_MOSI Y2 SPI3_MOSI CLK32K_OUT H34 45_AP_TO_TOUCH_CLK32K_RESET_L OUT 29

SPI_AP_TO_MESA_SCLK 1
0.00 2 SPI_AP_TO_MESA_SCLK_R AA3
27 OUT SPI3_SCLK
MESA_TO_AP_INT AC4 NAND_SYS_CLK AM24 AP_TO_NAND_SYS_CLK_R
01005 1/32W MF
SPI3_SSIN
0% 27 IN
R0945
1
0.00 2 AP_TO_NAND_SYS_CLK OUT 13

0%
1/32W
MF
BUTTON PULL-UP RESISTORS AND BUFFERS 01005
ROOM=SOC

PP1V8_SDRAM 8 12 14 15 16 17 24 26 30 33
SPI PROBE POINTS
1
R0951 ROOM=SOC
PP0906
ROOM=SOC
PP0908
100K
5% P2MM-NSM P2MM-NSM
1/32W SM SM
MF 1 SPI_TOUCH_TO_AP_MISO 8 29 PP 1 SPI_CODEC_TO_AP_MISO 8 24
01005 PP
2 ROOM=SOC

ANTI-ROLLBACK EEPROM 32 16 8 BUTTON_RINGER_A I2C PROBE POINTS


ROOM=SOC
PP0907
ROOM=SOC
PP0909
P2MM-NSM P2MM-NSM
128kbit SM
1 SPI_AP_TO_TOUCH_MOSI
SM
PP1V8_SDRAM 8 12 14 15 16 17 24 26 30 33 8 29 PP 1 SPI_AP_TO_CODEC_MOSI 8 24
APN:335S0946 ROOM=SOC
PP

1
R0950 P3MM-NSM ROOM=SOC
PP09010
392K
U0901 26 16 8 I2C0_AP_SCL 1
SM
PP PP0900 P2MM-NSM
PP1V8 1%
28 21 20 14 13 12 9 8 7 6 5 3
29 1/32W
MF 74LVC1G34GX 26 16 8 I2C0_AP_SDA 1
PP PP0901 SM
1 SPI_AP_TO_CODEC_SCLK
5

C0900
8 24
1 CRITICAL 2 01005 SOT1226 PP
A1

SM
BUTTON_MENU_KEY_L 2 4 BUTTON_MENU_KEY_BUFF_L P3MM-NSM
1.0UF ROOM=SOC 27 IN OUT 9 16
ROOM=SOC
20%
NC
VCC

2 6.3V
X5R
3

ROOM=SOC

A U0900
0201-1
A
1

ROOM=SOC NC P3MM-NSM

B1
M34128-FCS6_P/T
A2
30 25 17 8 I2C1_AP_SCL 1
SM
PP PP0902 SYNC_MASTER=N/A SYNC_DATE=N/A
SCL SDA I2C_SEP_BI_EEPROM_SDA PAGE TITLE
WLCSP
I2C_SEP_TO_EEPROM_SCL
BI 8
30 25 17 8 I2C1_AP_SDA 1
PP PP0903 SOC:SERIAL & GPIO
IN 8 PP1V8_ALWAYS 8 12 15 17
VSS

SM
P3MM-NSM DRAWING NUMBER SIZE
1
R0952 ROOM=SOC
Apple Inc.
051-00648 D
392K
B2

1% U0902 ROOM=SOC
P3MM-NSM
REVISION
1/32W
MF 74LVC1G34GX I2C2_AP_SCL 1
SM
PP0904
R
4.0.0
5

20 8
2 01005 SOT1226 PP
NOTICE OF PROPRIETARY PROPERTY: BRANCH
32 IN
BUTTON_HOLD_KEY_L 2 4 BUTTON_HOLD_KEY_BUFF_L OUT 9 16 20 8 I2C2_AP_SDA 1
PP PP0905 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
NC

SM THE POSESSOR AGREES TO THE FOLLOWING: PAGE


P3MM-NSM
3

ROOM=SOC I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE


9 OF 49
1

NC II NOT TO REPRODUCE OR COPY IT


SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 8 OF 60
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1

SOC - OWL POWER STATE CONTROL PROBE POINTS


ROOM=SOC
P3MM-NSM
SM
16 9 OWL_TO_PMU_ACTIVE_REQUEST 1
PP PP1020
ROOM=SOC
P3MM-NSM
SM

D
30 26 16 9 5 PMU_TO_OWL_ACTIVE_READY 1
PP PP1021 D
ROOM=SOC
P3MM-NSM
SM
16 9 OWL_TO_PMU_SLEEP1_REQUEST 1
PP PP1022
ROOM=SOC
P3MM-NSM
SM
16 11 9 PMU_TO_OWL_SLEEP1_READY 1
PP PP1023

OMIT_TABLE
U0600
MAUI-2GB-25NM-DDR-H
FCMSP
SC58980X0B-A040
SYM 7 OF 14
OWL_TO_PMU_SLEEP1_REQUEST AD30 OWL_DDR_REQ CFSB_AOP W33 PMU_TO_SYSTEM_COLD_RESET_L
PP1003
16 9 OUT IN 3 5 16
ROOM=SOC SM
PMU_TO_OWL_SLEEP1_READY AB33 1
C 16 11 9 IN

AF35
OWL_DDR_RESET*
AWAKE_REQ AA33 OWL_TO_PMU_ACTIVE_REQUEST OUT 9 16
PP
P2MM-NSM C
SPI_OWL_TO_COMPASS_CS_L AWAKE_RESET* AD32 PMU_TO_OWL_ACTIVE_READY
19 9 OUT

19 COMPASS_TO_OWL_INT AH32
OWL_FUNC_0
OWL_FUNC_1
IN 5 9 16 26 30
1
SM
PP
PP1002
IN
CRITICAL PMGR_MISO AL2 DWI_PMU_TO_PMGR_MISO 16 P2MM-NSM
19 ACCEL_TO_OWL_INT2_R AG32 OWL_FUNC_2
IN
IN
PMGR_MOSI AL1 45_DWI_PMGR_TO_PMU_BACKLIGHT_MOSI 16 26 PP1V8
19 ACCEL_GYRO_TO_OWL_INT1 AG31 OWL_FUNC_3
OUT 3 5 6 7 8 12 13 14 20 21 28 29
IN
PMGR_SCLK0 AK4 45_DWI_PMGR_TO_PMU_SCLK
PP1004
16
SPI_OWL_TO_ACCEL_GYRO_CS_L AG30 OWL_FUNC_4
OUT
SM
19 9 OUT
AL3 45_DWI_PMGR_TO_BACKLIGHT_SCLK 1 1
19 IN
ACCEL_GYRO_TO_OWL_INT2 AF33 OWL_FUNC_5
PMGR_SSCLK1 OUT 26 PP
P2MM-NSM R1002
AE34 OWL_FUNC_6 RT_CLK32768 AD31 PMU_TO_OWL_CLK32K 1.00K
NC IN 16
5%
33 29 28 8 LCM_TO_AP_HIFA_BSYNC AF34 OWL_FUNC_7 1/32W
IN
OWL_SWD_TCK_OUT AE33 SWD_AP_PERIPHERAL_SWCLK 13 33
MF
OWL_TO_PMU_SHDN_BI_TIGRIS_SWI AF31 OWL_FUNC_8
OUT 01005
9
OWL_SWD_TMS0 AD35 2 ROOM=SOC
AF32 OWL_FUNC_9 NC
NC OWL_SWD_TMS1 AC33 SWD_AP_BI_BB_SWDIO 33
BI
19 9 OUT SPI_OWL_TO_DISCRETE_ACCEL_CS_L AH31 OWL_I2CM_SCL SWD_TMS2 U31 SWD_AP_BI_NAND_SWDIO BI 13

ACCEL_TO_OWL_INT1_R AH33 OWL_I2CM_SDA SWD_TMS3 T31


19 IN NC
19 9 IN
SPI_IMU_TO_OWL_MISO AK31 OWL_SPI_MISO HOLD_KEY* U3 BUTTON_HOLD_KEY_BUFF_L IN 8 16

19 9 OUT SPI_OWL_TO_IMU_MOSI AK32 OWL_SPI_MOSI


AL33 SKEY* W4 NC
19 9 OUT SPI_OWL_TO_IMU_SCLK OWL_SPI_SCLK
AJ32 MENU_KEY* V4 BUTTON_MENU_KEY_BUFF_L 8 16
33 IN
UART_BB_TO_OWL_RXD OWL_UART0_RXD
IN

33 OUT
UART_OWL_TO_BB_TXD AK33 OWL_UART0_TXD

33 OUT
OWL_TO_WLAN_CONTEXT_B AH30 OWL_UART1_RXD
33 OUT
OWL_TO_WLAN_CONTEXT_A AJ31 OWL_UART1_TXD
AJ34 OWL_UART2_RXD
NC
AJ33 OWL_UART2_TXD
NC
24 8 OUT 45_I2S_AP_OWL_TO_CODEC_XSP_BCLK AD34 OWL_I2S_BCLK

B 24 8 IN
I2S_CODEC_TO_AP_OWL_XSP_DIN AA34
AE32
OWL_I2S_DIN
OWL_I2S_MCK
B
NC
24 8 OUT I2S_AP_OWL_TO_CODEC_XSP_LRCLK AE31 OWL_I2S_LRCK

PP1005 SM
PP
1 SPI_OWL_TO_IMU_MOSI 9 19
P2MM-NSM
OWL SYSTEM SHUTDOWN OPTION
PP1006 SM
PP
1 SPI_IMU_TO_OWL_MISO 9 19
P2MM-NSM NOSTUFF
PP1007 SM
1
R1020
SPI_OWL_TO_IMU_SCLK 9 19 10
P2MM-NSM
PP 1 2 1/32W SWI_AP_BI_TIGRIS BI 8 17
MF 5% 01005
ROOM=SOC
PP1008 SM
PP
1 SPI_OWL_TO_DISCRETE_ACCEL_CS_L 9 19 OWL_TO_PMU_SHDN_BI_TIGRIS_SWI
P2MM-NSM 9
NOSTUFF
A PP1009 SM
R1021
10 SYNC_MASTER=N/A SYNC_DATE=N/A A
1 SPI_OWL_TO_ACCEL_GYRO_CS_L 9 19 1 2 1/32W OWL_TO_PMU_SHDN 16 PAGE TITLE
PP OUT
P2MM-NSM MF 5%
ROOM=SOC
01005
SOC:OWL
PP1010 SM
PP
1 SPI_OWL_TO_COMPASS_CS_L 9 19
DRAWING NUMBER

051-00648
SIZE

D
P2MM-NSM Apple Inc.
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 9 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PP_SOC
SOC - CPU, GPU & SOC RAILS
14
0.825V @4.7A MAX
0.725V @TBDA MAX
AA17
OMIT_TABLE
W23
1 C1150 1 C1151
10UF 10UF
AA19 U0600 Y14 20%
6.3V
20%
2 CERM-X5R 2 6.3V
AA23 MAUI-2GB-25NM-DDR-H Y16 0402-9
CERM-X5R
0402-9 XW1120
SHORT-10L-0.1MM-SM
AB14 FCMSP Y20 ROOM=SOC ROOM=SOC
1 2 45_BUCK2_PP_SOC_FB
14 10 PP_GPU AB16 SC58980X0B-A040 Y22
OUT 14

0.8V @10.5A MAX ROOM=SOC


SYM 9 OF 14
AB20 Y24
XW1110 ROOM=SOC
1 C1100 1 C1101 1 C1103 1 C1104 1 C1105 SHORT-10L-0.1MM-SM AB22 Y26

D 20%
10UF 10UF
20%
2.2UF
20% 20%
2.2UF
20%
2.2UF 1 2 45_BUCK1_PP_GPU_FB OUT 14 16 AB24
CRITICAL
VDD_SOC G29 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC D
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
ROOM=SOC
AB26 AA27 C1153 C1154 C1155 C1156 C1157
0402-9 0402-9 0201 0201 0201 AC17 F17 4.3UF 1UF 1UF 1UF 0.47UF
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC 20% 20% 20% 20% 20%
AC19 F20
TP1120
0.50MM AC23 L29
4V
CERM
0402
4V
CERM
0402
4V
CERM
0402
4V
CERM
0402
6.3V
CERM
0402
SM
1 AD16 N29 1 3 1 3 1 3 1 3 1 3
PP
PP_GPU 10 14
AD20 V28
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC AA7 OMIT_TABLE G15 2 4 2 4 2 4 2 4 2 4
C1106 C1107 C1108 C1109 C1110 C1111 AA9 U0600 W13
AD22
AD24
4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF AA11 MAUI-2GB-25NM-DDR-H T12
20% 20% 20% 20% 20% 20% AD26
4V 4V 4V 4V 4V 4V AB6 FCMSP M6
CERM CERM CERM CERM CERM CERM AE5
0402 0402 0402 0402 0402 0402 AB10 SC58980X0B-A040 U9 L22
1 3 1 3 1 3 1 3 1 3 1 3 AE15
AB12 SYM 8 OF 14 V12 L24
AE17
AC13 ROOM=SOC W9 L26
2 4 2 4 2 4 2 4 2 4 2 4 AE19
AD6 CRITICAL M12 L28
AE23
AD8 M18 M1
AF14
AD10 N15 M5
AF16
AD12 N21 M7
AF20
AE7 N9 M9
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC AF22
C1112 C1113 C1114 C1115 C1116 C1117 AE9
AE11
F10
H14
AF24
M11
M13
1UF 1UF 1UF 1UF 0.47UF 0.47UF AF26
20% 20% 20% 20% 20% 20% AE13 H16 M17
4V 4V 4V 4V 6.3V 6.3V AG17
CERM CERM CERM CERM CERM CERM AF8 H20 M21
0402 0402 0402 0402 0402 0402 AG19
1 3 1 3 1 3 1 3 1 3 1 3 AF10 H22 M23
AG23
AF12 H6 M25
AH16
2 4 2 4 2 4 2 4 2 4 2 4 AH6 H8 M27
AH20
AH8 J11 M29
AH22
C AH10
AH12
J13
J17
AH24
M35
N6
C
VDD_CPU AH26
AJ5 J19 N10
AJ15
AJ7 J23 N12
AJ17
PP_CPU AJ9 J7 N14
14 10 AJ19
0.625V @TBDA MAX AJ11 K10 N16
AJ23
0.9V @10.5A MAX AJ13 K14 N18
1.0V @12.5A MAX 1 C1120 1 C1121 1 C1122 1 C1123 1 C1125 AK6 K16
AK14
J29
G19
10UF 10UF 2.2UF 2.2UF 2.2UF AK10 K20 VDD_SOC N22
20% 20% 20% 20% 20%
G23
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
6.3V
2 X5R-CERM AL7 K22 N24
0402-9 0402-9 0201 0201 0201 AK22
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC AL9 K6 N26
F6
TP1100 AL11 K8
F14
N28
0.50MM AM6 L11 N30
SM
1 PP_CPU AL15
PP 10 14 AM8 L13 N33
AM5
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC AM10 L15 P9
G25
C1126 C1127 C1128 C1129 C1130 C1131 AN7 L17
G27
P11
4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF AN11 L19 P13
20% 20% 20% 20% 20% 20% H24
4V 4V 4V 4V 4V 4V AL13 VDD_GPU L21 P15
CERM CERM CERM CERM CERM CERM H26
0402 0402 0402 0402 0402 0402 Y8 M24 P17
1 3 1 3 1 3 1 3 1 3 1 3 H28
Y10 L7 VSS P19
J27
Y12 L9 P21
2 4 2 4 2 4 2 4 2 4 2 4 K24
AM12 F8 P23
K26
M8 P25
K28
N11 P27
L27
N13 P29
L23
N17 P35
M26
B
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
B C1132 C1133 C1134 C1135 C1136 C1137
N19
P10
M28
R4
R6
4.3UF 4.3UF 1UF 1UF 1UF 1UF AL19
20% 20% 20% 20% 20% 20% G11 R8
4V 4V 4V 4V 4V 4V N7
CERM CERM CERM CERM CERM CERM P12 R10
0402 0402 0402 0402 0402 0402 N27
1 3 1 3 1 3 1 3 1 3 1 3 P14 R12
P24
P16 R14
P26
2 4 2 4 2 4 2 4 2 4 2 4 P20 M19
P28
R15 R18
R17
R19 R20
R27
G13 R22
R29
R9 R24
T22
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC T10 R26
T26
C1138 C1139 C1140 C1141 T14
T7
R28
0.47UF 0.47UF 0.47UF 0.47UF T16 R30
20% 20% 20% 20% T28
6.3V 6.3V 6.3V 6.3V U11 T1
CERM CERM CERM CERM U17
0402 0402 0402 0402 V14 T2
1 3 1 3 1 3 1 3 V8
V16 R33
V20
G7 T9
2 4 2 4 2 4 2 4 V22
R23 T11
V24
G9 T13
V26
H10 T15
W7
T24
XW1100
SHORT-10L-0.1MM-SM P22
W11
T17
P7
45_BUCK0_PP_CPU_FB 2 1 Y28
14 OUT W17 T23
ROOM=SOC
N23 AJ20 VDD_SOC_SENSE T25
G17 T27
AK21
A G21
T18
VSS_SOC_SENSE T30
T35 SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
T20
PP1100 SM
1
U6
SOC:POWER (1/3)
PP U10
P2MM-NSM ROOM=SOC AP_CPU_SENSE_P Y6 VDD_CPU_SENSE VDD_GPU_SENSE G20 DRAWING NUMBER SIZE
U12
AP_CPU_SENSE_N Y7 VSS_CPU_SENSE VSS_GPU_SENSE H19 Apple Inc.
051-00648 D
PP1101 SM
1 REVISION

P2MM-NSM
PP
ROOM=SOC
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
PP1102 SM
PP
1 AP_GPU_SENSE_N AP_SOC_SENSE_N 1
SM
PP
PP1104 THE INFORMATION CONTAINED HEREIN IS THE
P2MM-NSM ROOM=SOC ROOM=SOC
P2MM-NSM PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PP1103 SM
PP
1 AP_GPU_SENSE_P AP_SOC_SENSE_P 1
SM
PP
PP1105 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
11 OF 49
P2MM-NSM ROOM=SOC ROOM=SOC
P2MM-NSM III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET

IV ALL RIGHTS RESERVED 10 OF 60


8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - POWER SUPPLIES


DDR IMPEDANCE CONTROL
1.06 - 1.17V @635mA MAX
D INTERNALLY SUPPLIES VDDQ 14 11 PP1V1 D
1 1 1 1 1 1
14 11 PP1V1 R1200 R1201 R1202 R1203 R1204 R1205
240 240 240 240 240 240
1% 1% 1% 1%
1 C1240 1 C1241 1 C1242 1 C1243 1 C1244 1 C1248 1/32W
MF
1/32W
MF
1/32W
MF
1/32W
MF
1%
1/32W
MF
1%
1/32W
MF
10UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2 01005 2 01005 2 01005 2 01005 01005 01005
20% 20% 20% 20% 20% 20% ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC 2 ROOM=SOC 2 ROOM=SOC
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0402-9 0201 0201 0201 0201 0201 A20 OMIT_TABLE DDR0_RREF C21 45_DDR0_RREF
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
A22 U0600 DDR1_RREF AP17 45_DDR1_RREF
B11 MAUI-2GB-25NM-DDR-H DDR2_RREF V31 45_DDR2_RREF
B15 FCMSP DDR3_RREF P5 45_DDR3_RREF
ROOM=SOC
C1245
ROOM=SOC
C1246
1 C1247 1 C1249 B23 SC58980X0B-A040
1.0UF 1.0UF B25 SYM 11 OF 14 DDR0_ZQ B21 45_DDR0_ZQ
4.3UF 1UF 20% 20%
20% 20% 2 6.3V 2 6.3V
D16 VDDIO11_DDR0 ROOM=SOC DDR3_ZQ P2 45_DDR3_ZQ
X5R X5R
4V 4V 0201-1 0201-1 D20 CRITICAL
CERM CERM
0402 0402 ROOM=SOC ROOM=SOC
D22 DDR0_RET* C18 PMU_TO_OWL_SLEEP1_READY
1 3 1 3 IN 9 16
E15 DDR1_RET* AP15
E17 DDR2_RET* Y31
2 4 2 4
E19 DDR3_RET* U4 FL1280
E21 1.1V @7mA MAX 100OHM-25%-0.12A
F19 45_PP1V1_DDR_PLL 1 2 PP1V1 11 14
AK18 01005
AN19 ROOM=SOC
AR18
VDDIO11_PLL_DDR W26 1 C1280
P8 0.22UF
AR21 20%
0.8V @TBDA MAX AR8 2 6.3V
X5R
0.9V @TBDA MAX 01005-1
AT13 ROOM=SOC
1.0V @1.0A MAX
C 0.802-TBDV @1.1A MAX
PP_FIXED AA15
OMIT_TABLE
AC11 PP_CPU_SRAM
AT16
AM14
C
14 7 6
U0600 14 VDDIO11_DDR1
AA21 MAUI-2GB-25NM-DDR-H AC7 AM16
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
AA25 FCMSP AC9 AM18
1 C1200 C1201 C1202 C1203 AB18 SC58980X0B-A040 AA13 C1220 C1221 C1222 1 C1223 AM20 D19 PP1V1_SDRAM
10UF 4.3UF 1UF 0.47UF 0.47UF 1UF 4.3UF 2.2UF
AN17
12 14 15
20% 20% 20% 20% AC15 VDD_CPU_SRAM AG11 20% 20% 20% 20% AR15
2 6.3V 4V 4V 6.3V 6.3V 4V 4V 6.3V
2 X5R-CERM 1.06 - 1.17V
CERM-X5R CERM CERM CERM AC21 SYM 10 OF 14 AG7 CERM CERM CERM AN13 VDDIO11_RET_DDR W31
0402-9 0402 0402 0402 0402 0402 0402 0201
ROOM=SOC 1 3 1 3 1 3 AC25 ROOM=SOC AG9 1 3 1 3 1 3 ROOM=SOC AN15 T4
AD14 CRITICAL AK12
2 4 2 4 2 4 AD18 2 4 2 4 2 4
AE21 H12
AB29 DDR0_SYS_ALIVE C19 SYSTEM_ALIVE 13 16 17
AE25 H18 IN
V29 DDR1_SYS_ALIVE AP16
AF18 R21
0.8V @0.5A MAX Y29 DDR2_SYS_ALIVE W32
AG15 U15
PP_GPU_SRAM 14 Y35 DDR3_SYS_ALIVE T3
AG21 J15
AB35
AH25 J21 ROOM=SOC ROOM=SOC ROOM=SOC
AG34
AH14 J9 C1224 C1225 C1226 1 C1227 M34 VDDIO11_DDR2
AH18 K12 0.47UF 1UF 4.3UF 2.2UF
20% 20% 20% 20% R35
AJ21 K18 6.3V 4V 4V 2 6.3V
CERM CERM CERM X5R-CERM T29
AK16 VDD_GPU_SRAM M10 0402 0402 0402 0201
1 3 1 3 1 3 ROOM=SOC T34
F12 M14
AA30
G10 M16
2 4 2 4 2 4 U30
V18 M20
AC30
AL17 P18
J25 R11
L25 R13
N25 U13 AA1
B R25
VDD_FIXED
V10 ROOM=SOC
AC2 B
R7 M22 C1228 V6
AN6 4.3UF W2
20%
U25 4V H2
CERM
W15 0402 M2
1 3
W21 U5 VDDIO11_DDR3
W25 2 4 P6
Y18 T6
F21 U1
F26 N5
AB28 R5
AC27 W5
G18
AK20
F16
R16
T8
V7
U19
W27
U27
AF4
AF27
U21

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

15
0.756-TBDV @44mA MAX
PP0V8_OWL AH29
SOC:POWER (2/3)
DRAWING NUMBER SIZE
AD29
1 C1250 AF29
VDD_LOW
Apple Inc.
051-00648 D
1.0UF REVISION
20%
2 6.3V
X5R
R
4.0.0
0201-1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
ROOM=SOC
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
12 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 11 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

A1
A2
A11
U0600
OMIT_TABLE

MAUI-2GB-25NM-DDR-H
AF23
AF25
AF30
AN12
AN14
AN18
U0600
OMIT_TABLE

MAUI-2GB-25NM-DDR-H
E12
E16
E18
SOC - POWER SUPPLIES
A16 FCMSP AG1 AN29 FCMSP E20
A21 SC58980X0B-A040 AG2 AN33 SC58980X0B-A040 E22
SYM 13 OF 14 SYM 14 OF 14
A24 AG3 AP2 E24
ROOM=SOC ROOM=SOC
A25 AG6 AP13 E26
D A27
CRITICAL
AG8 AP14
CRITICAL
E29 1.70-1.95V @100mA(TBD) MAX D
A34 AG10 AP20 E32 OMIT_TABLE
PP1V8_SDRAM A10 U14
A35 AG14 AP25 F4
33 30 26 24 17 16 15 14 8
A26 U0600 U16
MAUI-2GB-25NM-DDR-H
AA6
AA8
AG16
AG18
AP26
AP27
F5
F7
1 C1300 1 C1301 1 C1302 AD1
FCMSP
U18
2.2UF 2.2UF 2.2UF AH35 U22
AA10 AP30 20% 20% 20%
AG20 F9 AT22 VDD1 SC58980X0B-A040 U24
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
AA12 AG22 AP31 F11 0201 0201 0201 AT7 SYM 12 OF 14
U26
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
AA14 AG24 AP32 F13 G1 U28
AA16 U7 AP33 F15 CRITICAL
L35 U35
AA18 AG29 AR1 F18 1.06-1.17V @1.3A(TBD) MAX
V1
AA20 AG33 AR5 D18 15 14 11 PP1V1_SDRAM A15
V5
AA22 AG35 AR9 F23 A23
AA29
AA24 AH5 AR14 E30 1 C1310 1 C1312 1 C1313 1 C1314 AB34
U29
AA26 AH7 AR16 F25 10UF 2.2UF 2.2UF 2.2UF AD2
20% 20% 20% 20% V9
N8 AH9 AR25 F27 2 6.3V 2 6.3V 2 6.3V 2 6.3V AH34
CERM-X5R X5R-CERM X5R-CERM X5R-CERM V11
AA28 AH11 AR34 F28
0402-9 0201 0201 0201 AR13
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC V13
AA35 AH13 AR35 F29 AR17
V15
AB1 AH15 AT1 G4 AR22
V17
C17 AH17 AT2 G5 AR7
V19
AB3 AH19 AT6 G6 ROOM=SOC ROOM=SOC AT15 VDD2
AB5 AH21 AT8 G8 C1316 C1317 B10
V21
V23
AB7 AH23 AT9 G12 1UF 1UF B26
20% 20% V25
AB9 AH27 AT14 G14 4V 4V G2
CERM CERM V27
AB11 AJ6 AT17 G16 0402 0402 L34
1 3 1 3 W30
AB13 AJ8 AT18 E6 N2
W1
AB15 AJ10 AT21 G22 R1
2 4 2 4 W6
U34
C AB17
AB19
AJ12
AJ14
AT25
AT34
G24
G26 V2
W10
W12
C
AB21 AJ16 AT35 G28 W35
1.62-1.98V @41mA MAX W14
AB23 AJ18 B1 G33 PP1V8 F30 W16
28 21 20 14 13 12 9 8 7 6 5 3
AB25 W8 B2 H1 29
H30 W18
AB27
AB30
AJ22
AG12
B16
B20
H7
H9
1 C1320 1 C1321 1 C1322 1 C1323 K30 W20
10UF 2.2UF 2.2UF 2.2UF M30 VDDIO18_GRP1 W22
AC1 AK24 B22 H11 20% 20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
N31 VSS W24
AC6 AJ28 B24 H13 0402-9 0201 0201 0201 P30 W28
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
AC8 AK2 B27 H15 H5 W29
AC10 AK3 B34 H17 K5 VDDIO18_GRP2 W34
AC12 AK5 B35 E28 AN9 Y1
AC14 VSS VSS AK7 C2 H21 AA5 Y9
AC16 AK9 C3 VSS VSS H23 AC5 Y11
VDDIO18_GRP3
AC18 AK11 C4 H25 AG5 Y13
AC20 AK13 C5 H27 VDDIO18_GRP10:1.62-1.98V @8mA MAX AL5 Y15
AC22 AK15 C6 H29 VDDIO18_LPOSC:1.62-1.98V @1mA MAX AM23 VDDIO18_GRP4 Y17
AC24 B28 C7 J2 PP1V8_IMU_OWL AE28 Y19
19 14
AC26 AK17 C8 J5 AG28 VDDIO18_GRP10 (OWL) Y21
T5 M15 C9 J6 PP1V8_ALWAYS 1.62-1.98V @1mA MAX Y5 VDDIO18_GRP11 Y23
17 15 8 (AON)
AC28 AP28 C10 J30 Y25
AC34 AK26 C11 J8 AG26 VDD18_LPOSC Y27
AC35 AK30 C12 J10 28 21 20 14 13 12 9 8 7 6 5 3 PP1V8 AM22 VDD18_FMON
29 Y34
AD5 AK34 C13 J12 AD13 VDD18_UVD
VDD18_FMON :1.62-1.98V @1mA MAX AC29
AD7 AK29 C14 J14 VDD18_UVD :1.62-1.98V @5mA MAX
1 C1330 AN24 VDD18_AMUX AD28
AD9 AL6 C20 J16 2.2UF AG13
VDD18_AMUX :1.62-1.98V @1mA MAX 20% AE27
AD11 AL8 C22 J18 2 6.3V AK8
B AD15 AL10 C23 J20
VDD18_TSADC:1.645-1.89V @2mA MAX X5R-CERM
0201
ROOM=SOC
AB8
AG27
AJ30
B
AD17 AL12 C24 J22 N20 VDD18_TSADC
AJ35
AD19 AF28 C25 J24 U23
AK19
AD21 AL14 C26 J26 AK23
AT27
AD23 AM29 C27 J28 D31
AD25 AL16 C28 K7 G30
AD27 AR27 C29 K9 L30
AD33 AL18 C30 K11 P4
AE6 Y30 C31 K13 U8
AE8 AL20 C32 K15 V30
AE10 AL25 C33 K17 A28
AE12 AL28 D3 K19 AL32
AE14 AL30 D4 K21 T21
AE16 AL31 D5 K23
AE18 AM7 D6 K25
AE20 AM9 D11 K27
AE22 AM11 D17 K29
AE24 AM13 D21 K34
AE26 AM15 D23 K35
AE29 AM17 D26 L1
AE30 AM19 D27 L5
AE35 AM21 D28 L6
AF5 AM33 D29 K4
AF7 AM34 D30 L8
AF9 AM35 E1 L10

A AF11
AF15
AN3
AN5
E3
E4
L12
L14 SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
AF17 AN16 E5 L16
AF19 AN8 D7 L18 SOC:POWER (3/3)
AF21 AN10 E9 L20 DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
13 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 12 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

S3E NAND
R1530
PP1V8 1
24.9 2 PP1V8_NAND_AVDD
28 21 20 14 13 12 9 8 7 6 5 3
29
1%

D
1/32W
MF
01005
1 C1530
2.2UF
1 C1531
0.1UF
D
ROOM=NAND 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 01005
13 NAND_AGND ROOM=NAND ROOM=NAND

1 C1520 1 C1521 1 C1522 1 C1524 1 C1525 1 C1526 1 C1523


15UF 15UF 10UF 0.1UF 100PF 100PF 15UF
20% 20% 20% 20% 5% 5% 20%
6.3V
2 6.3V
X5R 2 6.3V
X5R 2 CERM-X5R 2 6.3V
X5R-CERM 2 16V
NP0-C0G 2 16V
NP0-C0G 2 6.3V
X5R
0402-1 0402-1 0402-9 01005 01005 01005 0402-1
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
PP3V0_NAND 15

1 C1500 1 C1501 1 C1502 1 C1503


1 C1527 1 C1528 15UF
20%
15UF
20% 20%
15UF
20%
15UF
2.2UF 2.2UF 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0402-1
ROOM=NAND
0402-1
ROOM=NAND
0402-1
ROOM=NAND
0402-1
ROOM=NAND
0201 0201
ROOM=NAND ROOM=NAND

1 C1504 1 C1506 1 C1505


15UF 15UF 15UF
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V
15 PP0V9_NAND X5R
0402-1
X5R
0402-1
X5R
0402-1
ROOM=NAND ROOM=NAND ROOM=NAND
1 C1548 1 C1540 1 C1541 1 C1542 1 C1543
15UF 15UF 15UF 10UF 10UF
20% 20%
C
20% 20% 20%
C 2 6.3V
X5R
0402-1
2 6.3V
X5R
0402-1
2 6.3V
X5R
0402-1
6.3V
2 CERM-X5R
0402-9
6.3V
2 CERM-X5R
0402-9 1 C1509 1 C1507 1 C1508 1 C1510
ROOM=NAND ROOM=NAND
ROOM=NAND ROOM=NAND ROOM=NAND 100PF 100PF 100PF 100PF
5% 5% 5% 5%
2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
NP0-C0G
01005 01005 01005 01005
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
1 C1546 1 C1550 1 C1551 1 C1554
15UF

OG10
OD10
OB10

OA10
OF10
0.1UF 0.1UF 1000PF

OG0
OD0
OB0

OA0
OF0
20%

M4

C3

R3
R7

R5
10%

K4
K6

E5

A3
A7

A5
F2
20% 20%

J5

J7

J1
J9
2 6.3V
X5R 2 6.3V 2 6.3V 2 6.3V
0402-1 X5R-CERM X5R-CERM X5R-CERM
PP1V8 01005 01005 01005

PCI_AVDD_CLK1
PCI_AVDD_CLK2

PCI_AVDD_H

PCI_VDD1
PCI_VDD2

AVDD1

VREF

VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

VCC
VCC
VCC
VCC
VCC
VCC
28 21 20 14 13 12 9 8 7 6 5 3 ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
29
NOSTUFF
1 C1560 1
R1560
0.01UF 10K
10%
2 6.3V
1%
1/32W
MF
U1500
X5R
01005 2 01005
ROOM=NAND
THGBX5G7D2KLFXG
ROOM=NAND NAND_VREF WLGA
8 AP_TO_NAND_SYS_CLK D2 CLK_IN EXT_D0 G3 PMU_TO_NAND_LOW_BATT_BOOT_L 16
IN
VER-1 IN
1 C1561 1
R1561 90_PCIE_AP_TO_NAND_REFCLK_P H8 PCIE_REFCLK_P
EXT_D1 J3 AP_TO_NAND_FW_STRAP IN 8

0.01UF 10K 13 6 IN
EXT_D2 H2
10% 1% 90_PCIE_AP_TO_NAND_REFCLK_N H6 PCIE_REFCLK_M BOMOPTION=OMIT_TABLE NC
2 6.3V 1/32W 13 6 IN
EXT_D3 E3
X5R MF ROOM=NAND NC ROOM=NAND
01005 2 01005 PCIE_NAND_TO_AP_CLKREQ_L G9 PCIE_CLKREQ* EXT_D4 E7
ROOM=NAND ROOM=NAND 6 OUT NC P3MM-NSM
F6
NOSTUFF
45_PCIE_NAND_RESREF M6 PCI_RESREF
CRITICAL EXT_D5
C7
NC 1
SM
PP PP1520
EXT_D6 NC
90_PCIE_AP_TO_NAND_TXD0_P M8 B8 SYSTEM_ALIVE
1
R1501 13 6 IN
90_PCIE_AP_TO_NAND_TXD0_N K8
PCIE_RX0_P
PCIE_RX0_M
EXT_D7 IN 11 16 17
R1520
3.01K 13 6 IN
EXT_NCE G1 PCIE_AP_TO_NAND_RESET_L IN 6 1
0.00 2 SWD_AP_BI_NAND_SWDIO
1% BI 9
1/20W 90_PCIE_AP_TO_NAND_TXD1_P N5 PCIE_RX1_P 0% MF 1/32W
MF 13 6 IN
EXT_NRE F4 SWD_AP_BI_NAND_SWDIO_R 01005
2 201 13 6 90_PCIE_AP_TO_NAND_TXD1_N N3 PCIE_RX1_M ROOM=NAND
IN

B
ROOM=NAND
B 6 OUT
90_PCIE_NAND_TO_AP_RXD0_P P8 PCIE_TX0_P
EXT_NWE C5 SWD_AP_NAND_SWCLK_R R1521
0.00
90_PCIE_NAND_TO_AP_RXD0_N N7 PCIE_TX0_M EXT_RNB G5 1 2 SWD_AP_PERIPHERAL_SWCLK IN 9 33
6 OUT NC 0% MF 1/32W
01005
90_PCIE_NAND_TO_AP_RXD1_P M2 PCIE_TX1_P EXT_CLE H4 ROOM=NAND
6 OUT NC
90_PCIE_NAND_TO_AP_RXD1_N K2 PCIE_TX1_M D4
PP1521
6 OUT
EXT_ALE 1
PP
SM
P3MM-NSM
5 AP_TO_NAND_RESET_L F8 RESET* ROOM=NAND
IN

D8 TRST*
NC
45_NAND_ZQ D6 ZQ

VSSA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
R1500
B2

B4
B6
OE10
G7
L3
L5
L7
P2
P4
P6
OC0
OC10
OE0
34.8
0.5%
1/32W
MF
01005 13 NAND_AGND
2 ROOM=NAND

PCIE RECEIVE-SIDE PROBE POINTS


ROOM=NAND
P3MM-NSM
13 6 90_PCIE_AP_TO_NAND_REFCLK_P 1
SM
PP PP1500
13 6 90_PCIE_AP_TO_NAND_REFCLK_N 1
PP PP1501
SM
P3MM-NSM
ROOM=NAND

A ROOM=NAND
P3MM-NSM SYNC_MASTER=N/A SYNC_DATE=N/A A
13 6 90_PCIE_AP_TO_NAND_TXD0_P 1
SM
PP1502 PAGE TITLE

13 6 90_PCIE_AP_TO_NAND_TXD0_N 1
PP

PP PP1503 NAND
DRAWING NUMBER SIZE
SM
P3MM-NSM
ROOM=NAND Apple Inc.
051-00648 D
REVISION
ROOM=NAND
P3MM-NSM
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY:
13 6 90_PCIE_AP_TO_NAND_TXD1_P 1
SM
PP PP1504 THE INFORMATION CONTAINED HEREIN IS THE
BRANCH

13 6 90_PCIE_AP_TO_NAND_TXD1_N 1
PP PP1505 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
SM
P3MM-NSM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
15 OF 49
ROOM=NAND SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 13 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ANTIGUA PMU - Buck Supplies

CRITICAL
D U2000 OMIT_TABLE D
ANTIGUA-D2255A080
L2000
1.0UH-20%-3.6A-0.060OHM
15 VCC_MAIN_SNS V3 VDD_MAIN_SNS CSP
IN
R6
A3 BUCK0_LX0 1 2 PP_CPU 10
33 26 25 24 22 21 17 15 PP_VCC_MAIN SYM 2 OF 5
B3 PIQA20161T-SM VOLTAGE=1.03V
ROOM=PMU BUCK0_LX0
F10 ROOM=PMU
1 C2085 1 C2086 1 C2087 1 C2088 L13
C3 CRITICAL 1 C2000 1 C2001 1 C2002 1 C2003 1 C2004 1 C2005 0.625V/0.9V/1.03V

L2001 15UF 15UF 15UF 15UF 15UF 15UF

BAT/USB
10UF 10UF 10UF 10UF L5 VDD_MAIN 0.47UH-20%-3.8A-0.048OHM 20% 20% 20% 20% 20% 20%
20% 20% 20% 20% 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V VOLTAGE=6.3V
2 X5R
2 VOLTAGE=6.3V VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V R8 X5R X5R X5R X5R X5R

12.5A MAX
CERM-X5R 2 CERM-X5R CERM-X5R CERM-X5R A5 BUCK0_LX1 1 2 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1

BUCK0
0402-9 0402-9 0402-9 0402-9 L4 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU B5 PIQA20121T-SM
BUCK0_LX1 ROOM=PMU
A4 C5 CRITICAL
B4
VDD_BUCK0_01 L2002
1.0UH-20%-3.6A-0.060OHM
C4 1 C2006 1 C2007 1 C2008 1 C2009 1 C2010 1 C2011
1 C2089 1 C2090 1 C2091 1 C2092 A8
A7 BUCK0_LX2 2 1 15UF
20%
15UF
20%
15UF
20%
15UF
20%
15UF
20% 20%
15UF
2.2UF 2.2UF 2.2UF 2.2UF B7 PIQA20161T-SM
20% 20% 20% 20% B8 BUCK0_LX2 ROOM=PMU 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R
VOLTAGE=6.3V
2 X5R 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R
2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V VDD_BUCK0_23 C7 CRITICAL 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1
X5R-CERM X5R-CERM X5R-CERM X5R-CERM C8
0201
ROOM=PMU
0201
ROOM=PMU
0201
ROOM=PMU
0201
ROOM=PMU
L2003 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU

0.47UH-20%-3.8A-0.048OHM
A16
A9 BUCK0_LX3 2 1
B16
VDD_BUCK1_01 B9 PIQA20121T-SM
C16 BUCK0_LX3 ROOM=PMU
C9 CRITICAL
1 C2093 1 C2094 1 C2095 A12
2.2UF 2.2UF 10UF
20% 20% 20% B12
VDD_BUCK1_23 BUCK0_FB F8 45_BUCK0_PP_CPU_FB 10
2 VOLTAGE=6.3V
VOLTAGE=6.3V IN
2 VOLTAGE=6.3V
2 X5R-CERM X5R-CERM CERM-X5R C12 L2010

BUCK INPUT
0201 0201 0402-9
ROOM=PMU ROOM=PMU ROOM=SOC 1.0UH-20%-3.6A-0.060OHM
J17
J18
A17 BUCK1_LX0 1 2 PP_GPU 10
VDD_BUCK2 B17 PIQA20161T-SM VOLTAGE=0.9V
C J19 BUCK1_LX0
C

m
ROOM=PMU
C17 CRITICAL 1 C2012 1 C2013 1 C2014 1 C2015 1 C2016 0.70V/0.80V/0.9V
1 C2099 T18 L2011 15UF 15UF 15UF 15UF 15UF

10.5A MAX
20% 20% 20% 20% 20%
100PF T19 VDD_BUCK3 0.47UH-20%-3.8A-0.048OHM VOLTAGE=6.3V VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V

o
2 X5R 2 X5R

BUCK1
5% X5R X5R X5R
VOLTAGE=16V
2 NP0-C0G A15 BUCK1_LX1 1 2 0402-1 0402-1 0402-1 0402-1 0402-1
V12 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
01005 B15 PIQA20121T-SM

.c
ROOM=PMU Y12 BUCK1_LX1 ROOM=PMU
VDD_BUCK4 C15 CRITICAL
Z12
L2012
N17 1.0UH-20%-3.6A-0.060OHM 1 C2017 1 C2018 1 C2019 2X 15UF BULK CAPS

x
N18 A13 BUCK1_LX2 2 1 15UF 15UF 15UF REMOVED FOR N69
VDD_BUCK5 20% 20% 20%
N19 B13 PIQA20161T-SM
BUCK1_LX2 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V

fi
ROOM=PMU X5R X5R X5R
C13 CRITICAL 0402-1 0402-1 0402-1
J1 ROOM=PMU ROOM=PMU ROOM=PMU
J2 VDD_BUCK6

a
E1 A11
VDD_BUCK7
NC 4TH PHASE INDUCTOR
E2 B11

in
BUCK1_LX3 NC REMOVED FOR N69
C11
E17 NC
E18
VDD_BUCK8 BUCK1_FB F12 45_BUCK1_PP_GPU_FB

h
10 16
E19 IN
L2020
PP1V8 VOLTAGE=1.8V U18 1.0UH-20%-3.6A-0.060OHM

.c
29 28 21 20 13 12 9 8 7 6 5 3
V18 H17 BUCK2_LX0 1 2 PP_SOC 10

4.7A MAX
Y18 BUCK3_SW1 H18 VOLTAGE=0.825V

BUCK2
PIQA20161T-SM
BUCK2_LX0 ROOM=PMU 0.725V/0.825V
Z18 H19 CRITICAL 1 C2022 1 C2023 1 C2024 1 C2025 1 C2026
L2021

w
PP1V8_TOUCH U16 BUCK3_SW2 15UF 15UF 15UF 15UF 15UF
29 VOLTAGE=1.8V 0.47UH-20%-3.8A-0.048OHM 20% 20% 20% 20% 20%
19 12 PP1V8_IMU_OWL VOLTAGE=1.8V U15 BUCK3_SW3 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R
K17 BUCK2_LX1 1 2

w
0402-1 0402-1 0402-1 0402-1 0402-1

B V16
BUCK2_LX1
K18
K19
PIQA20121T-SM
ROOM=PMU
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
B
11 PP1V1 VOLTAGE=1.1V CRITICAL

CRITICAL
L2050
Y16
Z16
BUCK4_SW1 w BUCK2_FB J14 45_BUCK2_PP_SOC_FB IN 10

1.0UH-20%-3.6A-0.060OHM L2030
1.0UH-20%-3.6A-0.060OHM
1.1A MAX

PP_FIXED 2 1 BUCK5_LX0 M17


BUCK5

11 7 6
R18 BUCK3_LX0 1 2 PP1V8_SDRAM

1.5A MAX
8 12 15 16 17 24 26 30 33
VOLTAGE=0.85V PIQA20161T-SM M18

BUCK3
BUCK5_LX0 BUCK3_LX0
1 C2050 1 C2051 ROOM=PMU
M19
R19 CRITICAL PIQA20161T-SM VOLTAGE=1.8V

20%
15UF 15UF
20%
XW2050
SHORT-10L-0.1MM-SM
ROOM=PMU
XW2030
SHORT-10L-0.1MM-SM
1 C2030 1 C2031 1 C2032
2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 1 45_BUCK5_FB M13 BUCK5_FB V19 45_BUCK3_FB 1 2 15UF 15UF 100PF
X5R X5R BUCK3_FB 20% 20% 5%
0402-1 0402-1 ROOM=PMU ROOM=PMU 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=16V
ROOM=PMU ROOM=PMU X5R X5R NP0-C0G
L2060 U17
0402-1
ROOM=PMU
0402-1
ROOM=PMU
01005
ROOM=PMU
1UH-20%-1.2A-0.320OHM V17
400mA MAX

PP1V2_CAMERA 2 1 BUCK6_LX0 H1 VBUCK3_SW Y17


BUCK6

21
VOLTAGE=1.2V 0603 H2 BUCK6_LX0 Z17
1 C2060 1 C2061 1 C2062 CRITICAL
ROOM=PMU

15UF 15UF 100PF


20% 20% 5% 21 45_BUCK6_FB J5 BUCK6_FB
VOLTAGE=16V IN
2 VOLTAGE=6.3V 2 VOLTAGE=6.3V L2040

4.7A MAX
X5R X5R 2 NP0-C0G CRITICAL

BUCK4
01005
0402-1
ROOM=PMU
0402-1
ROOM=PMU ROOM=PMU L2070 1.0UH-20%-3.6A-0.060OHM
1.0UH-20%-2.25A-0.15OHM V11 BUCK4_LX0 1 2 PP1V1_SDRAM 11 12 15

11 PP_CPU_SRAM 2 1 BUCK7_LX0 F1
BUCK4_LX0
Y11 PIQA20161T-SM
ROOM=PMU
VOLTAGE=1.1V
1.1A MAX

BUCK7_LX0
VOLTAGE=1.0V F2 Z11 CRITICAL C2040 C2041 C2042 C2043 C2044
BUCK7

PIXB2016FE-SM 1 1 1 1 1
0.80V/0.90V/1.0V 1 C2070 1 C2071 XW2070
ROOM=PMU
L2041 15UF 15UF 15UF 15UF 100PF
15UF 15UF SHORT-10L-0.1MM-SM 0.47UH-20%-3.8A-0.048OHM 20% 20% 20% 20% 5%
20% 20% 2 1 45_BUCK7_FB C1 BUCK7_FB 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=6.3V 2 VOLTAGE=16V
2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R V13 BUCK4_LX1 1 2 X5R
0402-1
X5R
0402-1
X5R
0402-1
X5R
0402-1
NP0-C0G
01005
A 0402-1
ROOM=PMU
0402-1
ROOM=PMU
L2080
ROOM=PMU
BUCK4_LX1
Y13 CRITICAL PIQA20121T-SM
ROOM=PMU
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
SYNC_MASTER=N/A SYNC_DATE=N/A A
Z13
1.0UH-20%-2.25A-0.15OHM XW2040 PAGE TITLE

11 PP_GPU_SRAM 2 1 BUCK8_LX0 F17


BUCK4_FB T9 45_BUCK4_FB
SHORT-10L-0.1MM-SM
1 2
SYSTEM POWER:PMU (1/3)
VOLTAGE=1.0V PIXB2016FE-SM F18 DRAWING NUMBER SIZE
1.1A MAX

BUCK8_LX0
C2080 C2081
BUCK8

ROOM=PMU ROOM=PMU
0.80V/0.90V/1.0V 1 1
CRITICAL F19
V15 Apple Inc.
051-00648 D
15UF 15UF
20% 20% XW2080 Y15
REVISION

2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R
SHORT-10L-0.1MM-SM
2 1 C19 BUCK8_FB
VBUCK4_SW
Z15
R
4.0.0
0402-1 0402-1 45_BUCK8_FB NOTICE OF PROPRIETARY PROPERTY: BRANCH
ROOM=PMU ROOM=PMU ROOM=PMU
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
20 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 14 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ANTIGUA LDO SPECS


ANTIGUA PMU - LDOs LDO#

LDO1 (A)
ADJ.RANGE

2.5-3.3V
ACCURACY

+/-2.5%
MAX.CURRENT

50mA

LDO2 (B) 1.2-1.9V +/-2.5% 50mA

LDO3 (A) 2.5-3.3V +/-2.5% 50mA


PP_VCC_MAIN LDO4 (D) 0.7-1.2V +/-2.5% 50MA
D
33 26 25 24 22 21 17 14

D 1 C2120 1 C2121 1 C2122 LDO5 (F) 2.5-3.3V +/-2.5% 1000mA


10UF 10UF 10UF
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V LDO6 (C1) 1.2-3.6V +/-2.5% 150mA
CERM-X5R CERM-X5R CERM-X5R
0402-9 0402-9 0402-9
XW2105
SHORT-10L-0.1MM-SM
ROOM=PMU ROOM=PMU ROOM=PMU LDO7 (C) 2.5-3.3V +/-25MV 200MA

14 VCC_MAIN_SNS 2 1 LDO8 (C) 2.5-3.3V +/-25mV 200MA


OUT
ROOM=PMU
1 C2123 1 C2124 1 C2125 LDO9 (C) 2.5-3.3V +/-25mV 250mA
10UF 10UF 10UF
20% 20% 20% LDO10 (G) 0.7-1.2V +/-2.5% 1335mA
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
0402-9 0402-9 0402-9
ROOM=PMU ROOM=PMU ROOM=PMU LDO11 (C) 2.5-3.3V +/-25mV 250mA

LDO12 (E) 1.8V +/-5% 10mA

1 C2126 1 C2127 CRITICAL LDO13 (C) 2.5-3.3V +/-25mV 250mA


10UF 10UF OMIT_TABLE
20% 20%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
U2000 LDO14 (H) 0.8-1.5V +/-2.5% 250mA
0402-9 0402-9 ANTIGUA-D2255A080
ROOM=PMU ROOM=PMU CSP LDO15 (B) 1.2-2.0V +/-2.5% 50mA
SYM 1 OF 5
M3 VDD_LDO1_3 ROOM=PMU
V2 VDD_LDO2
14 12 11 PP1V1_SDRAM M2 VDD_LDO4
VLDO1 M1 VOLTAGE=3.3V PP3V3_USB 5 LDO1
U1
C2130 1 C2131 1 VLDO2 V1 PP1V8_VA LDO2

LDO INPUT
U2 VDD_LDO5 VOLTAGE=1.8V 24 25
2.2UF 2.2UF VLDO3 L1 VOLTAGE=3.0V PP3V0_TRISTAR 26 30 31 33 LDO3
20% 20% L2 VDD_LDO6
6.3V 6.3V VLDO4 N1 PP0V8_OWL LDO4
X5R-CERM 2 X5R-CERM 2 Y6 VOLTAGE=0.8V 11

C VDD_LDO7
C

m
0201 0201 T1 VOLTAGE=3.0V PP3V0_NAND 13 LDO5
ROOM=PMU ROOM=PMU Y4 VDD_LDO8 VLDO5 T2
Y3 VDD_LDO9
VLDO6 K1 VOLTAGE=3.3V PP3V3_ACC LDO6

o
30
Y9
VBYPASS K2
Z9 VDD_LDO10
VLDO7 Z6 VOLTAGE=3.0V PP3V0_PROX_ALS 20 LDO7
R3

.c
VDD_LDO11

LDO
VLDO8 Z4 VOLTAGE=3.1V PP3V1_VIBE 32 LDO8
Y5 VDD_LDO13
VLDO9 Z3 VOLTAGE=2.5V PP2V5_RCAM_AF 21 LDO9
PP1V8_SDRAM Y7
33 30 26 24 17 16 14 12 8 VDD_LDO14
VLDO9_FB Y2 RCAM_AF_FB 1 2 XW2100
N2 VDD_LDO15

x
C2132 1 K3 VDD_BYPASS VLDO10
Y8
Z8
ROOM=PMU SHORT-10L-0.1MM-SM VOLTAGE=0.9V PP0V9_NAND 13 LDO10
2.2UF

fi
20% P12 VPP_OTP R2
6.3V 2 VLDO11 VOLTAGE=3.0V PP3V0_PROX_IRLED 20 LDO11
X5R-CERM
0201 VLDO12 K6 VOLTAGE=1.8V PP1V8_ALWAYS 8 12 17 LDO12
ROOM=PMU
VLDO13 Z5 VOLTAGE=3.1V PP3V1_MESA LDO13

a
27

VLDO14 Z7 VOLTAGE=1.2V PP1V2 5 6 7 LDO14


VLDO15 P2 VOLTAGE=1.9V PP1V9_MESA LDO15

in
27

U2000 VPUMP U19 45_PMU_VPUMP


ANTIGUA-D2255A080 1 C2100 1 C2101 1 C2103 1 C2107 1 C2109 1 C2111 1 C2113 1 C2115 1 C2116
2.2UF

h
CSP 47NF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
VPUMP:10nF min. @ 4.6V 20% 20% 20% 20% 20% 20% 20% 20% 20%
SYM 5 OF 5 2 6.3V
D10 J15 2 6.3V X5R-CERM 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM

.c
ROOM=PMU 0201
D11 J16 01005 ROOM=PMU
0201 0201 0201 0201 0201 0201 0201
D12 CRITICAL J3
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
OMIT_TABLE
D13 J4 U2000

w
D14 K15 ANTIGUA-D2255A080
D15 K16 CSP
1 C2102 1 C2104 1 C2106 1 C2108 1 C2110 1 C2112 1 C2114
SYM 4 OF 5 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
D16 L15 A1 L9 20% 20% 20% 20% 20% 0.1UF 20%

w
2 6.3V 20%
2 6.3V 2 6.3V 6.3V 2 6.3V 2 6.3V
B
ROOM=PMU
B D17 L16 A10 M8 2 X5R-CERM 2 6.3V
X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM
0201 0201 0201 0201 0201 X5R-CERM 0201
D18 M14 A14 CRITICAL M9 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 01005 ROOM=PMU
OMIT_TABLE ROOM=SOC
D2
D5
D6
M15
M16
N14
A18
A19
A2
N10
N12
N13
w
D7 N15 A6 N9
D8 N16 B1 P10
D9 P13 B10 P11
D3 P14 B14 P18
E10 P15 B18 P19
E11 P16 B19 P5
E12 P17 B2 R10
E13 R13 B6 R11
D4 NC NC R14 C10 R12
E15 R15 C14 R9
E16 R16 C18 T16
E3 R17 C2 T3 45_PMU_VSS_RTC
VSS 16
E4 T10 C6 T6 NOTE: T3 IS XTAL REF GND
E5 T11 D1 T8
E7 T12 D19 U3
E8 T13 E14 U9
E9 T14 G1 V10
F14 T15 G17 V14
F15 T17 G18 V8
F16 U10 G19 V9
F3 U11 G2 Y1
A F4
G14
U12
U13
H7
J6
Y10
Y14 SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
G15 U14 K12 Y19
G16 U4 K7 Z1 SYSTEM POWER:PMU (2/3)
DRAWING NUMBER SIZE
G3 U5 L17 Z10
G4 U6 L18 Z14 Apple Inc.
051-00648 D
REVISION
H15 V4 L19 Z19
H16 V5 L6 Z2
R
4.0.0
H3 V6 L7 NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


H4 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
21 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 15 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CONTROL PIN NOTES:


ANTIGUA PMU - GPIOs, NTCs NOTE (1):INPUT PULL-DOWN 100-300k
NOTE (2):INPUT PULL-DOWN 1M
NOTE (3):INPUT PULL-UP OR DOWN 100k-300k
NOTE (4):OUTPUT OPEN-DRAIN, REQUIRES PULL-UP

D D

CRITICAL
ROOM=PMU
OMIT_TABLE
33 30 26 24 17 15 14 12 8 PP1V8_SDRAM U2000
ANTIGUA-D2255A080
1 1
R2260 R2261 CSP
SYM 3 OF 5
100K 100K P7
5% 5% 5 IN
AP_TO_PMU_WDOG_RESET RESET_IN1 (3) IREF K5 45_PMU_IREF
1/32W 1/32W P8
MF MF 30 IN
TRISTAR_TO_PMU_HOST_RESET RESET_IN2 (3)
01005 01005

RESETS
2 2 AP_TO_PMU_SOCHOT1_L P9 VREF M4 PMU_VREF

REFS
ROOM=PMU ROOM=PMU 8 IN RESET_IN3 (3)
1
9 5 3 OUT PMU_TO_SYSTEM_COLD_RESET_L K4 RESET* (4) 1 C2270 R2270
OWL_TO_PMU_SHDN N8 SHDN (1) 0.22UF 200K
C2260
9 IN
1 20% 1%
1000PF 2 6.3V
X5R
1/20W
MF
10% 9 IN
OWL_TO_PMU_SLEEP1_REQUEST N3 SLEEP1_REQ (1) 0201 2 201
2 6.3V
X5R-CERM 11 9 OUT PMU_TO_OWL_SLEEP1_READY N7 SLEEP1_RDY
ROOM=PMU ROOM=PMU
01005
ROOM=PMU 9 OWL_TO_PMU_ACTIVE_REQUEST P3 ACTIVE_REQ (1)
IN
30 26 9 5 OUT PMU_TO_OWL_ACTIVE_READY P4 ACTIVE_RDY PRE_UVLO M5 PMU_TO_AP_SOCHOT0_L 8
OUT

COMPARATOR
9 OUT PMU_TO_OWL_CLK32K T4 SLEEP_32K R2201
R4 OUT_32K
0.00
33 16 OUT
45_PMU_TO_WLAN_CLK32K VDROOP G5 PMU_VDROOP_OUT 1 2 1/32W
MF 0% 01005
ROOM=PMU
SYSTEM_ALIVE H6 SYS_ALIVE
17 13 11 OUT (4)
VDROOP_DET H5 PMU_VDROOP_DET_IN 1
R22052 1/32W 45_BUCK1_PP_GPU_FB 10 14
L3 TMPR_DET (2) MF 1% 01005
IN
NC
PMU_TO_AP_IRQ_L L8 IRQ*
1 C2205 150
ROOM=PMU NOTE:VDROOP_DET R/C Low-pass Fc=1.06MHz
8 OUT (4) 1000PF NO_XNET_CONNECTION=1

C 26 16 8 IN
I2C0_AP_SCL R7 SCL
10%
2 10V
X5R
C
26 8 BI
I2C0_AP_SDA T7 SDA 01005
ROOM=PMU

9 IN
45_DWI_PMGR_TO_PMU_SCLK U7 SCLK (1) IN 16 26

PMGR
45_DWI_PMGR_TO_PMU_BACKLIGHT_MOSI U8 MOSI
26 9 IN
DWI_PMU_TO_PMGR_MISO V7 MISO
(1) 1 C2203
9 OUT 1000PF
10%
F13 BRICK_ID T5 TRISTAR_TO_PMU_USB_BRICK_ID 16 30 2 6.3V
X5R-CERM

ADC
5 AP_TO_PMU_AMUX_OUT AMUX_A0
IN
IN
G13 ADC_IN R5 CHESTNUT_TO_PMU_ADCMUX 01005
16 9 8 BUTTON_MENU_KEY_BUFF_L AMUX_A1 ROOM=CHESTNUT
FOREHEAD NTC 32 16 8
IN
BUTTON_RINGER_A J12 AMUX_A2
IN
AP_TO_PMU_TEST_CLKOUT H13 AMUX_A3 BUTTON1 G6 BUTTON_MENU_KEY_BUFF_L
1
5 IN IN 8 9 16
BUTTON1 + BUTTON2 ASSERTED FOR

BUTTONS
16 9 8 BUTTON_HOLD_KEY_BUFF_L H14 AMUX_A4 BUTTON2 F6 BUTTON_HOLD_KEY_BUFF_L 8 9 16 >TBD SECONDS CAUSES TWO-FINGER RESET
IN IN
LCM_TO_CHESTNUT_PWR_EN K10 AMUX_A5 BUTTON3 E6 BUTTON_RINGER_A
C2210 1 R2210 28 26 IN
TRISTAR_TO_PMU_USB_BRICK_ID K11 AMUX_A6 BUTTON4 F5
IN 8 16 32

100PF 10KOHM-1%
30 16 IN NC
FOREHEAD_NTC_RETURN CHESTNUT_TO_PMU_ADCMUX K13

AMUX
5% 26 16 AMUX_A7
16V 2 01005
IN
NP0-C0G 3 OUT PMU_AMUX_AY J13 AMUX_AY
01005 2 ROOM=PMU GPIO1 F7 TIGRIS_TO_PMU_INT_L
R2200
IN 17
ROOM=PMU
33 BB_TO_PMU_AMUX_SMPS1 N11 AMUX_B0 GPIO2 G7 BB_TO_PMU_HOST_WAKE_L 33
IN IN
M12 J7 PMU_TO_BB_PMIC_RESET_R_L 1
1.00K 2 PMU_TO_BB_PMIC_RESET_L
NC AMUX_B1 GPIO3 OUT 33

33 BB_TO_PMU_AMUX_LDO5 L11 AMUX_B2 GPIO4 G8 TRISTAR_TO_AP_INT 8 30 5%


IN IN
1/32W
32 8 BUTTON_VOL_DOWN_L M10 AMUX_B3 GPIO5 H8 STOCKHOLM_TO_PMU_HOST_WAKE 33 MF
IN IN
01005
45_PMU_TO_WLAN_CLK32K L14 AMUX_B4 GPIO6 J8 PMU_TO_NAND_LOW_BATT_BOOT_L
REAR CAMERA NTC 33 16 IN OUT 13 ROOM=PMU
33 IN
BB_TO_PMU_AMUX_LDO11 L12 AMUX_B5 GPIO7 K8 WLAN_TO_PMU_HOST_WAKE IN 33

BUTTON_VOL_UP_L M11 AMUX_B6 GPIO8 F9 CODEC_TO_PMU_MIKEY_INT_L


1 32 8 IN IN 24

33 IN
BB_TO_PMU_AMUX_SMPS4 L10 AMUX_B7 GPIO9 G9 PMU_TO_BT_REG_ON OUT 33

C2220 1 R2220 3 OUT PMU_AMUX_BY K14 AMUX_BY GPIO10 H9 BT_TO_PMU_HOST_WAKE 33

GPIO
IN

B 100PF
5% 10KOHM-1% RCAM_NTC_RETURN
FOREHEAD_NTC M6
GPIO11 J9
G10
PMU_TO_WLAN_REG_ON OUT 33 B
16V 2 01005 TDEV1 GPIO12 NC
NP0-C0G
01005 ROOM=PMU SHORT-10L-0.1MM-SM REAR_CAMERA_NTC M7 TDEV2 GPIO13 H10 PMU_TO_CODEC_DIGLDO_PULLDN
2 24
XW2210
OUT
ROOM=PMU 1 2 N4 J10 CODEC_TO_AP_PMU_INT_L
RADIO_PA_NTC

NTC
ROOM=PMU TDEV3 GPIO14 IN 8 24

AP_NTC N5 TDEV4 GPIO15 F11 PMU_TO_BB_USB_VBUS_DETECT OUT 33

45_PMU_TCAL N6 TCAL GPIO16 G11 PMU_TO_STOCKHOLM_EN OUT 33


SHORT-10L-0.1MM-SM
H11 WLAN_TO_PMU_PCIE_WAKE_L
ROOM=PMU 1 2 XW2220 45_PMU_XTAL1 P1 XTAL1
GPIO17
K9
IN 33

GPIO18 NC

XTAL
45_PMU_XTAL2 R1 XTAL2 GPIO19 J11 PMU_TO_LCM_PANICB
RADIO PA NTC OUT 28

SHORT-10L-0.1MM-SM GPIO20 G12


NC
1 ROOM=PMU 1 2 XW2230 PMU_VDD_RTC P6 VDD_RTC GPIO21 H12 I2C0_AP_SCL IN 8 16 26

C2230 1 R2230 SHORT-10L-0.1MM-SM


1 C2202
100PF
5%
16V 2
10KOHM-1% PA_NTC_RETURN ROOM=PMU 1 2 XW2240 0.22UF
20%
NP0-C0G 01005 2 6.3V
X5R
01005 2 ROOM=PMU 0201
ROOM=PMU ROOM=PMU

AP NTC CRITICAL
Y2200
32.768KHZ-20PPM-12.5PF
1 1 2

C2240 1 R2240 1 C2250 1


R2250 C2200 1 1.60X1.00-SM
ROOM=PMU 1 C2201
100PF 18PF 18PF
A 5%
16V 2
10KOHM-1% AP_NTC_RETURN 5%
100PF 3.92K
0.1% 5%
16V 2
5%
2 16V XW2200 SYNC_MASTER=N/A SYNC_DATE=N/A A
NP0-C0G 01005 2 16V
NP0-C0G
1/20W
MF CERM CERM PAGE TITLE
01005 ROOM=PMU 01005 01005 SHORT-10L-0.1MM-SM
2 01005
ROOM=PMU ROOM=PMU 2
0201
ROOM=PMU ROOM=PMU 15 45_PMU_VSS_RTC ROOM=PMU 1 2
ROOM=PMU
SYSTEM POWER:PMU (3/3)
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
22 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 16 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

TIGRIS CHARGER
APN:343S00033

PP_VCC_MAIN 14 15 21 22 24 25 26 33
VOLTAGE=4.3V

1 C2330 1 C2331
10UF 10UF
20% 20%
6.3V
2 CERM-X5R 2 6.3V
CERM-X5R
0402-9 0402-9
ROOM=CHARGER ROOM=CHARGER

C TIGRIS_LDO
C
TIGRIS_PMID 1 C2307 1 C2305
100PF 2.2UF

D2
C2
A2
B2
5% 20%
C2320 C2321 C2322 2 16V 2 6.3V

A2
A3
B1
B2
B3
1 1 1 NP0-C0G X5R-CERM

VDD_MAIN
VDD_MAIN
VDD_MAIN
VDD_MAIN
4.2UF 4.2UF 100PF 01005 0201
S
CRITICAL
Q2300
10% 10% 5% ROOM=CHARGER ROOM=CHARGER
2 16V
X5R-CERM 2 16V
X5R-CERM 2 35V
NP0-C0G
0402-1 0402-1 01005 A1 CSD68827W
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER CRITICAL G
BGA
F5 PMID U2300 LDO G4 C2300 L2300 ROOM=CHARGER

0.047UF 1.0UH-20%-3.6A-0.060OHM
A5 SN2400AB0
31 30 3 PP5V0_USB VBUS WCSP BOOT G5 TIGRIS_BOOT 1 2 1 2 D
B5 VBUS PIQA20161T-SM
C2310 C2311 ROOM=CHARGER A4

C1
C2
C3
1 1 BUCK_SW 10% ROOM=CHARGER
D5 VBUS CRITICAL 16V
4.2UF 100PF C5 BUCK_SW B4 X5R
10% 5% VBUS 0201
15 12 8 PP1V8_ALWAYS 2 16V
X5R-CERM 2 35V
NP0-C0G E5 VBUS
BUCK_SW D4 ROOM=CHARGER C2301 1 C2302 1
0402-1 01005 BUCK_SW C4 TIGRIS_BUCK_LX 100PF 100PF
ROOM=CHARGER ROOM=CHARGER 5% 5%
1 R2310 30 25 8 BI I2C1_AP_SDA G3 SDA
BAT A1
16V
NP0-C0G 2
16V
NP0-C0G 2
100K I2C1_AP_SCL E4 SCL 01005 01005
5% 30 25 8 IN
BAT B1 ROOM=CHARGER ROOM=CHARGER
1/32W
MF SYSTEM_ALIVE E3 SYS_ALIVE BAT D1
2 01005 16 13 11
ROOM=CHARGER BAT C1 PP_BATT_VCC
F4
R2311
3 18 33
30 IN
TRISTAR_TO_TIGRIS_VBUS_OFF VBUS_OVP_OFF
100 G2 BAT_SNS E1 VBATT_SENSE 18
16 OUT
TIGRIS_TO_PMU_INT_L 1 2 TIGRIS_TO_PMU_INT_R_L INT
IN

1%
1/32W TIGRIS_VBUS_DETECT F1 VBUS_DET
ACT_DIODE E2 TIGRIS_ACTIVE_DIODE 1 C2306 1 C2303 1 C2304
MF 100PF 2.2UF 2.2UF
01005 F3 TEST HDQ_HOST G1 SWI_AP_BI_TIGRIS 8 9
NOSTUFF
5% 20% 20%
2 16V
BI
2 6.3V 2 6.3V

PGND
PGND
PGND
PGND
ROOM=CHARGER
HDQ_GAUGE F2 TIGRIS_TO_BATTERY_SWI_1V8 R2300 NP0-C0G X5R-CERM X5R-CERM
B R2320
17

100K
1 01005
ROOM=CHARGER
0201
ROOM=CHARGER
0201
ROOM=CHARGER B
5%
30.1K 2 A3 1/32W
B3
D3
C3
5 OUT
USB_VBUS_DETECT 1 MF
01005 2
1%
1/32W ROOM=CHARGER
MF
01005
ROOM=CHARGER

R2303
100
18 BI
TIGRIS_TO_BATTERY_SWI R2301 TIGRIS_TO_BATTERY_SWI_1V8_R 1 2 TIGRIS_TO_BATTERY_SWI_1V8 17

1
0.00 2 1/32W
5%
1/32W
MF 0% 01005 MF
01005
NOSTUFF ROOM=CHARGER
3

G
Q2301
33 30 26 24 16 15 14 12 8 PP1V8_SDRAM 2 DMN2990UFA
A 1
S DFN0806
SYNC_MASTER=N/A SYNC_DATE=N/A A
R2302 PAGE TITLE
40.2K
1%
1/32W
1
SYSTEM POWER:CHARGER
MF DRAWING NUMBER SIZE
01005
2
Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
23 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 17 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C
BATTERY CONNECTOR
THIS ONE ON MLB ---> 516S00104 (RCPT)
516S00105 (PLUG)

PP_BATT_VCC 3 17 33
VOLTAGE=4.3V
CRITICAL
ROOM=BATTERY_B2B 1 C2414 1 C2413 1 C2410 1 C2411 1 C2412
J2400 5%
27PF
5%
56PF
5%
56PF
5%
100PF 220PF
10%
RCPT-BATT-2BLADES 2 16V 2 16V 2 16V 2 16V 2 10V
F-ST-SM NP0-C0G NP0-C0G NP0-C0G NP0-C0G X7R-CERM
01005 01005 01005 01005 01005
11 ROOM=BATTERY_B2B ROOM=BATTERY_B2B ROOM=BATTERY_B2B ROOM=BATTERY_B2B ROOM=BATTERY_B2B
7 8
FL2400
120-OHM-210MA 1 5
17 BI
TIGRIS_TO_BATTERY_SWI 1 2 TIGRIS_BATTERY_SWI_CONN 3 2 XW2400
SHORT-10L-0.25MM-SM
01005 4 6
ROOM=BATTERY_B2B 1 C2400 1 2 VBATT_SENSE OUT 17

56PF 9 10
ROOM=BATTERY_B2B
5%
2 16V
NP0-C0G 12
01005
ROOM=BATTERY_B2B

B B

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SYSTEM POWER:BATTERY CONN


DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
24 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 18 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
CARBON - ACCEL & GYRO
INVENSENSE (APN 338S00017): C3013=0.22UF
MAGNESIUM - COMPASS
INVENSENSE 1.1 (APN 338S00087): C3013=0.22UF ALPS (APN:338S00084)

PP1V8_IMU_OWL 12 14 19
PP1V8_IMU_OWL 12 14 19
NOSTUFF
1 C3002 1 C3001 1 C3000
1 C3010 1 C3011 1 C3012 56PF 0.1UF 2.2UF

C4
0.1UF 0.1UF 2.2UF 5% 20% 20%
20% 20% 20% 2 16V
NP0-C0G 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM VDD 01005 01005 0201
01005 01005 0201 ROOM=MAGNESIUM ROOM=MAGNESIUM ROOM=MAGNESIUM
ROOM=CARBON ROOM=CARBON ROOM=CARBON U3000
COMPASS-MODULE

16

1
C2 VPP FLGA-POP
VDD VDDIO NC SDO B4 SPI_IMU_TO_OWL_MISO OUT 9 19

U3010 NC
B1 RSV SDA/SDI A4 SPI_OWL_TO_IMU_MOSI IN 9 19

MPU-6700-12-COMBO B3 RSV
NC SCL/SCK A3 SPI_OWL_TO_IMU_SCLK 9 19
LGA D1 RSV
IN

9 SPI_OWL_TO_ACCEL_GYRO_CS_L 5 CS SCL/SPC 2 SPI_OWL_TO_IMU_SCLK 9 19 D2 RSV CSB A2 SPI_OWL_TO_COMPASS_CS_L 9


IN IN IN
114K INT PU
8 FSYNC/GND SDA/SDI 3 SPI_OWL_TO_IMU_MOSI 9 19
IN
19 14 12 PP1V8_IMU_OWL D4 RST* TRG/SE C3 NC
GYRO_CHARGE_PUMP 14 REGOUT/GND_CAP SA0/SDO 4 SPI_IMU_TO_OWL_MISO 9 19 1.09M INT PU 114K INT PD
OUT
DRDY A1 COMPASS_TO_OWL_INT OUT 9

9 ACCEL_GYRO_TO_OWL_INT2 7 INT/INT2 DRDY/INT1 6 ACCEL_GYRO_TO_OWL_INT1 9 OMIT_TABLE


OUT OUT
ROOM=MAGNESIUM

C ROOM=CARBON
OMIT_TABLE
CRITICAL
VSS C
1 C3013 CRITICAL

C1
0.22UF
9 GND1

10 GND2

11 GND3

12 GND4

13 GND5

15 GND6

20%
2 6.3V
X5R
01005-1
ROOM=CARBON

DISCRETE ACCEL
BOSCH (APN:338S1163)

PP1V8_IMU_OWL 12 14 19

B 1 C3020 1 C3021 1 C3022 B


0.1UF 1.0UF 0.1UF
20% 20% 20%
8

2 6.3V
X5R-CERM 2 6.3V
X5R 2 6.3V
X5R-CERM
01005 0201-1 VDD VDDIO 01005

U3020
OMIT_TABLE OMIT_TABLE OMIT_TABLE

BMA282
LGA
4 CS* OMIT_TABLE
SPI_OWL_TO_DISCRETE_ACCEL_CS_L SCX 1 SPI_OWL_TO_IMU_SCLK OMIT_TABLE
R3022
9 IN IN 9 19

SDX 2 SPI_OWL_TO_IMU_MOSI IN 9 19
20.0
OMIT_TABLE SDO 3 ACCEL_TO_OWL_SDO 1 2 SPI_IMU_TO_OWL_MISO
R3021 OUT 9 19

5%
ACCEL_TO_OWL_INT1_R 1
20.0 2
1/32W
MF
9 OUT
01005
OMIT_TABLE 5% ACCEL_TO_OWL_INT1 6 INT1 PS 13
R3020 1/32W
MF ACCEL_TO_OWL_INT2 5 INT2
ACCEL_TO_OWL_INT2_R 1
20.0 2
01005
9 OUT
GND GNDIO
5%
1/32W
9
11
12
14

10

MF
01005

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SENSORS:MOTION SENSORS
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
30 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 19 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

FOREHEAD CONNECTOR
FOREHEAD FLEX (FCAM) PROX & ALS POWER
THIS ONE ON MLB ---> 516S0986 (RCPT) J3100
AA22L-S034VA1
20 15 PP3V0_PROX_IRLED 516S0987 (PLUG)
F-ST-SM
1 C3120 1 C3121 1 C3122 1 C3123 1 C3124 39
35 36
100PF 0.1UF 2.2UF 2.2UF 2.2UF
5% 20% 20% 20% 20%
2 16V
NP0-C0G 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
01005 01005 0201 0201 0201
1 2 AP_TO_FCAM_CLK_CONN
CAMERA POWER ROOM=CG_B2B ROOM=CG_B2B ROOM=CG_B2B ROOM=CG_B2B ROOM=CG_B2B
20 I2C_ISP_TO_FCAM_SCL_CONN
AP_TO_FCAM_SHUTDOWN_CONN_L
3
5
4
6 90_MIPI_FCAM_TO_AP_CLK_CONN_N 20
20

D
20

D FL3100 I2C_ISP_BI_FCAM_SDA_CONN 7 8 90_MIPI_FCAM_TO_AP_CLK_CONN_P 20


FL3125
20
FERR-22-OHM-1A-0.055OHM 9 10
29 28 21 14 13 12 9 8 7 6 5 3 PP1V8 1 2 PP1V8_FCAM_CONN 20 15 PP3V0_PROX_ALS 2 1 PP3V0_PROX_CONN 20 20 PP3V0_PROX_CONN 11 12 90_MIPI_FCAM_TO_AP_DATA0_CONN_N 20
0201
120-OHM-210MA 45_PROX_TO_CUMULUS_RX_CONN 13 14 90_MIPI_FCAM_TO_AP_DATA0_CONN_P 20
C3101 C3100 C3125
20
ROOM=CG_B2B 1 1 01005 1 15 16
0.1UF 100PF ROOM=CG_B2B 100PF CUMULUS_TO_PROX_RX_EN_1V8_CONN 17 18 PP2V85_FCAM_AVDD_CONN
20% 5% 5% 28 20
2 6.3V
X5R-CERM 2
16V
NP0-C0G 2
16V
NP0-C0G 20 I2C2_AP_BI_ALS_SDA_CONN 19 20
01005 01005 01005
ROOM=CG_B2B ROOM=CG_B2B ROOM=CG_B2B 20 ALS_TO_AP_INT_CONN_L 21 22 PP1V8_FCAM_CONN 20
20 I2C2_AP_TO_ALS_SCL_CONN 23 24 FRONTMIC3_TO_CODEC_AIN4_CONN_P 20
PP3V0_ALS_CONN 25 26 FRONTMIC3_TO_CODEC_AIN4_CONN_N 20
FL3126 20

FL3104 1 2 PP3V0_ALS_CONN
20 CODEC_TO_HAC_CONN_N 27 28 PP_CODEC_TO_FRONTMIC3_BIAS_CONN 20
FERR-22-OHM-1A-0.055OHM 20
20 CODEC_TO_HAC_CONN_P 29 30

PP2V85_CAM_AVDD_LDO 1 2 PP2V85_FCAM_AVDD_CONN 120-OHM-210MA CODEC_TO_RCVR_CONN_P 31 32 PGND_IRLED_K 20


C3130 C3129 C3128 C3127 C3126
20
21 20
1 1 1 01005 1 1
0201 CODEC_TO_RCVR_CONN_N 33 34 PP3V0_PROX_IRLED 15
C3104
20 20
2.2UF 2.2UF 2.2UF ROOM=CG_B2B 0.1UF 100PF
C3106 1 ROOM=CG_B2B 1 C3105 1
100PF
20% 20% 20% 20% 5%
2.2UF 0.1UF 5%
6.3V
X5R-CERM 2
6.3V
X5R-CERM 2
6.3V
X5R-CERM 2 2 6.3V
X5R-CERM 2 16V
NP0-C0G
20% 20% 16V 0201 0201 0201 01005 01005 37 38
6.3V
X5R-CERM 2 2 6.3V
X5R-CERM 2 NP0-C0G ROOM=CG_B2B ROOM=CG_B2B ROOM=CG_B2B ROOM=CG_B2B ROOM=CG_B2B
40
0201 01005 01005
ROOM=CG_B2B ROOM=CG_B2B ROOM=CG_B2B

PGND_IRLED_K 20

MIC3/HAC/RCVR INTERFACE 1
R3101
C 1%
11.5
1/20W
C
MF
FL3150 2 201

CAMERA I/O 24 PP_CODEC_TO_FRONTMIC3_BIAS


120-OHM-210MA
1 2 PP_CODEC_TO_FRONTMIC3_BIAS_CONN 20
PROX & ALS INTERFACE PGND_IRLED_D
01005
ROOM=CG_B2B 1 DZ3150 3
FL3110 6.8V-100PF
01005 D
45_AP_TO_FCAM_CLK 1 2 AP_TO_FCAM_CLK_CONN 2 ROOM=CG_B2B CRITICAL
Q3140
7 IN 20

120-OHM-210MA 1 C3110 CUMULUS_TO_PROX_TX_EN_BUFF 1 G DMN3730UFB4


FL3151
29 IN
01005 100PF
ROOM=CG_B2B 5% S DFN1006H4-3
70-OHM-25%-0.28A
2 16V
NP0-C0G
01005 2 1
1
R3140 SYM_VER_1
ROOM=CG_B2B
ROOM=CG_B2B 23 IN
CODEC_TO_HAC_N CODEC_TO_HAC_CONN_N 20 1.00M
01005 5% 2
ROOM=CG_B2B NO_XNET_CONNECTION=1 1/32W

FL3111
1 DZ3151 MF
2 01005
12V-33PF
01005-1
ROOM=CG_B2B

AP_TO_FCAM_SHUTDOWN_L 1 2 AP_TO_FCAM_SHUTDOWN_CONN_L
7 IN 20
2 ROOM=CG_B2B
120-OHM-210MA 1 C3111
01005 100PF FL3152
ROOM=CG_B2B
2
5%
16V
NP0-C0G
70-OHM-25%-0.28A R3143
01005 CODEC_TO_HAC_P 2 1 CODEC_TO_HAC_CONN_P 45_PROX_TO_CUMULUS_RX 1
0.00 2 45_PROX_TO_CUMULUS_RX_CONN
23 IN 20 29 OUT 20
ROOM=CG_B2B
01005 NO_XNET_CONNECTION=1 0%
R3102
ROOM=CG_B2B
1 DZ3152 1/32W
MF
1 C3143
0.00 12V-33PF 01005 56PF
01005-1 ROOM=CG_B2B 5%
7 IN
I2C_ISP_TO_FCAM_SCL 1 2 1/32W I2C_ISP_TO_FCAM_SCL_CONN OUT 20
2 16V
MF 0% 01005 2 ROOM=CG_B2B NP0-C0G
ROOM=CG_B2B 01005
1 C3112 FL3101 ROOM=CG_B2B
NOSTUFF
120-OHM-210MA
B 5%
2 16V
56PF FL3153
70-OHM-25%-0.28A 8 I2C2_AP_SDA 1 2 I2C2_AP_BI_ALS_SDA_CONN 20
B
NP0-C0G BI
MAKE_BASE=TRUE
01005 1 2 01005
ROOM=CG_B2B 23 IN
CODEC_TO_RCVR_N
01005
CODEC_TO_RCVR_CONN_N 20 1 C3144
ROOM=CG_B2B NO_XNET_CONNECTION=1 56PF
R3103 1 DZ3153 5%
2 16V
NP0-C0G
I2C_ISP_BI_FCAM_SDA 1
0.00 2 1/32W I2C_ISP_BI_FCAM_SDA_CONN 12V-33PF 01005
7 BI
MF 0% 01005
BI 20 01005-1
2 ROOM=CG_B2B FL3102 ROOM=CG_B2B
ROOM=CG_B2B 120-OHM-210MA
1 C3113
56PF I2C2_AP_SCL 1 2 I2C2_AP_TO_ALS_SCL_CONN
FL3154
8 IN 20
5% MAKE_BASE=TRUE 01005
2 16V
NP0-C0G
01005
70-OHM-25%-0.28A 1 C3145
ROOM=CG_B2B 23 IN
CODEC_TO_RCVR_P 1 2 CODEC_TO_RCVR_CONN_P 20
56PF
5%
01005 NO_XNET_CONNECTION=1 2 16V
CAMERA MIPI ROOM=CG_B2B
1 DZ3154
12V-33PF
01005-1 FL3146
NP0-C0G
01005
ROOM=CG_B2B

CRITICAL
L3100
65-OHM-0.1A-0.7-2GHZ
2 ROOM=CG_B2B
8 OUT ALS_TO_AP_INT_L 2 1 ALS_TO_AP_INT_CONN_L 20

TAM0605 120-OHM-210MA
7 OUT
90_MIPI_FCAM_TO_AP_DATA0_P 4 SYM_VER-2 1 90_MIPI_FCAM_TO_AP_DATA0_CONN_P 20 FL3155 01005 1 C3146
120-OHM-210MA ROOM=CG_B2B 100PF
5%
FRONTMIC3_TO_CODEC_AIN4_N 1 2 FRONTMIC3_TO_CODEC_AIN4_CONN_N 2 16V
7 OUT
90_MIPI_FCAM_TO_AP_DATA0_N 3 2 90_MIPI_FCAM_TO_AP_DATA0_CONN_N 20
23 OUT 20 NP0-C0G
01005
ROOM=CG_B2B 01005 NO_XNET_CONNECTION=1 ROOM=CG_B2B
ROOM=CG_B2B
1 DZ3155
CRITICAL 6.8V-100PF
L3102
65-OHM-0.1A-0.7-2GHZ
01005
2 ROOM=CG_B2B
TAM0605
90_MIPI_FCAM_TO_AP_CLK_P 4 1 90_MIPI_FCAM_TO_AP_CLK_CONN_P
FL3156
SYM_VER-2
7 OUT 20

A 120-OHM-210MA
SYNC_MASTER=N/A SYNC_DATE=N/A A
7 90_MIPI_FCAM_TO_AP_CLK_N 3 2 90_MIPI_FCAM_TO_AP_CLK_CONN_N 20 23 FRONTMIC3_TO_CODEC_AIN4_P 2 1 FRONTMIC3_TO_CODEC_AIN4_CONN_P 20 PAGE TITLE
OUT OUT
ROOM=CG_B2B
01005
ROOM=CG_B2B 1
NO_XNET_CONNECTION=1
DZ3156 CAMERA:FOREHEAD FLEX B2B
6.8V-100PF
01005
DRAWING NUMBER SIZE

2 ROOM=CG_B2B
Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
31 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 20 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

REAR CAMERA FLEX RCAM CONNECTOR


THIS ONE ON MLB ---> 516S00100 (RCPT)
R3202 XW3202
SHORT-10L-0.1MM-SM
3.00 516S00101 (PLUG)
21 15 PP2V5_RCAM_AF 1 2 PP2V5_RCAM_AF_COMP 1 2
1% 1/32W CRITICAL
MF 01005 ROOM=RCAM_B2B ROOM=RCAM_B2B
J3200
D
AA27D-S030VA1
F-ST-SM D
32 31

21 PP2V5_RCAM_AF_CONN 2 1
4 3 90_MIPI_RCAM_TO_AP_DATA3_CONN_N BI 7

21 PP1V2_RCAM_DIGITAL_CONN 6 5 90_MIPI_RCAM_TO_AP_DATA3_CONN_P BI 7
8 7
10 9 90_MIPI_RCAM_TO_AP_DATA1_CONN_N BI 7
12 11 90_MIPI_RCAM_TO_AP_DATA1_CONN_P BI 7

CAMERA POWER 21

21
BI

IN
I2C_ISP_BI_RCAM_SDA_CONN
I2C_ISP_TO_RCAM_SCL_CONN
14
16
13
15 90_MIPI_RCAM_TO_AP_CLK_CONN_N BI 7

21 PP1V8_RCAM_CONN 18 17 90_MIPI_RCAM_TO_AP_CLK_CONN_P BI 7
20 19
AP_TO_RCAM_SHUTDOWN_CONN_L 22 21 90_MIPI_RCAM_TO_AP_DATA0_CONN_N
U3200 FL3200 21 IN
RCAM_TO_LED_DRIVER_STROBE_EN_CONN 24 23 90_MIPI_RCAM_TO_AP_DATA0_CONN_P
BI 7

LP5907SNX-2.85 10-OHM-1.1A 21 OUT BI 7

4 VIN
X2SON 1 2 PP2V85_RCAM_AVDD_CONN 21 IN
AP_TO_RCAM_CLK_CONN 26 25
25 24 22 17 15 14 PP_VCC_MAIN VOUT 1 20 PP2V85_CAM_AVDD_LDO 21
33 26
VOLTAGE=2.85V 01005
28 27 90_MIPI_RCAM_TO_AP_DATA2_CONN_N BI 7

1 C3210 3 EN
ROOM=RCAM_B2B 1 C3200 1 C3211 ROOM=RCAM_B2B 1 C3201 1 C3202 21 PP2V85_RCAM_AVDD_CONN 30 29 90_MIPI_RCAM_TO_AP_DATA2_CONN_P BI 7

GND EPAD 2.2UF 2.2UF 0.1UF 100PF


2.2UF 20% 20% 20% 5% 34 33
20% 2 6.3V 6.3V
2 X5R-CERM 2 6.3V 2 16V
2

2 6.3V X5R-CERM X5R-CERM NP0-C0G


X5R-CERM 0201 0201 01005 01005
0201 ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B

8 CAM_EXT_LDO_EN

C C
FL3201
FERR-22-OHM-1A-0.055OHM
14 PP1V2_CAMERA 1 2 PP1V2_RCAM_DIGITAL_CONN 21
0201
ROOM=RCAM_B2B
2
1 C3203 1 C3204 1 C3206 1 C3205
2.2UF 2.2UF 2.2UF 100PF
XW3203
SHORT-10L-0.1MM-SM
ROOM=RCAM_B2B
20%
2 6.3V
X5R-CERM
0201
20%
2 6.3V
X5R-CERM
0201
20%
2 6.3V
X5R-CERM
0201
5%
2 16V
NP0-C0G
01005
DIGITAL I/O
1 ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B

FL3230
14 45_BUCK6_FB 120-OHM-210MA
45_AP_TO_RCAM_CLK 1 2 AP_TO_RCAM_CLK_CONN
FL3220 7 IN
01005
21

FERR-22-OHM-1A-0.055OHM NOSTUFF
1 2
C3230 1 ROOM=RCAM_B2B
1 C3299
29 28 20 14 13 12 9 8 7 6 5 3 PP1V8 PP1V8_RCAM_CONN 21 100PF 100PF
0201 5% 5%
16V
ROOM=RCAM_B2B 1 C3220 1 C3221 NP0-C0G
01005
2 2
16V
NP0-C0G
01005
1.0UF 100PF ROOM=RCAM_B2B ROOM=RCAM_B2B
20% 5%
2 6.3V
X5R
0201-1
2 16V
NP0-C0G FL3231
ROOM=RCAM_B2B
01005 120-OHM-210MA
ROOM=RCAM_B2B
7 AP_TO_RCAM_SHUTDOWN_L 1 2 AP_TO_RCAM_SHUTDOWN_CONN_L 21
IN

L3205 01005
ROOM=RCAM_B2B 1 C3231
FERR-22-OHM-1A-0.055OHM
100PF
21 15 PP2V5_RCAM_AF 1 2 PP2V5_RCAM_AF_CONN 21
5%
0201 2 16V
NP0-C0G
ROOM=RCAM_B2B 1 C3207 1 C3208 1 C3209
01005
ROOM=RCAM_B2B

B 1.0UF
20%
1.0UF
20% 5%
100PF B
2 6.3V
X5R 2 6.3V
X5R 2 16V
0201-1
ROOM=RCAM_B2B
0201-1
ROOM=RCAM_B2B
NP0-C0G
01005 FL3232
ROOM=RCAM_B2B 120-OHM-210MA
22 RCAM_TO_LED_DRIVER_STROBE_EN 1 2 RCAM_TO_LED_DRIVER_STROBE_EN_CONN 21
OUT IN
01005
ROOM=RCAM_B2B 1 C3232
100PF
5%

MIPI COMMON-MODE CHOKES 2 16V


NP0-C0G
01005
ROOM=RCAM_B2B
L3200
65-OHM-0.1A-0.7-2GHZ
4
TAM0605
SYM_VER-2 1 R3203
I2C_ISP_BI_RCAM_SDA 1
0.00 2 1/32W I2C_ISP_BI_RCAM_SDA_CONN
22 7 BI BI 21
MF 0% 01005
ROOM=RCAM_B2B
3
ROOM=RCAM_B2B
2 1 C3233
NOSTUFF 56PF
5%
2 16V
L3201
65-OHM-0.1A-0.7-2GHZ
L3203
65-OHM-0.1A-0.7-2GHZ
NP0-C0G
01005
ROOM=RCAM_B2B
4
TAM0605
SYM_VER-2 1 4
TAM0605
SYM_VER-2 1 R3204
I2C_ISP_TO_RCAM_SCL 1
0.00 2 1/32W I2C_ISP_TO_RCAM_SCL_CONN
22 7 IN OUT 21
MF 0% 01005
ROOM=RCAM_B2B
3
ROOM=RCAM_B2B
2 3
ROOM=RCAM_B2B
2 1 C3234
NOSTUFF NOSTUFF 56PF
5%
L3202
65-OHM-0.1A-0.7-2GHZ
L3204
65-OHM-0.1A-0.7-2GHZ
2 16V
NP0-C0G
01005
TAM0605 TAM0605 ROOM=RCAM_B2B
A 4 1 4 1
A
SYM_VER-2 SYM_VER-2

SYNC_MASTER=N/A SYNC_DATE=N/A
PAGE TITLE
3
ROOM=RCAM_B2B
NOSTUFF
2 3
ROOM=RCAM_B2B
NOSTUFF
2
CAMERA:REAR CAMERA B2B
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
PLACEHOLDER FOOTPRINTS NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH

PROPRIETARY PROPERTY OF APPLE INC.


THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
32 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 21 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

DUAL LED STROBE DRIVER


C APN:353S3899 C
PP_LED_BOOST_OUT
VOLTAGE=5.0V
33 26 25 24 21 17 15 14 PP_VCC_MAIN U3300 1 C3394 1 C3396
LM3564A1TMX 10UF 10UF
C3384 1 C3385 1 C3386 1 C3387 1 CRITICAL WLCSP 20%
2 6.3V
20%
2 6.3V
2.2UF
20%
2.2UF
20%
2.2UF
20%
10UF
20% L3300 D1 IN
ROOM=STROBE
CRITICAL
A3 CERM-X5R
0402-9
CERM-X5R
0402-9
6.3V 2 6.3V 2 6.3V 2 6.3V 2 1.0UH-20%-3.6A-0.060OHM B3 ROOM=STROBE ROOM=STROBE
X5R-CERM X5R-CERM X5R-CERM CERM-X5R OUT
0201 0201 0201 0402-9 1 2 PP_LED_DRIVER_SW A2 C3
ROOM=STROBE ROOM=STROBE ROOM=STROBE ROOM=STROBE
PIQA20161T-SM VOLTAGE=5.0V B2 SW
ROOM=STROBE
A4 PP_LED_DRIVER_COOL_LED 32
D3 INT 200K PD LED1 B4 VOLTAGE=5.0V
8 IN
AP_TO_LED_DRIVER_EN ENABLE
INT 200K PD
21 RCAM_TO_LED_DRIVER_STROBE_EN E3 STROBE
IN
INT 200K PD
C2 TORCH C4 PP_LED_DRIVER_WARM_LED
NC 32

BB_TO_LED_DRIVER_GSM_BURST_IND E4 INT 200K PD


TX LED2 D4 VOLTAGE=5.0V
C3308 C3373
33 26 IN
E2 1 1
21 7 BI
I2C_ISP_BI_RCAM_SDA SDA
D2 100PF 100PF
21 7 IN
I2C_ISP_TO_RCAM_SCL SCL TEMP E1 5% 5%
GND 2 16V
NP0-C0G 2 16V
NP0-C0G
AGND 01005 01005
ROOM=STROBE ROOM=STROBE

A1
B1

C1
LED_MODULE_NTC OUT 32

B B

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

CAMERA:STROBE DRIVER
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
33 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 22 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CALTRA AUDIO CODEC (ANALOG INPUTS & OUTPUTS)

D D

U3500
WLCSP-1
31 LOWERMIC1_TO_CODEC_AIN1_P L2 AIN1+ SYM 1 OF 3 AOUT1+ L9 CODEC_TO_RCVR_P 20
VOICE MIC LOWERMIC1_TO_CODEC_AIN1_N L1 AIN1- AOUT1- M9 CODEC_TO_RCVR_N

CS42L71
31 20

AOUT2+ L8 CODEC_TO_HAC_P 20

AOUT2- M8 CODEC_TO_HAC_N 20

HPOUTA K10 CODEC_TO_HPHONE_L 31

NC
K3 AIN2+ ROOM=CODEC HPOUTB K11 CODEC_TO_HPHONE_R 31
L3 AIN2-
NC CRITICAL HS3 M5 CODEC_TO_HPHONE_HS3 31

HS4 M4 CODEC_TO_HPHONE_HS4
C 31
C
HS3_REF L10 CODEC_TO_HPHONE_HS3_REF 31

K2 HS4_REF M10 CODEC_TO_HPHONE_HS4_REF 31


REARMIC2_TO_CODEC_AIN3_P AIN3+
C3505
32
ANC REF MIC ROOM=CODEC
32 REARMIC2_TO_CODEC_AIN3_N K1 AIN3-
0.1UF R3515
1 2 CODEC_HSIN_R_P 1
1.33K 2
20% 01005
6.3V ROOM=CODEC 1%
HSIN+ D1 CODEC_HSIN_P X5R-CERM
ROOM=CODEC 1 C3504 1/32W
MF
01005
HSIN- E1 CODEC_HSIN_N 220PF NO_XNET_CONNECTION=1

ANC ERROR MIC


20 FRONTMIC3_TO_CODEC_AIN4_P J3
J4
AIN4+ C3506 10%
2 10V R3550
20 FRONTMIC3_TO_CODEC_AIN4_N AIN4- 0.1UF X7R-CERM
01005
1 2 1
1.33K 2
20%
6.3V
01005 CODEC_HSIN_R_N 1%
X5R-CERM 1/32W
MF
HPDETECT J9
ROOM=CODEC
01005
ROOM=CODEC
F1 AIN5+ HPHONE_TO_CODEC_DETECT NO_XNET_CONNECTION=1
NC 31
G1 AIN5-
NC

F2 AIN6+ ROOM=CODEC
NC
NC
F3 AIN6- C3552
100PF
1 2

5%
16V
R3502 NP0-C0G
B NC
G2 AIN7+
1
20.0 2
01005
B
G3 AIN7-
NC 5%
1/32W
MF
A4 DMIC1_CLK DP J12 90_MIKEYBUS_CALTRA_DATA_P 01005 90_MIKEYBUS_DATA_P
NC ROOM=CODEC
30
B4 DMIC1_DATA DN H12 90_MIKEYBUS_CALTRA_DATA_N 90_MIKEYBUS_DATA_N
NC 30

NC
C4 DMIC2_CLK XW3500 R3503
C3 MBUS_REF G10 MBUS_REF_U3500 1 2 20.0
DMIC2_DATA 1 2
NC SHORT-10L-0.1MM-SM
ROOM=CODEC 5%
A3 DMIC3_CLK 1/32W
NC
NC
B3 DMIC3_DATA
MF
01005 C3554
ROOM=CODEC 100PF
A2 DMIC4_CLK 1 2
NC
B2 DMIC4_DATA
NC 5%
16V
NP0-C0G
A9 PDM_CLK 01005
NC ROOM=CODEC
B9 PDM_DATA
NC

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

AUDIO:CALTRA CODEC (1/2)


DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
35 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 23 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CALTRA AUDIO CODEC (POWER & I/O)


25 15 PP1V8_VA
1 C3640
D 2.2UF
20%
D
2 6.3V
X5R-CERM
0201
ROOM=CODEC

CODEC_AGND 24

33 26 25 22 21 17 15 14 PP_VCC_MAIN
1 C3600 1 C3601 1 C3602
10UF 0.1UF 0.1UF
20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0402-9 01005 01005
ROOM=CODEC ROOM=CODEC ROOM=CODEC

33 30 26 24 17 16 15 14 12 8 PP1V8_SDRAM 33 30 26 24 17 16 15 14 12 8 PP1V8_SDRAM
1 C3610 1 C3611 1 C3612 1
R3650
10UF 0.1UF 0.1UF 1.00K
20% 20% 20% 5%
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 1/32W
MF
0402-9 01005 01005 2 01005
ROOM=CODEC ROOM=CODEC ROOM=CODEC PP1V2_VD_FILT ROOM=CODEC

CODEC_RESET_L H3 RESET* JTAG_TMS D3


NC
1 C3670 JTAG_TCK D4
NC
1.0UF D2
20% U3500 JTAG_TDI

VD G12
NC

VD D12

VPROG_CP H11

VP_MBUS H10
VD_FILT E12
VCP J11
2 6.3V

VP M7
VD_FILT C1

VL A5
C2

VA J1
X5R
K8 JTAG_TDO NC
0201-1 16 CODEC_TO_PMU_MIKEY_INT_L WAKE* WLCSP-1
ROOM=CODEC SYM 3 OF 3
CODEC_TO_AP_PMU_INT_L K9 INT* TSTO D11
16 8
NC

CS42L71
TSTO B10
NC
SPI_AP_TO_CODEC_CS_L C9 CS* TSTO D5
C3650 8
NC
C
C 4.7UF 31 PP_CODEC_TO_LOWERMIC1_BIAS M6 MIC1_BIAS
U3500 FLYP K12 CALTRA_FLYP 8 SPI_AP_TO_CODEC_SCLK C8 CCLK TSTO D6
E5
NC
31 LOWERMIC1_BIAS_FILT_RET 1 2 LOWERMIC1_BIAS_FILT_IN K7 MIC1_BIAS_FILT TSTO NC
WLCSP-1 SPI_AP_TO_CODEC_MOSI B8 MOSI CRITICAL TSTO E6
20% SYM 2 OF 3
8
ROOM=CODEC NC
E7
6.3V 1 C3660 8 SPI_CODEC_TO_AP_MISO A8 MISO TSTO NC

CS42L71
X5R-CERM1 K4
402 2.2UF TSTO NC
ROOM=CODEC 20%
45_I2S_AP_TO_CODEC_MCLK C12 MCLK
2 6.3V
X5R-CERM
8

L6 0201 TSTI C10


NC MIC2_BIAS ROOM=CODEC
45_I2S_AP_TO_CODEC_ASP_BCLK C6 ASP_SCLK TSTI D10
NC
J7 MIC2_BIAS_FILT FLYC L12 CALTRA_FLYC 25 8

25 8 I2S_AP_TO_CODEC_ASP_LRCLK C5 ASP_LRCK/FSYNC TSTI D7


CRITICAL 25 8 I2S_AP_TO_CODEC_ASP_DOUT B5 ASP_SDIN TSTI D9
ROOM=CODEC B6 E8
25 8 I2S_CODEC_TO_AP_ASP_DIN ASP_SDOUT TSTI
ROOM=CODEC E9
XW3620 C3651 1 C3661 B11
TSTI
G11
SHORT-10L-0.1MM-SM 4.7UF 32 PP_CODEC_TO_REARMIC2_BIAS K6 MIC3_BIAS 2.2UF 9 8 45_I2S_AP_OWL_TO_CODEC_XSP_BCLK XSP_SCLK TSTI
20% H4
1 2 REARMIC2_BIAS_FILT_RET 1 2 REARMIC2_BIAS_FILT_IN L5 I2S_AP_OWL_TO_CODEC_XSP_LRCLK C11 XSP_LRCK/FSYNC TSTI
MIC3_BIAS_FILT 2 6.3V
X5R-CERM
9 8

0201 8 I2S_AP_TO_CODEC_XSP_DOUT A11 XSP_SDIN/DAC2B_MUTE TSTI M1


ROOM=CODEC 20% ROOM=CODEC
I2S_CODEC_TO_AP_OWL_XSP_DIN A10 XSP_SDOUT
6.3V
X5R-CERM1 FLYN M12 CALTRA_FLYN 9 8

402
45_I2S_AP_TO_CODEC_MSP_BCLK B7 MSP_SCLK GND A1
XW3630 C3653 J6 +VCP_FILT J10 CALTRA_VCP_FILTP
8

I2S_AP_TO_CODEC_MSP_LRCLK C7 MSP_LRCK/FSYNC GND A12


SHORT-10L-0.1MM-SM 4.7UF 20 PP_CODEC_TO_FRONTMIC3_BIAS MIC4_BIAS 8

1 2 K5 I2S_AP_TO_CODEC_MSP_DOUT D8 MSP_SDIN GND B12


1 2 FRONTMIC3_BIAS_FILT_RET FRONTMIC3_BIAS_FILT_IN MIC4_BIAS_FILT 8

ROOM=CODEC 20%
1 C3662 8 I2S_CODEC_TO_AP_MSP_DIN A7 MSP_SDOUT GND E2
E3
6.3V 4.7UF PMU_TO_CODEC_DIGLDO_PULLDN H5 GND
X5R-CERM1 20% 16 DIGLDO_PULLDN E4
402 2 6.3V J5 GND
ROOM=CODEC X5R-CERM1 DIGLDO_PDN
XW3660
SM
402
ROOM=CODEC
GND E10
F4
GND
GNDCP L11 CALTRA_GNDCP 1 2 F5
GND

B
ROOM=CODEC
B GND
GND
F6
F7
GND F8
1 C3663 GND F9
4.7UF
20% GND F10
2 6.3V
X5R-CERM1 G4
402 GND
ROOM=CODEC GND G5
-VCP_FILT M11 CALTRA_VCP_FILTN GND G6
G7
LP_FILT+ F12 CALTRA_LP_FILTP GND
GND G8
GND G9
1 C3665 GND H6
0.1UF H7
20% GND
6.3V
2 X5R-CERM GND H8
01005
CALTRA_HS_BIAS_FILT M3 ROOM=CODEC GND H9
HS_BIAS_FILT
M2 HS_BIAS_FILT_REF FILT+ H1 CALTRA_FILTP
1 C3654 GND J8
4.7UF
20%
2 6.3V
1 C3664
X5R-CERM1
402
10UF
20%
ROOM=CODEC 2 6.3V
CERM-X5R
0402-9
CALTRA_HS_BIAS_FILT_IN ROOM=CODEC
L4 GNDHS
GNDD
GNDD
GNDD
GNDD

L7 GNDP

J2 GNDA

FILT- H2
A6
B1
E11
F11

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

AUDIO:CALTRA CODEC (2/2)


XW3600 DRAWING NUMBER SIZE
SHORT-10L-0.1MM-SM
1 2 Apple Inc.
051-00648 D
24 CODEC_AGND REVISION
ROOM=CODEC R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
36 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 24 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

SPEAKER AMPLIFIER
APN: 338S1285

33 26 24 22 21 17 15 14 PP_VCC_MAIN PP1V8_VA 15 24

1 C3709 1 C3730
0.1UF 2.2UF
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
01005 0201
ROOM=SPKR_AMP ROOM=SPKR_AMP

VOLTAGE=8.0V
PP_SPKR_VBOOST
1 C3741 1 C3742 1 C3745 1 C3746
10UF 22UF 0.1UF 100PF
20% 20% 10% 5%
10V
2 X5R-CERM 2 10V 16V
2 X5R-CERM 2 16V

A1
B1
C1
D1

F5
A4
A5
X5R-CERM NP0-C0G
0402-8 0603-1 0201 01005
C ROOM=SPKR_AMP ROOM=SPKR_AMP ROOM=SPKR_AMP
VBST VP
VA C
CRITICAL
1 C3729 1 C3740
L3700 2.2UF 4.7UF
1.2UH-20%-3.0A-0.080OHM U3700 20%
2 6.3V
X5R-CERM
20%
2 6.3V
CER-X5R
CS35L21-XWZR 0201 0402
A2
1 2 PP_SPEAKERAMP_SW WLCSP FILT+ F2 SPEAKERAMP_FILT ROOM=SPKR_AMP ROOM=SPKR_AMP
VOLTAGE=8.0V B2 SW
PIQA20161T-SM
ROOM=SPKR_AMP
VER1 LDO_FILT C5 SPEAKERAMP_LDO_FILT
ROOM=SPKR_AMP
I2C1_AP_SDA D5
SDA CRITICAL
VSENSE- E3
30 17 8 BI
VSENSE_NEG
D6
30 17 8 IN
I2C1_AP_SCL SCL VSENSE+ E2 VSENSE_POS
A7
8 OUT SPEAKERAMP_TO_AP_INT_L INT* ISENSE- F1 NC
A6 ISENSE+ E1 NC
8 IN
AP_TO_SPEAKERAMP_RESET_L RESET*
OUT+ D2
1
R3729 D7 ALIVE
OUT- C2
XW3703
SHORT-10L-0.1MM-SM
100K C7 ADO 1 2
5%
1/32W 1M INT PD IREF+ B7 SPEAKERAMP_IREF
2
MF
01005 8 IN
45_I2S_AP_TO_SPEAKERAMP_MCLK E7
MCLK XW3704
1
R3735 SHORT-10L-0.1MM-SM
1M INT PD
ROOM=SPKR_AMP
45_I2S_AP_TO_CODEC_ASP_BCLK E6 1 2
24 8 IN SCLK
1M INT PD 44.2K
F6 1%
24 8 IN
I2S_AP_TO_CODEC_ASP_LRCLK LRCK/FSYNC 1/32W
1M INT PD MF
F7 2 01005
24 8 IN
I2S_AP_TO_CODEC_ASP_DOUT SDIN ROOM=SPKR_AMP
1M INT PD

I2S_CODEC_TO_AP_ASP_DIN E5
24 8 OUT SDOUT
1M INT PD

A3 GNDP GNDA
B3
B4

B5
B6
C3
C4
D3
D4

C6
E4
F3
F4
B SPEAKERAMP_TO_SPEAKER_OUT_POS 31
B

SPEAKERAMP_TO_SPEAKER_OUT_NEG 31

C3760 1 1 C3763 C3700 1 1 C3702


1000PF 1000PF 1000PF 1000PF
10% 10% 10% 10%
10V 10V 10V 2 2 10V
X5R 2 2 X5R X5R X5R
01005 01005 01005 01005
ROOM=SPKR_AMP ROOM=SPKR_AMP ROOM=SPKR_AMP ROOM=SPKR_AMP

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

AUDIO:SPEAKER DRIVER
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
37 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 25 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

DISPLAY & TOUCH - POWER SUPPLIES

D D

CHESTNUT DISPLAY PMU


APN:338S1172
33 26 25 24 22 21 17 15 14 PP_VCC_MAIN
1 C4000 1
CRITICAL 10UF
20%
L4000 VOLTAGE=6.3V 2
CERM-X5R U4000 PP_CHESTNUT_CP
VOLTAGE=6.0V
1.0UH-20%-2.25A-0.15OHM 0402-9
PIXB2016FE-SM ROOM=CHESTNUT TPS65730A0PYFF
BGA CF1 C4
1 C4002
ROOM=CHESTNUT 10UF
D1 VIN ROOM=CHESTNUT CF2 E4 20%
2 CRITICAL VOLTAGE=-6.0V 2 VOLTAGE=10V
X5R-CERM
PP_CHESTNUT_SW B2 SW PN_CHESTNUT_CN 0402-8
ROOM=CHESTNUT
VOLTAGE=6.3V
A2 SYNC LCMBST B3 PP6V0_LCM_BOOST
CPUMP B4
NO INT PULL
VOLTAGE=6.0V
26 16 8 I2C0_AP_SCL D3 SCL
IN

26 16 8 I2C0_AP_SDA D2 SDA VNEG E3 PN5V7_SAGE_AVDDN 28 29


BI
VOLTAGE=-5.7V
28 16 LCM_TO_CHESTNUT_PWR_EN C3 LCM_EN VNEG(SUB) E2
IN
200K INT PD

30 16 9 5 PMU_TO_OWL_ACTIVE_READY C2 RESET* HVLDO1 A4 VOLTAGE=5.7V PP5V7_SAGE_AVDDH 29


IN
NO INT PULL

16 CHESTNUT_TO_PMU_ADCMUX E1 ADCMUX HVLDO2 A3 VOLTAGE=5.7V PP5V7_LCM_AVDDH 28


OUT

B1 PGND1
D4 PGND2
C C

C1 AGND
HVLDO3 A1 VOLTAGE=5.1V PP5V1_GRAPE_VDDH 29

1 C4003 1 C4004 1 C4005 1 C4006 1 C4007


1UF 10UF 10UF 10UF 22UF
20% 20% 20% 20% 20%
2 VOLTAGE=16V
CER-X5R 2 VOLTAGE=10V
X5R-CERM 2 VOLTAGE=10V
X5R-CERM
VOLTAGE=10V
2 X5R-CERM 2 VOLTAGE=10V
X5R-CERM
0201 0402-8 0402-8 0402-8 0603-1
ROOM=CHESTNUT ROOM=CHESTNUT ROOM=CHESTNUT ROOM=CHESTNUT ROOM=CHESTNUT

LED BACKLIGHT DRIVER


APN:353S00640
MOJAVE MESA BOOST
APN:353S4207 (A1)
CRITICAL
L4021 CRITICAL
D4021 CRITICAL U4040
B 1.0UH-20%-3.6A-0.060OHM
PP_BL_SW2
DSN2 L4040 LM3638A1 PP11V3_MESA
B
33 26 25 24 22 21 17 15 14 PP_VCC_MAIN 1 2 A K 1.0UH-20%-0.4A-0.636OHM BGA
3 27
VOLTAGE=11.5V
C4020 1 C4021 1
PIQA20161T-SM
ROOM=BACKLIGHT
VOLTAGE=25V
NSR05F30NXT5G 33 26 25 24 22 21 17 15 14 PP_VCC_MAIN 1 2 PP13V0_MESA_SW B1 SW ROOM=MOJAVE
CRITICAL
1 C4042 1 C4043
ROOM=BACKLIGHT
0403 VOLTAGE=18.0V 56PF 2.2UF
10UF 10UF A2 VIN VOUT C3
20% 20% CRITICAL CRITICAL C4040 1 ROOM=MOJAVE 5%
2 VOLTAGE=25V
20%
VOLTAGE=6.3V 2
CERM-X5R
VOLTAGE=6.3V 2
CERM-X5R L4020 D4020 10UF B2 EN_M
NP0-C0G
0201
2 VOLTAGE=25V
X5R-CERM
0402-9 0402-9 15UH-20%-0.72A-0.9OHM NSR0530P2T5G
20%
VOLTAGE=6.3V 2 ROOM=MOJAVE
0402-1
ROOM=MOJAVE
ROOM=BACKLIGHT ROOM=BACKLIGHT CERM-X5R A3 EN_S
1 2 PP_BL_SW1 A K 0402-9
ROOM=MOJAVE C2 LDOIN
PITA32251T-SM VOLTAGE=25V PP12V0_MOJAVE_LDOIN PMID C1

A1 PGND

B3 AGND
ROOM=BACKLIGHT SOD-923-1 VOLTAGE=12.0V
ROOM=BACKLIGHT
ROOM=BACKLIGHT
1 C4041
U4020 20%
2.2UF
LM3539A1 VOLTAGE=35V
PP3V0_TRISTAR
D4 IN 33 31 30 15 2 VOLTAGE=25V
OUT A1 PP_LCM_BL_ANODE
DSBGA IN X5R-CERM
28 0402-1
CRITICAL MESA_TO_BOOST_EN ROOM=MOJAVE
D3 VIO/HWEN
C4022 C4023
27 3
PP1V8_SDRAM SW1 C4
IN
33 30 24 17 16 15 14 12 8 1 1

C2 SDI 100PF 10UF


16 9 IN
45_DWI_PMGR_TO_PMU_BACKLIGHT_MOSI SW2_1 A3 5% 20%
9 45_DWI_PMGR_TO_BACKLIGHT_SCLK C3 SCK SW2_2 A4 2 VOLTAGE=35V
NP0-C0G 2 VOLTAGE=35V
X5R-CERM
IN
VOLTAGE=21V 01005 0603
1 ROOM=BACKLIGHT ROOM=BACKLIGHT
R4020 B2 SDA
A2 SCL
LED1 C1 PP_LCM_BL_CAT1 28

200K LED2 B1 PP_LCM_BL_CAT2 28


1% VOLTAGE=21V
1/32W D1 TRIG
MF
01005
2 ROOM=BACKLIGHT
D2 INHIBIT
B3 GND
B4 GND

26 16 8 BI
I2C0_AP_SDA
A 26 16 8 IN
I2C0_AP_SCL
AP_TO_MUON_BL_STROBE_EN SYNC_MASTER=N/A SYNC_DATE=N/A A
7 IN PAGE TITLE

33 22 IN
BB_TO_LED_DRIVER_GSM_BURST_IND DISPLAY:POWER
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
40 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 26 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MESA POWER AND IO FILTERS

D D

MESA POWER
FL4100
80-OHM-25%-1000MA
15 PP3V1_MESA 1 2 PP3V1_MESA_CONN 31
0201
1 C4104 1 C4103 1 C4102 ROOM=MAMBA_MESA 1 C4101 1 C4100
2.2UF 2.2UF 2.2UF 0.1UF 100PF
20% 20% 20% 20% 5%
2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 16V
NP0-C0G
0201 0201 0201 01005 01005
ROOM=MAMBA_MESA ROOM=MAMBA_MESA ROOM=MAMBA_MESA ROOM=MAMBA_MESA ROOM=MAMBA_MESA

FL4105
70-OHM-25%-0.28A
15 PP1V9_MESA 1 2 PP1V9_MESA_CONN 31
01005
1 C4106 ROOM=MAMBA_MESA 1 C4105
2.2UF 100PF
20% 5%
2 6.3V
X5R-CERM 2 16V
0201 NP0-C0G
ROOM=MAMBA_MESA
01005
ROOM=MAMBA_MESA
FL4107
70-OHM-25%-0.28A
C 26 3 PP11V3_MESA 1 2 PP11V3_MESA_CONN 31
C
01005
ROOM=MAMBA_MESA 1 C4107
100PF
5%
2 35V
NP0-C0G
01005
ROOM=MAMBA_MESA

MESA DIGITAL I/O


FL4110
120-OHM-210MA
8 IN
SPI_AP_TO_MESA_MOSI 1 2 SPI_AP_TO_MESA_MOSI_CONN 31
01005
ROOM=MAMBA_MESA 1 C4110
56PF
5%
2 16V
NP0-C0G
01005
ROOM=MAMBA_MESA

R4111
SPI_AP_TO_MESA_SCLK 1
0.00 2 SPI_AP_TO_MESA_SCLK_CONN
8 IN 31

0%
B 1/32W
MF
01005
1 C4111
56PF
B
ROOM=MAMBA_MESA 5%
2 16V
NP0-C0G
FL4112 01005
ROOM=MAMBA_MESA
120-OHM-210MA
8 OUT
SPI_MESA_TO_AP_MISO 1 2 SPI_MESA_TO_AP_MISO_CONN 31
01005
ROOM=MAMBA_MESA 1 C4112
56PF
5%
2 16V
NP0-C0G
01005
FL4114 ROOM=MAMBA_MESA

120-OHM-210MA
8 OUT
MESA_TO_AP_INT 1 2 MESA_TO_AP_INT_CONN 31
01005
ROOM=MAMBA_MESA 1 C4115
100PF
5%
2 16V
NP0-C0G
01005
ROOM=MAMBA_MESA

R4116
MESA_TO_BOOST_EN 1
681 2 MESA_TO_BOOST_EN_CONN
26 3 OUT 31

1%
1/32W
MF
1 C4116
01005
ROOM=MAMBA_MESA 56PF
5%
2 16V
NP0-C0G
01005

A FL4143
120-OHM-210MA
ROOM=MAMBA_MESA
SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
BUTTON_MENU_KEY_L 1 2 BUTTON_MENU_KEY_CONN_L
8 OUT
01005 NOSTUFF
31
MESA POWER AND IO FILTERS
1 C4117 ROOM=MAMBA_MESA 1 DZ4101 DRAWING NUMBER SIZE

5%
56PF 12V-33PF
01005-1 Apple Inc.
051-00648 D
2 16V
NP0-C0G 2 REVISION
01005
ROOM=MAMBA_MESA
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
41 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 27 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

DISPLAY CONNECTOR
DISPLAY FLEX THIS ONE ON MLB ---> 516S1051 (RCPT)
516S1050 (PLUG)

DISPLAY POWER FL4200


240OHM-350MA
26 PP5V7_LCM_AVDDH 2 1 PP5V7_LCM_AVDDH_CONN 28
CRITICAL
0201 ROOM=LCM_B2B
C4200 1 C4201 1 C4202 1 ROOM=LCM_B2B 1 C4203 1 C4204 J4200
2.2UF 2.2UF 2.2UF 2.2UF 100PF
D
20%
6.3V
X5R-CERM 2
20%
6.3V
X5R-CERM 2
20%
6.3V
X5R-CERM 2
20%
2 6.3V
X5R-CERM 2
5%
16V
NP0-C0G
BM15AP-0.8-22DP-0.35V
24
M-ST-SM D
0201 0201 0201 0201 01005
ROOM=LCM_B2B ROOM=LCM_B2B ROOM=LCM_B2B ROOM=LCM_B2B ROOM=LCM_B2B 23

FL4205 29 PN_SAGE_TO_TOUCH_VCPL 2 1 PN5V7_SAGE_AVDDN_CONN 28

240OHM-350MA 4 3 PP5V7_LCM_AVDDH_CONN 28

29 21
9 8 7 6 5 3 PP1V8 2 1 PP1V8_LCM_CONN 28
28 90_MIPI_AP_TO_LCM_DATA0_CONN_P 6 5 PP1V8_LCM_CONN 28

90_MIPI_AP_TO_LCM_DATA0_CONN_N 8 7 LCM_TO_CHESTNUT_PWR_EN_CONN
DISPLAY CONTROL SIGNALS
20 14 13 12

ROOM=LCM_B2B
0201
1 C4205 1 C4206 28
10 9 AP_TO_LCM_RESET_CONN_L
28

2.2UF 100PF 28

20% 5%
16V 28 90_MIPI_AP_TO_LCM_DATA1_CONN_P 12 11 LCM_TO_AP_HIFA_BSYNC_CONN 28
6.3V 2 NP0-C0G
2 X5R-CERM
01005 28 90_MIPI_AP_TO_LCM_DATA1_CONN_N 14 13 PMU_TO_LCM_PANIC_CONN 28
0201
ROOM=LCM_B2B ROOM=LCM_B2B 16 15 LCD_TO_AP_PIFA_CONN
FL4207
3 28

28 3 OUT
LCD_TO_AP_PIFA_CONN 28 90_MIPI_AP_TO_LCM_CLK_CONN_P 18 17 PP_LCM_BL_ANODE_CONN 3 28
70-OHM-25%-0.28A
90_MIPI_AP_TO_LCM_CLK_CONN_N 20 19 PP_LCM_BL_CAT1_CONN
29 26 PN5V7_SAGE_AVDDN 2 1 PN5V7_SAGE_AVDDN_CONN 28
1 C4208 28
22 21 PP_LCM_BL_CAT2_CONN
3 28

56PF 3 28
01005
ROOM=LCM_B2B 1 C4207 5%
2 16V
100PF NP0-C0G
01005
25
5%
16V ROOM=LCM_B2B 26
2 NP0-C0G
01005
ROOM=LCM_B2B

BACKLIGHT FL4211 FL4220


240OHM-350MA 120-OHM-210MA
LCM_TO_CHESTNUT_PWR_EN 2 1 LCM_TO_CHESTNUT_PWR_EN_CONN
26 PP_LCM_BL_ANODE 1 2 PP_LCM_BL_ANODE_CONN 3 28
26 16 OUT 28
01005
0201
ROOM=LCM_B2B 1 C4211 ROOM=LCM_B2B 1 C4220
100PF 100PF
5% 5%
C 35V
2 NP0-C0G
01005
2 16V
NP0-C0G
01005
C
ROOM=LCM_B2B ROOM=LCM_B2B

FL4221
FL4212 120-OHM-210MA
240OHM-350MA 2 1
8 IN
AP_TO_LCM_RESET_L AP_TO_LCM_RESET_CONN_L 28
PP_LCM_BL_CAT1 1 2 PP_LCM_BL_CAT1_CONN 01005
C4221
26 3 28
0201
1 C4212 R4220 1 ROOM=LCM_B2B 1
100PF
ROOM=LCM_B2B 100K 5%
100PF 1%
5% 1/32W 2 16V
NP0-C0G
2 35V
NP0-C0G
MF
01005 01005
01005 ROOM=LCM_B2B 2 ROOM=LCM_B2B
ROOM=LCM_B2B
FL4222
120-OHM-210MA
FL4213 2 1
240OHM-350MA 16 IN
PMU_TO_LCM_PANICB PMU_TO_LCM_PANIC_CONN 28
01005
26 PP_LCM_BL_CAT2 1 2 PP_LCM_BL_CAT2_CONN 3 28
ROOM=LCM_B2B 1 C4222
0201 100PF
ROOM=LCM_B2B 1 C4213 5%
100PF 2 16V
NP0-C0G
5% 01005
2 35V
NP0-C0G ROOM=LCM_B2B
01005
DISPLAY MIPI ROOM=LCM_B2B

CRITICAL
L4200
65-OHM-0.1A-0.7-2GHZ
OWL TO TOUCH INTERFACE
TAM0605
7 IN
90_MIPI_AP_TO_LCM_CLK_P 4 SYM_VER-2 1 90_MIPI_AP_TO_LCM_CLK_CONN_P 28 FL4230
120-OHM-210MA
LCM_TO_AP_HIFA_BSYNC 2 1 LCM_TO_AP_HIFA_BSYNC_CONN
7 IN
90_MIPI_AP_TO_LCM_CLK_N 3 2 90_MIPI_AP_TO_LCM_CLK_CONN_N 28
33 29 9 8 OUT 28

B ROOM=LCM_B2B

CRITICAL
01005
ROOM=LCM_B2B 1 C4230 B
56PF
L4201 5%
65-OHM-0.1A-0.7-2GHZ 2 16V
NP0-C0G
TAM0605 01005
7 IN
90_MIPI_AP_TO_LCM_DATA0_P 4 SYM_VER-2 1 90_MIPI_AP_TO_LCM_DATA0_CONN_P 28 ROOM=LCM_B2B

7 IN
90_MIPI_AP_TO_LCM_DATA0_N 3
ROOM=LCM_B2B
2 90_MIPI_AP_TO_LCM_DATA0_CONN_N 28
PROX TO TOUCH INTERFACE
CRITICAL FL4241
L4202
65-OHM-0.1A-0.7-2GHZ 29 CUMULUS_TO_PROX_RX_EN_1V8 1 2 CUMULUS_TO_PROX_RX_EN_1V8_CONN 20
TAM0605 OUT
90_MIPI_AP_TO_LCM_DATA1_P 4 1 90_MIPI_AP_TO_LCM_DATA1_CONN_P
C4241
SYM_VER-2
7 IN 28 120-OHM-210MA 1
01005
ROOM=LCM_B2B 100PF
5%
7 IN
90_MIPI_AP_TO_LCM_DATA1_N 3 2 90_MIPI_AP_TO_LCM_DATA1_CONN_N 28 2 16V
NP0-C0G
ROOM=LCM_B2B 01005
ROOM=LCM_B2B

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

DISPLAY FLEX
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
42 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 28 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D403 (B2B,DRIVER ICS) 29 28 PN_SAGE_TO_TOUCH_VCPL


1 C4307 1 C4308 1 C4309 1 C4311 1 C4316
-12V
SAGE2 C0
APN: 343S0645 (CD3246C0, T6)
0.1UF 0.1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
2 16V
X5R-CERM 2 16V
X5R-CERM
16V
2 X6S-CERM 2 16V
X6S-CERM 2 16V
X6S-CERM 29 PP_SAGE_TO_TOUCH_VCPH
0201 0201 0402 0402 0402 13.5V
ROOM=SAGE ROOM=SAGE ROOM=SAGE ROOM=SAGE ROOM=SAGE
C4324 1 C4325 1 PP_SAGE_VCPL_F
3.5V
0.1UF 0.1UF
10%
16V
10%
16V
C4326 1
X5R-CERM 2 X5R-CERM 2 0.01UF
10%
R4307 0201 0201 25V

28 26 PN5V7_SAGE_AVDDN 1
4.7 2 PN5V7_SAGE_AVDDN_INT
ROOM=SAGE ROOM=SAGE X5R-CERM 2
0201
ROOM=SAGE
D
1% PP5V7_SAGE_AVDDH
1/32W
MF
1 C4312 1 C4317 A
DZ4301
29 26
5.45-5.98V PP1V8 3 5 6 7 8 9 12 13 14 20 21 28
01005 10UF 10UF GDZT2R6.2B
C4323 1 1 C4327

D2

AVDDL1 H5

VDDIO C3
A3

VCPH A1

VCPL_F E2
F3
F6

VCPL F1
ROOM=SAGE 20% 20% GDZ-0201
2 10V
X5R-CERM 2 10V
X5R-CERM K ROOM=SAGE
10UF 0.1UF

AVDDH1
AVDDH2
AVDDH3
AVDDH4
0402-1 0402-1 TO CLAMP THE 20% 20%

CUMULUS C1
ROOM=SAGE ROOM=SAGE 10V 2 6.3V
NEGATIVE RAIL X5R-CERM 2 X5R-CERM
0402-4 01005
ROOM=SAGE ROOM=SAGE

U4300
343S0638 SAGE2-C06
(TURN ON LATER THAN PP1V8_TOUCH)
(TURN OFF SAME TIME AS PP1V8_TOUCH) XW4302
SM 29 TOUCH_TO_SAGE_SENSE_IN<4> E4 SNS_IN0
CSP
ROOM=SAGE SNS_OUT0 E5 SAGE_TO_CUMULUS_IN<4> 29

TOUCH_TO_SAGE_SENSE_IN<3> D4 SNS_IN1 SNS_OUT1 D5 SAGE_TO_CUMULUS_IN<3>


26 PP5V1_GRAPE_VDDH 29 PP1V8_CUMULUS_VDDLDO 1 2 PP1V8_TOUCH 14 29
29 29

ROOM=CUMULUS 29 TOUCH_TO_SAGE_SENSE_IN<5> C4 SNS_IN2 SNS_OUT2 C5 SAGE_TO_CUMULUS_IN<5> 29


1 C4302 PP_CUMULUS_VDDCORE 1 C4306 29 TOUCH_TO_SAGE_SENSE_IN<0> B4 SNS_IN3 SNS_OUT3 B5 SAGE_TO_CUMULUS_IN<0> 29
10UF 1.0UF 29 TOUCH_TO_SAGE_SENSE_IN<12> A4 SNS_IN4 SNS_OUT4 A5 SAGE_TO_CUMULUS_IN<12> 29
20% 20%
2 10V TOUCH_TO_SAGE_SENSE_IN<7> A6 SNS_IN5 SNS_OUT5 A7 SAGE_TO_CUMULUS_IN<7>
X5R-CERM 2 6.3V
X5R
29 29
0402-1 PP_CUMULUS_VDDANA 0201-1 29 TOUCH_TO_SAGE_SENSE_IN<10> B6 SNS_IN6 SNS_OUT6 B7 SAGE_TO_CUMULUS_IN<10> 29
ROOM=CUMULUS ROOM=CUMULUS
TOUCH_TO_SAGE_SENSE_IN<1> C6 SNS_IN7 SNS_OUT7 C7 SAGE_TO_CUMULUS_IN<1>
1 C4304 1 C4305 29

TOUCH_TO_SAGE_SENSE_IN<11> D6 SNS_IN8 SNS_OUT8 D7 SAGE_TO_CUMULUS_IN<11>


29

4.7UF 4.7UF 29 29
20% 20% 29 TOUCH_TO_SAGE_SENSE_IN<2> E6 SNS_IN9 SNS_OUT9 E7 SAGE_TO_CUMULUS_IN<2> 29
2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 ROOM=CUMULUS E8 E9
TOUCH_TO_SAGE_SENSE_IN<13> SNS_IN10 SNS_OUT10 SAGE_TO_CUMULUS_IN<13>
402 402 R4304 29
D8 D9
29

VDDCORE C1

VDDH C8

C5
VDDANA B1

VDDLDO A1
ROOM=CUMULUS ROOM=CUMULUS

F4
ROOM=CUMULUS 220K 29 TOUCH_TO_SAGE_SENSE_IN<14> SNS_IN11 SNS_OUT11 SAGE_TO_CUMULUS_IN<14> 29
1 2 C8 C9
29 TOUCH_TO_SAGE_SENSE_IN<8> SNS_IN12 SNS_OUT12 SAGE_TO_CUMULUS_IN<8> 29
VDDIO 5% MF
29 TOUCH_TO_SAGE_SENSE_IN<9> B8 SNS_IN13 SNS_OUT13 B9 SAGE_TO_CUMULUS_IN<9> 29
45_PROX_TO_CUMULUS_RX 1/32W 01005
20
29 TOUCH_TO_SAGE_SENSE_IN<6> A8 SNS_IN14 SNS_OUT14 A9 SAGE_TO_CUMULUS_IN<6> 29

ROOM=CUMULUS SAGE_TO_CUMULUS_IN<2> B9 IN0_0 U4301 VSTM_0 E9 CUMULUS_TO_SAGE_VSTM_OUT<2> CUMULUS_TO_SAGE_VSTM_OUT<8> G1 DRV_IN0 DRV_OUT0 G6 SAGE_TO_TOUCH_VSTM_OUT<8>
C C4301 C
29 29 29 29
H1 H6
1000PF R4301 29 SAGE_TO_CUMULUS_IN<1> B8
A9
IN1_0 CUMULUS-C1
WLBGA
VSTM_1 E5
F7
CUMULUS_TO_SAGE_VSTM_OUT<5> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<6>
J1
DRV_IN1 DRV_OUT1
J6
SAGE_TO_TOUCH_VSTM_OUT<6> 29

1 2 45_PROX_TO_CUMULUS_RX_FILT 1
22.1K 2
29 SAGE_TO_CUMULUS_IN<6> IN2_0 VSTM_2 CUMULUS_TO_SAGE_VSTM_OUT<16> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<12> DRV_IN2 DRV_OUT2 SAGE_TO_TOUCH_VSTM_OUT<12> 29

29 SAGE_TO_CUMULUS_IN<7> B7 IN3_0 VSTM_3 E6 CUMULUS_TO_SAGE_VSTM_OUT<18> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<1> K1 DRV_IN3 DRV_OUT3 K6 SAGE_TO_TOUCH_VSTM_OUT<1> 29


1% MF
10% 1/32W 01005
29 SAGE_TO_CUMULUS_IN<4> B6 IN4_0 VSTM_4 E7 CUMULUS_TO_SAGE_VSTM_OUT<17> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<7> L1 DRV_IN4 DRV_OUT4 L6 SAGE_TO_TOUCH_VSTM_OUT<7> 29
6.3V ROOM=CUMULUS
X5R-CERM 29 SAGE_TO_CUMULUS_IN<8> A8 IN5_0 VSTM_5 F8 CUMULUS_TO_SAGE_VSTM_OUT<11> CUMULUS_TO_SAGE_VSTM_OUT<15> G2 DRV_IN5 DRV_OUT5 G7 SAGE_TO_TOUCH_VSTM_OUT<15>
C4303
29 29 29
01005 1
29 SAGE_TO_CUMULUS_IN<3> B5 IN6_0 VSTM_6 G9 CUMULUS_TO_SAGE_VSTM_OUT<13> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<14> H2 DRV_IN6 DRV_OUT6 H7 SAGE_TO_TOUCH_VSTM_OUT<14> 29
27PF B4 D6 J2 J7
5% 29 SAGE_TO_CUMULUS_IN<5> IN7_0 VSTM_7 CUMULUS_TO_SAGE_VSTM_OUT<7> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<18> DRV_IN7 DRV_OUT7 SAGE_TO_TOUCH_VSTM_OUT<18> 29
16V 2 K2 K7
NP0-C0G 29 SAGE_TO_CUMULUS_IN<9> A7 IN8_0 VSTM_8 D7 CUMULUS_TO_SAGE_VSTM_OUT<3> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<5> DRV_IN8 DRV_OUT8 SAGE_TO_TOUCH_VSTM_OUT<5> 29
01005 L2 L7
ROOM=CUMULUS 29 SAGE_TO_CUMULUS_IN<0> B3 IN9_0 VSTM_9 D8 CUMULUS_TO_SAGE_VSTM_OUT<9> THESE ARE ROUTED TOGETHER DRV_IN9 DRV_OUT9 SAGE_TO_TOUCH_VSTM_OUT<9> 29

29 SAGE_TO_CUMULUS_IN<14> A6 IN10_0 VSTM_10 F9 CUMULUS_TO_SAGE_VSTM_OUT<10> SPECIAL - CANNOT SWAP L3 DRV_IN10 DRV_OUT10 L8 SAGE_TO_TOUCH_VSTM_OUT<10> 29

29 SAGE_TO_CUMULUS_IN<10> A3 IN11_0 VSTM_11 D5 CUMULUS_TO_SAGE_VSTM_OUT<1> 29


SPECIAL - CANNOT SWAP 29 CUMULUS_TO_SAGE_VSTM_OUT<4> K3 DRV_IN11 DRV_OUT11 K8 SAGE_TO_TOUCH_VSTM_OUT<4> 29

29 SAGE_TO_CUMULUS_IN<13> A5 IN12_0 VSTM_12 F6 CUMULUS_TO_SAGE_VSTM_OUT<4> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<19> J3 DRV_IN12 DRV_OUT12 J8 SAGE_TO_TOUCH_VSTM_OUT<19> 29

29 SAGE_TO_CUMULUS_IN<11> A4 IN13_0 VSTM_13 F5 CUMULUS_TO_SAGE_VSTM_OUT<8> CUMULUS_TO_SAGE_VSTM_OUT<13> H3 DRV_IN13 DRV_OUT13 H8 SAGE_TO_TOUCH_VSTM_OUT<13>


PP4301
29 29 29
P2MM-NSM 1
ROOM=CUMULUS
SM PP
29 SAGE_TO_CUMULUS_IN<12> B2 IN14_0 VSTM_14 G4 CUMULUS_TO_SAGE_VSTM_OUT<12> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<16> G3 DRV_IN14 DRV_OUT14 G8 SAGE_TO_TOUCH_VSTM_OUT<16> 29
L4 L9
ROOM=CUMULUS PP4302
P2MM-NSM
SM PP
1 45_PROX_TO_CUMULUS_RX_IN A2 IN14_1 VSTM_15 E8 CUMULUS_TO_SAGE_VSTM_OUT<0> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<3>
K4
DRV_IN15 DRV_OUT15
K9
SAGE_TO_TOUCH_VSTM_OUT<3> 29

E4
VSTM_16 G8
G7
CUMULUS_TO_SAGE_VSTM_OUT<15> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<2>
J4
DRV_IN16 DRV_OUT16
J9
SAGE_TO_TOUCH_VSTM_OUT<2> 29 1
SM
PP PP4306
P4MM-NSM
8 SPI_AP_TO_TOUCH_CS_L H_CS* VSTM_17 CUMULUS_TO_SAGE_VSTM_OUT<19> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<0> DRV_IN17 DRV_OUT17 SAGE_TO_TOUCH_VSTM_OUT<0> 29
ROOM=SAGE
8 TOUCH_TO_AP_INT_L F1 H_INT* VSTM_18 G6 CUMULUS_TO_SAGE_VSTM_OUT<14> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<11> H4 DRV_IN18 DRV_OUT18 H9 SAGE_TO_TOUCH_VSTM_OUT<11> 29

8 SPI_AP_TO_TOUCH_SCLK D3 H_SCLK VSTM_19 G5 CUMULUS_TO_SAGE_VSTM_OUT<6> 29 29 CUMULUS_TO_SAGE_VSTM_OUT<17> G4 DRV_IN19 DRV_OUT19 G9 SAGE_TO_TOUCH_VSTM_OUT<17> 29

8 SPI_AP_TO_TOUCH_MOSI D2 H_SDI D3 BSYNC K5


R43022 E1 H_SDO GPIO_1/CK G1 NOTE: LCM_TO_AP_HIFA_BSYNC_BUFF
SAGE_VBIAS VBIAS LCM_TO_AP_HIFA_BSYNC 8 9 28 29 33
1
SM
PP PP4305
P4MM-NSM
8 SPI_TOUCH_TO_AP_MISO 1 TOUCH_TO_AP_SPI1_MISO_R GPIO_2/SD D4 CUMULUS_TO_SAGE_BOOST_EN 29 29 SAGE_TO_TOUCH_VCPH_REF A2 VCPH_REF/EN GCM_TEST F9 CUMULUS_TO_SAGE_GCM_SEL 29 ROOM=SAGE
01005
MF
10.2
ROOM=CUMULUS
1%
1/32W C4 JTAG_TCK GPIO_3 F2 U12_GPIO_3 1
SM
PP
P4MM-NSM
PP4303
ROOM=CUMULUS 29 SAGE_TO_TOUCH_VCPL_REF F2 VCPL_REF/EN
GO F7 NC
C3 JTAG_TDI GPIO_4 F3 CUMULUS_TO_SAGE_GCM_SEL 29
C4310 1 C4313 1 C4318 1
PP_SAGE_VBST_OUTH B1 VBST_OUTH
NC
E2 JTAG_TDO 0.01UF 0.01UF 0.1UF E1 VCM_IN J5 TOUCH_TO_SAGE_VCM_IN 29
C6 10% 10% 10% PN_SAGE_VBST_OUTL VBST_OUTL
PP1V8_CUMULUS_VDDLDO JTAG_TMS TM_ACS* C2 CUMULUS_TO_PROX_RX_EN_1V8 6.3V 2 6.3V 2 6.3V 2
I2C_SCL F5 NC
29 28

B XW4301 TM_OVR G3
X5R
01005
ROOM=SAGE
X5R
01005
ROOM=SAGE
CERM-X5R
0201
ROOM=SAGE
PP_SAGE_LX C1
D1
L_X
I2C_SDA G5 NC
B
CUMULUS_TO_PROX_TX_EN_1V8_L E3 BCFG_RTCK 1
R4303 PP_SAGE_LY L_Y

AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
SM 29

8 45_AP_TO_TOUCH_CLK32K_RESET_L 1 2 45_AP_TO_TOUCH_CLK32K_RESET_L_XW D1 CLKIN/RESET* 100K BOOST_EN B2 CUMULUS_TO_SAGE_BOOST_EN 29


5%
ROOM=CUMULUS AP_TO_TOUCH_RESET_L D9 RSTOVR*
8 1/32W
MF 1
SM
PP PP4304
P4MM-NSM

C2
B3
F4
F8
E3
L5
GND 2 01005
ROOM=CUMULUS 1 ROOM=SAGE

C4314 1 C4319 1 C4321 1


C7
C9
G2

PP1V8_TOUCH
1000PF 1000PF
0.33UF L4301
14 29

ROOM=SAGE 20% 10% 10%


20V 2 25V 25V 10UH-0.32A-1.56OHM
TANT X7R-CERM 2 X7R-CERM 2
0402 0201 0201 PSB12101T-SM
ROOM=SAGE ROOM=SAGE ROOM=SAGE

PP5V7_SAGE_AVDDH
J4300
29 26
ROOM=TOUCH_B2B 2
ON MLB ->
ON FLEX->
516S1071 PLUG
516S1070 RCPT
43
AA21
M-ST-SM
44
TOUCH B2B
C5 29 TOUCH_TO_SAGE_SENSE_IN<5> 1 2 TOUCH_TO_SAGE_SENSE_IN<6> 29 C6
C4 29 TOUCH_TO_SAGE_SENSE_IN<4> 3 4 TOUCH_TO_SAGE_SENSE_IN<13> 29 GS3
TOUCH_TO_SAGE_SENSE_IN<0> 5 6 TOUCH_TO_SAGE_SENSE_IN<7> 0603-LLP
C0 C7
C4320 C4322
29 29 TANT
7 8 25V 2 1 1
C3 29 TOUCH_TO_SAGE_SENSE_IN<3> SAGE_TO_TOUCH_VCPH_REF 29 VGH_REF 20%
TOUCH_TO_SAGE_SENSE_IN<11> 9 10 SAGE_TO_TOUCH_VCPL_REF 1UF-10OHM
1000PF 1000PF
GS1 29 29 VGL_REF 10% 10%
C2 29 TOUCH_TO_SAGE_SENSE_IN<2> 11 12 TOUCH_TO_SAGE_VCM_IN 29 VCOM C4315 1 25V
X7R-CERM 2
0201
25V
X7R-CERM 2
0201
C1 29 TOUCH_TO_SAGE_SENSE_IN<1> 13 14 TOUCH_TO_SAGE_SENSE_IN<12> 29 GS2 ROOM=SAGE ROOM=SAGE ROOM=SAGE
GS0 29 TOUCH_TO_SAGE_SENSE_IN<10> 15 16 TOUCH_TO_SAGE_SENSE_IN<9> 29 C9
VGL 29 28 PN_SAGE_TO_TOUCH_VCPL 17 18 TOUCH_TO_SAGE_SENSE_IN<8> 29 C8
VGH 29 PP_SAGE_TO_TOUCH_VCPH 19 20 TOUCH_TO_SAGE_SENSE_IN<14> 29 GS4
R10 29 SAGE_TO_TOUCH_VSTM_OUT<10> 21 22

A R7 29 SAGE_TO_TOUCH_VSTM_OUT<7>
SAGE_TO_TOUCH_VSTM_OUT<1>
23
25
24
26
SAGE_TO_TOUCH_VSTM_OUT<17>
SAGE_TO_TOUCH_VSTM_OUT<16>
29 R17 PP1V8_TOUCH 14 29 A
R1 29 29 R16 ROOM=CUMULUS PAGE TITLE

5
R5 29 SAGE_TO_TOUCH_VSTM_OUT<5> 27
29
28
30
SAGE_TO_TOUCH_VSTM_OUT<15> 29 R15
VCC
1
R4306 D403 (TOUCH B2B, DRIVER ICS)
R6 SAGE_TO_TOUCH_VSTM_OUT<6> SAGE_TO_TOUCH_VSTM_OUT<14> R14 100K
U4302
29 29
31 32 5% DRAWING NUMBER SIZE
R8 SAGE_TO_TOUCH_VSTM_OUT<8> SAGE_TO_TOUCH_VSTM_OUT<13> R13 1/32W
R9
29

29 SAGE_TO_TOUCH_VSTM_OUT<9> 33 34 SAGE_TO_TOUCH_VSTM_OUT<12>
29

29 R12
74AUP2G3404GN
SOT1115 MF
01005 Apple Inc.
051-00648 D
2 REVISION
R4 SAGE_TO_TOUCH_VSTM_OUT<4> 35 36 SAGE_TO_TOUCH_VSTM_OUT<11> R11 LCM_TO_AP_HIFA_BSYNC_BUFF 6 1Y 1A 1 LCM_TO_AP_HIFA_BSYNC
29
37 38
29 8 9 28 29 33 R
4.0.0
R3
R2
29 SAGE_TO_TOUCH_VSTM_OUT<3>
SAGE_TO_TOUCH_VSTM_OUT<2> 39 40
SAGE_TO_TOUCH_VSTM_OUT<0>
SAGE_TO_TOUCH_VSTM_OUT<18>
29 R0_RIGHT
R18
R4305 1
CUMULUS_TO_PROX_TX_EN_BUFF 4 2Y 2A 3 CUMULUS_TO_PROX_TX_EN_1V8_L
NOTICE OF PROPRIETARY PROPERTY: BRANCH
29 29 100K 20 29
THE INFORMATION CONTAINED HEREIN IS THE
R0_LEFT SAGE_TO_TOUCH_VSTM_OUT<0> 41 42 SAGE_TO_TOUCH_VSTM_OUT<19> R19 5% PROPRIETARY PROPERTY OF APPLE INC.
29 29
1/32W GND THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF
45 46 ROOM=CUMULUS
01005 2 2
ROOM=CUMULUS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
43 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 29 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

TRISTAR 2 (A3)
APN:343S0695
PP5V0_USB 3 17 31
33 31 26 15 PP3V0_TRISTAR PP3V3_ACC 15

3
1 C4500 1 C4501
1.0UF 0.1UF PP1V8_SDRAM D
20% 20% 33 26 24 17 16 15 14 12 8
2 6.3V 2 6.3V
X5R
0201-1
X5R-CERM
01005 1 C4502 Q4500
ROOM=TRISTAR ROOM=TRISTAR 0.01UF REVERSE_GATE 1 G CSD68822F4
10% 0402
2 6.3V
C X5R
01005 CRITICAL 1
ROOM=TRISTAR
CRITICAL C

ACC_PWR D5
VDD_1V8 F3

VDD_3V0 F4
S
ROOM=TRISTAR ROOM=TRISTAR R4500
10K

2
5%
1/32W
MF
2 01005
ROOM=TRISTAR

U4500
CBTL1610A3UK
C3 WLCSP
23 BI
90_MIKEYBUS_DATA_P DIG_DP P_IN F6 PP_TRISTAR_PIN
C4
90_MIKEYBUS_DATA_N DIG_DN ACC1 C5 PP_TRISTAR_ACC1
C4503
23 BI 3 31
1
A1 ACC2 E5 PP_TRISTAR_ACC2 3 31
33 BI
90_USB_BB_DATA_P USB1_DP 1UF
B1 20%
R4510 33 BI
90_USB_BB_DATA_N USB1_DN DP1 A2 90_TRISTAR_DP1_CONN_P BI 3 31
2 16V
CER-X5R
6.34K 2 C2 DN1 B2 90_TRISTAR_DP1_CONN_N 3 31 0201
16 OUT
TRISTAR_TO_PMU_USB_BRICK_ID 1 TRISTAR_USB_BRICK_ID_R BRICK_ID
BI
ROOM=TRISTAR
1% A3 DP2 A4 90_TRISTAR_DP2_CONN_P 3 31
1/32W 90_USB_AP_DATA_P USB0_DP
BI
1 C4510 MF
01005
5 BI
90_USB_AP_DATA_N B3
USB0_DN
DN2 B4 90_TRISTAR_DP2_CONN_N BI 3 31
0.01UF ROOM=PMU
5 BI
10%
E2 CON_DET_L E3 TRISTAR_CON_DETECT_L 3 31
2 6.3V UART_AP_TO_ACCESSORY_TXD IN
X5R 8 IN UART0_TX
E1
01005
ROOM=PMU 8 OUT
UART_ACCESSORY_TO_AP_RXD UART0_RX POW_GATE_EN* D6 TRISTAR_TO_TIGRIS_VBUS_OFF OUT 17 30

F2
8 IN
UART_AP_DEBUG_TXD UART1_TX SWITCH_EN E4 PMU_TO_OWL_ACTIVE_READY IN 5 9 16 26
F1
8 OUT
UART_AP_DEBUG_RXD UART1_RX HOST_RESET B6 TRISTAR_TO_PMU_HOST_RESET OUT 16

D2 D3 I2C1_AP_SDA
UART2_TX SDA IN 8 17 25
D1 D4 I2C1_AP_SCL
NC UART2_RX SCL BI 8 17 25

INT C6 TRISTAR_TO_AP_INT
SWD_DOCK_TO_AP_SWCLK A5 OUT 8 16
5 JTAG_CLK E6
OUT
B5 BYPASS TRISTAR_BYPASS
SWD_DOCK_BI_AP_SWDIO
B 5 BI JTAG_DIO
B

DVSS
DVSS
DVSS
1 C4504
1.0UF
20%

F5
C1
A6
2 6.3V
X5R
0201-1
ROOM=TRISTAR

ROOM=TRISTAR
P3MM-NSM
SM
30 17 TRISTAR_TO_TIGRIS_VBUS_OFF 1
PP PP4500

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

I/O:TRISTAR 2
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
45 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 30 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

DOCK FLEX CONNECTOR


DOCK FLEX CONNECTOR ANTENNA FL4620
120-OHM-210MA
THIS ONE ON MLB ---> 516S00116 (RCPT)
516S00117 (PLUG)
AUDIO JACK 33 30 26 15 PP3V0_TRISTAR 2 1 PP3V0_LAT_CONN 31

R4600 01005
1 C4620 CRITICAL
ROOM=DOCK_B2B
3.3K ROOM=DOCK_B2B
23 OUT HPHONE_TO_CODEC_DETECT 1 2 HPHONE_TO_CODEC_DETECT_CONN 31
100PF
5% J4600
16V AA27D-S038VA1
5%
1/32W
MF
1 C4600 2 NP0-C0G
01005
40
F-ST-SM
39
01005 56PF ROOM=DOCK_B2B

D
ROOM=DOCK_B2B 5%
2 16V
NP0-C0G
PP3V1_MESA_CONN
D
01005 31 25 SPEAKERAMP_TO_SPEAKER_OUT_POS 2 1 27
ROOM=DOCK_B2B
4 3 MESA_TO_BOOST_EN_CONN
FL4600 NC
6 5 SPI_AP_TO_MESA_SCLK_CONN
27

FERR-33-OHM-0.8A-0.09-OHM NC 27

31 25 SPEAKERAMP_TO_SPEAKER_OUT_NEG 8 7 BUTTON_MENU_KEY_CONN_L 27
23 CODEC_TO_HPHONE_HS3 1 2 CODEC_TO_HPHONE_HS3_CONN 31
BI
0201 27 PP11V3_MESA_CONN 10 9 SPI_AP_TO_MESA_MOSI_CONN 27
ROOM=DOCK_B2B 1 DZ4600 1 C4699 27 PP1V9_MESA_CONN 12 11 MESA_TO_AP_INT_CONN 27
6.8V-100PF 220PF 27 SPI_MESA_TO_AP_MISO_CONN 14 13 HPHONE_TO_CODEC_DETECT_CONN 31
01005 10%
2 ROOM=DOCK_B2B
NO_XNET_CONNECTION=1
2 10V
X7R-CERM
16 15 PP3V0_LAT_CONN 31
01005 18 17 BB_LAT_GPIO2_CONN 31
ROOM=DOCK_B2B
FL4601 31 CODEC_TO_HPHONE_L_CONN 20 19 BB_LAT_GPIO1_CONN 31

FERR-33-OHM-0.8A-0.09-OHM 31 CODEC_TO_HPHONE_HS4_REF_CONN 22 21

23 CODEC_TO_HPHONE_HS4 1 2 CODEC_TO_HPHONE_HS4_CONN 31
31 CODEC_TO_HPHONE_R_CONN 24 23 90_TRISTAR_DP1_CONN_P BI 3
BI 30
CODEC_TO_HPHONE_HS3_CONN 26 25 90_TRISTAR_DP1_CONN_N
0201
ROOM=DOCK_B2B 1 DZ4601 1 C4698
31

CODEC_TO_HPHONE_HS4_CONN 28 27 90_TRISTAR_DP2_CONN_N
BI 3
30

6.8V-100PF
01005 220PF FL4608 31

CODEC_TO_HPHONE_HS3_REF_CONN 30 29 90_TRISTAR_DP2_CONN_P
BI 3
30

2 ROOM=DOCK_B2B
10% 120-OHM-210MA 31 BI 3
2 10V
30
NO_XNET_CONNECTION=1 X7R-CERM 31 LOWERMIC1_TO_CODEC_AIN1_CONN_P 32 31
01005 33 BB_LAT_GPIO2 1 2 BB_LAT_GPIO2_CONN 31
IN
LOWERMIC1_TO_CODEC_AIN1_CONN_N 34 33 TRISTAR_CON_DETECT_CONN_L
FL4602 ROOM=DOCK_B2B
01005 31 31

600-OHM-25%-0.28A-0.75OHM ROOM=DOCK_B2B 1 C4601 31 PP_CODEC_TO_LOWERMIC1_BIAS_CONN 36 35 PP_TRISTAR_ACC1_CONN 31

56PF 24 LOWERMIC1_BIAS_FILT_RET 38 37 PP_TRISTAR_ACC2_CONN 31


23 OUT
CODEC_TO_HPHONE_HS4_REF 1 2 CODEC_TO_HPHONE_HS4_REF_CONN 31 5%
0201 2 16V
ROOM=DOCK_B2B 1 DZ4602 NP0-C0G
01005 42 41
6.8V-100PF
01005
ROOM=DOCK_B2B

2 ROOM=DOCK_B2B VOLTAGE=5.0V
NO_XNET_CONNECTION=1
FL4624 30 17 3 PP5V0_USB
120-OHM-210MA
FL4603
600-OHM-25%-0.28A-0.75OHM 33 IN BB_LAT_GPIO1 1 2 BB_LAT_GPIO1_CONN 31 C4650 1 C4651 1 C4652 1 C4653 1 C4654 1 C4655 1

C 23 OUT CODEC_TO_HPHONE_HS3_REF 1 2 CODEC_TO_HPHONE_HS3_REF_CONN 31


01005
ROOM=DOCK_B2B 1 C4624
0.1UF
10%
25V 2
0.1UF
10%
25V 2
0.1UF
10%
25V 2
56PF
5%
25V
100PF
5%
35V
220PF
10%
25V
C
0201 NP0-C0G-CERM 2 NP0-C0G 2 X7R-CERM 2
ROOM=DOCK_B2B 1 DZ4603 5%
56PF X5R
0201
X5R
0201
X5R
0201 01005 01005 0201
6.8V-100PF
01005 2 16V
NP0-C0G
ROOM=DOCK_B2B ROOM=DOCK_B2B ROOM=DOCK_B2B ROOM=DOCK_B2B ROOM=DOCK_B2B ROOM=DOCK_B2B

ROOM=DOCK_B2B
2 NO_XNET_CONNECTION=1 01005
ROOM=DOCK_B2B

FL4604
FERR-33-OHM-0.8A-0.09-OHM
23 IN CODEC_TO_HPHONE_L 1 2 CODEC_TO_HPHONE_L_CONN 31
0201
ROOM=DOCK_B2B 1 DZ4604 1 C4697
6.8V-100PF
01005
220PF
10%
2 ROOM=DOCK_B2B
NO_XNET_CONNECTION=1
2 10V
X7R-CERM
01005
ROOM=DOCK_B2B
TRISTAR
FL4605
FERR-33-OHM-0.8A-0.09-OHM
1/32W 2
R46401
23 IN
CODEC_TO_HPHONE_R 1 2 CODEC_TO_HPHONE_R_CONN 31 30 3 OUT
TRISTAR_CON_DETECT_L TRISTAR_CON_DETECT_CONN_L 31
0201 5%
ROOM=DOCK_B2B 1 DZ4610 1 C4696 MF 1.00K
01005 1 C4640
6.8V-100PF
01005
220PF ROOM=DOCK_B2B 27PF
10% 5%
2 ROOM=DOCK_B2B 2 10V
X7R-CERM 2 16V
LOWER MIC1
NO_XNET_CONNECTION=1 NP0-C0G
01005
ROOM=DOCK_B2B FL4641 01005
ROOM=DOCK_B2B
10-OHM-1.1A
FL4610 30 3 PP_TRISTAR_ACC1 1 2 PP_TRISTAR_ACC1_CONN 31

120-OHM-210MA 01005
C4641
23 OUT
LOWERMIC1_TO_CODEC_AIN1_P 2
01005
1 LOWERMIC1_TO_CODEC_AIN1_CONN_P 31
SPEAKER ROOM=DOCK_B2B 1
100PF
5%
16V
B ROOM=DOCK_B2B 1 C4610 2 NP0-C0G
B
56PF 31 25 SPEAKERAMP_TO_SPEAKER_OUT_POS FL4642 01005
ROOM=DOCK_B2B
5% 10-OHM-1.1A
2 16V
NP0-C0G 1 C4634
01005 100PF PP_TRISTAR_ACC2 1 2 PP_TRISTAR_ACC2_CONN
FL4611
30 3 31
ROOM=DOCK_B2B 5%
120-OHM-210MA 2
16V
NP0-C0G
01005
ROOM=DOCK_B2B 1 C4642
01005 100PF
23 OUT
LOWERMIC1_TO_CODEC_AIN1_N 2 1 LOWERMIC1_TO_CODEC_AIN1_CONN_N 31
ROOM=DOCK_B2B 5%
16V
01005 2 NP0-C0G
ROOM=DOCK_B2B 1 C4611 31 25 SPEAKERAMP_TO_SPEAKER_OUT_NEG 01005
ROOM=DOCK_B2B
56PF
5% 1 C4635
2 16V
NP0-C0G 100PF
5%
FL4612 01005
ROOM=DOCK_B2B 2
16V
NP0-C0G
120-OHM-210MA 01005
ROOM=DOCK_B2B
24 PP_CODEC_TO_LOWERMIC1_BIAS 2 1 PP_CODEC_TO_LOWERMIC1_BIAS_CONN 31
01005
ROOM=DOCK_B2B
1 C4612
100PF
5%
2 16V
NP0-C0G
01005
ROOM=DOCK_B2B

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

I/O:DOCK FLEX B2B


DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
46 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 31 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BUTTON FLEX
BUTTON FLEX CONNECTOR
516S1040 (PLUG)
THIS ONE ON MLB ---> 516S1041 (RCPT)
FL4700 D
D 120-OHM-210MA
24 PP_CODEC_TO_REARMIC2_BIAS 2 1 PP_CODEC_TO_REARMIC2_BIAS_CONN 32
BUTTON_B2B
01005 CRITICAL
ROOM=BUTTON_B2B 1 C4700 J4700
205847-018
100PF F-ST-SM
5% 20
2 16V
NP0-C0G
01005 19
ROOM=BUTTON_B2B

32 22 PP_LED_DRIVER_WARM_LED 2 1 LED_MODULE_NTC_CONN 32
FL4701 4 3 PP_CODEC_TO_REARMIC2_BIAS_CONN 32
MIC2 120-OHM-210MA 6 5 REARMIC2_TO_CODEC_AIN3_CONN_P 32
ANC REF MIC 23 REARMIC2_TO_CODEC_AIN3_P 2 1 REARMIC2_TO_CODEC_AIN3_CONN_P 32 32 BUTTON_HOLD_KEY_CONN_L 8 7 REARMIC2_TO_CODEC_AIN3_CONN_N 32
OUT
01005 10 9
ROOM=BUTTON_B2B
1 C4701 12 11
56PF 15
PP3V1_VIBE 14 13
5%
2 16V
NP0-C0G 32 BUTTON_RINGER_A_CONN 16 15 VIBE_RETURN
01005
ROOM=BUTTON_B2B
1 C4714 1 C4715 1 C4716 32 BUTTON_VOL_DOWN_CONN_L 18 17 BUTTON_VOL_UP_CONN_L 32
100PF 100PF 4.7UF K
D4701
5% 5% 20%
2 16V 2 16V 2 6.3V 21
FL4702 NP0-C0G
01005
NP0-C0G
01005
X5R-CERM1
402 LLP-DFN1006-2
BAS40LP 22 PP_LED_DRIVER_COOL_LED 22 32
120-OHM-210MA BUTTON_B2B BUTTON_B2B BUTTON_B2B
A BUTTON_B2B
23 REARMIC2_TO_CODEC_AIN3_N 2 1 REARMIC2_TO_CODEC_AIN3_CONN_N 32
OUT
01005
ROOM=BUTTON_B2B 1 C4702 3
56PF
5%
D
2 16V
NP0-C0G XW4701
01005
ROOM=BUTTON_B2B
SM
G
Q4701 1 C4703
AP_TO_VIBE_TRIG VIBE_PWM_G
C
1 2 100PF
C 8 1 DMN3730UFB4
S 5%
DFN1006H4-3
2 16V
1
R4701 SYM_VER_1
BUTTON_B2B
NP0-C0G
01005
10K BUTTON_B2B
1% 2
1/32W
MF
2 01005
BUTTON_B2B

32 22 PP_LED_DRIVER_WARM_LED
C4723 1 1 C4724
100PF 27PF
5% 5%
16V 2 16V
2 NP0-C0G
NP0-C0G 01005
01005 ROOM=BUTTON_B2B
ROOM=BUTTON_B2B

R4710 PP_LED_DRIVER_COOL_LED
0.00 32 22
BUTTON_HOLD_KEY_L 1 2 BUTTON_HOLD_KEY_CONN_L STROBE:
C4721
8 OUT 32
1
C4710 1
0%
1/32W 1 WARM LED 100PF
1 C4722
27PF
27PF MF
01005 DZ4710 COOL LED 5%
16V 5%
5%
6.3V 2 MODULE NTC NP0-C0G 2 2 16V
NP0-C0G
NP0-C0G
ROOM=BUTTON_B2B 5.5V-6.2PF 01005 01005
0201 0201 ROOM=BUTTON_B2B ROOM=BUTTON_B2B
ROOM=BUTTON_B2B 2 ROOM=BUTTON_B2B

B FL4720 B
120-OHM-210MA
22 LED_MODULE_NTC 1 2 LED_MODULE_NTC_CONN 32
OUT

FL4711 01005
120-OHM-210MA R47201 ROOM=BUTTON_B2B
1 C4720
51.1K 100PF
16 8 BUTTON_RINGER_A 1 2 BUTTON_RINGER_A_CONN 32
1% 5%
OUT 1/32W
01005 MF 2 16V
C4711 1 ROOM=BUTTON_B2B 1 01005 2 NP0-C0G
01005
27PF ROOM=BUTTON_B2B ROOM=BUTTON_B2B
5%
6.3V DZ4711
NP0-C0G 2 5.5V-6.2PF
0201 0201
ROOM=BUTTON_B2B ROOM=BUTTON_B2B
2

BUTTONS:
HOLD
RINGER
VOL UP/DOWN FL4712
120-OHM-210MA
16 8 BUTTON_VOL_DOWN_L 1 2 BUTTON_VOL_DOWN_CONN_L 32
OUT
01005
C4712 1 ROOM=BUTTON_B2B 1 DZ4712
100PF 12V-33PF
5% 01005-1
16V 2 2 ROOM=BUTTON_B2B
NP0-C0G
01005
ROOM=BUTTON_B2B

FL4713
A 120-OHM-210MA
SYNC_MASTER=N/A SYNC_DATE=N/A A
16 8 BUTTON_VOL_UP_L 1 2 BUTTON_VOL_UP_CONN_L 32 PAGE TITLE
OUT

C4713 1
01005
ROOM=BUTTON_B2B 1 DZ4713 I/O:BUTTON FLEX B2B
100PF 12V-33PF
01005-1
DRAWING NUMBER SIZE
5%
16V 2 2 ROOM=BUTTON_B2B
Apple Inc.
051-00648 D
NP0-C0G REVISION
01005
ROOM=BUTTON_B2B R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
47 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 32 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND, WLAN, BT & STOCKHOLM RF


I566

N69 CELLULAR/WLAN/BT/STOCKHOLM SUBDESIGN SYMBOL

SHARED POWER
51 18 17 3 IN
PP_BATT_VCC PP_BATT_VCC ADC_PP_LDO5 BB_TO_PMU_AMUX_LDO5 OUT 16 36

ADC_PP_LDO11 BB_TO_PMU_AMUX_LDO11 16 36
58 26 25 24 22 21 17 15 14 PP_VCC_MAIN OUT
IN PP_VCC_MAIN ADC_SMPS1 BB_TO_PMU_AMUX_SMPS1 OUT 16 36

D 33 30 26 24 17 16 15 14 12 8
58 57 56 IN
PP1V8_SDRAM PP_WL_BT_VDDIO_AP
ADC_SMPS4 BB_TO_PMU_AMUX_SMPS4 OUT 16 36
D
RFFE_VIO_S2R
36 16 IN
PMU_TO_BB_USB_VBUS_DETECT BB_USB_VBUS
33 30 26 24 17 16 15 14 12 8
58 57 56 IN
PP1V8_SDRAM PP_STOCKHOLM_1V8_S2R
56 31 30 26 15 IN
PP3V0_TRISTAR PAC_VDD_3V0

BASEBAND WLAN

36 5 BI
50_AP_BI_BB_HSIC0_DATA 50_BB_HSIC_DATA
36 5 BI
50_AP_BI_BB_HSIC0_STB 50_BB_HSIC_STROBE

36 8 OUT
BB_TO_AP_HSIC_DEVICE_RDY BB_DEVICE_RDY
36 8 IN
AP_TO_BB_HSIC_HOST_RDY BB_HOST_RDY

36 16 OUT
BB_TO_PMU_HOST_WAKE_L BB_WAKE_HOST_L HOST_WAKE_WLAN WLAN_TO_PMU_HOST_WAKE OUT 16 36
41 8 IN
AP_TO_BB_WAKE_MODEM AP_WAKE_MODEM
RADIO_MLB
WLAN_REG_ON PMU_TO_WLAN_REG_ON 16 36
IN

36 30 BI
90_USB_BB_DATA_N 90_BB_USB_N OSCAR_CONTEXT_A OWL_TO_WLAN_CONTEXT_A 9 36
IN
36 30 BI
90_USB_BB_DATA_P 90_BB_USB_P OSCAR_CONTEXT_B OWL_TO_WLAN_CONTEXT_B 9 36
IN

UART_WLAN_TO_AP_RXD 8 36
36 8 AP_TO_BB_RADIO_ON_L WLAN_UART_TXD OUT
IN RADIO_ON_L UART_AP_TO_WLAN_TXD 8 36
36 8 OUT BB_TO_AP_RESET_DETECT_L WLAN_UART_RXD IN
BB_RESET_DET_L UART_AP_TO_WLAN_RTS_L 8 36
36 8 AP_TO_BB_RESET_L WLAN_UART_CTS_L IN

36 16
IN
PMU_TO_BB_PMIC_RESET_L BB_RST_L
WLAN_UART_RTS_L
UART_WLAN_TO_AP_CTS_L OUT 8 36
IN RF_PMIC_RESET_L

PCIE_DEV_WAKE PCIE_AP_TO_WLAN_DEV_WAKE OUT 8 57


WLAN_PCIE_WAKE_L WLAN_TO_PMU_PCIE_WAKE_L OUT 16 57
I2S_BB_TO_AP_DIN PCIE_AP_TO_WLAN_RESET_L
C C
36 8 OUT
BB_I2S_TXD WLAN_PCIE_PERST_L IN 6 57

WLAN_PCIE_CLKREQ_L PCIE_WLAN_TO_AP_CLKREQ_L BI 6 57
36 8 IN
45_I2S_AP_TO_BB_BCLK BB_I2S_CLK
36 8 IN
I2S_AP_TO_BB_DOUT BB_I2S_RXD 90_PCIE_AP_TO_WLAN_REFCLK_N 6 57
90_WLAN_PCIE_REFCLK_N IN
36 8 IN
I2S_AP_TO_BB_LRCLK BB_I2S_WS 90_PCIE_AP_TO_WLAN_REFCLK_P 6 57
90_WLAN_PCIE_REFCLK_P IN
36 8 OUT
UART_BB_TO_AP_RXD BB_UART_TXD 90_WLAN_PCIE_RDN 90_PCIE_AP_TO_WLAN_TXD_N IN 6 36

36 8 IN
UART_AP_TO_BB_TXD BB_UART_RXD 90_WLAN_PCIE_RDP
90_PCIE_AP_TO_WLAN_TXD_P IN 6 36

36 8 UART_AP_TO_BB_RTS_L 90_WLAN_PCIE_TDN
90_PCIE_WLAN_TO_AP_RXD_N OUT 6 36
IN BB_UART_CTS_L
36 8 UART_BB_TO_AP_CTS_L 90_WLAN_PCIE_TDP 90_PCIE_WLAN_TO_AP_RXD_P OUT 6 36
OUT BB_UART_RTS_L

BLUETOOTH
36 29 28 9 8 IN
LCM_TO_AP_HIFA_BSYNC BB_FORCE_PWM

36 9 IN
UART_OWL_TO_BB_TXD BB_OTHER_RXD BT_UART_RXD
UART_AP_TO_BT_TXD IN 8 36

36 9 OUT UART_BB_TO_OWL_RXD BB_OTHER_TXD BT_UART_TXD UART_BT_TO_AP_RXD OUT 8 36

BT_UART_RTS_L UART_BT_TO_AP_CTS_L OUT 8 36

BT_UART_CTS_L UART_AP_TO_BT_RTS_L IN 8 36

36 9 BI
SWD_AP_BI_BB_SWDIO BB_JTAG_TMS
40 13 9 IN
SWD_AP_PERIPHERAL_SWCLK BB_JTAG_TCK BT_PCM_IN
I2S_AP_TO_BT_DOUT IN 8 36

BT_PCM_OUT
I2S_BT_TO_AP_DIN OUT 8 36

BT_PCM_CLK
45_I2S_AP_TO_BT_BCLK BI 8 36

BT_PCM_SYNC
I2S_AP_TO_BT_LRCLK IN 8 36
36 8 OUT BB_TO_AP_GPS_TIME_MARK BB_GPS_SYNC

BT_REG_ON
PMU_TO_BT_REG_ON IN 16 36

36 8 IN
AP_TO_BB_COREDUMP BB_CORE_DUMP WAKE_BT
AP_TO_BT_WAKE IN 8 36

HOST_WAKE_BT
BT_TO_PMU_HOST_WAKE OUT 16 36
41 8 BB_TO_AP_IPC_GPIO BB_IPC_GPIO1
CLK32K_AP
45_PMU_TO_WLAN_CLK32K IN 16 36
36 8 OUT AP_TO_BB_MESA_ON AP_TO_BB_MESA_ON

B B
41 26 22 OUT
BB_TO_LED_DRIVER_GSM_BURST_IND GSM_TXBURST_IND

ANTENNA STOCKHOLM

41 31 OUT
BB_LAT_GPIO1 BB_LAT_GPIO1 STOCKHOLM_UART_TXD
UART_STOCKHOLM_TO_AP_RXD IN 8 36

41 31 BB_LAT_GPIO2 STOCKHOLM_UART_RXD
UART_AP_TO_STOCKHOLM_TXD OUT 8 36
OUT BB_LAT_GPIO2
STOCKHOLM_UART_RTS
UART_STOCKHOLM_TO_AP_CTS_L OUT 8 36

STOCKHOLM_UART_CTS
UART_AP_TO_STOCKHOLM_RTS_L IN 8 36

AP_TO_STOCKHOLM_EN
PMU_TO_STOCKHOLM_EN IN 16 36

AP_TO_STOCKHOLM_FW_DWLD_REQ
AP_TO_STOCKHOLM_DWLD_REQUEST IN 7 36

STOCKHOLM_TO_PMU_HOST_WAKE STOCKHOLM_TO_PMU_HOST_WAKE OUT 16 36

AP_TO_STOCKHOLM_DEV_WAKE
AP_TO_STOCKHOLM_DEV_WAKE IN 8 58

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

BASEBAND:RADIO SYMBOL
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
49 OF 49
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 33 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
4 0004752417 ENGINEERING RELEASED 2015-08-24

N69 RADIO_MLB SUBDESIGN - EVT


D 8/19/2015 D

LAST_MODIFICATION=Wed Aug 19 10:34:24 2015

PAGE <CSA> CONTENTS SYNC DATE


1
34 page1
3
35 CELL:ALIASES
4
36 AP INTERFACE & DEBUG CONNECTORS
5
37 BASEBAND PMU (1 0F 2)
6
38 BASEBAND PMU (2 OF 2)
7
39 BASEBAND (1 OF 2)
8
40 BASEBAND (1 OF 2)
9
41 MOBILE DATA MODEM (2 OF 2)
10
42 RF TRANSCEIVER (1 0F 3)
11
43 RF TRANSCEIVER (2 OF 3)
C 44 12
RF TRANSCEIVER (3 OF 3) C
13
45 QFE DCDC
15
46 2G PA
20
47 VERY LOW BAND PAD
21
48 LOW BAND PAD
22
49 MID BAND PAD
23
50 HIGH BAND PAD
24
51 ANTENNA SWITCH
30
52 HIGH BAND SWITCH
31
53 RX DIVERSITY
32
54 RX DIVERSITY (2)
33
55 GPS
35
56 ANTENNA FEEDS
36
57 WIFI/BT: MODULE AND FRONT END
37
58 STOCKHOLM
40
59 OMIT_TABLE_RF
41
60 Radio Subdesign Ports
42

B 43 B
45

A ? A
DRAWING TITLE

SCH,MLB,N69
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 34 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BLANK PAGE
D D

C C

B B

A A
PAGE TITLE

CELL:ALIASES
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
30 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 35 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

AP INTERFACE & DEBUG CONNECTORS


NOT UNDER SIM UNDER THE SIM
PP3105_RF
P2MM-NSM
SM
1 CLK32K_AP
PP

PP3119_RF
P2MM-NSM
24 27

OPTIONAL NOSTUFF
SM
1 BT_UART_TXD J3100_RF D
D PP
WIFI_BT
24 27
AXE650124
M-ST-SM
PP3120_RF 53 51
P2MM-NSM
SM
1 BT_UART_RXD
PP
WIFI_BT
24 27 PP3131_RF BB_JTAG_RST_L 2 1 BB_DEBUG_STATUS
SM PP3132_RF
P4MM-NSM 7 8
27 7 BB_JTAG_TCK_IN
PP3101_RF
P2MM-NSM PP
1 P4MM-NSM
SM
4 3 BB_CORE_DUMP PP3138_RF PP3190_RF
27 7 BB_JTAG_TMS BB_USB_VBUS
PP 27 8 PP3139_RF
SM
SM 1 6 5 P4MM-NSM 1 P2MM-NSM
1 BT_UART_CTS_L PP
90_BB_USB_N SM AP_TO_BB_MESA_ON
PP3140_RF
24 27 SM
PP
WIFI_BT PP3123_RF 7
BB_JTAG_TDO 8 7 P4MM-NSM 1 1 8 27
PP PP
P2MM-NSM SM
PP3102_RF SM OSCAR_CONTEXT_A 7 BB_JTAG_TDI 10 9 90_BB_USB_P P4MM-NSM 1
P2MM-NSM 1
PP 12 11
PP
PP3191_RF
SM
1 BT_UART_RTS_L 7 BB_JTAG_TRST_L P2MM-NSM
24 27 SM BB_FORCE_PWM
PP
WIFI_BT 25 5 3 STOCKHOLM_TO_BBPMU_CLK_REQ 14 13 1 5 27
PP
PP3124_RF BB_I2S_CLK 16 15 BB_RST_L
27 8 5 27
P2MM-NSM
PP3121_RF 18 17 BB_RESET_DET_L
P2MM-NSM
SM
SM
PP
1
STOCKHOLM
OSCAR_CONTEXT_B
8 3
BB_HOST_RDY
BB_SIM_RESET 20 19
8 27 8 27
PP3115_RF
P4MM-NSM
1 BT_PCM_CLK SM
PP
STOCKHOLM 8 3 BB_SIM_CLK 22 21 BB_WAKE_HOST_L 8 27 1 50_BB_HSIC_STROBE 7 27
PP
PP3122_RF 24 23 BB_GPS_SYNC
P2MM-NSM
SM
8 3

8 3
BB_SIM_DATA
BB_SIM_DETECT 26 25
8 27
PP3116_RF
P4MM-NSM
1 BT_PCM_SYNC SM
PP
STOCKHOLM 25 6 4 3 PP_LDO5 28 27 BB_DEVICE_RDY 8 27 1 50_BB_HSIC_DATA 7 27
PP
PP_LDO11 30 29
PP3127_RF
P2MM-NSM
PP3174_RF
P2MM-NSM
12 11 10 8 7 6 4 3

27 5
RADIO_ON_L 32 31 BB_I2S_WS 8 27
PP3111_RF
P4MM-NSM
SM SM SM
1 BT_PCM_IN 1 STOCKHOLM_TO_SIM_SWP 25 8 BB_DEBUG_ERROR 34 33 BB_I2S_RXD 8 27 1 SPMI_DATA 5 7
PP PP PP
WIFI_BT STOCKHOLM RF_PMIC_RESET_L 36 35 BB_I2S_TXD
PP3129_RF
P2MM-NSM
27 5

5 PS_HOLD_PMIC 38 37
8 27
PP3112_RF
P4MM-NSM
PP3128_RF SM
1 40 39
SM
1 SPMI_CLK
P2MM-NSM PP
45_BBPMU_TO_STOCKHOLM_19P2M_CLK 5 25 7 5 PMIC_RESOUT_L AP_TO_STOCKHOLM_FW_DWLD_REQ PP 5 7
SM STOCKHOLM
1 BT_PCM_OUT 42 41 AP_TO_STOCKHOLM_EN
PP
WIFI_BT
PP3185_RF
27 25 3

27 25 3
STOCKHOLM_UART_RXD
STOCKHOLM_UART_TXD 44 43 BB_OTHER_TXD
25 27

8 27
PP3104_RF
P4MM-NSM
P2MM-NSM 46 45
SM
1 MDM_CLK
SM
1 WLAN_JTAG_SWDCLK 27 25 3 STOCKHOLM_UART_CTS BB_OTHER_RXD 8 27 5 7

C
PP

C PP3173_RF
PP
WIFI_BT
24
27 25 3 STOCKHOLM_UART_RTS 48 47 BB_COEX_UART_RXD 8 24

P2MM-NSM PP3186_RF 27 25 3
STOCKHOLM_TO_PMU_HOST_WAKE 50 49 BB_COEX_UART_TXD 8 24
SM
1 HOST_WAKE_BT P2MM-NSM
SM
PP
WIFI_BT 1 WLAN_JTAG_SWDIO 24
PP
WIFI_BT 54 52

PP3152_RF
P2MM-NSM
SM
1 WAKE_BT 24 27 PP3192_RF
CORONA PCIE RX/TX TP
PP
WIFI_BT P2MM-NSM
SM 90_WLAN_PCIE_RDN
PP3153_RF 1 24 27
PP
P2MM-NSM WIFI_BT
SM
1 WLAN_REG_ON
PP3193_RF
PP 24 27 P2MM-NSM
WIFI_BT SM
1 90_WLAN_PCIE_RDP 24 27
PP3154_RF PP3194_RF
PP
WIFI_BT
P2MM-NSM P2MM-NSM
SM SM
1 BT_REG_ON 24 27 1 90_WLAN_PCIE_TDN 24 27
PP PP
WIFI_BT WIFI_BT
PP3195_RF
PP3155_RF P2MM-NSM
P2MM-NSM SM
1 90_WLAN_PCIE_TDP
SM PP 24 27
1 HOST_WAKE_WLAN 24 27
WIFI_BT
PP
WIFI_BT

PP3157_RF
P2MM-NSM
SM
1 WLAN_UART_RTS_L PP3196_RF
PP 24 27 P2MM-NSM
WIFI_BT SM
PP3158_RF 1 BB_UART_TXD 8 27
PP
P2MM-NSM
SM
1 WLAN_UART_CTS_L 24 27
PP
WIFI_BT PP3197_RF
P2MM-NSM
SM
PP3162_RF 1 BB_UART_RXD 8 27
PP
P2MM-NSM
SM
1 WLAN_UART_RXD
PP
WIFI_BT
24 27

PP3198_RF SIM CARD ESD PROTECTION VR3101_RF


ESD5004
B PP3163_RF
P2MM-NSM
SM
P2MM-NSM
SM
1 BB_UART_CTS_L
LGA-1 B
1 WLAN_UART_TXD 24 27
PP 8 27
8 3
BB_SIM_DATA 1
PP
WIFI_BT
DZ3102_RF
PP3170_RF 5.5V-6.2PF 8 3
BB_SIM_RESET 2
P2MM-NSM PP3199_RF
SM
1
RFFE1_CLK P2MM-NSM BB_SIM_DETECT 1 2
STOCKHOLM_TO_SIM_SWP
8 12 13 14 15 16 17 SM
1 8 3 3
PP
PP
BB_UART_RTS_L 8 27

PP3171_RF 0201 8 3
BB_SIM_CLK 4
P2MM-NSM
SM RFFE1_DATA

2
1 NP0-C0G
PP 8 12 13 14 15 16 17
C3102_RF
100PF
01005
5%
PP3172_RF

5
10V

1
P2MM-NSM
SM RFFE2_CLK
1 8 18 19 21
PP

PP_LDO11
12 11 10 8 7 6 4 3

RADIO_BB RADIO_BB RADIO_BB


SIM CARD CONNECTOR PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD

PART NUMBER
1 1 1
R3102_RF R3103_RF R3104_RF TABLE_ALT_ITEM

10K 10K 10K 25 6 4 3 PP_LDO5 377S0163 371S00044 ALTERNATE VR3101 ESD ALTERNATIVE
1% 1% 1%
1/32W 1/32W 1/32W 1
MF MF MF 1 C3101_RF
01005 2 01005 2 01005 2 R3101_RF 2.2UF
8 BOOT_HSIC
15.00K
1%
20%
2 6.3V
1

1/32W X5R-CERM
BOOT_HSIC_USB MF 0201
8 VCC
A 8 WATCHDOG_DISABLE J3101_RF 2 01005
SYNC_MASTER=N/A SYNC_DATE=N/A A
41 36
BB_SIM_RESET 2 RST SIM-CARD-N48 I/O 7 BB_SIM_DATA 36 41
PAGE TITLE
IN F-ST-SM BI
XW3101_RF
SHORT-10L-0.1MM-SM
AP INTERFACE & DEBUG CONNECTORS
BB_SIM_CLK 3 CLK DETECT 12 BB_SIM_DETECT DRAWING NUMBER SIZE
VREG_SMPS1_0V90 1 2 ADC_SMPS1 41 36 IN OUT 36 41
6 4

XW3102_RF
OUT 33 60

Apple Inc.
051-00648 D
SHORT-10L-0.1MM-SM SWP 6 STOCKHOLM_TO_SIM_SWP BI 36 58 REVISION
GND
12 11 10 8 7 6 4 3
PP_LDO11 1 2 ADC_PP_LDO11
OUT 33 60
R
4.0.0
8
9
10
11
13
5

XW3103_RF NOTICE OF PROPRIETARY PROPERTY: BRANCH


SHORT-10L-0.1MM-SM
THE INFORMATION CONTAINED HEREIN IS THE
25 6 4 3
PP_LDO5 1 2 ADC_PP_LDO5
OUT 33 60 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
XW3104_RF
SHORT-10L-0.1MM-SM I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
31 OF 55
4
VREG_SMPS4_2V075 1 2 ADC_SMPS4
OUT 33 60 SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 36 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND PMU (1 OF 2)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

SWITCHERS OUTPUT CAPS


VREG_SMPS1_0V90 VREG_SMPS2_1V25
D RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC D
1 C3229_RF 1 C3231_RF 1 C3237_RF 1 C3239_RF

6 4 3

4
20UF
20%
20UF
20%
20UF
20%
20UF
20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM-X5R CERM-X5R CERM-X5R CERM-X5R
FOOTPRINT SAME AS 138S0716 0402 0402 0402 0402
27 25 24 13 4 PP_VCC_MAIN

RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC


1 C3270_RF 1 C3224_RF 1 C3223_RF 1 C3222_RF 1 C3216_RF 1 C3221_RF
100PF
5%
2.2UF
20%
2.2UF
20%
2.2UF
20%
15UF
20% 20%
15UF
2
16V
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
NP0-C0G X5R-CERM X5R-CERM X5R-CERM X5R X5R
01005 0201 0201 0201 0402-1 0402-1
VREG_SMPS3_0V95 VREG_SMPS4_2V075 3 4

RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC


1 C3230_RF 1 C3232_RF 1 C3238_RF 1 C3240_RF

4
20UF
20%
20UF
20%
20UF
20%
20UF
20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM-X5R CERM-X5R CERM-X5R CERM-X5R
0402 0402 0402 0402

C VREG_RF_CLK_BYP C
SWITCHERS BULK CAPS AVDD_BYP
1 RADIO_PMIC
C3228_RF
REF_BYP
FOOTPRINT SAME AS 138S0716 U_PMICRF_RF 1.0UF
20%
PM8019 2 10V
1 RADIO_PMIC
C3227_RF BGA X5R-CERM
1 RADIO_PMIC
C3226_RF 0201-1
0.1UF SYM 5 OF 5
1.0UF
20%
20%
4V
26 VDD_INT_BYP VREG_RFCLK 91
PP_VCC_MAIN VBATT_S1 2 X5R
2 10V 21 VREG_XO 74
60 46 37 33 IN 4
58 57 MAKE_BASE=TRUE
X5R-CERM 01005 REF_BYP REG VREG_XO_PMIC
15 L3201_RF
VBATT_S1 0201-1
GND_REF
VREG_S1 27
4 2.2UH-20%-1.5A-0.16OHM
MAKK2016-SM 1235MA
VBATT_S1 22 VDD_S1 VSW_S1_1 11
PP_VSW_S1 1 2 VREG_SMPS1_0V90
1 C3217_RF 4

VSW_S1_2 16
VOLTAGE=4.50V
OUT 36 37 39

15UF 4 VBATT_S2 88 VDD_S2 L3203_RF


20%
94 VREG_S2 82
2.2UH-20%-1.5A-0.16OHM
2 6.3V
X5R VDD_S2 MAKK2016-SM
PP_VSW_S2 1100MA
0402-1
47 VSW_S2 93 1 2 VREG_SMPS2_1V25 OUT 37
4 VBATT_S3 VDD_S3 VOLTAGE=4.50V L3204_RF
VREG_S3 62
2.2UH-20%-1.5A-0.16OHM
VBATT_S4 1 MAKK2016-SM 1350MA
60 46 37 33 IN
PP_VCC_MAIN VBATT_S2 4
4 VDD_S4
VSW_S3_1 53
PP_VSW_S3 1 2 VREG_SMPS3_0V95 OUT 37
MAKE_BASE=TRUE
58 57 VOLTAGE=4.50V
4 VREG_SMPS2_1V25 92 VDD_L1 VSW_S3_2 58
VBATT_S2 4 L3202_RF RADIO_PMIC
4 3 VREG_SMPS4_2V075 2 VDD_L2_3 VREG_S4 23
2.2UH-20%-1.2A-0.15OHM
PP_VSW_S4 550MA
1 C3218_RF 4 VDD_L7_8_11
VSW_S4_1 6
VOLTAGE=4.50V
1 2 0806 VREG_SMPS4_2V075 OUT 36 37
15UF VSW_S4_2 12
20% 4 3 VREG_SMPS4_2V075 77
2 6.3V VDD_L9 VREG_RX VOLTAGE=1.225V
X5R
0402-1 VREG_L1 86 PP_LDO1 OUT 39 43 44
72 VDD_L10 VOLTAGE=1.80V
VREG_L2 7 PP_LDO2 OUT 39

VREG_SMPS3_0V95 38 VDD_L12 VOLTAGE=1.80V


B VREG_L3 8
B
4
60 46 37 33 IN
PP_VCC_MAIN
MAKE_BASE=TRUE
VBATT_S3 4 PP_LDO3 OUT 38 39
58 57
VREG_SMPS4_2V075 85 VDD_XO_RFC VOLTAGE=3.075V
VREG_L4 68
4 3
VBATT_S3 4 PP_LDO4 OUT 39
49 GND VREG_SIM VOLTAGE=1.80V
VREG_L5 59 PP_LDO5
1 C3219_RF MDM_VREF_LPDDR2 52 VREF_DDR2
OUT 36 39 25

15UF 40 OUT
VREG_L6 48
20% NC
2 6.3V
6057
PP_VCC_MAIN 43 VIN_VPH1 VOLTAGE=1.90V
VREG_L7 10
X5R 37 33 IN
0402-1
46
58
PP_LDO7 OUT 39 41
54 VIN_VPH2 VREG_TX VOLTAGE=2.05V
VREG_L8 3 PP_LDO8 OUT 43 44

VOLTAGE=1.20V
60 46 37 33 IN
PP_VCC_MAIN
MAKE_BASE=TRUE
VBATT_S4 4 VREG_L9 71 PP_LDO9 OUT 39
58 57
VOLTAGE=0.90V
VBATT_S4 4 VREG_L10 83 PP_LDO10 OUT 39

VREG_IO VOLTAGE=1.80V
VREG_L11 9 PP_LDO11
1 C3220_RF VOLTAGE=0.95V
OUT 36 39 40 41 43 44 45 58

15UF VREG_L12 33 PP_LDO12 OUT 39


20%
2 6.3V VOLTAGE=2.95V
X5R
0402-1 VREG_L13 34 PP_LDO13 OUT 39 56

VOLTAGE=5.0V
VREG_L14 28 PP_LDO14_RFSW OUT 47 48 56

1 RADIO_PMIC RADIO_PMIC
C3201_RF 1 C3202_RF1
RADIO_PMIC 1 RADIO_PMIC 1 RADIO_PMIC 1 RADIO_PMIC
C3203_RF C3204_RF C3205_RF C3206_RF
RADIO_PMIC 1RADIO_PMIC 1RADIO_PMIC 1RADIO_PMIC 1 RADIO_PMIC 1RADIO_PMIC 1 RADIO_PMIC 1
1 C3208_RF C3209_RF C3210_RF C3211_RF C3212_RF C3213_RF C3214_RF
RADIO_PMIC
C3215_RF
1.0UF 10UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF 10UF 10UF 1.0UF 10UF 1.0UF 1.0UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 10V
X5R-CERM 2
6.3V
2
CERM-X5R
10V
X5R-CERM 2 10V
X5R-CERM
10V
2 X5R-CERM 10V
2 X5R-CERM 2 10V
X5R-CERM 2
6.3V
CERM-X5R 2
6.3V
CERM-X5R 2
6.3V
CERM-X5R 2 10V
X5R-CERM 2
6.3V
CERM-X5R 2 10V
X5R-CERM 2 10V
X5R-CERM
0201-1 0402-9 0201-1 0201-1 0201-1 0201-1 0201-1 0402-9 0402-9 0402-9 0201-1 0402-9 0201-1 0201-1

A A
BASEBAND PMU (1 0F 2)
PAGE TITLE

DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
32 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 37 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND PMU (2 OF 2)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C401
R411
L400
U404
BOARD_ID REVISION SKU_ID REVISION TABLE_ALT_HEAD

0.00V N69/69H PRE-PROTO 0.5V N69 PART NUMBER ALTERNATE FOR


PART NUMBER
BOM OPTION REF DES COMMENTS:

TABLE_ALT_ITEM

D
0.50V SPARE 1.1V N69H 197S0565

197S0598
197S0593

197S0593
ALTERNATE

ALTERNATE
Y3301_RF

Y3301_RF
XTAL 19MHZ

XTAL 19MHZ
TABLE_ALT_ITEM

D
0.70V N69/69H PROTO1
0.90V N69/69H PROTO2
1.10V N69/69H EVT1
1.30V N69/69H EVT2
1.40V SPARE
1.50V N69/69H DVT
1.60V SPARE
1.70V N69/69H PVT
RADIO_PMIC

Y3301_RF
19.2MHZ-10PPM-7PF-80OHM
2.0X1.6-SM
1 3 XTAL19M_IN U_PMICRF_RF
PM8019 RADIO_PMIC
RADIO_PMIC
PP_LDO3 4 2 BGA C3303_RF RADIO_PMIC
39 38 37 IN
1000PF R3309_RF
90
SYM 2 OF 5
64 1 2 1
100 2
C U_PMICRF_RF 84
XTAL_19M_IN
CLOCK
XO_OUT_A0 50_A0_PMCLK
50_PMIC_RF_CLK
50_RF_CLK OUT
C
2

XTAL19M_OUT XTAL_19M_OUT 67 45_BBPMU_TO_STOCKHOLM_19P2M_CLK10% 1% MF


XO_OUT_A1
R3305_RF 1/32W 01005
1/32W
01005

PM8019 OUT 6.3V


1%
MF

90.9K BGA XO_OUT_D0_EN 73 GND_XO X5R-CERM


40 IN
SLEEP_CLK 80 SLEEP_CLK_32K 01005
40
SYM 4 OF 5 OUT
1.10V(EVT) 39 13 RADIO_PMIC 79
1

5 BOARD_ID MPP_01 MPP_GPIO GPIO_01 NC BB_GPS_ENABLE R3308_RF XO_OUT_D0_EN 78


29 30 STOCKHOLM_TO_BBPMU_CLK_REQ XO_OUT_D0 MDM_CLK
CALCULATE BOARD_ID 5 5 SKU_ID MPP_02 GPIO_02 IN 36 58
PP_LDO3 1
100K 2 XO_THERM_Y1 57 XO_THERM
OUT 36 40

WITH 10M VDDPX_BIAS 18 MPP_03 GPIO_03 55 39 38 37 IN


PA_THERM1 42
39 OUT NC 1% 46 GND_XOADC NC
IN PARALLEL 44 MPP_04 GPIO_04 19 1/32W PA_THERM2 32 PA_CTL_QFE
NC NC MF
12
35 14 BB_BUA_SIM RADIO_PMIC
2

TO GND 41 OUT
VREF_DAC_BIAS MPP_05 GPIO_05 IN 41 01005 1 C3301_RF 37
BATT_ID_THERM
R3306_RF
1/32W
01005

24 MPP_06 GPIO_06 25 BB_FORCE_PWM


1%
MF

NC IN 33 36 60
1000PF
150K 10%
2 6.3V
X5R-CERM
1

01005

XO_GND
PP_LDO3 4 5 6 XW3301_RF
SHORT-10L-0.25MM-SM
1 2
1 RADIO_PMIC NOSTUFF
R3311_RF XW <2.0MM FROM XTAL GROUND PATCH
100K
1%
1/32W
MF
2 01005
OMIT_TABLE

SKU_ID 5

B B
2

R3312_RF
U_PMICRF_RF
1/32W
1%
MF

162K PM8019
01005 BGA
1

SYM 3 OF 5
5 GND_S1 GND 36
87 INPUT_PWR 40
GND_S2 GND
U_PMICRF_RF 63 GND_S3 GND 41
PM8019 17 GND_S4 GND 50
RADIO_PMIC BGA 51
R3301_RF SYM 1 OF 5 GND
1.00K 2 60
RADIO_ON_L 70 CBL_PWR* OPT 66 GND 60
BB_RST_L 1 36 33 IN
CONTROL NC
60 36 33 IN 31 PON_TRIG GND 61
1% MF GND 89 69
1/32W 01005
RADIO_PMIC 75 GND
PMIC_RESOUT_L PON_RST*
R3307_RF GND 56
40 36 OUT
20.0K 2
40 IN
PS_HOLD 1 3 PS_HOLD_PMIC 65 PS_HOLD GND 45
5% MF 20
1/32W 01005 36 33 IN
RF_PMIC_RESET_L RESIN*
60

40 36 SPMI_CLK 81 SPMI_CLK
BI
40 36 SPMI_DATA 76 SPMI_DATA
BI

A A
PAGE TITLE

BASEBAND PMU (2 OF 2) DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
33 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 38 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND (1 OF 3)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C538
R500
L500
U502
RADIO_BB
U_BB_RF
ASIC-MDM9625M-2
WLBGA (EBI1 PAD)
PP_LDO10 (MSM CORE) J15 SYM 5 OF 6 F19 PP_LDO9
39 37 IN VDD_CORE VDD_P1 IN 37 39
K14 PWR RADIO_BB
D K15
VDD_CORE
VDD_CORE
VDD_P1
VDD_P1
L19
L20 U_BB_RF
D
L13 VDD_CORE VDD_P1 M1 ASIC-MDM9625M-2
L14 VDD_CORE VDD_P1 T19 WLBGA
A2 GND GND M10
M8 VDD_CORE (SDC1 PAD) SYM 6 OF 6
M9 VDD_P2 B20 PP_LDO13 IN 37 39 56
A20 GND GND M11
VDD_CORE C14 GND M14
M12 VDD_CORE VDD_P3 B2 (GENIO PAD)
PP_LDO11 GND GND
IN 36 37 39 40 41 43 44 45 58 C20 GND GND M15
M13 VDD_CORE VDD_P3 J19
E14 GND GND M20
N7 VDD_CORE VDD_P3 K2
F12 GND GND N1
N8 VDD_CORE VDD_P3 V2
F13 GND GND N6
N11 VDD_CORE VDD_P3 V5
F14 GND GND N9
N12 VDD_CORE VDD_P3 V19
F20 GND GND N10
P7 VDD_CORE
P10 VDD_P4 R19 NC (UIM1 PAD) G7 GND GND N13
VDD_CORE G11 N14
P11 GND GND
VDD_CORE VDD_P5 U19 PP_LDO5 IN 36 37 (UIM2 PAD) G12 P6
25 GND GND
(MSM MEMORY) E15
39 37 IN
PP_LDO12 VDD_MEM VDD_P6 V9 PP_LDO9 IN 37 39 (HSIC PAD) H6 GND GND P8
F8 VDD_MEM H7 GND GND P9
F9 VREF_SDC A19 VDDPX_BIAS IN 38 39 H10 P12
VDD_MEM GND GND
F15 VREF_UIM U20 H11 R20
VDD_MEM GND GND
G8 VDD_MEM VDD_USB_CORE V13 PP_LDO12 37 39
H14 GND GND T20
IN
K10 VDD_MEM H15 GND GND V20
L9 VDD_USB_1P8 U11 PP_LDO2 IN 37 39 J1 W1
VDD_MEM GND GND
L10 VDD_MEM VDD_USB_3P3 V10 PP_LDO4 37
J6 GND GND W5
IN
N15 VDD_MEM J9 GND GND W9
P14 VDD_A2 C12 PP_LDO7 IN 37 39 41 J10 W20
VDD_MEM GND GND
P15 VDD_A2 C9 J13 W12
VDD_MEM GND GND
R7 B12 J14 A12
C R8
VDD_MEM
VDD_MEM
VDD_A2
VDD_A1 B9 PP_LDO1 IN 37 39 43 44
K8
GND
GND
GND
GND A6 C
VDD_A2 C6 K9 GND E12
E5 GND
VDD_MEM B6 K12 E9
VDD_A1 GND GND
(MODEM SUB SYSTEM)F6
VREG_SMPS1_0V90 K13 A9
VDD_MODEM GND GND
VDD_A1 B15
39 37 36 IN
F7 PP_LDO1 IN 37 39 43 44 K19 E6
VDD_MODEM GND GND
F10 VDD_MODEM VDD_PLL U13 PP_LDO10 37 39
K20 GND GND A17
IN
F11 VDD_MODEM VDD_PLL R12 L1 GND GND C17
G6 VDD_MODEM VDD_PLL D17 L7 GND GND B17
G9 VDD_MODEM VDD_PLL2 E16 PP_LDO3 37 38 39
L8 GND GND P13
IN
G10 VDD_MODEM L11 GND GND R13
G13 VDD_ALWAYS_ON T17 NC L12 R14
VDD_MODEM GND GND
(LPDDR2)
G14 VDD_MODEM VDD_DDR_CORE_1P8 J20 PP_LDO11 L15 GND
GND A15
IN 36 37 39 40 41 43 44 45 58
G15 VDD_MODEM VDD_DDR_CORE_1P8 K1 M6 GND
H8 VDD_MODEM (LPDDR2_CORE) M7 GND
VDD_DDR_CORE_1P2 E20 PP_LDO9
H9 VDD_MODEM
IN 37 39

VDD_DDR_CORE_1P2 H1
H12 VDD_MODEM
VDD_DDR_CORE_1P2 P1
H13 VDD_MODEM
VDD_DDR_CORE_1P2 P20
J7 VDD_MODEM
J8 (QFUSE PROGRAMMING)
VDD_MODEM VDD_QFPROM_PRG W8 PP_LDO3 IN 37 38 39
J11 VDD_MODEM
J12 VDD_MODEM
K6 VDD_MODEM
K7 VDD_MODEM
K11 VDD_MODEM
L6 VDD_MODEM

B B
(MSM CORE) (EBI1 PAD) (HSIC PAD) (USB 1.8V) (GPS ADC) (LPDDR2)
RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB
39 37 IN
PP_LDO10 39 37 IN
PP_LDO9 39 37 IN
PP_LDO9 39 37 IN
PP_LDO2 44 43 39 37 IN
PP_LDO1 45 44 43 41 40 39 37 36 IN
PP_LDO11
RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB 58 RADIO_BB
1 C3401_RF 1 C3404_RF 1 C3407_RF 1 C3410_RF 1 C3413_RF 1 C3416_RF 1 C3419_RF 1 C3422_RF 1 C3424_RF 1 C3427_RF 1 C3430_RF 1 C3432_RF 1 C3435_RF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.1UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V
X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R X5R-CERM X5R-CERM
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 01005 0201 0201
NOSTUFF
(MSM MEMORY) (SDC1 PAD) (SDC/UIM) (COMBO DAC/BBRX) (PLL) (LPDDR2 CORE)
RADIO_BB RADIO_BB NOSTUFF RADIO_BB RADIO_BB RADIO_BB RADIO_BB
39 37 IN
PP_LDO12 56 39 37 IN
PP_LDO13 39 38 IN
VDDPX_BIAS 41 39 37 IN
PP_LDO7 39 37 IN
PP_LDO10 39 37 IN
PP_LDO9
RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB
1 C3402_RF 1 C3405_RF 1 C3408_RF 1 C3411_RF 1 C3414_RF 1 C3417_RF 1 C3420_RF 1 C3425_RF 1 C3428_RF 1 C3433_RF 1 C3436_RF 1 C3438_RF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.1UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V
X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R X5R-CERM X5R-CERM X5R-CERM X5R-CERM
0201 0201 0201 0201 0201 0201 0201 01005 0201 0201 0201 0201
NOSTUFF NOSTUFF
(PLL) (QFUSE)
(MODEM SUB SYSTEM) (GENIO PAD) (USB CORE) (BBRX) RADIO_BB
PP_LDO3 RADIO_BB
PP_LDO3
RADIO_BB RADIO_BB RADIO_BB RADIO_BB 39 38 37 IN 39 38 37 IN
39 37 36 IN
VREG_SMPS1_0V90 45 44 43 41 40 39 37 36 IN
PP_LDO11 39 37 IN
PP_LDO12 44 43 39 37 IN
PP_LDO1 RADIO_BB RADIO_BB
58
RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB 1 C3434_RF 1 C3437_RF
1 C3403_RF 1 C3406_RF 1 C3409_RF 1 C3412_RF 1 C3415_RF 1 C3418_RF 1 C3421_RF 1 C3423_RF 1 C3426_RF 1 C3429_RF
2.2UF 2.2UF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 20%
4V
20%
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V 2 X5R-CERM 2 4V
X5R-CERM
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 0201 0201
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 NOSTUFF

A A
PAGE TITLE

BASEBAND (1 OF 2) DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
34 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 39 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND (2 OF 3)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C600
R606
L600
U602

D D

PP_LDO11
26 11 9 7

U3501_RF
74AUP1G34GX
5

SOT1226
60 33 BB_JTAG_TCK 2 4
IN
NC
1

C C
NC

RADIO_BB

U_BB_RF
ASIC-MDM9625M-2
W14 WLBGA
38 36 IN
PMIC_RESOUT_L RESIN* RESOUT* V17 NC RADIO_BB
SYM 1 OF 6
BB_JTAG_RST_L N2 SRST* PS_HOLD W18 PS_HOLD
36 IN
SLEEP_CLK_32K W17 SLEEP_CLK
DIGITAL
OUT 38

RADIO_BB
U_BB_RF
TDO P5 ASIC-MDM9625M-2
38 IN
BB_JTAG_TDO OUT 36
R3505_RF
R2 WLBGA
BB_JTAG_TCK_IN TCK 240 2
P3 PMIC_SPMI_DATA W15 SPMI_DATA BI 36 38 1 EBI1_CAL R1 EBI1_CAL SYM 2 OF 6 EBI1_VREF N20 MDM_VREF_LPDDR2 IN 37 40
BB_JTAG_TDI TDI
PMIC_SPMI_CLK V15 EBI1_VREF M5
36 IN
P2 SPMI_CLK BI 36 38 1% MF G1 EBI1_EBI2
BB_JTAG_TMS TMS 1/32W 01005 BDM_ZQ EBI1_ZQ
EBI1_VREF R16
60 36 33 IN
36 BB_JTAG_TRST_L T4 TRST* HSIC_CAL U9 BB_HSIC_CAL
IN
RADIO_BB F18 H20
R11 HSIC_DATA U10 50_BB_HSIC_DATA BI 33 36 60
1 RADIO_BB R3506_RF NC EBI2_CS* EBI2_AD_7 NC
MODE_0 R3502_RF F16 H19
NC
R9 HSIC_STROBE R10 50_BB_HSIC_STROBE 240 2 EBI2_CLE* EBI2_AD_6
NC MODE_1
BI 33 36 60
240
1%
1 NC
G20 EBI2_ALE* EBI2_AD_5 H18
NC

W19 UIM1_RESET M19 NC 1/32W 1% MF NC


G19 H16
NC
MDM_CLK CXO MF 1/32W 01005 EBI2_WE* EBI2_AD_4
UIM1_CLK N18 NC NC NC
40 38 36 IN
XO_OUT_D0_EN V18 CXO_EN 2 01005 G18 EBI2_OE* EBI2_AD_3 J18
UIM1_DATA P19 NC NC NC
38 OUT
G16 EBI2_BUSY* EBI2_AD_2 K18
N19 UIM1_DETECT NC NC
NC SDC1_DATA_3 B18 NC EBI2_AD_1 J16
NC
B19 SDC1_CMD SDC1_DATA_2 A18 NC EBI2_AD_0 K16
NC NC
NC
C19 SDC1_CLK SDC1_DATA_1 D20 NC
U12 SDC1_DATA_0 D19 NC
60 36 33 IN
BB_USB_VBUS USB_HS_VBUS
V12 USB_HS_ID USB_HS_DP V11 90_BB_USB_P
NC BI 33 36 60

B 7 5 3 MDM_CLK W13 USB_HS_SYSCLK USB_HS_DM W11


USB_HS_REXT W10
90_BB_USB_N
BB_USB_TRXTUNE
BI 33 36 60
B

1 RADIO_BB
R3501_RF
200
1% MDM_VREF_LPDDR2 4 7
1/32W
MF
2 01005 1 C3501_RF
1.0UF
20%
PP_LDO11 3 4 6 7 8 10 11 12 2
6.3V
X5R
0201-1
PP_LDO11 3 4 6 7 8 10 11 12
A1

VCC
1 1
U_EEP_RF R3507_RF R3508_RF
CAT24C08C4A 10K
1%
10K
1%
WLCSP 1/32W 1/32W
8 7 BB_EEPROM_SCL B1 SCL SDA B2 BB_EEPROM_SDA 7 8 MF MF
2 01005 2 01005

VSS
8 7 BB_EEPROM_SCL
A2

BB_EEPROM_SDA
A 8 7
A
PAGE TITLE

BASEBAND (1 OF 2) DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
35 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 40 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND (3 OF 3)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C704
R700
L700
U702

D D

PP_LDO11 3 4 6 7 8 10 11 12

RADIO_BB
1 RADIO_BB
R3601_RF
10K
1%
U_BB_RF
1/32W ASIC-MDM9625M-2
MF WLBGA
01005 2 R18 H5
36 OUT
BB_SIM_DATA GPIO_0 SYM 3 OF 6 GPIO_38 GSM_TXBURST_IND OUT 33 60

BB_SIM_DETECT BB_SIM_DETECT U18 GPIO_1 GPIO GPIO_39 H2 CTRL_FWD_REV


RADIO_BB
3 8 41 36 IN
BLSP1 NC
36 BB_SIM_RESET T18 GPIO_2 GPIO_40 H3 BB_IPC_GPIO1 33 60
IN OUT
U_BB_RF 36 OUT
BB_SIM_CLK P18 GPIO_3 GPIO_41 G3 UAT_SELECT
UAT_SELECT 23

ASIC-MDM9625M-2 BB_UART_TXD U15 GPIO_4 GPIO_42 G2 LAT_SELECT


60 36 33 OUT NC
WLBGA BB_UART_RXD U14 GPIO_5 GPIO_43 F1 BB_UAT_GPIO0
60 36 33 IN
BLSP2 GRFC NC
E11
SYM 4 OF 6 TX_DAC0_IREF C13 WTR_TX_IDAC OUT 41 42 60 36 33 IN
BB_UART_CTS_L V14 GPIO_6 GPIO_44 F2
NC BB_UAT_GPIO1
WTR_BB_PRX_I_P BBRX_IP_CH0
TX_DAC0_VREF E13 U16 D3
42 IN ANALOG VREF_DAC_BIAS BB_UART_RTS_L GPIO_7 GPIO_45 BB_UAT_GPIO3
WTR_BB_PRX_I_N C11 BBRX_IM_CH0
5 8 60 36 33 OUT NC
42 IN U3 GPIO_8 GPIO_46 C1
WTR_BB_PRX_Q_P E10 BBRX_QP_CH0 TX_DAC0_IP A14 WTR_BB_TX_I_P NC NC
42 IN OUT 42 U4 GPIO_9 GPIO_47 G5
WTR_BB_PRX_Q_N C10 BBRX_QM_CH0 TX_DAC0_IM B14 WTR_BB_TX_I_N NC BLSP3 NC
42 IN OUT 42 W2 GPIO_10 GPIO_48 F3
TX_DAC0_QP B13 WTR_BB_TX_Q_P NC NC
WTR_BB_DRX_I_P B11 BBRX_IP_CH1
OUT 42 V3 GPIO_11 GPIO_49 E3
42 IN
TX_DAC0_QM A13 WTR_BB_TX_Q_N NC NCWLAN_TX_BLANK
WTR_BB_DRX_I_N A11 BBRX_IM_CH1
OUT 42
BB_I2S_WS V7 GPIO_12 GPIO_50 F5
42 IN 60 36 33 OUT NC
WTR_BB_DRX_Q_P B10 BBRX_QP_CH1 TX_DAC1_IREF C8 PP_LDO7 BB_I2S_RXD V6 GPIO_13 GPIO_51 N5
42 IN 4 6 8 60 36 33 IN
BLSP4 NC
A10 TX_DAC1_VREF E8 W7 N3
C 42 IN
WTR_BB_DRX_Q_N
B5
BBRX_QM_CH1
A8
60 36 33

60 36 33
OUT

OUT
BB_I2S_TXD
BB_I2S_CLK U8
GPIO_14
GPIO_15
GPIO_52
GPIO_53 T3
BB_COEX_UART_TXD
BB_COEX_UART_RXD
OUT

IN
36 57

36 57
C
44 IN
WFR_BB_PRX_I_P BBRX_IP_CH2 TX_DAC1_IP M18 E2
A5 B8 NC GPIO_16 GPIO_54 WTR_SSBI_TX_GPS OUT 42
44 IN
WFR_BB_PRX_I_N BBRX_IM_CH2 TX_DAC1_IM M16 D1
B4 A7 NC GPIO_17 GPIO_55 WTR_SSBI_PRX_DRX IN 42
44 IN
WFR_BB_PRX_Q_P BBRX_QP_CH2 TX_DAC1_QP N16 BLSP5 SSBI D2
A4 B7 NC GPIO_18 GPIO_56 NC
44 IN
WFR_BB_PRX_Q_N BBRX_QM_CH2 TX_DAC1_QM L16 E1
NC GPIO_19 GPIO_57 WFR_SSBI OUT 44

WFR_BB_DRX_I_P C4 BBRX_IP_CH3 ET_DAC_M C7 ET_DAC_N BB_OTHER_TXD D18 GPIO_20 GPIO_58 T1


44 IN OUT 45 60 36 33 OUT NC BB_DEBUG_SYNC (DEV)
44 WFR_BB_DRX_I_N C5 BBRX_IM_CH3 ET_DAC_P E7 ET_DAC_P 45 60 36 33 BB_OTHER_RXD C18 GPIO_21 GPIO_59 R6 GSM_TX_PHASE_D1 42
IN OUT IN OUT
WFR_BB_DRX_Q_P B3 BB_EEPROM_SDA E19 BLSP6 R3 GSM_TX_PHASE_D0
44 IN BBRX_QP_CH3 V16 40 BI GPIO_22 GPIO_60 OUT 42
A3 DNC NC E18 U7
44 IN
WFR_BB_DRX_Q_N BBRX_QM_CH3 W16 40 BI
BB_EEPROM_SCL GPIO_23 GPIO_61 BB_CORE_DUMP IN 33 36 60
DNC NC P16 V8
C15 D4 60 36 33 OUT
BB_RESET_DET_L GPIO_24 GPIO_62 BB_DEBUG_STATUS OUT 36
42 IN
WTR_BB_GPS_I_P GNSS_BB_IP DNC NC L18 W4
C16 C3 60 33 IN
AP_WAKE_MODEM GPIO_25 GPIO_63 BB_DEBUG_ERROR OUT 36
42 IN
WTR_BB_GPS_I_N GNSS_BB_IM DNC NC L5 W3
B16 BB_LAT_GPIO0 NC GPIO_26 GPIO_64 NC BB_SWD_ENABLE
42 IN
WTR_BB_GPS_Q_P GNSS_BB_QP M3 U6
A16 BB_LAT_GPIO1 NC GPIO_27 GPIO_65 AP_TO_BB_MESA_ON BI 33 36 60
42 IN
WTR_BB_GPS_Q_N GNSS_BB_QM K3 T2
BB_LAT_GPIO2 NC GPIO_28 GPIO_66 BB_HOST_RDY IN 33 36 60

BB_LAT_GPIO3 L3 GPIO_29 GPIO_67 R15 BB_WAKE_HOST_L


NC OUT 33 36 60

BB_LAT_GPIO4 M2 GPIO_30 GPIO_68 V4 BB_DEVICE_RDY


NC OUT 33 36 60

BB_LAT_GPIO5 K5 GPIO_31 GPIO_69 U17 BB_BUA_SIM


NC GRFC IN 38
B1 GPIO_32 GPIO_70 V1 BB_GPS_SYNC
NC OUT 33 36 60
C2 GPIO_33 GPIO_71 W6
NC NC
36 WATCHDOG_DISABLE J5 GPIO_34 GPIO_72 U2 RFFE2_DATA 41 51 52 54
IN BI
36 BOOT_HSIC L2 GPIO_35 GPIO_73 U5 RFFE2_CLK 36 41 51 52 54
IN BI
BOOT_HSIC_USB J3 RFFE U1 RFFE1_DATA
36 IN GPIO_36 GPIO_74 BI 36 45 46 47 48 49 50
J2 GPIO_37 GPIO_75 R5 RFFE1_CLK
NC BI 36 45 46 47 48 49 50

9 8 WTR_TX_IDAC 8 5 VREF_DAC_BIAS
RADIO_BB RADIO_BB RADIO_BB
B 1 C3601_RF 1 C3603_RF 1 C3604_RF B
0.1UF
10%
2200PF
10%
2200PF
10%
2 6.3V
X7R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 01005 01005
PP_LDO7 NOSTUFF
8 6 4
U_BUFFER_RF
RF1352
WLCSP
21 19 18 17 16 14 13 8 RFFE_VIO 4 VIO GPO1 1 BB_LAT_GPIO1 33 60
OUT
GPO2 8 BB_LAT_GPIO2 OUT 33 60

21 19 18 8 3 RFFE2_CLK 2 SCLK SCLK_A 5 RFFE2_CLK_BUFFER 56


OUT

21 19 18 8 RFFE2_DATA 3 SDATA SDATA_A 6 RFFE2_DATA_BUFFER 56


OUT

GND

7
MAKE_BASE=TRUE
12 11 10 8 7 6 4 3 PP_LDO11 RFFE_VIO 8 13 14 16 17 18 19 21

VOLTAGE=1.80V

A A
PAGE TITLE
RFFE2_DATA
MOBILE DATA MODEM (2 OF 2) DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
1 C3602_RF REVISION

5%
22PF R
4.0.0
2 16V
CERM NOTICE OF PROPRIETARY PROPERTY: BRANCH
01005 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
36 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 41 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

WTR TRANSCEIVER (1 OF 2)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C802
R802
L800
U803

D D

U_WTR_RF U_WTR_RF
WTR1625 WTR1625
BGA BGA

50_B8_PRX_WTR_IN 102 PRX_LB1_IN SYM 1 OF 5 PRX_BB_IP 99 WTR_BB_PRX_I_P SYM 2 OF 5 RADIO_WTR


15 OUT 41
50_B8_B28B_DRX_WTR_IN 5 DRX_LB1_IN DRX_BB_IP 76 WTR_BB_DRX_I_P
LB1 DC PRX_BB_IM 108 WTR_BB_PRX_I_N LB1 DC
20 OUT
RADIO_WTR
50_B20_PRX_WTR_IN 92 PRX_LB2_IN
OUT 41
DRX_BB_IM 86 WTR_BB_DRX_I_N
15
PRX_BB_QP 107 WTR_BB_PRX_Q_P 50_B13_B17_DRX_WTR_IN 15 DRX_LB2_IN
OUT
RADIO_WTR
LB2 DC
OUT 41
LB2 DC
20
DRX_BB_QP 61 WTR_BB_DRX_Q_P
50_B26_PRX_WTR_IN 73 PRX_LB3_IN PRX_BB_QM 97 WTR_BB_PRX_Q_N OUT
RADIO_WTR
15 OUT 41
20 50_B26_B28A_DRX_WTR_IN 16 DRX_LB3_IN DRX_BB_QM 68 WTR_BB_DRX_Q_N 41
OUT
LB3 DC LB3 DC
14 50_B13_B17_B28_B29_PRX_WTR_IN65 PRX_LB4_IN 7 60 RADIO_WTR
20 50_B20_B29_DRX_WTR_IN DRX_LB4_IN GNSS_BB_IP WTR_BB_GPS_I_P OUT
LB4 DC
50_WFR_PRX_LB_CA_IN 91 LB4 DC 53 WTR_BB_GPS_I_N RADIO_WTR
44 OUT PRX_LB_CA_OUT 32 GNSS_BB_IM OUT
44 OUT
50_WFR_DRX_LB_CA_IN DRX_LB_CA_OUT 67 RADIO_WTR
MB1 NO DC 50 MB1 NO DC GNSS_BB_QP WTR_BB_GPS_Q_P OUT
44 IN
50_WFR_PRX_MB_CA_OUT PRX_MB_CA_IN 29 85 RADIO_WTR
44 IN
50_WFR_DRX_MB_CA_OUT DRX_MB_CA_IN GNSS_BB_QM WTR_BB_GPS_Q_N OUT 41
MB2 DC 51 MB2 DC 28
50_B34_B39_PRX_WTR_IN PRX_MB1_IN 50_B34_DRX_WTR_IN DRX_MB1_IN
DNC 37
18 20

MB3 DC MB3 DC NC
20 50_DCS_WTR_IN 43 PRX_MB2_IN 20 50_B39_DRX_WTR_IN 20 DRX_MB2_IN
HB1 NO DC 27 HB1 NO DC 1
20 50_PCS_WTR_IN PRX_MB3_IN NC DRX_MB3_IN
HB2 DC 19 HB2 DC 2
19 50_B40A_PRX_WTR_IN PRX_HMB4_IN 20 50_B40_DRX_WTR_IN DRX_HMB4_IN
HB3 DC HB3 DC 50_B38X_DRX_WTR_IN 4 DRX_HB1_IN
19 50_B40B_B38X_PRX_WTR_IN 9 PRX_HB1_IN
20

HBMB4 NO DC HBMB4 NO DC 50_B41A_DRX_WTR_IN 12 DRX_HB2_IN


19 50_B41A_PRX_WTR_IN 17 PRX_HB2_IN
20

50_B7_DRX_WTR_IN 13 DRX_HB3_IN
17 50_B7_PRX_WTR_IN 18 PRX_HB3_IN
20

30 DRX_HB_CA_OUT
33 NC
C NC PRX_HB_CA_OUT
22 100_GPS_WTR_IN_P 36 GNSS_RF_INP
C
22 100_GPS_WTR_IN_N 44 GNSS_RF_INM

U_WTR_RF
WTR1625
BGA
WTR_BB_TX_I_P 151 TX_BB_IP SYM 3 OF 5 TX_LB1_OUT 162
8
NC
8 WTR_BB_TX_I_N 160 TX_BB_IM TX_LB2_OUT 153 50_LB_2G_WTR_TX_OUT 13

8 WTR_BB_TX_Q_P 152 TX_BB_QP TX_LB3_OUT 163 50_B8_B26_B20_WTR_TX_OUT 15

8 WTR_BB_TX_Q_N 161 TX_BB_QM TX_LB4_OUT 154 50_B13_B17_B28_WTR_TX_OUT 14


WTR_TX_IDAC 127 DAC_REF
8
TX_MB1_OUT 146 50_B3_B4_WTR_TX_OUT 16

8 GSM_TX_PHASE_D0 123 GP_DATA0 TX_MB2_OUT 138 50_HB_2G_WTR_TX_OUT 13

8 GSM_TX_PHASE_D1 104 GP_DATA1 TX_MB3_OUT 139 50_B1_B25_B34_B39_WTR_TX_OUT 16

B RADIO_WTR
141 GND TX_MB4_OUT 155
NC B
94 GND TX_HB1_OUT 130 50_B7_WTR_TX_OUT
R3702_RF 17

1
4.75K2 WTR_RTUNE 71 RTUNE TX_HB2_OUT 121 50_B40_B38_B41_WTR_TX_OUT 17

1% 140
1/32W GND ADC_IN 109
MF
01005 55 GND PDET_RFFB 117 50_FWD_OR_REV_RF 18
118 GND
105 GND 122
8 WTR_SSBI_TX_GPS SSBI_TX_GNSS
8 WTR_SSBI_PRX_DRX 95 SSBI_PRX_DRX
156 GND
131 XO_IN

11 5 50_RF_CLK

A A
PAGE TITLE

RF TRANSCEIVER (1 0F 3) DRAWING NUMBER SIZE


RF_CLK IS SHARED BETWEEN WTR AND WFR. LENGTH DIFFERENCE BETWEEN THE TWO SHOULD BE < 5MM.
Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
37 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 42 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

WTR TRANSCEIVER (2 OF 2)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
XW3801_RF
C934
R926
L3802_RF
U902
11 4

6 4
11
PP_LDO8
MAKE_BASE=TRUE
PP_LDO1
MAKE_BASE=TRUE
XW3802_RF
VREG_2V_WTR
VREG_1P3V_WTR
10

10
WTR DECOUPLING CAPS
L3801_RF
RADIO_WTR 22NH-3%-0.25A
VREG_2V_WTR MAKE_BASE=TRUE VDD_DRX_BB_2V VREG_1P3V_WTR MAKE_BASE=TRUE 1 2 VDD_PRX_PLL_1P3V VREG_1P3V_WTR MAKE_BASE=TRUE VDD_PRX_LO_HB_1P3V
D
10 10 10 10 10

D WTR DECOUPLING SHARED WITH C3808_RF 0201


RADIO_WTR
RADIO_WTR
1 C3830_RF
RADIO_WTR
1 C3801_RF RADIO_WTR
1 C3808_RF 0.1UF
20%
10UF
20%
10UF
20% 2 4V
X5R U_WTR_RF
2 6.3V 6.3V
2 CERM-X5R 01005
90 WTR1625
CERM-X5R
0402-9 0402-9 10 VDD_PRX_VCO_1P3V VDD_RF1_P_VCO BGA
10 VDD_PRX_VCO_2V 80 VDD_RF2_P_VCO SYM 4 OF 5 VDD_RF2_T_DA 129 VDD_TX_DA_2V 10

VDD_TX_DA_2V 10 VDD_SHDR_PLL_1P3V 10 VDD_DRX_LB_1P3V 10 10 VDD_PRX_LO_HB_1P3V 25 VDD_RF1_P_HB_LO VDD_RF1_T_DA 137 VDD_TX_DA_1P3V 10

RADIO_WTR RADIO_WTR 72
1 C3813_RF 1 C3821_RF 10 VDD_PRX_LB_1P3V VDD_RF1_P_LB VDD_RF1_T_UPC 136 VDD_TX_UPC_1P3V 10

100PF
5%
0.1UF
20% 10 VDD_PRX_HBMB_1P3V 34 VDD_RF1_P_HMB VDD_RF1_T_LO 135 VDD_TX_LO_1P3V 10

2 10V 2 4V
NP0-C0G
01005
X5R
01005 10 VDD_PRX_LO_HBMB_1P3V 57 VDD_RF1_P_HMB_LO VDD_RF2_T_BB 126 VDD_TX_BBF_2V 10

10 VDD_PRX_PLL_1P3V 79 VDD_RF1_P_PLL VDD_RF2_FBRX 116 VDD_FBRX_2V 10


RADIO_WTR
RADIO_WTR VDD_PRX_BB_2V 10 10 VDD_PRX_BB_2V 98 VDD_RF2_P_BB VDD_RF2_T_VCO 157 VDD_TX_VCO_2V 10

VDD_TX_BBF_2V VDD_PRX_HBMB_1P3V VDD_PRX_LB_1P3V 100 VDD_RF1_T_VCO 149


10 10 10
MAKE_BASE=TRUE
10 VDD_PRX_2V VDD_RF2_P_RX VDD_TX_VCO_1P3V 10

10 VDD_DRX_LO1_1P3V 14 VDD_RF1_D_LB_LO VDD_RF1_T_SYN 115 VDD_TX_SYNTH_1P3V 10

10 VDD_DRX_LO2_1P3V 38 VDD_RF1_D_LOM VDD_RF2_T_PLL 114 VDD_TX_PLL_2V 10

10 VDD_DRX_LB_1P3V 31 VDD_RF1_D_LB VDD_RF1_G_LNA 52 VDD_GPS_LNA_1P3V 10

10 VDD_DRX_HB_1P3V 22 VDD_RF1_D_HB VDD_RF1_G_VCO 74 VDD_GPS_VCO_1P3V 10


I188
10 VDD_DRX_MB_1P3V 11 VDD_RF1_D_MB VDD_RF1_G_PLL 93 VDD_GPS_PLL_1P3V 10
NBC
VDD_PRX_VCO_2V 10 VDD_SHDR_VCO_1P3V VDD_DRX_LO2_1P3V 10

RADIO_WTR RADIO_WTR RADIO_WTR VDD_DRX_BB_2V 54 VDD_RF2_D_BB VDD_RF1_G_BB 59 VDD_GPS_BB_1P3V


1 C3815_RF
0.1UF
1 C3823_RF
0.1UF
1 C3833_RF
0.1UF 10 VDD_SHDR_VCO_1P3V 48 VDD_RF1_S_VCO GND 113
C
20% 20% 20%
2 4V 2 4V 2 4V VDD_SHDR_VCO_2V 62 VDD_RF2_S_VCO VDD_RF2_XO 147 VDD_XO_2V
X5R X5R X5R 10 10
01005 01005 01005
10 VDD_SHDR_PLL_1P3V 78 VDD_RF1_S_PLL VDD_DIO 103 VDD_MSM_1P8V 10

VDD_SHDR_VCO_2V 10 VDD_PRX_VCO_1P3V 10
VDD_DRX_LO1_1P3V 10

RADIO_WTR RADIO_WTR
1 C3816_RF 1 C3809_RF
0.1UF
20% DELETED C3805 PR REVIEW FEEDBACK 0.1UF
20%
2 4V
X5R 2 4V
X5R
01005 01005

VDD_TX_VCO_2V VDD_PRX_LO_HBMB_1P3V VDD_DRX_MB_1P3V


89 GND U_WTR_RF
10 10 10
56 GND WTR1625
RADIO_WTR RADIO_WTR 83 BGA GND 111
1 C3817_RF 1 C3806_RF GND
82 GND SYM 5 OF 5 GND 101
0.1UF
20%
0.1UF
20% 58 GND
2 4V
X5R 2 4V
X5R GND 110
01005 01005 35 GND
GND 145
8 GND
GND 144
26 GND
GND 143
64 GND
VDD_TX_PLL_2V VDD_TX_SYNTH_1P3V VDD_DRX_HB_1P3V GND 128
10 10 10
42 GND
RADIO_WTR GND 120
41 GND
1 C3824_RF GND 119
B 0.1UF
20%
81 GND
GND 106 B
2 4V 21 GND GND 150
X5R
01005 6 GND GND 134
24 GND
GND 159
39 GND
GND 142
VDD_XO_2V 10 VDD_TX_LO_1P3V 10 VDD_GPS_LNA_1P3V 10 10 GND GND 125
RADIO_WTR RADIO_WTR RADIO_WTR MAKE_BASE=TRUE 3 GND GND 124
1 C3803_RF 1 C3825_RF 1 C3828_RF 23 GND GND 148
0.1UF
10%
0.1UF
20%
0.1UF
20%
46 GND GND 158
2 10V 2 4V VDD_GPS 2 4V GND 133
X5R-CERM X5R MAKE_BASE=TRUE X5R 49 GND
0201 01005 01005 GND 112
69 GND
GND 132
88 GND
70 GND GND 45
VDD_FBRX_2V 10 VDD_TX_UPC_1P3V 10 VDD_GPS_BB_1P3V 10 63 GND GND 66
RADIO_WTR RADIO_WTR 40 GND GND 84
I175 1 C3818_RF 1 C3826_RF VDD_GPS_PLL_1P3V GND 75
10 47 GND
VDD_PRX_2V 10 0.1UF 100PF RADIO_WTR MAKE_BASE=TRUE
87
20% 5%
1 C3829_RF GND GND 164
2 4V
X5R 2 10V
NP0-C0G 77
01005 01005 0.1UF GND
20%
RADIO_WTR 96 GND
2 4V
X5R
XW3803_RF 01005

12 11 8 7 6 4 3 PP_LDO11 MAKE_BASE=TRUE VDD_MSM_1P8V 10 VDD_TX_VCO_1P3V 10

RADIO_WTR
1 C3811_RF 1 C3807_RF VDD_GPS_VCO_1P3V 10

A 1.0UF
10%
0.1UF
20% A
2 6.3V
X5R-CERM 2 4V
X5R PAGE TITLE
0201-1
RADIO_WTR
L3802_RF
01005
RF TRANSCEIVER (2 OF 3) DRAWING NUMBER SIZE
8.2NH-3%-0.19A-1.6OHM
Apple Inc.
051-00648 D
1 2 VDD_TX_DA_1P3V 10 REVISION
01005 R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
38 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 43 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

WFR TRANSCEIVER
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C1019
R1016
L1000
U1002
XW3900_RF
10 4 PP_LDO8
MAKE_BASE=TRUE
VREG_2V_WFR 11
U_WFR_RF
WFR1620
D BGA GND 1 D
MB1 DC SYM 1 OF 2
16 50_B3_PRX_WFR_IN 22 PRX_MB1_IN GND 61
RX_OTHER
MB2 NO DC 50_B1_B4_PRX_WFR_IN 16 PRX_MB2_IN
SSBI_PRX_DRX 13
16
6 WFR_SSBI 8
16 50_B25_PRX_WFR_IN PRX_MB3_IN
XW3901_RF MB3 DC 34
27 GND
4 PP_LDO1 PPLDO1_WFR VDD_DIG_1P3V VREG_2V_WFR VDD_PRX_VCO_WFR_2V 50_WFR_PRX_HB_CA_IN PRX_HB_CA_IN
11 MAKE_BASE=TRUE
10 6 11 11
NC
PRX_MB_CA_OUT 5
MAKE_BASE=TRUE MAKE_BASE=TRUE
RADIO_WFR RADIO_WFR 3 50_WFR_PRX_MB_CA_OUT OUT 42
1 C3904_RF 1 C3912_RF 42 IN
50_WFR_PRX_LB_CA_IN PRX_LB_CA_IN
0.1UF RADIO_WFR
1 C3903_RF 0.1UF MB1 DC 49 DRX_MB_CA_OUT 65 50_WFR_DRX_MB_CA_OUT OUT 42
1 RADIO_WFR 20% 20% 20 50_B25_DRX_WFR_IN DRX_MB1_IN
C3901_RF
10UF
4V
2 X5R 10UF
20% 2 4V
X5R MB2 NO DC 20 50_B1_B4_DRX_WFR_IN 54 DRX_MB2_IN PRX_BB_IP 29 WFR_BB_PRX_I_P 8
20% 01005 6.3V
2 CERM-X5R 01005 50_B3_DRX_WFR_IN 66 DRX_MB3_IN PRX_BB_IM 28 WFR_BB_PRX_I_N
2 6.3V
20 8
MB3 DC 25
CERM-X5R
0402-9
0402-9
43 PRX_BB_QP WFR_BB_PRX_Q_P 8
NC DRX_HB_CA_IN 30
PRX_BB_QM WFR_BB_PRX_Q_N 8
RADIO_WFR
50_WFR_DRX_LB_CA_IN 36
42IN DRX_LB_CA_IN 62
VDD_DRX_LO_1P3V 11 VDD_XO_WFR_2V 11 DRX_BB_IP WFR_BB_DRX_I_P 8

RADIO_WFR RADIO_WFR RADIO_WFR 52 GND DRX_BB_IM 63 WFR_BB_DRX_I_N 8


1 C3905_RF 1 C3913_RF DRX_BB_QP 57 WFR_BB_DRX_Q_P
R3901_RF WFR_RTUNE 19 R_TUNE
8
0.1UF
20%
0.1UF
20% 4.75K2 DRX_BB_QM 64 WFR_BB_DRX_Q_N 8
1
2 4V
X5R
4V
2 X5R 1%
7 XO_IN
01005 01005 1/32W
MF
01005

VDD_DRX_LB_WFR_1P3V 11

9 5 50_RF_CLK

C C
I113
VDD_DRX_MB_HB_FE_1P3V 11 VDD1_DRX_BB_2V 11

RADIO_WFR
1 C3915_RF
0.1UF
20%
2 4V
X5R
01005
U_WFR_RF
WFR1620
I114 BGA
VDD_PRX_MBHB_FE_1P3V 11 VDD1_PRX_BB_2V 11
37
11 VDD_PRX_VCO_WFR_2V VDD_RF2_P_VCO SYM 2 OF 2 GND 46
RADIO_WFR PWR_GND
1 C3916_RF 11 VDD_PRX_VCO_WFR_1P3V 33 VDD_RF1_P_VCO GND 35
0.1UF 31
20% VDD_PRX_LO_WFR_1P3V VDD_RF1_P_LO GND 42
2 4V
11
X5R
01005 11 VDD_PRX_PLL_WFR_1P3V 44 VDD_RF1_P_PLL GND 53

11 VDD_PRX_LB_FE_1P3V 15 VDD_RF1_P_LB_FE GND 20

11 VDD1_PRX_BB_2V 23 VDD_RF2_P_BB GND 51


VDD_PRX_LB_FE_1P3V 11

11 VDD_PRX_MBHB_FE_1P3V 10 VDD_RF1_P_MHB_FE GND 41

11 VDD_DRX_LO_1P3V 47 VDD_RF1_D_LO GND 45

11 VDD1_DRX_BB_2V 56 VDD_RF2_D_BB GND 50

B GND 18 B
11 VDD_DRX_LB_WFR_1P3V 39 VDD_RF1_D_LB_FE GND 9
XW3902_RF
VDD_PRX_VCO_WFR_1P3V 11 12 10 8 7 6 4 3 PP_LDO11 VDD1_1P8V 11 11 VDD_DRX_MB_HB_FE_1P3V 59 VDD_RF1_D_MHB_FE GND 11
RADIO_WFR MAKE_BASE=TRUE
RADIO_WFR 24
1 C3910_RF 1 C3917_RF 11 VDD_DIG_1P3V VDD_RF1_DIG GND 21
0.1UF
20%
0.1UF
20%
14 GND GND 32
2 4V
X5R 2 4V
X5R 2
01005 01005 11 VDD1_1P8V VDD_DIO GND 4

11 VDD_XO_WFR_2V 17 VDD_RF2_XO GND 38

GND 55
VDD_PRX_PLL_WFR_1P3V
GND 40
11

RADIO_WFR
1 C3911_RF GND 60
0.1UF
20% GND 48
2 4V
X5R
01005 GND 58

GND 26

GND 8
VDD_PRX_LO_WFR_1P3V 11

RADIO_WFR GND 12
1 C3902_RF
0.1UF
20%
2 4V
X5R
01005
A A
PAGE TITLE

RF TRANSCEIVER (3 OF 3) DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
39 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 44 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

QFE DCDC
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C1110
R1102
L1104
U1101

D D

XW4001_RF
SHORT-10L-0.25MM-SM
27 21 19 18 12 PP_BATT_VCC 1 2 VBATT_SW 12
L4002_RF U_QPOET_RF
NOSTUFF RADIO_QPOET 22-OHM-25%-1800MA QFE1100
SHOULD BE PLACED PP_BATT_VCC QPOET_BATT BGA PP_BATT_VCC
MAX 0.25MM AWAY 1 C4001_RF 1 2 14 BYP_BATT VDD_BATT 15
FROM QPOET 27 21 19 18 12 12 18 19 21 27
10UF 17 16 15 14 12 VPA_ET 0201 10 BYP_LOAD VDD_BATT 16
20%
XW4002_RF 2 6.3V
SHORT-10L-0.25MM-SM CERM-X5R 12 VBATT_SW 28 VDD_BUCK VDD_AMP 5 APT_VINPUT 12
1 2 0402-9
SW_GROUND 12
SW_GROUND 27 GND_BUCK VDD_1P8 17 PP_LDO11
NOSTUFF 12 3 4 6 7 8 10 11 12
BOTH XW'S
7 QPOET_VSW 1.5UH-1.95A-0.111OHM
> 1.0MM
TO CREATE 41 IN
ET_DAC_P AMP_INP VSW_BUCK 23 1 2
PSB25201T-SM
INDUCTANCE ET_DAC_N 2 AMP_INM L4003_RF
RADIO_QPOET
AMP_OUT 4
41 IN
VPA_ET 12 14 15 16 17 15 14 12 VPA_ET
17 16
RFFE1_DATA 26 SDATA
C_BUCK 11
50 49 48 47 46 41 36 BI
VPA_APT 12 VPA_APT
13 17
RFFE1_CLK 21 SCLK C_BUCK 12
RADIO_QPOET
50 49 48 47 46 41 36 BI RADIO_QPOET 1 C4008_RF
1 C4007_RF
PA_CTL_QFE 13 MPP1 C_SW_BUCK 8 470PF
5
BST_L 4.7UF 10% X5R
C_SW_BUCK 9 20% 2 10V 01005
C 27 21 19 18 12
PP_BATT_VCC 1 2 20 VSW_BOOST 2 10V
X5R-CERM VPA_ET_FILTER C
C_GSM 6
0805 0402
2.2UH-20%-0.7A-0.23OHM 19 GSM_CAP 12 GSM_CAP 1 RADIO_QPOET
USID_LSB (USID) R4001_RF
PA_VBAT 18
RADIO_QPOET
22 VPA_BATT 14 15 16 2.2
GND 17 RADIO_QPOET RADIO_QPOET 5%
CRITICAL TO STAY
24 GND_BOOST
VOUT_BOOST 25 VOUT_BOOST 12
1 C4005_RF @ 4.7UF TO MEET
QPOET TIMING
1/32W
MF
20UF 2 01005
L4001_RF GND 1 20%
2 6.3V
CERM-X5R
PP_BATT_VCC 12 18 19 21 GND_AMP 3 0402
27 (CAN BE CHANGED TO 20UF)
RADIO_QPOET
1 C4010_RF
VOUT_BOOST_GND 12
470PF
10% X5R
10V 01005
2
MITIGATE RX1 DESENSE
IN VLB (B13)

B B
BOOST FILTER
I/O @ 1.8V
L4004_RF
22-OHM-25%-1800MA
12 11 10 8 7 6 4 3 PP_LDO11 12 VOUT_BOOST 1 2 APT_VINPUT 12

0201
1 C4002_RF
RADIO_QPOET 1 RADIO_QPOET
C4003_RF 1 RADIO_QPOET
C4006_RF
10UF 10UF 10UF
20% 20% 20%
2 6.3V
CERM-X5R
6.3V
2 CERM-X5R 6.3V
2 CERM-X5R
0402-9 0402-9 0402-9

12 VOUT_BOOST_GND

2
XW4004_RF
SHORT-10L-0.25MM-SM
NOSTUFF
1

A A
PAGE TITLE

QFE DCDC DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
40 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 45 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

2G PA
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C1208
R1200
L1204
U1201

D D

R4100_RF
600-OHM-25%-0.1A
27 25 24 4 PP_VCC_MAIN 1 2 2G_PA_VBATT_10UA VPA_APT 12 17
0201-1 RADIO_2G RADIO_2G
RADIO_2G
1 C4107_RF 1 C4108_RF 1 C4109_RF 1 C4112_RF L4101_RF
56PF
5%
2.2UF
20%
2.2UF
20%
100PF
5%
4.7NH+/-0.3%-0.4A
2 16V
NP0-C0G 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 16V
NP0-C0G
50_LB_2G_PA_OUT 1 2 50_LB_2G_ASM_IN 18
01005 0201 0201 01005 0201
1 C4118_RF
0.5PF
+/-0.05PF
2 16V
C0G-CERM
01005

RADIO_2G

C4104_RF
100PF 50_LB_2G_PA_IN VBATT VCC
1 2
9 50_LB_2G_WTR_TX_OUT U_2GPA_RF
5% SKY77357
16V
C NP0-C0G
01005 LBRFIN
LGA
LBRFOUT
C
HBRFIN HBRFOUT
RADIO_2G

C4103_RF RFFE_VIO VIO


100PF 50_HB_2G_PA_IN
21 19 18 17 16 14 8

RFFE1_DATA SDATA
9 50_HB_2G_WTR_TX_OUT 1 2 17 16 15 14 12 8 3

17 16 15 14 12 8 3 RFFE1_CLK SCLK
5% GND
16V EPAD
NP0-C0G
01005
L4102_RF
1.5NH+/-0.1NH-1.0A
50_HB_2G_PA_OUT 1 2 50_HB_2G_ASM_IN 18
RADIO_2G
0201
1 C4113_RF
0.8PF
+/-0.1PF
2 16V
NP0-C0G
01005
NOSTUFF

B B

A A
PAGE TITLE

2G PA
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
41 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 46 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

VERY LOW BAND PAD (B13, B17, B28)


CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C1332
R1300
L4215_RF
U1304
OMIT_TABLE
L4216_RF
7.5NH+/-3%-0.2A

D 1 2 50_B28A_ASM_TRX 18 D
01005

OMIT_TABLE
1 C4211_RF
2.2PF
17 16 15 12 VPA_ET +/-0.1PF
2 16V
NP0-C0G
01005-1

1 C4208_RF
68PF
5%
2 16V
NP0-C0G OMIT_TABLE
01005 L4217_RF
10NH-3%-0.170A
17 16 15 12 VPA_BATT PLACE INDUCTOR CLOSE TO PA 1 2 50_B28B_ASM_TRX 18
01005
RADIO_VLB_PAD
1 C4207_RF OMIT_TABLE
1.0UF 1 C4213_RF
20% 2.5PF
2 10V
X5R-CERM
+/-0.1PF
0201-1 2 16V
NP0-C0G
01005

FL_B17LP_RF
BAND17
VBAT VCC LFL15710MTCTD717
B28A_ANT 50_B28A_PAD_ANT L4222_RF 0402
OMIT_TABLE 7.5NH+/-3%-0.2A
50_B28_PAD_IN B28_IN B28B_ANT 50_B28B_PAD_ANT
U_VLBPAD_RF
14
PLACE INDUCTOR CLOSE TO PA 50_B17_ASM_TRX
14 50_B12B17_PAD_IN B17_IN B17_ANT 50_B17_PAD_ANT 1 2 50_B17_PAD_LPF_IN 4 IN OUT 2 18
SKY77802-23
C
50_B13_PAD_IN 50_B13_PAD_ANT
C
14 B13_IN B13_ANT 01005
LGA
50_B29_PAD_ANT
1 C4227_RF GND
USE OMIT TABLE TO SELECT SKU VARIANT. B29_RX_IN 2.7PF
14CTRL_VLB_BAND_SELECT_1 SW1

1
3
+/-0.1PF
CTRL_VLB_BAND_SELECT_2 SW2 L4224_RF 2 16V
NP0-C0G
22-OHM-25%-0.2A-0.9DCR 01005-1

RX_OUT VIO 15 1
LB_VLB_VIO 2 RFFE_VIO 8 13 16 17 18 19
21 OMIT_TABLE
SCLK 01005 RFFE1_CLK
RFFE1_DATA
3 8 12 13 15 16 17
L4223_RF
SDATA 5.1NH-3%-0.250A
1 2 50_B13_ASM_TRX 18
THRM OMIT_TABLE
GND PAD
1 C4230_RF 01005
15PF
5%
1 C4231_RF
2 16V 1.5PF
NP0-C0G-CERM +/-0.05PF
01005
2 16V
NP0-C0G-CERM
01005

PLACE INDUCTOR CLOSE TO PA

L4221_RF
2.4NH+/-0.1NH-0.370A
1 2 50_B29_ASM_TRX 18
01005

B B

C4221_RF L4211_RF
100PF 22NH-5%-0.1A
1 2 1 2
50_B13_B17_B28_B29_PRX_WTR_IN
50_B13_B17_B28_B29_PAD_RX 50_B13_B17_B28_B29_MCH_RX 9
01005
5%
16V
NP0-C0G
XW4200_RF
01005 1 C4219_RF
SHORT-10L-0.1MM-SM
PP_LDO14_RFSW 1.0PF
VCC_VLB_SW 4 15 23
+/-0.1PF
16V
2 NP0-C0G
01005
1 C4201_RF NOSTUFF
47PF
5%
2 16V
CERM
01005

C4206_RF VDD
100PF
5%
10V U_VLB_SW_RF
NP0-C0G
01005 CXA2973GC
14 CTRL_VLB_BAND_SELECT_1 V1 BGA RF1 50_B13_B17_B28_WTR_TX_OUT
9
14 CTRL_VLB_BAND_SELECT_2 V2 RF2 50_B12B17_PAD_IN 14
A RF3 50_B13_PAD_IN NOSTUFF A
C4224_RF GND
RF4 50_B28_PAD_IN 14
1 C4223_RF
PAGE TITLE
OMIT_TABLE
3.3PF
100PF
5%
10V
NP0-C0G
+/-0.1PF
2 16V
NP0-C0G
VERY LOW BAND PAD DRAWING NUMBER SIZE
01005 01005
Apple Inc.
051-00648 D
OUT V2 V1 BAND REVISION

4.0.0
14
RF3 0 1 B12B17 P2 DOE R

NOTICE OF PROPRIETARY PROPERTY: BRANCH

RF2 1 0 B13 THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE

RF4 1 1 B28 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
42 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 47 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

LOW BAND PAD (B8, B26, B20)


CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C4318_RF
R1400
L4322_RF
U1402

C4309_RF L4322_RF
100PF
18NH-3%-0.140A
D 1 2 50_B20_MATCH_1 50_B20_PRX_WTR_IN 9 D
01005-1
5%
16V
NP0-C0G
01005

C4314_RF
L4312_RF 47PF
7.5NH+/-3%-0.2A
1 2 1 2 50_B26_PRX_WTR_IN
01005
50_B26_MATCH
5%
1 16V
CERM
01005
VPA_ET 12 14 16 17
L4313_RF
C4300_RF 1 8.2NH-3%-0.19A-1.6OHM
01005
47PF
5%
16V 2
CERM 2
01005
17 16 14 12 VPA_BATT

C4304_RF CAPACITOR THAT'S SUPPOSED TO GO HERE IS LOCATED ON


100PF VERY LOW BAND PAD. THE 2 PAD'S NEED TO SHARE DECOUPLING
15 50_B20_WTR_TX_OUT 1 2

5%
C 10V
NP0-C0G
01005 C4311_RF L4315_RF C
100PF
15NH-3%-0.140A
1 2 50_B8_MATCH_1 1 2 50_B8_PRX_WTR_IN 9
01005
5%
16V
NP0-C0G
01005 1 C4313_RF
VBATT VCC1 VCC2 0.9PF
+/-0.05PF
2 16V
CERM
15 CTRL_LB_BAND_SELECT_1 SW1 B20RX 50_B20_PAD_RX 01005
CTRL_LB_BAND_SELECT_2 SW2 U_LBPAD_RF B26RX 50_B26_PAD_RX
C4303_RF
15

18PF 50_B20_PAD_IN B20IN


TQF6410 B8RX 50_B8_PAD_RX
LGA
15 50_B26_WTR_TX_OUT 1 2 50_B26_PAD_IN B26IN B20ANT 50_B20_PAD_ANT
5%
50_B8_PAD_IN B8IN B26ANT 50_B26_PAD_ANT
16V
CERM B8ANT 50_B8_PAD_ANT L4316_RF
C4321_RF 01005
VIO LB_VLB_VIO
5.1NH-3%-0.250A
0.7PF 14
1 2 50_B20_ASM_TRX 18
+/-0.1PF
16V SCLK RFFE1_CLK 3 8 12 13 14 16 17
01005
NP0-C0G SDATA RFFE1_DATA 3 8 12 13 14 16 17
01005
1 C4317_RF
THRM 1.0PF
GND PAD +/-0.1PF
2 16V
NP0-C0G
01005

B L4320_RF B
5.6NH-3%-0.23A-1.3OHM
1 2 50_B26_ASM_TRX 18
01005

1 C4318_RF
1.5PF
+/-0.1PF
2 16V
NP0-C0G
XW4300_RF 01005
SHORT-10L-0.1MM-SM
VCC_LB_SW PP_LDO14_RFSW

C4305_RF
47PF
5% L4321_RF
16V 3.3NH+/-0.1NH-290MA
CERM
01005 1 2 50_B8_ASM_TRX 18
01005
1
15 CTRL_LB_BAND_SELECT_1
RADIO_LB_PAD
1

CTRL_LB_BAND_SELECT_2
15
VDD L4306_RF
50_LB_SW_MCH_IN 18NH-3%-140MA
U_LB_SW_RF 15
01005
CXA2973GC V2 V1 BAND NOSTUFF
3 V1 BGA 6
C4301_RF L4301_RF 2 V2
RF1
RF2 5 50_B8_PAD_IN 0 1 B8
2

100PF
6.8NH-140MA 15

50_B8_B26_B20_WTR_TX_OUT RF3 7 50_B26_WTR_TX_OUT


9
1 2 50_LB_SW_T_MCH 1 2 50_LB_SW_MCH_IN 15
4 50_B20_WTR_TX_OUT
15
1 0 B26
A WTR OUTPUT HAS DC 5%
10V
01005 GND
RF4 15

1 1 B20 A
NP0-C0G PAGE TITLE
8
9

FIRST SHUNT MUST


BE A CAPACITOR.
01005
1 C4320_RF LOW BAND PAD DRAWING NUMBER SIZE
2.7PF
+/-0.1PF
2 16V
NP0-C0G Apple Inc.
051-00648 D
01005 REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
43 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 48 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C4426_RF
MID BAND PAD (B1, B25, B3, B4, B34, B39)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
R1500
L4409_RF
U1501
L4404_RF C4425_RF
2.2NH+/-0.1NH-0.380A 33PF
1 2 1 2 50_B3_PRX_WFR_IN 11
50_B3_PRX_MATCH
01005

D L4403_RF
5%
16V
NP0-C0G-CERM
D
01005
3.6NH+/-0.1NH-0.280A RADIO_WFR
1 2
01005

VPA_ET
RADIO_MB_PAD
12 14 15 17
L4405_RF
1.5NH+/-0.1NH-0.400A
1 C4408_RF
1 2 50_B1_B4_PRX_WFR_IN
47PF
5%
11
01005
2 16V
CERM
01005
L4406_RF
2.7NH+/-0.1NH-0.370A
1 2
01005
RADIO_WFR

VPA_BATT
17 15 14 12

RADIO_MB_PAD
L4409_RF C4423_RF
1.2NH+/-0.1NH-220MA 33PF
1 C4407_RF
1 2 1 2 50_B25_PRX_WFR_IN
1.0UF
20% 1
11
01005 50_B25_PRX_MATCH
2 10V
X5R-CERM
5%
16V
0201-1 NP0-C0G-CERM
L4402_RF 01005
RADIO_WFR

26
2.2NH+/-0.1NH-200MA
C C
01005

VBATT 36

VCC1 27
VCC2
2

35 B3RX 12 50_B3_PAD_RX
50_B3_B4_WTR_TX_OUT B3/4IN
B1/4RX 10 50_B1_B4_PAD_RX
9
RADIO_MB_PAD
OMIT_TABLE
U_MBPAD_RF B25RX 5 50_B25_PAD_RX FL_B39LP_RF
AFEM-8020-AP1 BAND34-39
LGA OMIT_TABLE LFL151G95TCSD734
B1/3/4ANT 16 50_B1_B3_B4_PAD_ANT L4421_RF 0402
34 B1/25/34/39IN B25ANT 8 50_B25_PAD_ANT
0.8NH+/-0.1NH-0.630A
B34_39_OUT 24 50_B34_B39_PAD_ANT 4 IN OUT 2 50_B34_B39_HB_SWITCH_IN 19
50_B34_B39_LPF_IN
01005
VIO 1 RFFE_VIO 8 13 14 17 18 19
GND
SCLK 2
21
RFFE1_CLK 3 8 12 13

SDATA 3
14 15 17

1
3
RFFE1_DATA 3 8 12 13
14 15 17

EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
9 50_B1_B25_B34_B39_WTR_TX_OUT

4
6
7
9
11
14
13
15
17
18
19
20
21
22
23
25
28
29
30
31
32
33
37
38
39
40
41
42
43
44
45
46
47
48
L4407_RF
1.3NH+/-0.1NH-0.400A
1 2 50_B1_B3_B4_ASM_TRX 18
01005
1 C4418_RF
0.2PF
+/-0.1PF
2 16V
NP0-C0G
01005
NOSTUFF
B B

L4401_RF L4408_RF
2.5NH+/-0.1NH-0.2A 3.6NH+/-0.1NH-180MA
2 1 50_B25_ASM_MATCH 1 2 50_B25_ASM_TRX 18
01005 01005

1 C4413_RF
1.4PF
+/-0.1PF
2 16V
NP0-C0G
01005

A A
PAGE TITLE

MID BAND PAD DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
44 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 49 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C4533_RF
HIGH BAND PAD (B7, B38, B40, B41, XGP)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
R1600
L1616
U1601
L4512_RF
3.3NH+/-0.1NH-290MA
1 2 50_B7_PRX_WTR_IN 9

RADIO_WTR 01005

D VPA_ET
D
12 14 15 16
1 C4522_RF OMIT_TABLE
1.8PF
+/-0.1PF
1 C4507_RF OMIT_TABLE
2 16V
NP0-C0G
68PF 01005
5%
2 16V
NP0-C0G
OMIT_TABLE 01005

R4509_RF
1
0.00 2 50_B7_ASM_TRX
RADIO_HB_PAD 18
OMIT_TABLE
C4501_RF 0%
18PF
OMIT_TABLE
1 C4500_RF 1/32W
MF
01005
9 50_B7_WTR_TX_OUT 1 2 0.7PF
+/-0.1PF
2% 2 16V
NP0-C0G
16V OMIT_TABLE 01005
CERM RADIO_HB_PAD
01005
1 C4503_RF 16 15 14 12 VPA_BATT
1.0PF RADIO_HB_PAD OMIT_TABLE
OMIT_TABLE
L4522_RF
+/-0.1PF 1 C4505_RF VPA_APT 2.7NH+/-0.1NH-0.6A
2 16V
12 13
NP0-C0G 1.0UF RADIO_HB_PAD 50_B41B_FILTER_IN
01005 C4532_RF
17
20% 1 C4506_RF 1
OMIT_TABLE 2 10V
X5R-CERM 1.0UF 68PF
0201
0201-1
2 10V
20%
2
5%
25V
1 C4520_RF OMIT_TABLE
X5R-CERM
0201-1
NP0-C0G-CERM
01005
0.3PF
+/-0.5PF
2 16V
CERM
OMIT_TABLE 01005

VCC1
VBATT

VCC2

VAPT
C OMIT_TABLE
FT_B40_RF
C
RADIO_HB_PAD B7RX 50_B7_RX_PAD
RADIO_HB_PAD
50_B7_ANT_PAD TX-BAND40-LTE
C4533_RF
50_B7_PAD_IN B7IN
U_HBPAD_RF B7ANT
L4520_RF SAFFU2G35MA0F57 L4526_RF
100PF OMIT_TABLE TQF6430 B41B 50_B41B_TX_PAD 1.3NH+/-0.1NH-0.400A LGA 2.2NH+/-0.1NH-0.380A
50_B40_B38_B41_WTR_TX_OUT 1 2 LGA 1 2 OMIT_TABLE
1 UNBAL_PRT1 4 1 2 50_B40B_TX_HB_SWITCH_IN
9 50_B38_B40_B41_PAD_IN B38_40_41 B40B 50_B40B_TX_PAD 50_B40B_TX_FILTER_IN UNBAL_PRT450_B40B_TX_FILTER_OUT
50_B41C_TX_PAD

GND
GND
GND
B41C 01005 01005
5% OMIT_TABLE OMIT_TABLE
16V RADIO_HB_PAD B40A/B41A 50_B40A_B41A_TX_PAD 1 OMIT_TABLE
NP0-C0G 1
01005

2
3
5
VIO RFFE_VIO 21
L4527_RF
8 13 14

C4502_RF
16 18 19
1 SCLK RFFE1_CLK 3 8 12 16
13 14 15 9.1NH-3%-0.17A-1.7OHM L4523_RF
1PF SDATA RFFE1_DATA 3 8 12 16 01005 9.1NH-3%-0.17A-1.7OHM
+/-0.1PF 13 14 15 01005
16V
OMIT_TABLE 2 NP0-C0G OMIT_TABLE
01005
2 OMIT_TABLE

EPAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2

L4515_RF
2.7NH+/-0.1NH-0.6A
R4531_RF 50_B41C_FILTER_IN 17

50_B40A_TX_HB_SWITCH_MCH 1
0.00 50_B40A_TX_HB_SWITCH_IN
2 0201 OMIT_TABLE
0% 1
1/32W
1
MF
01005
L4528_RF
1 C4528_RF
OMIT_TABLE
0.3PF
7.5NH-5NH%-140MA +/-0.1PF
L4506_RF 01005 2 16V
NP0-C0G
4.3NH-3%-0.270A 01005
OMIT_TABLE 01005 OMIT_TABLE
2

FTB40A41A_RF 2 C4521_RF
SAW-BAND-40A-41A-TDD-LX OMIT_TABLE
B 7
885058
4
ANT_B40A B40A_PORT
3.0PF
1 2 50_B40A_B41A_FILTER_IN
B
8 LGA 1
50_B41A_TX_HB_SWITCH_IN
17 50_B40A_B41A_FILTER_IN ANT_B41A B41A_PORT 19
+/-0.1PF
16V OMIT_TABLE
NP0-C0G
GND
GND
GND
GND
GND
GND

01005
1 1
1
10
9
6
5
2
3

L4517_RF L4516_RF
1.5NH+/-0.1NH-0.400A L4507_RF 3.1NH-+/-0.1NH-0.29A
01005 7.5NH+/-3%-0.2A 01005
01005

OMIT_TABLE
2 OMIT_TABLE 2
2

OMIT_TABLE
OMIT_TABLE

L4524_RF
1.8NH+/-0.1%-0.380A
OMIT_TABLE 1 250_B41B_TX_HB_SWITCH_IN

RADIO_HB_PAD OMIT_TABLE 01005

FT_41BC_RF
A SAW-BAND-41B-41C-TDD-TX
SAWEN2G58QA0F57 L4525_RF A
50_B41B_FILTER_IN 9 RF2/ RF1/ 1 50_B41B_TX_HB_SWITCH_MCH 1.4NH+/-0.1NH-1.1A PAGE TITLE
17

17 50_B41C_FILTER_IN
B41BOUT
6 RF4/
B41COUT
LGA
B41BIN
RF3/
B41CIN
4 50_B41C_TX_HB_SWITCH_MCH
0201
50_B41C_TX_HB_SWITCH_IN HIGH BAND PAD DRAWING NUMBER SIZE
GND
GND
GND
GND
GND
GND

OMIT_TABLE
Apple Inc.
051-00648 D
REVISION

4.0.0
10
8
7
5
3
2

NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
45 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 50 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ANTENNA SWITCH
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C1702
R1700
L4608_RF
U1702

D D

R4607_RF
VCC_ASM_FILTERED 1
0.00 2 PP_BATT_VCC 12 19 21 27

0%
1 C4602_RF 1/32W
MF
47PF 01005
5%
2 16V
CERM
01005

C C

29
OMIT_TABLE
VDD
OMIT_TABLE FRX34B39_RF 1 U_ASM_RF_RF
BAND34-39 19 50_HB_SWITCH_TX RF1
L4601_RF SAWFD1G90LC0F57 19 50_HB_SWITCH_RX 2 RF3 RF5159 FWD/REV 32 50_FWD_OR_REV_RF 9
2.4NH+/-0.1NH-200MA LGA
17 50_B7_ASM_TRX 3 RF7
LGA

50_B34_B39_PRX_WTR_IN 1 2 50_B34_B39_FILT_RX 1 INPUT OUT_FIL1 9


9
50_B39_RX_ASM_OUT 4 RX1
01005
OUT_FIL2 6 50_B34_RX_ASM_OUT 22 TRX6
1
16 50_B1_B3_B4_ASM_TRX 23 TRX7 A2 21 50_ANT2_CONN 23
GND 50_B25_ASM_TRX 24 TRX8
L4602_RF
16
2
3
4
5
7
8
10

3.3NH+/-0.1NH-180MA 13 50_HB_2G_ASM_IN 12 HBTX


01005
21 50_HB_DIVERSITY_ASM 20 HBRF2
2 OMIT_TABLE TO DIVERSITY MODULE 8
14 50_B17_ASM_TRX TRX2
15 50_B8_ASM_TRX 18 TRX3
14 50_B28A_ASM_TRX 9 TRX0
14 50_B28B_ASM_TRX 10 TRX1
15 50_B26_ASM_TRX 16 TRX4 A1 5 50_ANT1_CONN 23

14 50_B13_ASM_TRX 17 TRX5
15 50_B20_ASM_TRX 11 TRX11
14 50_B29_ASM_TRX 7 RX2 VIO 26 RFFE_VIO 8 13 14 16 17 19 21

SCLK 28 RFFE2_CLK
50_LB_2G_ASM_IN 14 LBTX 3 8 19 21

TO DIVERSITY MODULE SDATA 27 RFFE2_DATA 8 19 21


1 1 50_LB_DIVERSITY_ASM 19 LBRF2
B B
21

GND 1 C4606_RF
L4603_RF L4604_RF 22PF
5%

13
15
25
30
6
31
33
1.0NH+/-0.1NH-0.22A-0.9OHM 1.0NH+/-0.1NH-0.22A-0.9OHM 2
16V
01005 01005 CERM
01005
NOSTUFF NOSTUFF

2 2

A A
PAGE TITLE

ANTENNA SWITCH DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
46 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 51 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

HIGH BAND SWITCH


CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

D D

OMIT_TABLE
C4703_RF
18PF
9 50_B40A_PRX_WTR_IN 1 2 50_B40A_PRX_FILTER
5% XW4700_RF
16V 1 SHORT-10L-0.1MM-SM
CERM VCC_HBS PP_BATT_VCC 12 18 21 27
01005 OMIT_TABLE
L4705_RF OMIT_TABLE 1 C4710_RF
2.0NH+/-0.1NH-0.380A
01005 FR40A41A_RF 47PF
SAW-BAND-40A-41A-TDD-RX 5%
885055 2 16V
CERM
2 9 RX_B40A 01005
2
6 RX_B41A LGA ANT 19 50_B40A_B41A_RX OMIT_TABLE
1

1
GND
GND
GND
GND
GND
GND
GND
OMIT_TABLE VBATT
L4709_RF U_HBS_RF
C C

10
8
7
5
4
3
1
2.2NH+/-0.1NH-200MA
OMIT_TABLE OMIT_TABLE 01005 50_B40B_TX_HB_SWITCH_IN 11 TX1 CXM3652UR
C4720_RF R4700_RF
17 50_B41B_TX_HB_SWITCH_IN 12
7
TX2 UQFN
OMIT_TABLE
50_B41A_PRX_WTR_IN
100PF 50_B41A_PRX_MATCH 0.00 50_B41A_PRX_FILTER
2 16 50_B34_B39_HB_SWITCH_IN TX3
9
1 2 1 2 17 50_B40A_TX_HB_SWITCH_IN 8 TX4 TX RF1 5 50_HB_SWITCH_TX 18

0% 17 50_B41C_TX_HB_SWITCH_IN 9 TX5
5% 1/32W
6.3V MF 1 17 50_B41A_TX_HB_SWITCH_IN 10 TX6
CERM 01005
01005 OMIT_TABLE
L4706_RF 50_B40A_B41A_RX 14 RX1
19
1.4NH+/-0.1NH-0.4A
01005 19 50_B38X_RX 13 RX2 RX RF1 16 50_HB_SWITCH_RX
19 50_B40B_RX 15 RX3
2
21 18 17 16 14 13 8 RFFE_VIO 4 VIO
21 18 8 3 RFFE2_CLK 3 SCLK
21 18 8 RFFE2_DATA 2 SDATA
THRM
GND PAD

17
OMIT_TABLE

FR38X40B_RF
C4701_RF L4713_RF
OMIT_TABLE
SAW-BAND-40B-38X-TDD-RX
100PF 2.7NH+/-0.1NH-0.370A 885056
1 2 50_B40B_B38X_PRX_MATCH2 1 2 RF3/RX_B40B 9
2 RF1/ANT LGA 19 50_B40B_RX
50_B40B_B38X_PRX_WTR_IN
RF2/RX_B38X 6
9
19 50_B38X_RX 1
01005 50_B40B_B38X_PRX_FILTER
5%
10V 1
GND
GND
GND
GND
GND
GND
GND

NP0-C0G
01005
1
1 L4710_RF
B OMIT_TABLE
L4704_RF L4708_RF
12NH-3%-0.140A
01005 B
1
3
4
5
7
8
10

3.7NH-+/-0.1NH-0.27A L4712_RF 2.9NH-+/-0.1NH-0.36A


01005
OMIT_TABLE
01005 2.7NH+/-0.1NH-0.370A OMIT_TABLE 2
OMIT_TABLE 01005
OMIT_TABLE RADIO_HBSWITCH
2
2
2

A A
PAGE TITLE

HIGH BAND SWITCH DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
47 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 52 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

RX DIVERSITY (1)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C4826_RF
R1800
L1829
U1801
MIDBAND
D
MIDBAND DIVERSITY - WFR HIGHBAND DIVERSITY - WTR LOWBAND DIVERSITY - WTR D
L4806_RF OMIT_TABLE
L4813_RF L4825_RF
1.1NH+/-0.1NH-220MA
3.3NH+/-0.1NH-290MA 22NH-5%-0.1A
11 50_B1_B4_DRX_WFR_IN 1 2 50_B1_B4_DRX_DSM 21
9 50_B7_DRX_WTR_IN 1 2 50_B7_DRX_DSM 21 50_B8_B28B_DRX_WTR_IN 1 2 50_B8_B28B_DRX_DSM 21
01005
01005 01005

NOSTUFF
1 C4803_RF OMIT_TABLE
C4809_RF 1 C4820_RF
2.2PF 1.1PF
+/-0.1PF 0.3PF
2 16V 1 2 +/-0.05PF
NP0-C0G 2
16V
01005-1 C0G-CERM
+/-0.1PF 01005
16V
NP0-C0G
01005

C4805_RF L4805_RF OMIT_TABLE


C4827_RF L4826_RF
100PF 1.8NH+/-0.1%-0.380A 100PF 22NH-5%-0.1A
11 50_B3_DRX_WFR_IN 1 2 1
50_B3_DRX_MATCH 2 50_B3_DRX_DSM 21 9 50_B38X_DRX_WTR_IN 1 2 50_B38X_DRX_DSM 21 9
1 2 50_B13_B17_DRX_DSM 21
01005 50_B13_B17_DRX_WTR_IN 01005
5% 5%
16V 10V
NP0-C0G
01005 L4801_RF NP0-C0G
01005 OMIT_TABLE
2.4NH+/-0.1NH-0.370A
L4814_RF
1 C4831_RF
1 2
1.8NH+/-0.1%-0.380A 0.8PF
+/-0.05PF
16V
C C
01005 2 C0G-CERM
1 2
01005
01005

OMIT_TABLE
C4804_RF L4804_RF L4830_RF L4823_RF
100PF 1.6NH+/-0.1NH-0.390A 0.4NH+/-0.1NH-0.990A 22NH-5%-0.1A
1 2 1 2 1 2 1 2 50_B20_B29_DRX_DSM
11 50_B25_DRX_WFR_IN 50_B25_DRX_MATCH 50_B25_DRX_DSM 21 9 50_B40_DRX_WTR_IN 50_B40_DRX_FILTER 21 9 21
01005 01005 50_B20_B29_DRX_WTR_IN 01005
5%
16V
NP0-C0G
01005 L4802_RF
2.3NH+/-0.1NH-0.370A OMIT_TABLE 1 C4832_RF
1 2
L4816_RF 0.8PF
+/-0.05PF
2.4NH+/-0.1NH-200MA 2 16V
01005 C0G-CERM
1 2 01005
01005

PLACE AT WTR END OF TRACE

OMIT_TABLE
L4829_RF
C4816_RF OMIT_TABLE C4826_RF 8.2NH-3%-0.19A-1.6OHM
100PF R4815_RF 100PF
1 2 1 2
50_B26_B28A_DRX_DSM
0.00 50_B26_B28A_DRX_WTR_IN
MIDBAND DIVERSITY - WTR
9 21
9 50_B41A_DRX_WTR_IN 1 2 1 2 50_B41A_DRX_FILTER 21
01005
50_B26_B28A_DRX_WTR_MCH
5% 50_B41A_DRX_WTR_MCH 0% 5%
1/32W 16V
16V MF NP0-C0G 1
NP0-C0G 01005 01005
B L4807_RF
01005 OMIT_TABLE
L4817_RF L4827_RF B
2.0NH+/-0.1NH-0.380A 1.3NH+/-0.1NH-0.400A 10NH-3%-0.170A
01005
9 50_B34_DRX_WTR_IN 1 2 50_B34_DRX_DSM 21
1 2
01005 01005
2
PLACE AT WTR END OF TRACE
L4808_RF
3.6NH+/-0.1NH-180MA
1 2
01005
NOSTUFF

C4817_RF L4819_RF
2.2NH+/-0.1NH-0.380A
50_PCS_WTR_IN 100PF
9
1 2
50_PCS_DRX_MATCH 1 2 50_PCS_DSM_OUT 21

C4808_RF L4809_RF
2.4NH+/-0.1NH-0.370A 5%
16V
01005
100PF NP0-C0G
9 50_B39_DRX_WTR_IN 1 2 1 2 50_B39_DRX_DSM 21
01005

5%
50_B39_DRX_MATCH 01005 L4820_RF
16V 2.7NH+/-0.1NH-0.370A
NP0-C0G
01005 L4810_RF 1 2
2.2NH+/-0.1NH-0.380A 01005
1 2
01005

C4818_RF L4822_RF
A 50_DCS_WTR_IN 100PF 2.2NH+/-0.1NH-0.380A A
1 2 50_DCS_DRX_MATCH 1 2 50_DCS_DSM_OUT PAGE TITLE
9

5%
16V
01005
21

RX DIVERSITY DRAWING NUMBER SIZE


NP0-C0G
01005
L4821_RF Apple Inc.
051-00648 D
5.6NH-3%-0.23A-1.3OHM REVISION

1 2
R
4.0.0
01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
48 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 53 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

RX DIVERSITY (2)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C1900
R1900
L1900
U1901

D D

L4905_RF
22-OHM-25%-0.2A-0.9DCR
C VCC_DSM 1 2 PP_BATT_VCC 12 18 19 27
C
01005
1 C4901_RF
15PF
5%
2 16V
NP0-C0G-CERM
01005

VDD 2
VIO 3 RFFE_VIO
U_DSM_RF
8 13 14 16 17 18 19

50_B1_B4_DRX_DSM 32 RX_BAND_1_4
SDATA 4
20
33
RFFE2_DATA 8 18 19
20 50_B3_DRX_DSM RX_BAND_3
16 M472B
20 50_B7_DRX_DSM RX_BAND_7 SCLK 5 RFFE2_CLK 3 8 18 19
19 LGA
50_B8_B28B_DRX_DSM RX_BAND_8+28B
ANT_LB 7
20
25 OMIT_TABLE 50_LB_DIVERSITY_ASM 18
20 50_B13_B17_DRX_DSM RX_BAND_12+13
20 50_B25_DRX_DSM 34 RX_BAND_25 ANT_HB 9 50_HB_DIVERSITY_ASM 18

50_B26_B28A_DRX_DSM 21 RX_BAND_26+28A
PCS 29
20
23
50_PCS_DSM_OUT 20
20 50_B20_B29_DRX_DSM RX_BAND_20
OMIT_TABLE 12
20 50_B34_DRX_DSM RX_BAND_34 DCS 30 50_DCS_DSM_OUT 20
FD40B41A_RF 20 50_B39_DRX_DSM 13 RX_BAND_39
SAW-2-1-BAND-40-41A-DRX
20 50_B38X_DRX_DSM 17 RX_BAND_38X
B39252B9920P810
20 50_B40_DRX_FILTER 6 B40OUT B40IN 4 50_B40_DRX_DSM 14 RX_BAND_40
20 50_B41A_DRX_FILTER 9 B41AOUT LGA B41AIN 1 50_B41A_DRX_DSM 15 RX_BAND_41A
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
THRM
PAD
1 1
OMIT_TABLE 1 OMIT_TABLE 1
10
8
7
5
3
2

1
6
8
10
11
18
20
22
24
26
27
28
31

35
36
37
38
39
40
B L4901_RF
OMIT_TABLE
L4903_RF
OMIT_TABLE
B
15NH-3%-0.140A L4902_RF 5.6NH-3%-140MA L4904_RF
01005 5.6NH-3%-0.23A-1.3OHM 01005 5.1NH-3%-0.250A
01005 01005

2 2
2 2

A A
PAGE TITLE

RX DIVERSITY (2) DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
49 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 54 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

GPS
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
C1900
R1900
L1900
U1901

D D

C C
L5002_RF
10NH-3%-0.170A
FL_GPSRF_RF 100_GPS_FIL_OUT_P 1 2 100_GPS_WTR_IN_P 9
LNA-GNSS-BAL 01005
B8821
LGA RADIO_GPS
BAL_PORT 3 1 C5001_RF
50_GPS_DSM_IN 1 UNBAL_PORT BAL_PORT 4
23
1.0PF
+/-0.1PF

GND
GND
2 16V
NP0-C0G
01005

2
5
L5003_RF
10NH-3%-0.170A
100_GPS_FIL_OUT_N 1 2 100_GPS_WTR_IN_N 9
01005

B B

A A
PAGE TITLE

GPS DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
50 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 55 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ANTENNA FEEDS
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
ANT & COAX CONNECTOR FOR LOWER & UPPER SECTION OF MLB L5107_RF
20NH-3%-.14A-2.9OHM
PAC_VDD_3V0_IN PAC_VDD_3V0 4 14 15 23
01005
1 C5106_RF 1 C5107_RF
VBAT
D FL5146_RF L5101_RF U_ANTPAC_RF
5%
33PF 0.01UF
10%
RADIO_LOW_ANT
D
UPPER_LBMB_ANT_RF FLTR-GPS-0603 RF1346
2 16V
NP0-C0G-CERM
01005
6.3V
2 X5R
01005
LOW_COAX_RF
MM5829-2700
1.6X1.21MM LFE18832MHC1D449 2.4NH+/-0.2NH-0.57A-0.07OHM
SM-NSP 03015 WLCSP F-ST-SM1
1 50_UPPER_LBMB 1 IN 3 50_NTCH_FILT_OUT 1 2 50_UAT_PAC RF1 VIO VIO_FILT
OUT 23
18 50_ANT2_CONN
NC BYPASS CAPS FOR ALTERNATE ANTENNA WITHOUT U_ASWNT
23 50_UAT_CELL_F RF2 SDATA RFFE2_PAC_DATA_FILT 23

2
NC SCLK RFFE2_PAC_CLK_FILT 23
R5137_RF
1 C5105_RF 0.00
0.8PF OMIT_TABLE
+/-0.05PF NC NC 1%
2 16V
C0G-CERM NC NC
1/20W
01005 MF
NC NC
0201
GND
SHORT-10L-0.1MM-SM
23 15 14 4 PP_LDO14_RFSW
XW5100_RF

C5109_RF VCC_SWANT
47PF
5%
L5103_RF 16V
CERM
20NH-3%-.14A-2.9OHM 01005

27 RFFE_VIO_S2R 23 VIO_FILT TO THE PAC FOR LBMB


01005
1 C5103_RF 1 C5104_RF UP_COAX_RF VDD
L5108_RF L5109_RF
10%
0.01UF
5%
33PF MM5829-2700
F-ST-SM1
U_SWUANT_RF 2.5NH+/-0.1NH-500MA
CXA4011GC 2.5NH+/-0.1NH-500MA
2 6.3V
X5R 2 16V
NP0-C0G-CERM 50_ANT2_UPPER_COAX_CONN 1 2 1 2
01005 01005 RF RF1 50_UAT_CELL 50_UAT_CELL_F
23
OMIT_TABLE 0201 50_UAT_CELL_LPF 0201
XFLGA
8 UAT_SELECT VC1 RF2 1
0=UPPER_LBMB_ANT
C R5104_RF
1=UPPER_HB_ANT
GND
L5111_RF C
0.00 RFFE2_PAC_DATA_FILT
1 C5110_RF 7.5NH-+/-0.2NH-440MA
8 RFFE2_DATA_BUFFER
23
1.1PF
+/-0.05PF 03015
0% 2 25V
C0G-CERM
1/32W
MF
01005
1 C5102_RF 0201 2
120PF
R5105_RF 10%
2 10V
CER-X7R
RFFE2_CLK_BUFFER
0.00 RFFE2_PAC_CLK_FILT 23
01005
8

0%
1/32W
MF
1 C5101_RF
01005 120PF
10%
2 10V
CER-X7R
01005

50_WIFI_2G_NOTCHPLEXER_IN BI 57

L5123_RF
1.7NH-+/-0.1NH-0.8A-0.07OHM
0201
RADIO_LOW_ANT
UPPER_HB_ANT_RF DPX165950DT-8030D1 FLCELWIF_RF
MM5829-2700
F-ST-SM1
FLWIFDIP_RF DIPLEXER-CELL-WIFI
885072 NOSTUFF L5122_RF
1 SM
R5101_RF
LOW_BAND 6
50_WIFI_2G_DIPLEXER_IN2
1
0.002 50_WIFI_2G_DIPLEXER_IN 9 RF1
LGA

RF3 1
12NH-3%-0.140A
P2 DOE
B 50_WIFI_2G_NOTCHPLEXER_IN2
B
2
3
4

50_WIFI_5G_IN_OUT 1% 01005
HIGH_BAND 4 BI 57 1/20W 7 SMD2_RF1/SMD4_GND RF2 4
MF
0201
COMMON 2 1 SMD1_RF2 6
GND L5106_RF
50_UPPER_HB_ANT_FEED

R5102_RF
GND 4.3NH+/-3%-0.5A
C5138_RF

L5120_RF

10
8
5
3
2

2
1 2 50_UPPER_HB_CELL NOSTUFF
5
3
1

3.0NH+/-0.1NH-0.6A
50_WICE_CELL2_IN 0201 1%
+/-0.1PF
8.2PF

0201 MF
L5102_RF 1/20W 49.9
201
0201

1
2 25V
CER

1.2NH-+/-0.05NH-1.1A-0.04OHM 2
50_WICE_ANT2_GND
50_UPPER_HB_ANT_FEED2 50_UPPER_HB_ANT_FEED1
1

0201
NOSTUFF 1
1 C5139_RF
0.2PF L5121_RF
+/-0.05PF
2 25V 5.6NH-3%-0.23A-1.3OHM
COG-CERM 01005
0201

R5136_RF 2
PP_LDO13_GPS
0.00 PP_LDO13 4 6
VOLTAGE=2.95V
1%
1 C5129_RF
1/20W
MF
1 C5130_RF
22PF 0201 2.2UF
5% 20%
2 16V
CERM 2 6.3V
X5R
01005 0201-2
GPS FEED MODULE INCLUDES INTERNAL DECOUPLING NOSTUFF NOSTUFF
VCC
RADIO_LOW_ANT
GPS_SP1_RF C5136_RF U_GPSLNA_RF LOW_ANT_RF
A 1.6X1.21MM
SM-NSP 1.8PF R5135_RF SKY65736 L5129_RF MM5829-2700 A
1 50_GPS_ANT_FEED 1 2 1
0.00 2 50_GPS_ANT LGA 1.4NH+/-0.1NH-1.1A F-ST-SM1
50_GPS_ANT_MATCH RFIN RFOUT 50_GPS_DSM_IN 22
PAGE TITLE

+/-0.05PF
25V
C0G-CERM 1 I248
1%
1/20W
MF
0201
18 50_ANT1_CONN
1
NOSTUFF 1

C5128_RF
0201
2 50_ANT1_CONN_R 1
ANTENNA FEEDS DRAWING NUMBER SIZE

4
3
2
0201 NOSTUFF
GND
THRM_PAD
0.3PF
+/-0.05PF Apple Inc.
051-00648 D
L5135_RF 2 25V
C0G-CERM REVISION

SP3_RF 22NH-100MA
0201
0201 R
4.0.0
SPRING-OVERPASS-GND-NORTH-X145 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1
CLIP-SM THE INFORMATION CONTAINED HEREIN IS THE
2 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
51 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 56 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

WLAN/BT
WIFI_BT
PP_VCC_MAIN
60 58 46 37 33 IN

WIFI_BT
1 WIFI_BT
C5202_RF 1 WIFI_BT
C5203_RF 1 WIFI_BT
C5222_RF
C5221_RF C5220_RF R5214_RF D
D 2.2UF
20%
4.7UF
20%
20%
4.7UF
2 6.3V
27PF
5%
2 16V
27PF
5%
2 16V 1
0 2
50_WIFI_2G_NOTCHPLEXER_IN
6.3V 6.3V CER-X5R NP0-C0G NP0-C0G BI 56
X5R-CERM CER-X5R 0402 01005 01005 WIFI_BT 5% WIFI_BT
0201 0402
1 C5213_RF 1/20W
MF
201
1 C5211_RF
0.2PF 0.2PF
+/-0.1PF +/-0.1PF
WIFI_BT 2 16V
NP0-C0G 2 16V
NP0-C0G
R5208_RF 01005 01005
PP_WL_BT_VDDIO_AP 1
0.00 2
24 PP_WLAN_VDDIO_1V8 NOSTUFF NOSTUFF
60 33 IN
VOLTAGE=1.80V
0%
1/32W WIFI_BT
1 C5204_RF 1 WIFI_BT
MF C5205_RF WIFI_BT
01005 0.01UF 27PF
10%
2 6.3V
5%
2 16V
L5216_RF FL5201_RF
X5R NP0-C0G 1.3NH+/-0.1NH-1.1A LFH185G53RG1D868
01005 01005
50_WIFI_5G_BPF_RADIO SM 50_WIFI_5G_IN_OUT
4 IN OUT 2 BI 56
0201
GND

VDDIO_1P8V 22

VBATT 23
VBATT 24

VBATT_RF_VCC 54
VBATT_RF_VCC 55
1 1 3
NOSTUFF
32K INTERFACE TO AP WIFI_BT WIFI_BT
L5208_RF 1 C5212_RF
0.2PF
+/-0.05PF
0201
WIFI_BT 2 25V
50_WLAN_G_ANT COG-CERM
60 36 33 IN
CLK32K_AP 36 CLK32K 2G_ANT 45 2.7NH+/-0.1NH-0.50A 0201
50_WLAN_A_ANT
5G_ANT 58 2 NOSTUFF
WLAN_BUCK_OUT 26 VIN_LDO WIFI_BT
WIFI_BT
C5201_RF WLAN_SR_VLX 28 SR_VLX
7.5UF WIFI_BT U5201_RF
20% LBEE5U8ZKC-646 GPIO_1 8 PCIE_DEV_WAKE
4V L5201_RF HOST_WAKE_BT
IN 33 60

CERM 2.2UH-20%-0.3A-0.38OHM 60 36 33 IN
WLAN_REG_ON 9 WL_REG_ON LGA BT_HOST_WAKE 43 OUT 33 36 60
0402 WAKE_BT
BT_REG_ON 10 BT_REG_ON BT_DEV_WAKE 42
1 3 1 2 60 36 33 IN IN 33 36 60

C WLAN_SR_LC 0603
38 BT_UART_CTS_L 1 WIFI_BT
C
2 4 BT_UART_CTS* IN 33 36 R5210_RF
60
60 36 33
HOST_WAKE_WLAN 30 GPIO_0 BT_UART_RTS* 39 BT_UART_RTS_L 33 36 100K
OUT OUT
WLAN_PCIE_WAKE_L 12 41 BT_UART_RXD
60 5%
60 33 OUT PCIE_WAKE* BT_UART_RXD IN 33 36 1/32W
WLAN_PCIE_PERST_L 14 40 BT_UART_TXD
60 MF
60 57 33 IN PCIE_PRST* BT_UART_TXD OUT 33 36
2 01005
60
60 33
WLAN_PCIE_CLKREQ_L 13 PCIE_CLKREQ*
BI
60 33
90_WLAN_PCIE_REFCLK_N 16 PCIE_REFCLK_N
IN
60 33
90_WLAN_PCIE_REFCLK_P 17 PCIE_REFCLK_P
IN
BT_PCM_CLK 49 BT_PCM_CLK 33 36 60
60 36 33
90_WLAN_PCIE_RDN 20 PCIE_RDN
BI
IN
BT_PCM_SYNC 50 BT_PCM_SYNC 33 36 60
60 36 33
90_WLAN_PCIE_RDP 21 PCIE_RDP
BI
IN
BT_PCM_IN 48 BT_PCM_IN 33 36 60
60 36 33
90_WLAN_PCIE_TDN 18 PCIE_TDN
IN
OUT
BT_PCM_OUT 47 BT_PCM_OUT 33 36 60
60 36 33
90_WLAN_PCIE_TDP 19 PCIE_TDP
OUT
OUT

DC BLOCKS LOCATED ON AP SIDE


SWIZZLE DATA LANE ON TOP-LEVEL UART_RTS(GPIO_7) 56 WLAN_UART_RTS_L
OUT 33 36 60

UART_CTS(GPIO_8) 4 WLAN_UART_CTS_L 33 36 60
IN
JTAG_SEL
24 11 JTAG_SEL UART_RX(GPIO_9) 3 WLAN_UART_RXD 33 36 60
IN
36
WLAN_JTAG_SWDCLK 31 JTAG_TCK(GPIO_2) UART_TX(GPIO_10) 2 WLAN_UART_TXD 33 36 60
IN OUT
WLAN_JTAG_SWDIO 34 WIFI_BT
36 BI JTAG_TMS(GPIO_3) R5206_RF
60 36 33 IN
OSCAR_CONTEXT_A 32 JTAG_TDI(GPIO_4)
SECI_TX(GPIO_13) 6 WLAN_COEX_TXD 1
0.00 2 BB_COEX_UART_RXD 3 8
35 JTAG_TDO(GPIO_5)
NC SECI_RX(GPIO_14) 5 WLAN_COEX_RXD 0%
60 36 33
OSCAR_CONTEXT_B 33 JTAG_TRST(GPIO_6) 1/32W
RF_SW_CTRL_8 7
IN
NC
MF
01005
GND THRM_PAD
WIFI_BT
R5205_RF
0.00 2
1
15
25
27
29
37
44
46
51
52
53
57

59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
B 1
0%
BB_COEX_UART_TXD 3 8
B
1/32W
MF
01005

WLAN_PCIE_PERST_L
27 24
PP_WLAN_VDDIO_1V8 24

1 WIFI_BT
R5201_RF
1 C5215_RF 10K
5%
100PF 1/32W
5% MF
2 16V
NP0-C0G 2 01005
01005 NOSTUFF

JTAG_SEL 24

A 1 WIFI_BT
R5202_RF
10K SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
5%
1/32W
MF
2 01005
WIFI/BT: MODULE AND FRONT END
DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.

MODULE
MODULE BOOT-STRAPPED
BOOT-STRAPPED TO
TO PCIE
HSIC INTERNALLY
BY GPIO6/SDIO2/SDIO1=110 THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
PAGE

52 OF 55
SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 57 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C2101

STOCKHOLM
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST. U5302_RF
WLCSP
R2100
L2102
U2100

FAN48614BUC50X
PP_VCC_MAIN A3 VIN VOUT A1 STOCKHOLM_5V
D
27 25 24 13 4 25

D L5303_RF B1 SW VOUT A2
1.8UH-0.7A
1 C5321_RF 1 2
B2 SW
15UF
20% 0603 STOCKHOLM_BOOST_SW B3 EN 1 C5322_RF 1 C5323_RF
2 6.3V 15UF 15UF

C1 PGND
C2 PGND

C3 AGND
X5R 20% 20%
0402-1
2 6.3V
X5R 2 6.3V
X5R
0402-1 0402-1

USE LDO11 TO MATCH IMPLEMENTATION OF N71/66

25 STOCKHOLM_5V
R5309_RF
R5313_RF PP_LDO11 25 27
0.00 STOCKHOLM_DC_BOOST_EN
1
0.00 2
1 2
27 25 24 13 4
PP_VCC_MAIN STOCKHOLM_TVDD 0%
RADIO_STOCKHOLM 0% 1/32W
1 C5330_RF 1/32W MF
MF 01005
1UF 01005
20%
2 10V
RADIO_STOCKHOLM
1 C5324_RF R5310_RF X5R
0201
0.00
1UF 1 2
20%
2 10V
X5R
0201
0%
1/32W
MF
PP_PN66_SIM_PMU C5308_RF R5303_RF
01005 1000PF 560
1 2 STOCKHOLM_RXP_CAP 1 2
STOCKHOLM_DVDD STOCKHOLM_SVDD_IN
VOLTAGE=1.80V 5%
27 25 PP_STOCKHOLM_1V8_S2R RADIO_STOCKHOLM 2% 1/20W
1 C5304_RF 25V MF
RADIO_STOCKHOLM PP_STOCKHOLM_ESE C0G-NP0 201
1 C5302_RF
25
1UF
C
0201
C 1UF
VOLTAGE=1.80V RADIO_STOCKHOLM
1 C5303_RF
20%
2 10V
NOSTUFF
ESE_VDD C5
VUP G2
C6
C7

D3

AVDD D7

X5R
B5

TVDD E7

SVDD B7

20%
0.1UF L5301_RF
2 10V
X5R 10%
0201
PP5302_RF 160NH-10%-0.48A-0.33OHM C5312_RF
VDD
VBAT
SIM_PMU_VCC
PVDD

0201 2 10V P2MM-NSM 82PF


X5R-CERM SM STOCKHOLM_ANT_MATCH
0201 STOCKHOLM 1 1 2 STOCKHOLM_BAL1 1 2
PP
0402
PP5303_RF 1 C5310_RF 2%

BAL1 3
UNBAL 4
P2MM-NSM 50V
SM 560PF NP0-C0G
STOCKHOLM 1 2% 0201
STOCKHOLM_ANT
2 25V
PP

ATB201206E-20011
NPO-C0G
U5301_RF 0201
SPIM_IRQ F1
C5313_RF

T5301_RF
PN66VEU3-A101D003 NC
60 36 33
STOCKHOLM_TO_PMU_HOST_WAKE D1 IRQ SIM_SWIO A4 STOCKHOLM_TO_SIM_SWP 36 560PF NOSTUFF
OUT BI
UFLGA C5316_RF C5318_RF

0805
A5 SVDD_REQ GPIO0 A7 STOCKHOLM_SIM_PRES 1 2 1 C5315_RF 1
NC 25
C5319_RF TP5303_RF

2
AP_TO_STOCKHOLM_FW_DWLD_REQ B2 DWL SPIM_NSS A6 1000PF 1000PF 330PF 100PF 1
58 36 33
60 IN NC 2% 2% 2% 2% 2% A
STOCKHOLM_TO_BBPMU_CLK_REQ A2 CLK_REQ TX_PWR_REQ D5 STOCKHOLM_DC_BOOST 25V 2 25V 25V 25V TP-P55
2 50V

1
38 36 OUT C0G-NP0
NPO-C0G C0G-NP0 NPO-COG C0G
38 36
45_BBPMU_TO_STOCKHOLM_19P2M_CLK A3 NFC_CLK_XTAL1 SH_DWP_M 0201 0201 0201 0201 0201
IN
ESE_DWPM_DBG G7

2 BAL0
1 GND
STOCKHOLM_UART_RXD C1 RX SH_DWP_S
58 36 33
60 IN
B1 ESE_DWPS_DBG G6 L5302_RF
TX
60 36 33 OUT
STOCKHOLM_UART_TXD
STOCKHOLM_UART_CTS D2 CTS RXP F6 STOCKHOLM_RXP
160NH-10%-0.48A-0.33OHM C5314_RF
58 36 33
60 IN 1 2 STOCKHOLM_BAL0 22PF
60 36 33 STOCKHOLM_UART_RTS A1 RTS RXN F5 STOCKHOLM_RXN 1 2 USE FIDUCIAL FOR SH ANTENNA GND
OUT 0402
AP_TO_STOCKHOLM_EN E1 VEN 1 C5311_RF
TX1 G3
58 36 33 IN
60 STOCKHOLM_TX1 5%
560PF 50V
25 PP_STOCKHOLM_ESE E3 SMX_RST* TX2 G5 STOCKHOLM_TX2 2% C0G
E4 2 25V
NPO-C0G 0201
NC SMX_CLK E5 AP_TO_STOCKHOLM_DEV_WAKE 0201 NOSTUFF
F4 WKUP_REQ IN 33 58 60
NC ESE_IO1
B3 SPIM_MOSI F7 STOCKHOLM_VMID
NC VMID
B4 P2MM-NSM
SPIM_MISO SM PP5304_RF
NC SE2_PWR_REQ F2 SE2_PWR_REQ 1 STOCKHOLM
E6 SPIM_SCK
PP 25
NC SE2_SVDD_IN G1 SE2_SVDD_IN
C5309_RF
B R5304_RF B
25
C3 XTAL2 1000PF
NC 560
DVSS
DVSS
AVSS
AVSS
AVSS

PVSS

STOCKHOLM_RXN_CAP
TVSS

NOSTUFF 1 2 1 2
VSS

R5316_RF
RADIO_STOCKHOLM 5%
1 C5317_RF 2% 1/20W
0.00 25V MF
E2

D4
D6
F3

B6
C4

G4
C2

0.1UF 1 2 PP_STOCKHOLM_1V8_S2R 25 27
C0G-NP0 201
20% 0201
2 6.3V
X5R-CERM 0%
01005 1/32W
MF
01005

TP5301_RF
1 STOCKHOLM_SIM_PRES
A 25
TP-P55 PU FOR MAUI IO WAKE GLITCH

27 25 PP_STOCKHOLM_1V8_S2R
27 25 PP_STOCKHOLM_1V8_S2R
1 RADIO_STOCKHOLM
R5301_RF 1 RADIO_STOCKHOLM
100K R5306_RF
5% 100K
1/32W 5%
MF 1/32W
2 01005 MF
60 58 36 33 AP_TO_STOCKHOLM_EN 2 01005
IN
60 58 36 33 IN
STOCKHOLM_UART_CTS
60 58 36 33 IN AP_TO_STOCKHOLM_FW_DWLD_REQ
1 RADIO_STOCKHOLM
R5302_RF
100K 27 25 PP_STOCKHOLM_1V8_S2R
5%
1/32W 1 RADIO_STOCKHOLM
MF R5307_RF
2 01005 100K
5%
A 1/32W
MF
2 01005 SYNC_MASTER=N/A SYNC_DATE=N/A A
STOCKHOLM_UART_RXD PAGE TITLE
60 58 33 IN AP_TO_STOCKHOLM_DEV_WAKE 60 58 36 33 IN

1 RADIO_STOCKHOLM
R5305_RF
STOCKHOLM
DRAWING NUMBER SIZE
100K
5%
1/32W Apple Inc.
051-00648 D
MF REVISION
2 01005 R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
53 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 58 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

N69 SKU BOM OPTION TABLE


N69H
PART#
N69H TDD
QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
N69
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD

D
D
TABLE_5_ITEM TABLE_5_ITEM

353S4180 1 RADIO HIGH BAND PAD U_HBPAD_RF CRITICAL N69H 353S00373 1 DSM M471A NO B7 U_DSM_RF CRITICAL N69
TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

131S0417 1 18PF 01005 16V C4501_RF CRITICAL N69H 131S0307 1 100PF 01005 C4827_RF CRITICAL N69H 353S00331 1 SKY77826 U_VLBPAD_RF CRITICAL N69
TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

131S0375 1 1.0PF 01005 16V C4503_RF CRITICAL N69H 152S1720 1 1.8NH 01005 L4814_RF CRITICAL N69H 118S0729 1 39K 1% 01005 R3312_RF CRITICAL N69
TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

131S0635 1 68PF 01005 16V C4507_RF CRITICAL N69H 152S1544 1 0.4NH 01005 L4830_RF CRITICAL N69H 118S0724 1 0R 0201 R5137_RF CRITICAL N69
TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

138S0706 1 1UF 0201 10V C4505_RF CRITICAL N69H 152S1564 1 2.4NH 01005 L4816_RF CRITICAL N69H 152S1993 1 5.1NH 0.1NH 01005 250MA L4223_RF CRITICAL N69
TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

152S1907 1 3.3NH 01005 +/-0.1NH L4512_RF CRITICAL N69H 131S0307 1 100PF 01005 C4816_RF CRITICAL N69H 131S0599 1 01005 1.5PF C4231_RF CRITICAL N69
TABLE_5_ITEM TABLE_5_ITEM

131S0247 1 1.8PF 01005 16V C4522_RF CRITICAL N69H 117S0161 1 0R 01005 R4815_RF CRITICAL N69H
TABLE_5_ITEM TABLE_5_ITEM

152S1900 1 1.3NH 01005 L4817_RF CRITICAL N69H 118S0652 1 01005 49.9R C4211_RF CRITICAL N69
TABLE_5_ITEM TABLE_5_ITEM

353S00374 1 TDK MODULE M472A NO B12/B13/B17 U_DSM_RF CRITICAL N69H 118S0652 1 01005 49.9R C4213_RF CRITICAL N69
TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

152S1998 1 IND 0.8NH 630MA 01005 L4421_RF CRITICAL N69H 152S1996 1 15NH 01005 L4901_RF CRITICAL N69H 118S0652 1 01005 49.9R C4500_RF CRITICAL N69
TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

353S00390 1 SKY77827 U_VLBPAD_RF CRITICAL N69H 152S1571 1 5.6NH 01005 L4902_RF CRITICAL N69H 117S0161 1 0R 01005 R4509_RF CRITICAL N69
TABLE_5_ITEM TABLE_5_ITEM

131S0387 1 2.2PF 0.1PF 01005 COG C4211_RF CRITICAL N69H 152S1571 1 5.6NH 01005 L4903_RF CRITICAL N69H
TABLE_5_ITEM TABLE_5_ITEM

152S1567 1 3.3NH 01005 L4813_RF CRITICAL N69H 152S1623 1 5.1NH 01005 L4904_RF CRITICAL N69H
TABLE_5_ITEM TABLE_5_ITEM

131S0376 1 1.1PF 01005 C4809_RF CRITICAL N69H 155S0908 1 SAW DRX B40B41A FD40B41A_RF CRITICAL N69H
TABLE_5_ITEM TABLE_5_ITEM

152S1977 1 10NH 01005 170MA L4217_RF CRITICAL N69H 117S0161 1 0R 01005 R4509_RF CRITICAL N69H
TABLE_5_ITEM TABLE_5_ITEM

131S0390 1 2.5PF 0.1PF 01005 COG C4213_RF CRITICAL N69H 152S1907 1 3.3NH 01005 290MA L4602_RF CRITICAL N69H
TABLE_5_ITEM TABLE_5_ITEM

152S1853 1 7.5NH 3% 01005 200MA L4216_RF CRITICAL N69H 155S0981 1 FLTR SAW DUAL FILTER B34B39 FRX34B39_RF CRITICAL N69H
TABLE_5_ITEM TABLE_5_ITEM

118S0726 1 162K 1% 01005 R3312_RF CRITICAL N69H 152S1988 1 2.4NH 01005 370MA L4601_RF CRITICAL N69H
C C

m
TABLE_5_ITEM TABLE_5_ITEM

353S3876 1 SWTICH SPDT 1.1X1.1 U_SWUANT_RF CRITICAL N69H 155S0906 1 SAW FILTER B40A B41A FTB40A41A_RF CRITICAL N69H
TABLE_5_ITEM TABLE_5_ITEM

152S2045 1 3.0NH 0201 L5120_RF CRITICAL N69H 152S1983 1 1.5NH 01005 +/-0.1NH L4517_RF CRITICAL N69H

o
TABLE_5_ITEM TABLE_5_ITEM

152S1851 1 5.6NH 01005 L5121_RF CRITICAL N69H 152S2061 1 7.5NH 01005 3% L4507_RF CRITICAL N69H

.c
TABLE_5_ITEM

117S0161 1 0R 01005 R4531_RF CRITICAL N69H


TABLE_5_ITEM TABLE_5_ITEM

118S0652 1 01005 49.9R C4231_RF CRITICAL N69H 152S2040 1 4.3NH 01005 3% L4506_RF CRITICAL N69H

x
TABLE_5_ITEM

131S00042 1 0.3PF +-0.05PF 01005 16V C4528_RF CRITICAL N69H


TABLE_5_ITEM

fi
131S0307 1 100PF 01005 16V C4533_RF CRITICAL N69H
TABLE_5_ITEM

131S0244 1 1PF 01005 16V C4502_RF CRITICAL N69H

a
TABLE_5_ITEM

138S0706 1 1UF 0201 10V C4506_RF CRITICAL N69H


TABLE_5_ITEM

in
131S0644 1 68PF 01005 25V C4532_RF CRITICAL N69H
TABLE_5_ITEM

131S00042 1 0.3PF 01005 16V C4520_RF CRITICAL N69H


TABLE_5_ITEM

152S2002 1 2.7NH 0201 +/-0.1NH L4522_RF CRITICAL N69H

h
TABLE_5_ITEM

152S1982 1 1.3NH 01005 +/-0.1NH L4520_RF CRITICAL N69H

.c
TABLE_5_ITEM

155S0982 1 FILTER B40 FT_B40_RF CRITICAL N69H


TABLE_5_ITEM

152S1986 1 2.2NH 01005 +/-0.1NH L4526_RF CRITICAL N69H

w
TABLE_5_ITEM

152S1853 1 9.1NH 01005 3% L4523_RF CRITICAL N69H


TABLE_5_ITEM

152S2002 1 2.7NH 0201 +/-0.1NH L4515_RF CRITICAL N69H

w
B B
TABLE_5_ITEM

152S1408 1 7.5NH 01005 5% L4528_RF CRITICAL N69H


TABLE_5_ITEM

152S00035 1 3.1NH 01005 +/-0.1NH L4516_RF CRITICAL N69H

131S0395

152S1853
1

1
w
3.0PF 01005 +/-0.1PF

9.1NH 01005 3%
C4521_RF

L4527_RF
CRITICAL

CRITICAL
N69H

N69H
TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

155S0900 1 FILTER SAW BAND 41B 41C FT_41BC_RF CRITICAL N69H


TABLE_5_ITEM

152S1965 1 1.8NH 01005 380MA L4524_RF CRITICAL N69H


TABLE_5_ITEM

152S2024 1 1.4NH 0201 1.1A L4525_RF CRITICAL N69H


TABLE_5_ITEM

353S4167 1 SWITCH IC LGA16 U_HBS_RF CRITICAL N69H


TABLE_5_ITEM

155S0903 1 FILTER SAW B40B 38X FR38X40B_RF CRITICAL N69H


TABLE_5_ITEM

155S0881 1 FILTER LOW PASS B39 FL_B39LP_RF CRITICAL N69H


TABLE_5_ITEM

131S0214 1 18PF 01005 C4703_RF CRITICAL N69H


TABLE_5_ITEM

152S1917 1 2.0NH 01005 380MA L4705_RF CRITICAL N69H


TABLE_5_ITEM

117S0161 1 0OHM 01005 R4700_RF CRITICAL N69H


TABLE_5_ITEM

131S0307 1 100PF 01005 C4720_RF CRITICAL N69H


TABLE_5_ITEM

155S0902 1 FILTER SAW BAND 40A B41A FR40A41A_RF CRITICAL N69H


TABLE_5_ITEM

152S1619 1 2.2NH 01005 200MA L4709_RF CRITICAL N69H


TABLE_5_ITEM

131S0214 1 18PF 01005 C4701_RF CRITICAL N69H


TABLE_5_ITEM

A 152S00036 1 3.7NH 01005 270MA L4704_RF CRITICAL N69H


TABLE_5_ITEM
A
152S1989 1 2.7NH 01005 370MA L4713_RF CRITICAL N69H PAGE TITLE

152S1989 1 2.7NH 01005 370MA L4712_RF CRITICAL N69H


TABLE_5_ITEM

OMIT_TABLE_RF
DRAWING NUMBER SIZE
TABLE_5_ITEM

152S00034 1 2.9NH 01005 360MA L4708_RF CRITICAL N69H


TABLE_5_ITEM

Apple Inc.
051-00648 D
152S1576 1 12NH 01005 140MA L4710_RF CRITICAL N69H REVISION

131S0216 1 47PF 01005 C4710_RF CRITICAL N69H


TABLE_5_ITEM
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
TABLE_5_ITEM

152S1946 1 1.4NH 01005 220MA L4706_RF CRITICAL N69H I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
54 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 59 OF 60
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

RADIO SYMBOL(HEIARCHY)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

D D

FCT TESTING WLAN/BT HOUSE KEEPING ANTENNA CONTROL


21 19 18 12
PP_BATT_VCC 24 3
CLK32K_AP
IO IN 33 36 57
WLAN_REG_ON
24 3 IN 33 36 57
8 BB_LAT_GPIO1 OUT 33 41
PP_VCC_MAIN HOST_WAKE_WLAN
25 24 13 4 IO 27 24 3 OUT 33 36 57 60
8 BB_LAT_GPIO2 OUT 33 41
24 3
BT_REG_ON
IN 33 36 57

24 3
WAKE_BT
IN 33 36 57
3
ADC_SMPS1 33 36 HOST_WAKE_BT
OUT 24 33 36 57
OUT
3
ADC_PP_LDO11 33 36
OUT

3
ADC_PP_LDO5 33 36
OUT

3
ADC_SMPS4 33 36
OUT

24
PP_WL_BT_VDDIO_AP
IO

25 PP_STOCKHOLM_1V8_S2R IO

23 RFFE_VIO_S2R IO

PAC_VDD_3V0
23 15 14 4 IO
WLAN PCIE IPC WLAN/OWL UART
27 24 3
HOST_WAKE_WLAN 33 36 57 60
OUT
WLAN_PCIE_WAKE_L 24
OSCAR_CONTEXT_A
24 33 57 IN 33 36 57
OUT
WLAN_PCIE_PERST_L 24
OSCAR_CONTEXT_B
24 IN 33 36 57
IN 33 57

24
WLAN_PCIE_CLKREQ_L 33 57
OUT

C CELLULAR HOUSE KEEPING 24

24
90_WLAN_PCIE_REFCLK_N
90_WLAN_PCIE_REFCLK_P
IN 33 57
C
IN 33 57

24 3
90_WLAN_PCIE_RDN
IN 33 36 57
5 3
RADIO_ON_L 90_WLAN_PCIE_RDP
IN 33 36 38 24 3 IN 33 36 57
8 3
BB_RESET_DET_L 33 36 41 90_WLAN_PCIE_TDN
OUT 24 3 33 36 57
OUT
5 3
RF_PMIC_RESET_L 90_WLAN_PCIE_TDP
IN 33 36 38
24 3 33 36 57
OUT
5 3
BB_RST_L
IN 33 36 38
PCIE_DEV_WAKE
24 IN 33 57

8
AP_WAKE_MODEM
IN 33 41

8 3
BB_WAKE_HOST_L 33 36 41
OUT

8 3
AP_TO_BB_MESA_ON 33 36 41
OUT

8
GSM_TXBURST_IND 33 41

8
BB_IPC_GPIO1
OUT

OUT 33 41
WLAN/BT UART STOCKHOLM INTERFACES
5 3
BB_FORCE_PWM
IN 33 36 38
WLAN_UART_TXD STOCKHOLM_UART_RTS
24 3 OUT 33 36 57 25 3 OUT 33 36 58

24 3
WLAN_UART_RXD STOCKHOLM_UART_CTS
IN 33 36 57 25 3 IN 33 36 58

BT_UART_CTS_L 25 3
STOCKHOLM_UART_TXD 33 36 58
24 3 OUT
IN 33 36 57

BT_UART_RTS_L 25 3 STOCKHOLM_UART_RXD IN 33 36 58
24 3 33 36 57

HSIC IPC 24 3
BT_UART_RXD
BT_UART_TXD
OUT

IN 33 36 57
25 3

25
AP_TO_STOCKHOLM_FW_DWLD_REQ
AP_TO_STOCKHOLM_DEV_WAKE
IN 33

IN 33
36 58

58
24 3 33 36 57
7 3
50_BB_HSIC_DATA 33 36 40
OUT
25 3
STOCKHOLM_TO_PMU_HOST_WAKE 33 36 58
OUT OUT

7 3
50_BB_HSIC_STROBE WLAN_UART_CTS_L 25 3
AP_TO_STOCKHOLM_EN
IN 33 36 40 24 3 IN 33 36 57 IN 33 36 58

8 3
BB_HOST_RDY
IN 33 36 41 WLAN_UART_RTS_L
24 3 33 36 57
8 3
BB_DEVICE_RDY 33 36 41
OUT
OUT

8 3
BB_GPS_SYNC 33 36 41
OUT

B B
BT AUDIO PCM
AUDIO I2S BB_I2S_CLK
24

24
BT_PCM_CLK
BT_PCM_IN
IN 33 36 57

8 IN 33 36 57
IN 33 36 41
BB_I2S_RXD 24
BT_PCM_OUT 33 36 57
8 3 OUT
IN 33 36 41
BB_I2S_TXD 24
BT_PCM_SYNC
8 3 33 36 41 IN 33 36 57
OUT

8 3
BB_I2S_WS
IN 33 36 41

OSCAR UART
8 3
BB_OTHER_RXD
IN 33 36 41

8 3
BB_OTHER_TXD
OUT 33 36 41 BB UART
8 3 BB_UART_TXD OUT 33 36 41

8 3 BB_UART_RXD IN 33 36 41

8 3 BB_UART_CTS_L IN 33 36 41

8 3 BB_UART_RTS_L OUT 33 36 41

BB DEBUG INTERFACES
8 3
BB_CORE_DUMP
IN 33 36 41

7 3
BB_USB_VBUS
IO

7 3
90_BB_USB_N 33 36 40
OUT
90_BB_USB_P
A 7 3 OUT 33 36 40
A
7 3
BB_JTAG_TCK PAGE TITLE
IN 33 40

7 3 BB_JTAG_TMS IN 33 36 40 Radio Subdesign Ports


DRAWING NUMBER SIZE

Apple Inc.
051-00648 D
REVISION
R
4.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
55 OF 55
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 60 OF 60
8 7 6 5 4 3 2 1

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