Schem, MLB, Pb15: Bom Options (In Common Parts)

8 7 6 5 4 3 2 1
DRAWING CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
C 329994 PRODUCTION RELEASED 05/27/04?
D PAGE CONTENTS PAGE CONTENTS D

VIDEO CONNECTORS - INVERTER, DVI, S-VIDEO,
1 TITLE PAGE AND CONTENTS 22
2 SYSTEM BLOCK DIAGRAM 23
LVDS
KBD,TPAD,HALL EFFECT,PWR BUTTON,LMU/SENSOR
SCHEM,MLB,PB15 Thu May 27 14:58:03 2004
INTERNAL CONNECTORS - AIRPORT, HARD DRIVE,
3 POWER BLOCK DIAGRAM 24
www.laptop-schematics.com
OPTICAL DRIVE
4 PCB NOTES AND HOLES 25 FAN CONTROLLER, USB MODEM/SOFT MODEM,

SOUND/LEFT USB/BLUETOOTH, SERIAL DEBUG
5 MPC7447A MAXBUS INTERFACE 26 GIGABIT ETHERNET INTERFACE

BOM OPTIONS (IN COMMON PARTS)
6 MPC7447A DATA / NC PINS / BOOTBANGER 27 FIREWIRE PHY STUFF NO STUFF
1_8V_MAXBUS 1_5V_MAXBUS
7 CPU PLL AND CONFIGURATION STRAPS 28 FIREWIRE PORTS
NO_SSCG SSCG
C 8 INTREPID MAXBUS AND BOOT STRAPS 29 PMU 5V_HD_LOGIC 3V_HD_LOGIC C
9 INTREPID MEMORY INTERFACE / BOOT ROM 30 BATTERY CHARGER AND CONNECTOR

NO_BBANG BBANG
INT_2_5V_COLD INT_2_5V_HOT
10 DDR MEMORY MUXES 31 PBUS SUPPLY / PMU SUPPLY / BACKUP BATTERY ATI_MEMIO_HI ATI_MEMIO_LO
11 400PIN STACKED DDR SODIMM CONNECTOR 32 3.3V / 5V SYSTEM POWER SUPPLY

SOFT_MODEM USB_MODEM
EXT_TMDS
GPU_PWRMSR
12 INTREPID AGP 4X/PCI 33 CPU CORE VOLTAGE POWER SUPPLY
GPU_SS
13 INTREPID ENET/FW/UATA/EIDE INTERFACES 34 1.5V/ 1.8V / 2.5V SYSTEM POWER SUPPLIES VGA_BUFFER_RES
INT_TMDS
14 INTREPID GPIOS/SERIAL/USB INTERFACES/SSCG 35 SIGNAL CONSTRAINTS (1 OF 4) - DDR MEM/CLK
15 INTREPID POWER RAILS/1.5V LDO 36 SIGNAL CONSTRAINTS (2 OF 4) - CPU
B 16 INTREPID DECOUPLING 37 SIGNAL CONSTRAINTS (3 OF 4) - DIGITAL/DIFF B
17 USB 2.0 INTERFACE (uPD720101) 38 SIGNAL CONSTRAINTS (4 OF 4) - POWER NETS
18 CARDBUS INTERFACE (PCI1510) 39 FUNCTIONAL TESTPOINTS
19 M11 AGP INTERFACE & SPREAD SPECTRUM SUPPORT

External TMDS (DVI Transmitter SIL1162) 40 REVISION HISTORY
20 M11 LVDS/TMDS/GPIO & GPU VCORE 41 SIGNAL LOCATIONS
21 M11 POWER 42 COMPONENT LOCATIONS (1 OF 2)
43 COMPONENT LOCATIONS (2 OF 2)
DIMENSIONS ARE IN MILLIMETERS
METRIC Apple Computer Inc.

XX
A TABLE_5_HEAD
X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
TABLE_5_ITEM AGREES TO THE FOLLOWING
051-6653 1 SCHEM,MLB,PB15 SCH1 ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
TABLE_5_ITEM ANGLES II NOT TO REPRODUCE OR COPY IT
820-1600 1 PCBF,MLB,PB15 PCB1 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
QA APPD DESIGNER TITLE
DO NOT SCALE DRAWING
RELEASE SCALE
NONE
SCHEM,MLB,PB15
SIZE DRAWING NUMBER
MATERIAL/FINISH
NOTED AS D 051-6653 REV.
C
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J24 J20 J2
J23
FW - B RUX Board
Ethernet FW - A Connector
Connector Connector Connector P.23
P.26 P.28 P.28 J19
J26 J27
LMU LUX Board
2 DATA PAIRS
2 DATA PAIRS
Connector Battery Power Supply DC-In
4 DATA PAIRS @ 200MHz
U36
@ 400MHZ P.23 Connector & Charger Connector
D U43 J13 P.30 P.30-34 P.30 D
FireWire OPTICAL DRIVE
Ethernet PHY Connector J3 J8
PHY P.27 LIO/Audio SLEEP SMBUS
P.26 P.24 Connector LED 3.3V
G/MII J12
P.25 P.23
3.3V 1394 OHCI ULTRA ATA/100 U28
10/100/1000 3.3V Connector
8BIT TX
8BIT RX
8BIT TX/RX
50MHZ P.24 EIDE
I2S I2C
U53/J1/J18
Fan
PMU
125MHZ I2C Circuit P.29 J5
UIDE P.25 SERIAL
5V CARDBUS
NOT USED J10 J11 Connector
ETHERNET FIREWIRE UATA 100 EIDE CARDSLOT I2S I2C TRACKPAD Keyboard P.18
10/100/1000 400 MB/S Connector Connector
P.13 P.13 P.13 P.14 P.13 J28
P.13 P.13 P.14 P.23 P.23 33MHZ
C Serial Debug 16/32 BITS C
NOT USED USB PORT A SCCA Connector 3.3V/5V
P.14 P.14
P.25 U8
NOT USED USBP.14
PORT B
U51 VIA/PMU
P.14 U11 J6
TI PCI1510
CardBus
NOT USED USBP.14
PORT C
J3
BlueTooth (LIO) NOT USED USB PORT D
P.14
INTREPID BOOTROM
P.12
BOOT ROM
1M X 8
P.9
AIRPORT
Connector
Controller
P.18
P.25 P.24
USB PORT E PCI
J15 P.14 64BITS PCI BUS
33MHZ 32BITS
Modem/SW Modem USB PORT F 33MHZ
P.14 P.12
Connector AGP BUS 3.3V
P.25 1.5V/3.3V U47
32BITS MEMORY MEMORY
B
MAXBUS
P.8 4X AGP
66MHZ ATI CH. A CH. C
U17
B
INTREPID NEC USB2.0
I2C MAXBUS DDR MEMORY
P.9
P.12
M10 (INTERNAL MEM)(INTERNAL MEM)
MEMORY MEMORY
EHCI HC
1.8V
167MHZ
32BIT ADDRESS MEMORY BUS
64MB CH. B CH. D
P.17
J3
64BIT DATA 2.5V P.19-21 (INTERNAL MEM)(INTERNAL MEM)
167MHZ J4 LEFT USB
(VIA SIL1162)
COMPOSITE
64BITS (VIA LIO)
U56 U16/U18/U28/U27
EDID (I2C)
Inverter P.25
S-VIDEO
Connector
TMDS
CPU PLL
APOLLO Config
2:1 DDR MUXES J17
LVDS
P.22
RGB
DDC
P.10 RIGHT USB
CPU P.7
J14 J21 J22
(VIA STATLER)
P.25
(MPC7447) PMU
P.5-6 LCD Panel S-Video DVI-I
J25 Connector Connector Connector
DDR SDRAM DIMM 0 P.22 P.22 P.22 SYSTEM BLOCK DIAGRAM
A NOTICE OF PROPRIETARY PROPERTY
A
DDR SDRAM DIMM 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
SO-DIMM Connector I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
P.11 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
2 OF
44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POWER SYSTEM ARCHITECTURE

+5V_MAIN
1V20_REF -
>~13.44V TURNS-ON
PG 31
+
BACKLIGHT VCC MAP31 DDR CORE DCDC_EN
<~13.44V SHUTS-OFF
INVERTER MAP31 DDR I/O SLEEP
MAIN 2.5V/1.5V DDR POWER
D AC RUN/SS D
DC/DC +2.5V_MAIN
BUCK
+PBUS
INRUSH MAXBUS
ADAPTER LIMITER +24V_PBUSVCC REGULATOR (MAX1715) SEQUENCING
IN +PBUS PG 34 PGOOD 1_5V_2_5V_OK
PG 30 (LTC1625)
PG 30 PG 31 SHUTDOWN: STOPPED
+1.5V_MAIN
14V_PBUS AC: 12.8V +5V_MAIN SLEEP: RUNNING
RUN: RUNNING
NO AC: BATTERY VOLTAGE INTREPID CORE
1625 NOT RUNNING TURNS ON OUTPUT @ 2.4V AGP I/O +5V_MAIN
ON1/ON2
SHUTDOWN: RUNNING
SLEEP: RUNNING VCC SHDN
RUN: RUNNING
+5V_MAIN
DCDC_EN_L
AFTER PMU IS UP AND RUNNING
DCDC_EN_L WILL PULL ON1/ON2
DC/DC
+3V_PMU RC AT 1M*0.047UF @ 24V
STARTS 2.0MSEC AFTER DCDC_EN_L BECOMES LOW
LOW IN SHUTDOWN (MAX1717)
+5V_MAIN
+BATT LDO +3V_PMU SHUTDOWN: STOPPED
+4_6V_BU
RUN/SS - 5V
TURNS ON AT >1V +5V_MAIN +PBUS EXT_VCC SLEEP: STOPPED
RUN: RUNNING
C <100UA ALLOWED VCC C
PG 31 INTERNAL ZENER CLAMP TO 6V DC/DC PG 33
MAIN 3V/5VPGOOD 3V_5V_OK (LTC1778) GPU_VCORE
DC/DC SHUTDOWN: STOPPED +1.2V
(LTC3707) HOLDS BOTH RUN/SS AT GND DCDC_EN SLEEP: D3COLD CPU_VCORE
WHEN IT’S CONNECTED TO GND (+1.385V)
14V_PBUS
VCC
PG 32STBYMD TURNS CONTROL TO RUN/SS
WHEN IT’S OPEN
SLEEP
D3_COLD
RUN: RUNNING
TURNS ON AS LOW AS 0.8V/TYP 1.5V
INTERNAL 1.2UA CURRENT SOURCE
SHUTDOWN: STOPPED
SLEEP: RUNNING GPU_VCORE RUN/SS PG 20
RUN: RUNNING SEQUENCING 1_5V_2_5V_OK WILL NOT PULL LOW UNTIL
BACKUP 14V CHARGES BACKUP BATTERY
INTERNAL ZENER CLAMP TO 6V
<100UA ALLOWED +3.3V_MAIN
+5V_MAIN TURNS ON
HOWEVER, 5V SHOULD TURN ON ~2.23MS AFTER
1M & 0.1UF @14V, IT TAKES DCDC_EN_L OR PMU_POWERUP_L
BATTERY TURNS ON AT >1V
RUN/SS - 3V
~5.88MS TO START SWITCHER 1_5V_2_5V_OK
D3_HOT
BECOMES ’1’; MUCH LESS THAN THE
RC CHARGING AT INT_VCC (5V)
DCDC_EN_L
D3_HOT
24V IS OUTPUT ONLY FROM
BACKUP BATTERY
RC AT 1M*0.1UF @ 24V
CHARGER INPUT STARTS ~4.25MSEC AFTER DCDC_EN_L BECOMES LOW
SHUT-DOWN RUN SLEEP RUN SHUT-DOWN
& BOOST OUTPUT NO INRUSH PROTECTION
WHEN ONLY BATTERY IS CONNECTED SLEEP
B PG 31 +24V_PBUS SLEEP_L_LS5 B
BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS
DCDC_EN
AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V DC/DC DCDC_EN_L
(UNTIL DRAINED)
(LTC3411)+1.8V_MAIN +5V_MAIN ~2.23MS
BATTERY +5V_SLEEP
SHUTDOWN: STOPPED MAXBUS +3V_MAIN ~7.36MS
CHARGER SLEEP: STOPPED
RUN: RUNNING +3V_SLEEP
(MAX1772) PG 34 3V_5V_OK 2.4V - ??? MS
PG 30 +2_5V_MAIN ??? MS
+2_5V_SLEEP
+BATT +1_5V_MAIN ??? MS
NO INRUSH PROTECTION +1_5V_SLEEP

3S 2P 18650 CELLS WHEN ONLY BATTERY IS CONNECTED
1_5V_2_5V_OK
(MAX1715 OUTPUT)
A
BATTERY VOLTAGE 1_5V_2_5V_OK
(AT LTC1778 RUN/SS)
POWER BLOCK DIAGRAM
+PBUS GPU_VCORE ~8.2MS NOTICE OF PROPRIETARY PROPERTY
A
FEED-IN PATH (D3HOT)
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
GPU_VCORE PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
PG 30 (D3COLD) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
3 OF
44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOARD HOLES
CHASSIS MOUNTS
D
PCB SPECS ASICS HEATSINK MOUNTS I/O AREA
ZT7
HOLE-VIA-20R10 LEFT CPU
1
ZT85
HOLE-VIA-20R10
1
CHGND2
DVI
INVERTER
1
SH1
2 OG-503040
3
SHLD-SM
D
ZT21
HOLE-VIA-20R10 UPPER RT GPU
THICKNESS : 1.2 MM / 0.047 IN 1
ZT86
HOLE-VIA-20R101394
1
DVI CHGND3
1/2 OZ CU THICKNESS: 0.7 MILS ZT58

HOLE-VIA-20R10 LWR CPU
1
CHGND1
1.0 OZ CU THICKNESS: 1.4 MILS MECH. HOLES
ZT59 ZT16
HOLE-VIA-20R10 LWR
1
RT GPU HOLE-VIA-20R10
1
ZT74
HOLE-VIA-20R10
BATT. CHRGR 1
CHGND5
IMPEDANCE : 50 OHMS +/- 10% ZT36

HOLE-VIA-20R10
DIELECTRIC: FR-4 ZT301_SPN
NO_TEST=TRUE
1
ZT23
LAYER COUNT: 10 ZT302_SPN
HOLE-VIA-20R10
1
SIGNAL TRACE WIDTH: 4 MILS NO_TEST=TRUE
ZT42
HOLE-VIA-20R10
SIGNAL TRACE SPACING: 4 MILS ZT10_SPN
NO_TEST=TRUE
1
C PREPREG THICKNESS: 2-3 MILS C
SEE PCB CAD FILES FOR MORE SPECIFIC INFO.

GROUND VIAS
ZT48 ZT11 ZT25
BOARD STACK-UP AND CONSTRUCTION ZT76
HOLE-VIA-20R10
1
ZT50
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
1-8-1 BLIND MICROVIA/20R10 BURIED VIA/20R10 TH VIA ZT28 ZT51 ZT47 ZT34
HOLE-VIA-20R10
ZT19
HOLE-VIA-20R10
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
1 SIGNAL (1/2 OZ + COPPER PLATING) 1 1 1 1 1
ZT72 ZT52 ZT54 ZT20 ZT24

PREPREG (3 MIL) HOLE-VIA-20R10 HOLE-VIA-20R10 1 1
2 SIGNAL (1/2 OZ) 1 1 1

HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
1 1 1
1 1
PREPREG (3 MIL)
3 GROUND (1/2 OZ)
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
1 1 1
1 1
CORE (3 MIL)
4 SIGNAL (1/2 OZ)
B HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1 HOLE-VIA-20R10
1
B
PREPREG (5 MIL) ZT9
5 CUT POWER PLANE (1 OZ) ZT61 ZT82 ZT5 HOLE-VIA-20R10 ZT31
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 1 HOLE-VIA-20R10
1 1 1 1
6 CORE (5 MIL) ZT38 ZT22 ZT15 ZT75

CUT POWER PLANE (1 OZ) HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT1
1 1 1 1 HOLE-VIA-20R10
1
ZT39 ZT17 ZT44 ZT73

PREPREG (5 MIL) HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT14
7 SIGNAL (1/2 OZ) 1 1 1 1 HOLE-VIA-20R10
1
ZT40 ZT35 ZT4 ZT63

HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT12
8 CORE (3 MIL) 1 1 1 1 HOLE-VIA-20R10
1
GROUND (1/2 OZ)
ZT41 ZT45 ZT8 ZT77
HOLE-VIA-20R10
1 1 ZT27
HOLE-VIA-20R10
1 1
9 PREPREG (3 MIL)
SIGNAL (1/2 OZ) ZT6 ZT66
1
ZT46
HOLE-VIA-20R10
ZT79
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT26
1 1 1 1 HOLE-VIA-20R10
10 PREPREG (3 MIL)
SIGNAL (1/2 OZ + COPPER PLATING) ZT32 ZT62
1
ZT71
HOLE-VIA-20R10
ZT81
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT30
1 1 1 1 HOLE-VIA-20R10
1
ZT78 ZT83 ZT3 ZT65

ZT33
A
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1 HOLE-VIA-20R10
1
BOARD INFORMATION
ZT80 ZT49 ZT10 ZT13 A
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT18 NOTICE OF PROPRIETARY PROPERTY
1 1 1 1 HOLE-VIA-20R10 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
4 OF
44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MAXBUS_SLEEP 5 6 7 8 15 16 33 38 1_5V_MAXBUS
+1_5V_SLEEP
CPU_VCORE_SLEEP 5 6 33 38 39
CPU_VCORE DECOUPLING NETWORK CPU_OVDD DECOUPLING NETWORK R281
0 MPC7447 PULL-UPS
1 2
5%
1/16W
R381 C32 C59 1 C104 1 C26 1 C39 1 C50 1 C45 1 C29 1 C55 1 C2 1 C108 R89 1 1 C38 1 C88 1 C44 1 C20 1 C87 1 C61 MF
603 MAXBUS_SLEEP
470 10uF 10uF 10uF 0.1uF 0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20% 0.1uF 470 0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20% 1_8V_MAXBUS
38 33 16 15 8 7 6 5
20% 20% 20% 20% 20% 5% +1_8V_SLEEP

5%
1/16W 6.3V 6.3V 2 6.3V 10V
2 CERM 2 10V
CERM
10V
2 CERM 10V
2 CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM 10V
2 CERM 1/16W 10V
2 CERM 10V
2 CERM 10V
2 CERM 2 10V
CERM
10V
2 CERM 10V
2 CERM R283
MF
402 2
CERM
805
CERM
805
CERM
805 402 402 402 402 402 402 402 402
MF
402 2 402 402 402 402 402 402
1
0 2
R24
10K
8 5 CPU_TBEN 1 2
5%
1/16W 5%
MF
603
1/16W
MF R4
1 C33 1 C58 1 C107 1 C30 1 C49 1 C31 1 C47 1 C27 1 C53 1 C103 1 C110 1 C18 1 C89 1 C72 1 C10 1 C69 1 C81 402
1
10K 2
D
D 10uF
20%
10uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
2 10V 10V
0.1uF
20%
0.1uF
20%
10V 2 10V
0.1uF
20%
0.1uF
20%
2 10V
0.1uF
20%
10V 10V
0.1uF
20%
0.1uF
20%
10V
0.1uF
20%
10V
0.1uF
20%
10V 2 10V
0.1uF
20%
0.1uF
20%
10V
0.1uF
20%
10V
5 CPU_CHKS_L
5%
2 6.3V
CERM
805
2 6.3V
CERM
805
10V
2 CERM
402
10V
2 CERM
402
CERM
402
2 CERM
402
2 CERM
402
CERM
402
CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
CERM
402
2 CERM
402
2 CERM
402
R25
10K
1/16W
MF
402
5 CPU_SHD0_L 1 2
CPU INTERNAL PLL FILTERING 5%
For CPU DFS mode, Must stuff R748
1/16W
MF
402
R46
10K
1 C34 1 C62 1 C109 1 C28 1 C48 1 C56 1 C46 1 C25 1 C54 1 C68 1 C1 1 C86 1 C9 1 C75 1 C73 1 C17 1 C82 NO STUFF 5 CPU_SHD1_L 1 2
2.2uF 2.2uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 5%
20% 20% 20% 20% 20%
2 10V 10V
20% 20%
10V 2 10V
20% 20%
2 10V
20%
10V 20% 20%
10V
20%
10V
20%
10V 2 10V
20% 20%
10V
20%
10V R453 R13 1/16W
MF
2 10V
CERM
10V
2 CERM 10V
2 CERM 10V
2 CERM CERM 2 CERM 2 CERM CERM CERM 2 CERM 10V
2 CERM 2 CERM 2 CERM 2 CERM CERM 2 CERM 2 CERM 10 10K 2 402
805 805 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 2 1 CPU_VCORE_SLEEP 5 6 33 38 39
5 CPU_MCP_L 1
1% 5%
1/16W
R748 1/16W
R26
MF MF
402 10 402
38 CPU_AVDD 2 1 38 CPU_AVDD_VOUT
CPU_LSSD_MODE 1
10K 2
5
1%
1/16W 5%
MF R8 1/16W
H10
H12
J11
J13
K10
K12
K14
L11
L13
M10
M12
C12
P11
R13
R16
U12
U16
V10
V14
E18
G18
MORE 0805 10UF CAPS ON VCORE POWER SUPPLY PAGE (PG 32) 402 10K MF
C810 C811
H8
J7
J9
K8
L7
L9
M8
B4
C2
D5
F2
H3
J5
K2
L5
M3
N6
P2
P8
R4
T6
T9
U2
V4
V7
A8
1 1 1 2 402
OMIT 5 CPU_L2TSTCLK
XW34
SM VDD OVDD AVDD
0.1uF
20%
4.7uF
20% 5%
25 ADT7460_VCORE_MON 1 2 OVDDSENSE
10V
2 CERM
402
6.3V
2 CERM
805
1/16W
MF
402
R7
1K
39 5 CPU_CHKSTP_OUT_L 1 2
36 8 CPU_BR_L D2 BR* BVSEL B7 CPU_BUS_VSEL 7 5%
36 8 CPU_BG_L M1 BG* +3V_SLEEP R28
10K
1/16W
MF
402
NC SYSCLK A10 SYSCLK_CPU 8 35 CPU_SRWX_L 1 2
5
36 8 CPU_TS_L L4 TS* CLK_OUT H2 CPU_CLKOUT_SPN NO_TEST=TRUE 5%
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
PLL_CFG0 B8 CPU_PLL_CFG<0> 7
1/16W
MF R27
5 CPU_PULLDOWN E11 A0 TABLE_5_ITEM PLL_CFG1 C8 CPU_PLL_CFG<1> 7
Vout=0.59*(1+R1/R2)
CPU_PMONIN_L
402
1
10K 2
5
H1 337S2912 1 IC,APOLLO7 PM,R1.1,1,1.50GHZ,1.24VCORE U56 CRITICAL CPU_BST C7 Place R449 & R452 close to U5 pin 6&5
A1 PLL_CFG2 CPU_PLL_CFG<2> 7 R3021 5%
C11 A2 337S2913 1 IC,APOLLO7 PM,R1.1,1,1.33GHZ,1.18V CORE U56 CRITICAL CPU_BTR
TABLE_5_ITEM
PLL_CFG3 D7 CPU_PLL_CFG<3> 7 0 CPU_BST R33 1/16W

MF
C CPU_ADDR<0>
G3
F10
A3
(Nap Voltage=0.98V for both Config.)
PLL_CFG4 A7
M2
CPU_PLL_CFG<4>
CPU_DBG_L
7
5%
1/16W
MF U5 C626
0.001uF
1 1
R449 5 CPU_EMODE1_L 1
10K 2
402
C
36 8 A4 DBG* 8 36 603 2 FAN2558 10% 110K 5%
36 8 CPU_ADDR<1> L2 A5 DRDY* R3 CPU_DRDY_L 8 36
CPU_AVDD_VIN 1 VIN
SOT23-6
VOUT 6
50V
CERM
R1 1%
1/16W
1/16W
MF R3
36 8 CPU_ADDR<2> D11 A6 DTI0 G1 CPU_EDTI 5
38
402 2 MF
CPU_PULLUP
402
1
1K 2
4 PG 2 402 5
36 8 CPU_ADDR<3> D1 A7 DTI1 K1 CPU_DTI<0> 8 36
CPU_AVDD_SHDN_L 3 EN ADJ 5 CPU_AVDD_ADJ
1 C102 5%
CPU_ADDR<4> C10 A8 DTI2 P1 CPU_DTI<1> 1uF 1/16W
36 8
CPU_ADDR<5> G2 A9 DTI3 N1 CPU_DTI<2>

8 36
D17 GND
10%
2 6.3V
R20 MF
402
36 8 8 36
SM 1
R452 CERM
CPU_HRESET_L 1
10K 2
36 8 CPU_ADDR<6> D12 A10 2 1 1 C85 2
100K
402 39 7 6 5
36 8 CPU_ADDR<7> L3 A11 2.2uF R2 1%

5%
1/16W
10%
36 8 CPU_ADDR<8> G4 A12 TDI B9 JTAG_CPU_TDI 5 6 39
MBR0530
R455 2 6.3V
CERM1
1/16W
MF
MF
402 R34
36 8 CPU_ADDR<9> T2 A13 TDO A4 JTAG_CPU_TDO_TP 39 100K
603 2 402
CPU_SMI_L 1
10K 2
29 5
CPU_ADDR<10> F4 A14 TMS F1 JTAG_CPU_TMS
36 8 5 6 39 5%
CPU_ADDR<11> V1 C6 JTAG_CPU_TCK 5% 1/16W
A15 TCK
36 8
CPU_ADDR<12> J4 A16 TRST* A5 JTAG_CPU_TRST_L

5 6 39 1/16W
MF
1 C502 R32 MF
402
36 8
R2 OMIT E8
5 6 39 402 0.1uF
20% 33 VCORE_SHDN_L 470OHM FOR BOOT BANGER 39 JTAG_CPU_TMS 1
470 2
36 8 CPU_ADDR<13> A17 LSSD_MODE* CPU_LSSD_MODE 5 10V
6 5
2 CERM 5%
36 8 CPU_ADDR<14>
CPU_ADDR<15>
K5
W2
A18
A19
U56 L1_TSTCLK
L2_TSTCLK
G8
B3
CPU_L1TSTCLK
CPU_L2TSTCLK
5 402 1
R755 1/16W
MF
R2
36 8
36 8 CPU_ADDR<16> J2 A20
1.XXGHZ 5
5%
0 402
470
36 8 CPU_ADDR<17> K4 A21 APOLLO7-1.XXV TA* K6 CPU_TA_L 8 36
1/16W
MF
2 402
470OHM FOR BOOT BANGER 39 6 5 JTAG_CPU_TDI 1
5%
2
36 8 CPU_ADDR<18> N4 A22 BGA TEA* L1 CPU_TEA_L 8 36 VCORE_SHDN_L_3V 1/16W

MF
36 8 CPU_ADDR<19> J3 A23
(1 OF 3)
1
NO STUFF R19
10K
402
36 8 CPU_ADDR<20> M5 A24 R775 14 5 MPIC_CPU_INT_L 1 2
CPU_ADDR<21> P5 A25 TBEN E1 CPU_TBEN 200K
36 8 5 8
5% 5%
CPU_ADDR<22> N3 P4 CPU_QREQ_L 1/16W 1/16W
36 8 A26 QREQ* 8 36
MF MF
36 8 CPU_ADDR<23> T1 A27 QACK* G5 CPU_QACK_L 8 36 2 402
402 R6
10K 2
36 8 CPU_ADDR<24> V2 A28 CKSTP_IN* A3 39 5 CPU_SRESET_L 1
B 36 8
36 8
CPU_ADDR<25>
CPU_ADDR<26>
U1
N5
A29
A30
CKSTP_OUT* B1 CPU_CHKSTP_OUT_L 5 39

TABLE_5_HEAD
5%
1/16W
MF
B
W1 402
36 8 CPU_ADDR<27> A31 TABLE_5_ITEM
36 8 CPU_ADDR<28> B12 A32 114S1005 1 RES,MF,1/16W,100k ohm,1%,0402,SMD R449 (R1) CPU_BTR

36 8 CPU_ADDR<29> C4 A33
INT* D4 MPIC_CPU_INT_L 5 14
36 8 CPU_ADDR<30> G10 A34
SMI* F9 CPU_SMI_L 5 29
36 8 CPU_ADDR<31> B11 A35
MCP* C9 CPU_MCP_L 5
SRESET* A2 CPU_SRESET_L
NC C1 AP0
HRESET* D8 CPU_HRESET_L
5 39
5 6 7 39
R37
10K
NC E3 AP1 CPU_L1TSTCLK 1 2
5
NC H6 AP2 5%
F5 1/16W
NC
G7
AP3 MF
402
R36
NC AP4 CPU_EDTI 1
10K 2
5
CPU_TT<0> E5 PMON_IN* D9 CPU_PMONIN_L 5 5%

1/16W
36 8 TT0 R11
CPU_TT<1> E6 PMON_OUT* A9 NC MF
402
36 8 TT1 MAXBUS_SLEEP 10K
CPU_TT<2> F6 5 6 7 8 15 16 33 38
39 6 5 JTAG_CPU_TCK 1 2
36 8 TT2
CPU_TT<3> E9 BMODE0* G9 CPU_EMODE0_L 7 BBANG 5%
36 8 TT3 1/16W
CPU_TT<4> C5 BMODE1* F8 CPU_EMODE1_L 5 1
R9 MF R45
36 8 TT4 402 470 2
36 8 CPU_TBST_L F11 TBST* 470 5 CPU_PULLDOWN 1
470OHM FOR BOOT BANGER 5%
36 8 CPU_TSIZ<0> G6 TSIZ0 1/16W 5%
CPU_TSIZ<1> F7 EXT_QUAL A11 CPU_PULLDOWN 5
MF
2 402
1/16W
MF
36 8 TSIZ1 402
36 8 CPU_TSIZ<2> E7 TSIZ2 CHKS* A12 CPU_CHKS_L 5
E2 39 6 5 JTAG_CPU_TRST_L
36 8 CPU_GBL_L GBL*
SRW0* B10 NO_BBANG
A
36 8
36 8
36 8
CPU_WT_L
CPU_CI_L
CPU_AACK_L
D3
J1
R1
WT*
CI*
AACK*
SRW1* E10
IARTRY0* B6
CPU_SRWX_L
CPU_PULLUP
5
5
1
R10
200
5%
1/16W
MPC7447 MAXBUSA
36 8 CPU_ARTRY_L N2 ARTRY* MF NOTICE OF PROPRIETARY PROPERTY
CPU_SHD0_L E4 DX* D10 CPU_PULLDOWN 5
2 402
5 SHD0* THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5 CPU_SHD1_L H5 SHD1* PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
B2 AGREES TO THE FOLLOWING
36 8 CPU_HIT_L HIT*
GND III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

B5
C3
D6
D13
E17
F3
G17
H4
H7
H9
H11
H13
J6
J8
J10
J12
K7
K3
K9
K11
K13
L6
L8
L10
L12
M4
M7
M9
M11
M13
N7
P3
P9
P12
R5
R14
R17
T7
T10
U3
U13
U17
V5
V8
V11
V15
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
5 OF
44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
BOOT BANGER - TWEAK PROCESSOR BITS AFTER POWER-ON
NC A14 N/C_1
NC B14
NC C14
N/C_2 U56 +3V_SLEEP
NC D14
N/C_3
N/C_4
1.XXGHZ
NC E14 N/C_5
BGA
(3 OF 3) BBANG
NC F14 N/C_6
APOLLO7-1.XXV
NC G14 N/C_7 1 C120 D
D NC A15 N/C_8 BBANG 0.1uF
20%
36 8 CPU_DATA<0> R15 D0 OMIT NC B15 N/C_9 8 10V
2 CERM
NC C15 N/C_10 VCC 402
36 8
36 8
CPU_DATA<1>
CPU_DATA<2>
W15
T14
D1
D2
U56 NC D15 N/C_11 U52
32KX8_M24256B
36 8 CPU_DATA<3> V16 D3 1.XXGHZ NC E15 N/C_12
6 BB_EEPR_ADDR 1 NC1
SOI
SDA 5 INT_I2C_DATA0 6 11 13 23 39
W16 NC F15 N/C_13
36 8 CPU_DATA<4> D4 BGA NC G15
2 NC2 SCL 6 INT_I2C_CLK0 6 11 13 23 39
36 8 CPU_DATA<5> T15 D5 (2 OF 3) N/C_14 3 NC3
CPU_DATA<6> U15 D6 NC H15 N/C_15
APOLLO7-1.XXV
36 8
WC* 7 BB_EEPR_WP_PD
36 8 CPU_DATA<7> P14 D7 NC J15 N/C_16 VSS BBANG
CPU_DATA<8> V13 D8 NC K15 N/C_17 SYM_VER2
4 1
36 8
NC L15 R637
36 8 CPU_DATA<9> W13 D9 N/C_18 10K
36 8 CPU_DATA<10> T13 D10 NC C16 N/C_19 1%
1/16W
36 8 CPU_DATA<11> P13 D11 NC D16 N/C_20 MF
U14 NC C17 N/C_21 2 603
36 8 CPU_DATA<12> D12
36 8 CPU_DATA<13> W14 D13 NC D17 N/C_22
36 8 CPU_DATA<14> R12 D14 NC C18 N/C_23
+3V_SLEEP
36 8 CPU_DATA<15> T12 D15 NC D18 N/C_24
36 8 CPU_DATA<16> W12 D16 NC C19 N/C_25
36 8 CPU_DATA<17> V12 D17 NC D19 N/C_26 BBANG
36 8 CPU_DATA<18> N11 D18 NC H16 N/C_27 RP46 +3V_SLEEP
BBANG
CPU_DATA<19> N10 D19 NC J16 N/C_28 1
10K
36 8
R11 NC K16 N/C_29 R692 BBANG 5%
1/32W
36 8 CPU_DATA<20>
U11
D20
NC L16 N/C_30
10K
1%
1 C762 25V
36 8 CPU_DATA<21> D21 1/16W (Ra) 0.1uF
CPU_DATA<22> W11 NC J17 N/C_31 MF 20% ESP_EN_L 1 5
2 10V
6
36 8 D22 2 603
36 8 CPU_DATA<23> T11 D23 NC K17 N/C_32 CERM
402 6 BFR_TDO 2 10
CPU_DATA<24> R10 D24 NC L17 N/C_33 6 ICT_TRST_L 3
C
36 8
36 8 CPU_DATA<25> N9 D25 NC J18

NC K18
N/C_34 1
NO STUFF
R709 20
6 BBANG_JTAG_TCK 4
BB_MOSI 6
C
36 8 CPU_DATA<26> P10 D26 N/C_35 10K 6
BBANG VCC
U10 NC L18 N/C_36 1% (Rb) BB_MISO 7
36 8 CPU_DATA<27> D27
NC J19 N/C_37
1
R707 1/16W U54 6
BB_SCK 8
36 8 CPU_DATA<28> R9 D28 10K MF
2 603
AT90S1200A 6
36 8 CPU_DATA<29> W10 D29 NC K19 N/C_38 1% SSOP 6 BB_EEPR_ADDR 9

1/16W BB_RESET_L 1 RESET*
36 8 CPU_DATA<30> U9 D30 NC L19 N/C_39 MF 39
SM
V9 2 603 5
OMIT
36 8 CPU_DATA<31> D31 39 38 33 5 CPU_VCORE_SLEEP A13 BB_XTAL1_SPN XTAL1
36 8 CPU_DATA<32> W5 D32 A16 4 XTAL2
36 8 CPU_DATA<33> U6 D33 A18 BBANG
1
36 8 CPU_DATA<34> T5
U5
D34 B17 R712 39 29 6 PMU_CPU_HRESET_L 12 PB0 PD0 2 ESP_EN_L 6
36 8 CPU_DATA<35> D35 B19 10K RESET_VREF 13 PB1 PD1 3 BFR_TDO 6

W7 1% 14 6
36 8 CPU_DATA<36> D36 C13 1/16W 6 BBANG_HRESET_L PB2 PD2 ICT_TRST_L 6
R6 MF 15 7
CPU_DATA<37> D37 E13 INT_I2C_CLK0 PB3 PD3 BBANG_JTAG_TCK
36 8
2 603 39 23 13 11 6 6
36 8 CPU_DATA<38> P7 D38 E16 39 23 13 11 6 INT_I2C_DATA0 16 PB4 PD4 8 JTAG_CPU_TMS 5 39
36 8 CPU_DATA<39> V6 D39 F12 6 BB_MOSI 17 PB5 PD5 9 JTAG_CPU_TDI 5 39
36 8 CPU_DATA<40> P17 D40 F17 6 BB_MISO 18 PB6 PD6 11 JTAG_CPU_TRST_L 5 39
36 8 CPU_DATA<41> R19 D41 F19 6 BB_SCK 19 PB7

36 8 CPU_DATA<42> V18 D42 G11 GND
CPU_DATA<43> R18 VDD 10
36 8 D43 G16
36 8 CPU_DATA<44> V19 D44 H14
36 8 CPU_DATA<45> T19 D45 H17 UNSTUFFING Ra AND STUFFING Rb
36 8 CPU_DATA<46> U19 D46 H19 WILL DISABLE THE CONTROLLER
36 8 CPU_DATA<47> W19 D47 M14 TABLE_5_HEAD
36 8 CPU_DATA<48> U18 D48 M16 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
36 8 CPU_DATA<49> W17 D49 M18 009-6240 FW GT4 BBANGER TABLE_5_ITEM
341S1135 1 MCU,PROGRAMMED W/ BBANGER U54 BBANG

36 8 CPU_DATA<50> W18 D50 N15
B 36 8
36 8
CPU_DATA<51>
CPU_DATA<52>
T16
T18
D51
D52
N17
P16
B
CPU_DATA<53> T17 38 33 16 15 8 7 6 5 MAXBUS_SLEEP
36 8 D53 P18
36 8 CPU_DATA<54> W3 D54 +3V_SLEEP
V17 N12 MAXBUS_SLEEP
36 8 CPU_DATA<55> D55 38 33 16 15 8 7 6 5
G13 SENSEVDD
36 8 CPU_DATA<56> U4 D56 BBANG NO_BBANG
CPU_DATA<57> U8 D57 A17
36 8
CPU_DATA<58> U7 D58 A19

R1001 BBANG BBANG R104
36 8 10K R1051 R1031 1
0 2
CPU_DATA<59> R7 D59 B13 5%
36 8
1/16W 10K 10K 5%
36 8 CPU_DATA<60> P6 D60 B16 MF 5% 5%
1/16W
402 2 1/16W 1/16W
CPU_DATA<61> R8 MF MF MF
36 8 D61 B18 5 SN74AUC1G08 402 2 402 2 402
36 8 CPU_DATA<62> W8 D62 E12 BBANG_TCK_EN 1 SC70-5
A 5 SN74AUC1G08
T8 4 1 SC70-5
36 8 CPU_DATA<63> D63 E19
2
U9 Y JTAG_CPU_TCK 5 39 39 29 6 PMU_CPU_HRESET_L A
4
T3
F13 6 BBANG_JTAG_TCK B BBANG
BBANG_HRESET_L 2
U10 Y CPU_HRESET_L 5 7 39
NC DP0 F16 3 6 B BBANG

NC W4 DP1 F18 INPUTS ARE 3V TOLERANT 3 INPUTS ARE 3V TOLERANT
NC T4 DP2 G19
NC W9 DP3 H18 GND
NC M6 DP4 J14
NC V3 DP5 L14
NC N8 DP6 M15
NC W6 DP7 M17
M19
N14
A
N16
P15
MPC7447/BBANG
P19
NOTICE OF PROPRIETARY PROPERTY
A
N13
G12 SENSEGND THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
25 CPU_THERM_DP N18 TEMP_ANODE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
N19 TEMP_CATHODE II NOT TO REPRODUCE OR COPY IT

25 CPU_THERM_DM
NC A6 HPR*
APPLE COMPUTER INC.

D 051-6653 C
SCALE SHT OF
NONE
6 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU PLL CONFIG CIRCUITRY CPU FREQUENCY CONFIGURATION

38 33 16 15 8 7 6 5 MAXBUS_SLEEP APOLLO 7
CORE FREQUENCY
1
R35 1
R50 1
R68 1
R79 1
CPU_BST
R18
MULTIPLIER (AT BUS FREQUENCY) CPU_PLL_CFG
10K
5% 5%
10K
5%
10K 10K
5%
10K
5%
167MHZ 133MHZ
1/16W 1/16W 1/16W 1/16W 1/16W 4 0123
D MF
2 402
MF
2 402
MF
2 402
MF
2 402
MF
2 402 (Bus-to-Core) (MHZ) E ABCD HEX D
CPU_PLL_CFG<0>
CPU_PLL_CFG<1>
5
5
0.0X PLL OFF 0 1111 0F
CPU_PLL_CFG<2>
CPU_PLL_CFG<3>
5
5
1.0X PLL BYPASS 0 0011 03
1
CPU_PLL_CFGEXT CPU_PLL_CFG<4> 5
2.0X 333 267 0 0100 04
S
+5V_SLEEP NOW REQUIRED FOR PLL_STOP_L R01A R00A R10A R01B R00B R10B R01C R00C R10C R01D R00D R10D R01E R10E CPU_BST R00E 3.0X 500 400 0 1000 08
G
PULLUP TO ENSURE THAT Vgs OF PASS
TRANSISTOR ON CPU_PLL_CFG<4> IS MET. CPU_BST NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF CPU_BTR NO STUFF NO STUFF CPU_BTR NO STUFF NO STUFF NO STUFF NO STUFF Q3 CPU_BTR
2N7002DW
2
1
1
R43 1
R44 1
R48 1
R60 1
R63 1
R64 1
R70 1
R76 1
R78 1
R84 1
R88 1
R92 1
R23 1
R31 SOT-363 R12 4.0X 667 533 0 1010 0A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+3V_SLEEP +5V_SLEEP 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
MF MF MF MF MF MF MF MF MF MF MF MF MF MF
STUFF PASS TRANSISTOR ONLY IF
MF
2 402
5.0X 833 667 0 1011 0B
2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
R10E, R01E, OR PULLUP STUFFED
CPU_PLL_FS01
5.5X 917 733 0 1001 09
R1331 R141 1
R132
47K
5%
82K
5%
10K
5% 3 6.0X 1000 800 0 1101 0D
1/16W 1/16W 1/16W 7 PLL_STOP_L 3
MF MF MF D
402 2 402 2 2 402
CPU_BST 6.5X 1083 867 0 0101 05
D Q3
1 G S 2N7002DW
29 7 CPU_PLL_STOP_OC
5 G S
SOT-363 7.0X 1167 933 0 0010 02
Q13 2
2N7002
SM CPU_PLL_FS00
4 7.5X 1250 1000 0 0001 01
6 8.0X 1333 1067 0 1100 0C
D
Q14 8.5X 1417 1133 0 0110 06
C 7 PLL_STOP_L
2 G S
2N7002DW
SOT-363
C
Q14 9.0X 1500 1200 1 0111 17
2N7002DW 3 1
SOT-363
D CPU_PLL_FS10
9.5X 1583 1267 0 0111 07
29 7 CPU_PLL_STOP_OC 5 G S CPU_PLL_STOP_BASE
10.0X 1667 1333 1 1010 1A
3
4 R131 10.5X 1750 1400 1 1000 18
249K 2
1 1 Q12 STATE ENCODING CPU_PLL_STOP_OC CPU_VCORE_HI_OC
1% 2N3904 11.0X 1833 1467 1 1001 19
1/16W SM
MF
402
2 LOW SPEED 0 0
HIGH SPEED 0 1 11.5X 1917 1533 0 0000 00
PLL DISABLE 1 X 12.0X 2000 1600 1 1011 1B
CPU_VCORE_HI_OC
33 29
12.5X 2083 1667 1 1111 1F
13.0X 2167 1733 1 0101 15
CPU CONFIGURATION 13.5X

14.0X
2250
2333
1800
1867
0
1
1110 0E
1100 1C
15.0X 2500 2000 1 0001 11
16.0X 2667 2133 1 1101 1D
B B
17.0X 2833 2267 1 0000 10
MAXBUS VSEL 18.0X 3000 2400 1 0010 12
INVERTED HRESET_L
20.0X 3333 2667 1 0011 13
38 33 16 15 8 7 6 5 MAXBUS_SLEEP
BUSTYPE SELECT 21.0X 3500 2800 1 0100 14
1.5V INTERFACE 24.0X 4000 3200 1 0110 16
1_5V_MAXBUS
1_5V_MAXBUS R110
U12 1
22 2
28.0X 4667 3733 1 1110 1E
5
SN74AUC1G04
R5 39 7 6 5 CPU_HRESET_L CPU_EMODE0_L 5
2 4 1
22 2
5%
39 7 6 5 CPU_HRESET_L CPU_HRESET_INV CPU_BUS_VSEL 5 1/16W
04 MF
SC70-5 5% 402
3 1/16W
MF
402 1_8V_MAXBUS
APOLLO ONLY SUPPORTS MAXBUS
R171
10
5% 1.8V INTERFACE
1/16W
MF
402 2
CPU CONFIGURATION
A DESKTOP HAD PROBLEM USING NOTICE OF PROPRIETARY PROPERTY
A
SIGNAL TIED APPLICATION
INVERTER TO INVERT HRESET_L THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
CPU_EMODE0_L HIGH 60X BUS MODE PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
NEED TO CHARACTERIZE (PROCESSOR) AGREES TO THE FOLLOWING
CPU_HRESET_L MAX BUS MODE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
CPU_HRESET_L 2.5V INTERFACE II NOT TO REPRODUCE OR COPY IT
CPU_BUS_VSEL III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

LOW 1.8V INTERFACE
(PROCESSOR) SIZE DRAWING NUMBER REV.
CPU_HRESET_INV 1.5V INTERFACE
APPLE COMPUTER INC.
D 051-6653 C
SCALE SHT OF
NONE 7 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE FOLLOWING STRAP BITS CAN BE
CHANGED BY SOFTWARE: MAXBUS PULL-UPS
INTREPID BOOT STRAPS +1_5V_INTREPID_PLL 1
R159
4.7 2 +1_5V_INTREPID_PLL7
1/
2/
D47 - SELAGPSPREADCLK - SLEEP/WAKE CYCLE REQUIRED
D46 - SELPCI1SPREADCLK - SLEEP/WAKE CYCLE REQUIRED
MAXBUS_SLEEP 5 6 7 8 15 16 33 38
38 14 12
5%
38
3/
4/
D44 - PLL4MODESEL_NXT<0> - SLEEP/WAKE CYCLE REQUIRED
RP3
10K
MAXBUS_SLEEP 1/16W 2 7
38 33 16 15 8 7 6 5
BIT 32 TO 39 C187 1 MF
402
5/
6/
D33 - ANALYZERCLK_EN_H - IMMEDIATE EFFECT
36 8 5 CPU_TS_L
0.22uF
20%
5%
1/16W
6.3V 2
CERM H26 IF A STRAP IS NOT LISTED, THEN SM1 RP3
NO STUFF NO STUFF NO STUFF 402 IT CANNOT BE CHANGED BY SOFTWARE 10K
VDD15A_7
R6401 R6391 R6381 R6661 (PLL6) 36 8 5 CPU_TA_L 1 8
10K
5%
10K
5%
10K
5%
10K
5%
5%
1/16W
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
OMIT
U51 D_0 D10 CPU_DATA<0> 6 36 RP3 SM1
D 402 2 402 2 402 2 402 2

36 8 5 CPU_BR_L E29 BR INPUT INTREPID-REV2.1
D_1 G12 CPU_DATA<1>
D_2 E11 CPU_DATA<2>
6 36
36 8 5 CPU_ARTRY_L 4
10K 5 D
36 8 6 CPU_DATA<32> CPU_BG_L E26 6 36
36 8 5 BG NO BUS KEEPER BGA H11 CPU_DATA<3> 5%
36 8 6 CPU_DATA<33> D_3 6 36 1/16W
SM1
36 8 6 CPU_DATA<34> D_4 B9
B8
CPU_DATA<4> 6 36 RP2
10K
36 8 6 CPU_DATA<35> B27 D_5 CPU_DATA<5> 6 36 1 8
36 8 5 CPU_TS_L TS NO BUS KEEPER 36 8 5 CPU_BR_L
D_6 A9 CPU_DATA<6> 6 36
36 8 6 CPU_DATA<36> (1 OF 9) 5%
CPU_ADDR<0> D24 A_0 D_7 A8 CPU_DATA<7> 6 36 1/16W
36 8 6 CPU_DATA<37> 36 5
CRITCAL
D25 A_1 E12 SM1
36 8 6 CPU_DATA<38> 36 5 CPU_ADDR<1> D_8 CPU_DATA<8> 6 36
R152
36 8 6 CPU_DATA<39> 36 5 CPU_ADDR<2> A27 A_2 D_9 D11 CPU_DATA<9> 6 36
CPU_HIT_L 1
10K 2
36 8 5
36 5 CPU_ADDR<3> E24 A_3 D_10 B10 CPU_DATA<10> 6 36
NO STUFF 5%
CPU_ADDR<4> G23 A_4 J13 CPU_DATA<11> 6 36 1/16W
R6221 R6191 R6181 R653 R6211 R6201 R6521 R6501 1 36 5 D_11 MF
RP2
CPU_ADDR<5> B26 A_5 A10 CPU_DATA<12> 6 36 402
10K 10K 10K 10K 10K 10K 10K 10K 36 5 D_12
10K
5% 5% 5% 5% 5% 5% 5% 5% CPU_ADDR<6> A26 A_6 D_13 D12 CPU_DATA<13> 6 36 3 6
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 36 5
36 8 5 CPU_DRDY_L
MF MF MF MF MF MF MF MF 36 5 CPU_ADDR<7> D23 A_7 D_14 E13 CPU_DATA<14> 6 36
1: TDI output
0: TDI input (JTAG)
DDR_TPDModeEnable_h
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 5%

36 5 CPU_ADDR<8> A25 A_8 D_15 G13 CPU_DATA<15> 6 36 1/16W
SM1
36 5 CPU_ADDR<9> E23 A_9 D_16 B11 CPU_DATA<16> 6 36 RP2
10K
1: Active
0: Inactive
AnalyzerClk_En_h
1: Active low
0: Active high
DDR_TPDEn_Pol
1: Active low
0: Active high
ExtPLL_SDwn_Pol
Spare
Spare
Spare
Spare
CPU_ADDR<10> J22 A_10 D_17 D13 CPU_DATA<17> 6 36 4 5
36 5
36 8 5 CPU_TEA_L
36 5 CPU_ADDR<11> B25 A_11 D_18 A11 CPU_DATA<18> 6 36
MAXBUS 5%
CPU_ADDR<12> H22 A_12 D_19 G14 CPU_DATA<19> 6 36 1/16W
36 5
36 5 CPU_ADDR<13> G22 A_13 INTERFACE

D_20 H14 CPU_DATA<20> 6 36
SM1 RP2
10K
36 5 CPU_ADDR<14> D22 A_14 D_21 E14 CPU_DATA<21> 6 36 36 8 5 CPU_AACK_L 2 7
36 5 CPU_ADDR<15> B24 A_15 D_22 B12 CPU_DATA<22> 6 36 5%
B23 A_16 G15 1/16W
36 5 CPU_ADDR<16> D_23 CPU_DATA<23> 6 36 SM1
38 33 16 15 8 7 6 5 MAXBUS_SLEEP 36 5 CPU_ADDR<17> E22 A_17 D_24 B13 CPU_DATA<24> 6 36 R150
10K
BIT 40 TO 47 36 5 CPU_ADDR<18>
CPU_ADDR<19>
J21 A_18
G21 A_19
D_25 H15
D14
CPU_DATA<25> 6 36
CPU_DATA<26> 6 36
36 8 5 CPU_DBG_L 1
5%
2
36 5 D_26 1/16W
CPU_ADDR<20> E21 A_20 D_27 B14 CPU_DATA<27> 6 36 MF RP3
C NO STUFF
R6411R6651R6641 R6931 R6941 R6991
SSCG NO STUFF NO_SSCG NO STUFF NO STUFF 36 5
36 5 CPU_ADDR<21> A24 A_21

D21 A_22
D_28 A12
G16
CPU_DATA<28> 6 36 36 8 5 CPU_BG_L
402
3
10K 6 C
10K 10K 10K 10K 10K 10K 36 5 CPU_ADDR<22> D_29 CPU_DATA<29> 6 36
5%
5% 5% 5% 5% 5% 5% 36 5 CPU_ADDR<23> A23 A_23 D_30 E15 CPU_DATA<30> 6 36 1/16W
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W SM1
MF MF MF MF MF MF H20 A_24 J16
402 2 402 2 402 2 402 2 402 2 402 2 36 5 CPU_ADDR<24> D_31 CPU_DATA<31> 6 36 R151
36 5 CPU_ADDR<25> B22 A_25 D_32 D15 CPU_DATA<32> 6 8 36
CPU_QREQ_L 1
10K 2
36 8 6 CPU_DATA<40> CPU_ADDR<26> H21 A_26 A14 CPU_DATA<33> 6 8 36
36 8 5
36 5 D_33 5%
36 8 6 CPU_DATA<41> CPU_ADDR<27> A22 A_27 A13 CPU_DATA<34> 6 8 36 1/16W
36 5 D_34 MF
36 8 6 CPU_DATA<42> CPU_ADDR<28> E20 A_28 D16 CPU_DATA<35> 6 8 36 402
36 5 D_35
36 8 6 CPU_DATA<43> CPU_ADDR<29> B21 A_29 E16 CPU_DATA<36> 6 8 36
36 5 D_36
36 8 6 CPU_DATA<44> CPU_ADDR<30> D20 A_30 G17 CPU_DATA<37> 6 8 36
36 5 D_37
6 CPU_DATA<45>
36 8
36 8
36 8
6 CPU_DATA<46>
6 CPU_DATA<47>
36 5
36 5
CPU_ADDR<31>
CPU_CI_L
A21 A_31
G26 CI
D_38
D_39
B15
H17
A15
CPU_DATA<38> 6 8 36
CPU_DATA<39> 6 8 36
CPU_DATA<40> 6 8 36
INTREPID BOOT STRAPS
CPU_GBL_L A29 D_40
NO_SSCG SSCG 36 5 GBL B16 CPU_DATA<41> 6 8 36 MAXBUS_SLEEP
CPU_TBST_L A28 D_41 38 33 16 15 8 7 6 5
R6481 R6771R6231R6511R6491 R6781 R6791 R6841 36 5
CPU_TSIZ<0> G24
TBST
D_42 E17 CPU_DATA<42> 6 8 36
BIT 56 TO 63
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
36 5
H24
TSIZ_0
D_43 A16 CPU_DATA<43> 6 8 36
36 5 CPU_TSIZ<1> TSIZ_1
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W D_44 J18 CPU_DATA<44> 6 8 36
MF MF MF MF MF MF MF MF 36 5 CPU_TSIZ<2> D26 TSIZ_2
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 D_45 H18 CPU_DATA<45> 6 8 36 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
CPU_TT<0> E25
36 5
CPU_TT<1> G25
TT_0
D_46 D17 CPU_DATA<46> 6 8 36 R6691 R6451 R6971 R6701 R6441 R6461
BIT2 BIT1 BIT0
36 5 TT_1
D_47 G18 CPU_DATA<47> 6 8 36 10K 10K 10K 10K 10K 10K
Spare
Spare
1: Active
0: Inactive
InternalSpreadEn
1: PLL4
0: PLL5 (no spread)
PCI1 Source Clock
1: PLL4
0: PLL5 (no spread)
PCI0 Source Clock
36 5 CPU_TT<2> B28 TT_2 5% 5% 5% 5% 5% 5%

D_48 A17 CPU_DATA<48> 6 8 36 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
(SW CNTL ONLY)
36 5 CPU_TT<3> D27 TT_3 MF MF MF MF MF MF

PLL4MODESEL_NXT[2:0] D_49 B17 CPU_DATA<49> 6 8 36 402 2 402 2 402 2 402 2 402 2 402 2
000: 166.4MHZ (2.5X) 36 5 CPU_TT<4> J25 TT_4
D_50 E18 CPU_DATA<50> 6 8 36
001: 149.76MHZ CPU_WT_L D28 36 8 6 CPU_DATA<56>
36 5 WT B18 CPU_DATA<51> 6 8 36
010: 133.12MHZ (2.0X) D_51 36 8 6 CPU_DATA<57>
011: 99.84MHZ (1.5X) CPU_AACK_L B29 AACK NO BUS KEEPER - PU D_52 D18 CPU_DATA<52> 6 8 36
100: 83.20MHZ
36 8 5
36 8 6 CPU_DATA<58>
CPU_ARTRY_L H23 ARTRY NO BUS KEEPER - PU D_53 A18 CPU_DATA<53> 6 8 36
MODE A (2.5X) IS FOR STATIC OPERATION 36 8 5
36 8 6 CPU_DATA<59>
B MODE C (2.0X) IS FOR CLOCK SLEW OPERATION 36 8 5 CPU_HIT_L B31 HIT INPUT - PU D_54
D_55
A19
H19
CPU_DATA<54> 6 8 36
CPU_DATA<55> 6 8 36
36 8 6 CPU_DATA<60> B
36 8 6 CPU_DATA<61>
D_56 B19 CPU_DATA<56> 6 8 36
CPU_QREQ_L A32 INPUT - PD 36 8 6 CPU_DATA<62>
MAXBUS_SLEEP
36 8 5 QREQ J19 CPU_DATA<57> 6 8 36
38 33 16 15 8 7 6 5 D_57 36 8 6 CPU_DATA<63>
A20 CPU_DATA<58> 6 8 36
BIT 48 TO 55 36 5 CPU_QACK_L G27 QACK NO BUS KEEPER - ?
D_58
D19 CPU_DATA<59> 6 8 36
NO STUFF
29 INT_SUSPEND_REQ_L AK9 SUSPENDREQ
D_59
E19 CPU_DATA<60> 6 8 36
R6561 R6851 R6571 R6281 R6821 R6581 R6271 R6291
SSCG SSCG NO STUFF NO STUFF NO STUFF 29 INT_SUSPEND_ACK_L AM8 SUSPENDACK
D_60 10K 10K 10K 10K 10K 10K 10K 10K
D_61 G19 CPU_DATA<61> 6 8 36 5% 5% 5% 5% 5% 5% 5% 5%
R6961 R6951 R6671 R6681 R6431 R6421 R6981 FB BUFFER HAS 50 OHM OUTPUT IMPEDANCE D_62 B20 CPU_DATA<62> 6 8 36
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
10K 10K 10K 10K 10K 10K 10K Vin = Intrepid Vcore (1.5V)
G20 CPU_DATA<63> 6 8 36
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2
5% 5% 5% 5% 5% 5% 5% Vout = MaxBus rail (1.8V)
J24 CPU_FB_IN D_63
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 35 8 INT_CPUFB_IN
MF MF MF MF MF MF MF H16 CPU_FB_OUT
INT_CPUFB_OUT NO BUS KEEPER - PU DBG A30 CPU_DBG_L
1: 0-1 IDE / 2-3 PCI1

0: 0 IDE / 1 PCI1
ROM_Ovrly_Rng
OBSOLETE
1: GPIOs
0: REQ/GNT
PCI1_REQ2_L / PCI1_GNT2_L
1: GPIOs
0: REQ/GNT
PCI1_REQ1_L
1: GPIOs
0: REQ/GNT
PCI1_REQ0_L / PCI1_GNT0_L
402 2 402 2 402 2 402 2 402 2 402 2 402 2 35 8 5 8 36
Spare
Spare
1: B-mode interface
0: Legacy interface
FireWire PHY interface
1: 60x bus (G3)

0: Max Bus (G4)
Processor Bus Mode
R1691 SYSCLK_LA_TP G8 ANALYZER_CLK
36 8 6 CPU_DATA<48> 511 G28 CPU_DRDY_L
1% INPUT - PU DRDY 5 8 36
36 8 6 CPU_DATA<49> 1/16W AH9
MF 29 CPU_CLK_EN STOPCPUCLK
36 8 6 CPU_DATA<50> 402 2 K25 CPU_DTI<0>
NO BUS KEEPER - ? DTI_0 5 36
36 8 6 CPU_DATA<51> H13 ACS_REF D29 CPU_DTI<1>
INTREPID_ACS_REF NO BUS KEEPER - ? DTI_1 5 36
CPU_DATA<52> R168
/ PCI1_GNT1_L
36 8 6
NO BUS KEEPER - ? DTI_2 B30 CPU_DTI<2> 5 36
36 8 6 CPU_DATA<53>
SYSCLK_CPU 1
0 2 35 SYSCLK_CPU_UF J15 CPU_CLK
35 5
36 8 6 CPU_DATA<54> NO BUS KEEPER - PU TA E27 CPU_TA_L 5 8 36
5% NO BUS KEEPER - PU TEA E28 CPU_TEA_L
36 8 6 CPU_DATA<55> 1/16W 5 8 36
MF INTREPID OUTPUTS HIGH BY DEFAULT
NO_SSCG NO_SSCG NO STUFF NO STUFF 402 A31 TBEN
5 CPU_TBEN VSSA_7
1 1 1 1 1 1 1 1 1
R681 R680 R654 R655 R625 R624 R683 R626 R161 NO BUS KEEPER - PU (PLL6)
10K 10K 10K 10K 10K 10K 10K 10K 1K H25
5% 5% 5% 5% 5% 5% 5% 5% 1%
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2 Intrepid MaxBus
A SHORT = 1" SHORTER THAN MATCHED LENGTH
LONG = 1" LONGER THAN MATCHED LENGTH
NO STUFF A
1: Active
0: Inactive
BUF_REF_CLK_OUTEnable_h
1: External source
0: PLL5
SelPLL4ExtSrc
1: BootROM on PCI1
0: BootROM on IDE/CardSlot
En_PCI_ROM_P
OBSOLETE (Should remain high)
1: TI PHY workaround
0: Normal 1394b
TI 1394b workaround
Spare
BIT2 BIT1 BIT0 NOTICE OF PROPRIETARY PROPERTY

R155
0
R140
0
R128
0
MaxBus output impedance 35 8 INT_CPUFB_OUT2 1 35 INT_CPUFB_OUT_SHORT 1 2 35 INT_CPUFB_OUT_NORM 1 2 35 INT_CPUFB_LONG THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
111: 28.6 ohm 5% 5% 5% AGREES TO THE FOLLOWING
1/16W 1/16W 1/16W
011: 33.3 ohm MF NO STUFF MF MF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
101: 40 ohm 402 R1461 402 R1411 402 II NOT TO REPRODUCE OR COPY IT
0 0
001: 50 ohm 5% 5% NO STUFF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W 1/16W
110: 66.6 ohm MF
010: 100 ohm
MF
402 2 R147
0
402 2 R136
0
100: 200 ohm

000: 200 ohm
35 8 INT_CPUFB_IN 1
5%
2 35 INT_CPUFB_IN_NORM 1
5%
2
APPLE COMPUTER INC.
D 051-6653 C
1/16W 1/16W
MF
402
MF
402
SCALE
NONE
SHT
8 OF
44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SERIES RESISTORS FOR CLOCK/CONTROL SIGNALS
RP20
4
22 5
35 9 SYSCLK_DDRCLK_A1_UF SYSCLK_DDRCLK_A1 11 35
RP20
22
5%
1/16W
PINS ARE SWAPABLE FOR RPAKS 9
35
SYSCLK_DDRCLK_A1_L_UF3 6
SM1
SYSCLK_DDRCLK_A1_L 11 35
5%
1/16W
SM1
RP22
22
35 9 SYSCLK_DDRCLK_A0_UF 1 8 SYSCLK_DDRCLK_A0 11 35
1MB BOOT ROM
CLOCKS
H35 MEM_ADDR<0> 9 5%
35 10 MEM_DATA<0> AK32 DDR_DATA_0 DDR_A_0
G35
35
RP22 1/16W
SM1
MEM_DATA<1> AK33 DDR_DATA_1 DDR_A_1 MEM_ADDR<1> 9 35 22
35 10 SYSCLK_DDRCLK_A0_L_UF 2 7 SYSCLK_DDRCLK_A0_L
D 35 10 MEM_DATA<2> AK31 DDR_DATA_2 OMIT DDR_A_2 G36
F36
MEM_ADDR<2> 9
MEM_ADDR<3> 9
35
35 9
5%
11 35
+3V_MAIN D
35 10 MEM_DATA<3> AK35 DDR_DATA_3 U51 DDR_A_3
F35
35
1/16W
SM1 RP20
35 10 MEM_DATA<4> AK36 DDR_DATA_4 INTREPID-REV2.1
BGA
DDR_A_4
E35
MEM_ADDR<4> 9 35
2
22 7
AJ32 DDR_DATA_5 DDR_A_5 MEM_ADDR<5> 9 35 35 9 SYSCLK_DDRCLK_B1_UF SYSCLK_DDRCLK_B1 11 35
35 10 MEM_DATA<5> (2 OF 9) E36 MEM_ADDR<6> 9
35 10 MEM_DATA<6> AJ35 DDR_DATA_6 CRITICAL
DDR_A_6
DDR_A_7 G32 MEM_ADDR<7> 9
35
35
RP20
22
5%
1/16W
SM1
AJ36 DDR_DATA_7
35 10 MEM_DATA<7>
AG33 DDR_DATA_8 DDR_A_8 D36 MEM_ADDR<8> 9 35
35 9 SYSCLK_DDRCLK_B1_L_UF1 8 SYSCLK_DDRCLK_B1_L 11 35
1 C125 1 C773 1 C122
35 10 MEM_DATA<8> H36 MEM_ADDR<9> 9 5% 2.2uF 0.1uF 0.1uF
35 10 MEM_DATA<9> AG35 DDR_DATA_9 DDR_A_9
G33
35
1/16W
SM1
RP22 20%
2 10V
20%
2 10V
20%
2 10V
MEM_DATA<10> AH35 DDR_DATA_10 DDR_A_10 MEM_ADDR<10> 9 35
3
22 6
CERM
805
CERM
402
CERM
402
35 10
H33 MEM_ADDR<11> 9 35 9 SYSCLK_DDRCLK_B0_UF SYSCLK_DDRCLK_B0 11 35
MEM_DATA<11> AG36 DDR_DATA_11 DDR_A_11 35
35 10
D35 MEM_ADDR<12> 9 5%
35 10 MEM_DATA<12> AH36 DDR_DATA_12 DDR_A_12
L30
35
RP22 1/16W
SM1
MEM_DATA<13> AH32 DDR_DATA_13 DDR_BA_0 MEM_BA<0> 9 35 22
35 10
M29 MEM_BA<1> 9 35 9 SYSCLK_DDRCLK_B0_L_UF 4 5 SYSCLK_DDRCLK_B0_L 11 35
MEM_DATA<14> AG32 DDR_DATA_14 DDR_BA_1 35
35 10
MEM_DATA<15> AG31 DDR_DATA_15 DDRCS_0 AN34 MEM_CS_L<0>

5%
1/16W RP31
35 10
AE32 DDR_DATA_16 AN36
9 35
SM1
3
22 6 11 30 31
35 10 MEM_DATA<16> DDRCS_1 MEM_CS_L<1> 9 35 ’0’ & ’1’ GO TO SLOT A 35 9 MEM_CS_L<0> RAM_CS_L<0> 11 35
MEM_DATA<17> AF35 DDR_DATA_17 AL35 MEM_CS_L<2> ’2’ & ’3’ GO TO SLOT B

35 10 DDRCS_2 9 35
RP31 5%
1/16W VPP OMIT VCC
35 10 MEM_DATA<18>
MEM_DATA<19>
AF36 DDR_DATA_18
AE36 DDR_DATA_19
DDRCS_3 AL33 MEM_CS_L<3> 9 35
35 9 MEM_CS_L<1> 2
22 7
SM1
RAM_CS_L<1> 11 35
U11
FEPR-1MX8
35 10 DDR AJ31 MEM_DQS<0> 10 1MX8-3.3V
CS
MEM_DATA<20> AE35 DDR_DATA_20 MEMORY DDR_DQS_0 35
5% PCI_AD<0> 21 25 PCI_AD<24> 12
35 10
35 10 MEM_DATA<21> AE33 DDR_DATA_21

INTERFACE DDR_DQS_1 AH31 MEM_DQS<1> 10 35
1/16W
SM1
RP29
22
39 37 24 18 17 12
39 37 24 18 17 12 PCI_AD<1> 20
A0 TSOP DQ0
26 PCI_AD<25> 12
17 18 24 37 39
17 18 24 37 39
AD36 DDR_DATA_22 DDR_DQS_2 AD32 MEM_DQS<2> 10 35 MEM_CS_L<2> 3 6 RAM_CS_L<2> A1 DQ1
35 10 MEM_DATA<22> 35 9 11 35
39 37 24 18 17 12 PCI_AD<2> 19 27 PCI_AD<26> 12 17 18 24 37 39
DDR_DQS_3 AB30 MEM_DQS<3> 10 35
5%
A2 DQ2
MEM_DATA<23> AD35 DDR_DATA_23 PCI_AD<3> 18 28 PCI_AD<27> 12
35 10
AA36 DDR_DATA_24 DDR_DQS_4 V30 MEM_DQS<4> 10 35 RP29 1/16W
SM1
39 37 24 18 17 12
17
A3 DQ3
32
17 18 24 37 39
35 10 MEM_DATA<24>
DDR_DQS_5 P32 MEM_DQS<5> 10 4
22 5
39 37 24 18 17 12 PCI_AD<4>
A4 DQ4 PCI_AD<28> 12 17 18 24 37 39
35 10 MEM_DATA<25> AA35 DDR_DATA_25 35

35 9 MEM_CS_L<3> RAM_CS_L<3> 11 35
39 37 24 18 17 12 PCI_AD<5> 16 33 PCI_AD<29> 12 17 18 24 37 39
DDR_DQS_6 N29 MEM_DQS<6> 10 35
5%
A5 DQ5
MEM_DATA<26> AA33 DDR_DATA_26 PCI_AD<6> 15 34 PCI_AD<30> 12
35 10
MEM_DATA<27> AB36 DDR_DATA_27 DDR_DQS_7 L32 MEM_DQS<7> 10 35

1/16W
SM1 RP31 39 37 24 18 17 12
PCI_AD<7> 14
A6 DQ6
35 PCI_AD<31> 12
17 18 24 37 39
35 10
AB35 DDR_DATA_28 AJ33 1
22 8
39 37 24 18 17 12
8
A7 DQ7 17 18 24 37 39
C 35 10
35 10
MEM_DATA<28>
MEM_DATA<29> AC36 DDR_DATA_29
DDR_DM_0
DDR_DM_1 AH33
MEM_DQM<0> 10
MEM_DQM<1> 10
35
35
35 9 MEM_CKE<0>
RP31 5%
1/16W
RAM_CKE<0> 9 11 35 39 37 24 18 17 12
39 37 24 18 17 12
PCI_AD<8>
PCI_AD<9> 7
A8
A9
C
MEM_DATA<30> AA32 DDR_DATA_30 DDR_DM_2 AD33 MEM_DQM<2> 10 22 SM1 PCI_AD<10> 36
35 10
AB33 DDR_DATA_31 AC35
35
MEM_CKE<1> 4 5 RAM_CKE<1> 9
39 37 24 18 17 12
A10
6
CKE
35 10 MEM_DATA<31> DDR_DM_3 MEM_DQM<3> 10 35
35 9 11 35
39 37 24 18 17 12 PCI_AD<11>
A11
24
MEM_DATA<32> V36 DDR_DATA_32 T35 5% +3V_MAIN 5
MEM_DQM<4> 10 PCI_AD<12>
35 10
U33 DDR_DATA_33
DDR_DM_4
T33
35
1/16W
SM1
RP29 ROM_CS_TP_L 39 37 24 18 17 12
4
A12
35 10 MEM_DATA<33> DDR_DM_5 MEM_DQM<5> 10 35
1
22 8
39 37 24 18 17 12 PCI_AD<13>
A13
MEM_DATA<34> U32 DDR_DATA_34 N32 MEM_DQM<6> 10 35 9 MEM_CKE<2> RAM_CKE<2> 9 11 35 PCI_AD<14> 3
35 10 DDR_DM_6 35 37 24 18 17 12
39 A14
MEM_DATA<35> V35 DDR_DATA_35 L33 MEM_DQM<7> 10 5% PCI_AD<15> 2
35 10
T30 DDR_DATA_36
DDR_DM_7 35
RP29 1/16W
SM1 NO STUFF
39 37 24 18 17 12
1
A15
35 10 MEM_DATA<36>
DDRRAS L29 MEM_RAS_L 9 2
22 7
1
R236 1
R691 R112 1 37 24 18 17 12
39
PCI_AD<16>
A16
MEM_DATA<37> U36 DDR_DATA_37 35
35 9 MEM_CKE<3> RAM_CKE<3> 9 11 35 PCI_AD<17> 40
35 10
U35 DDR_DATA_38 DDRCAS H32 MEM_CAS_L 9 35
5%
0
5%
10K
5%
10K
5%
24 18 17 12
39 37 A17
MEM_DATA<38> PCI_AD<18> 13
35 10
K30 MEM_WE_L 9 1/16W 1/16W 1/16W 1/16W 24 18 17 12
A18
35 10 MEM_DATA<39> T36 DDR_DATA_39 DDRWE
AN35
35
SM1 RP14 MF
2 402
MF
2 402
MF 39
402 2
39 37
37 24 18 17 12 PCI_AD<19> 37
A19
MEM_DATA<40> P33 DDR_DATA_40 DDRCKE0 MEM_CKE<0> 9 35
3
22 6 PCI_AD<20> 38
35 10
AM35 MEM_ADDR<0> RAM_ADDR<0> 39 37 24 18 17 12
A20
MEM_DATA<41> R30 DDR_DATA_41 DDRCKE1 MEM_CKE<1> 9 35 ’0’ & ’1’ GO TO SLOT A 35 9 11 35
R674
35 10
MEM_DATA<42> P35 DDR_DATA_42 DDRCKE2 AM36 MEM_CKE<2> 9 35

’2’ & ’3’ GO TO SLOT B RP12 5%
1/16W 39 12 ROM_CS_L 1
1K 2 39 ROM_ONBOARD_CS_L 22
35 10
P36 DDR_DATA_43 DDRCKE3 AL36 MEM_CKE<3> 9 35
2
22 7
SM1
24
CE
35 10 MEM_DATA<43> 35 9 MEM_ADDR<1> RAM_ADDR<1> 11 35 5% 39 12 ROM_OE_L
R36 DDR_DATA_44 AB32 MEM_MUXSEL_MSB_L_TP
1/16W OE
35 10 MEM_DATA<44> DDR_SELHI_0 5% MF 39 12 ROM_RW_L 9
R35 DDR_DATA_45 AE29 MEM_MUXSEL_MSB 10 35 ’0’S ARE SAME POLARITY (ACTIVE-LO) 1/16W RP12 402 WE
MEM_DATA<45> ROM_WP_L 12
35 10
R33 DDR_DATA_46
DDR_SELHI_1
N30 MEM_MUXSEL_LSB_L_TP ’1’S ARE SAME POLARITY (ACTIVE-HI)
SM1
1
22 8
R1 10
WP
35 10 MEM_DATA<46> DDR_SELLO_0 35 9 MEM_ADDR<2> RAM_ADDR<2> 11 35
ROM_ONBOARD_CS_TP_L
1
0 NO2 STUFF 29 13 INT_RESET_L
PWD
24
35 10 MEM_DATA<47> R32 DDR_DATA_47 DDR_SELLO_1 T32 MEM_MUXSEL_LSB 10 35 5% GND
35 10 MEM_DATA<48> N35 DDR_DATA_48
Y32
RP12
22
1/16W
SM1
5%
1/16W
DDR_MCLK_0_P SYSCLK_DDRCLK_A0_UF 9 35 MF
35 10 MEM_DATA<49> M36 DDR_DATA_49 35 9 MEM_ADDR<3> 4 5 RAM_ADDR<3> 11 35 402 23 39
Y33 SYSCLK_DDRCLK_A0_L_UF
35 10 MEM_DATA<50> L35 DDR_DATA_50 DDR_MCLK_0_N
Y35
9 35
5% R271NO STUFF
MEM_DATA<51> M35 DDR_DATA_51 DDR_MCLK_1_P SYSCLK_DDRCLK_A1_UF 9 35 1/16W RP12 ROM_OE_TP_L 1
0 2 OVERRIDE ROM MODULE
35 10
Y36 SM1 24
MEM_DATA<52> M33 DDR_DATA_52 DDR_MCLK_1_N SYSCLK_DDRCLK_A1_L_UF 9 35

3
22 6 5%
INTERCEPTS ROM CHIP SELECT
35 10
Y30 INT_DDRCLK2_P_TP 35 9 MEM_ADDR<4> RAM_ADDR<4> 11 35 1/16W
MEM_DATA<53> L36 DDR_DATA_53 DDR_MCLK_2_P MF
35 10
MEM_DATA<54> N33 DDR_DATA_54 DDR_MCLK_2_N W30 INT_DDRCLK2_N_TP RP9 5%

1/16W 402
R194NO
35 10
22
B 35 10 MEM_DATA<55> M30 DDR_DATA_55
J32 DDR_DATA_56
DDR_MCLK_3_P
DDR_MCLK_3_N
W32
W33
SYSCLK_DDRCLK_B0_UF
SYSCLK_DDRCLK_B0_L_UF
9 35
9 35
35 9 MEM_ADDR<5> 2 7
SM1
RAM_ADDR<5> 11 35
24 ROM_RW_TP_L 1
0 2
STUFF
B
MEM_DATA<56> 5%
35 10
MEM_DATA<57> J33 DDR_DATA_57 DDR_MCLK_4_P V33 SYSCLK_DDRCLK_B1_UF 9 35 1/16W

SM1
RP9 5%
1/16W
35 10
V32 22
ADDR
J35 DDR_DATA_58 DDR_MCLK_4_N SYSCLK_DDRCLK_B1_L_UF 9 35

1 8 MF TABLE_5_HEAD
35 10 MEM_DATA<58> W35 35 9 MEM_ADDR<6> RAM_ADDR<6> 11 35 402 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
K32 DDR_DATA_59 DDR_MCLK_5_P INT_DDRCLK5_P_TP
MEM_DATA<59> 5% TABLE_5_ITEM
35 10
35 10 MEM_DATA<60> K33 DDR_DATA_60 DDR_MCLK_5_N W36 INT_DDRCLK5_N_TP RP14

22
1/16W
SM1
341S1542 1 IC,BootRom Q16A U11 CRITICAL ?
35 10 MEM_DATA<61> J36 DDR_DATA_61 DDR_REF AA22 INT_MEM_REF_H 38 35 9 MEM_ADDR<7> 2 7 RAM_ADDR<7> 11 35
MEM_DATA<62> K36 DDR_DATA_62 5%

35 10
35 10 MEM_DATA<63> K35 DDR_DATA_63 DDR_VREF_0 Y22 INT_MEM_VREF 9 38 1/16W

SM1
RP9
22
DDR_VREF_1 T22 MEM_ADDR<8> 4 5 RAM_ADDR<8>
35 9 11 35
RP14
22
5%
1/16W
SM1
1
R209 35 9 MEM_ADDR<9> 4 5 RAM_ADDR<9> 11 35
1K 5%
1%
1/16W 1/16W
SM1
RP14
22
MEM_VREF MF
2 402 35 9 MEM_ADDR<10> 1 8 RAM_ADDR<10> 11 35
Weak pulldowns ensure CKEs stay low
RP17 5%
1/16W after 2.5V I/O to Intrepid shuts off.
22 SM1
35 9 MEM_ADDR<11> 4 5 RAM_ADDR<11> 11 35
35 11 9 RAM_CKE<0>
38 16 15 10 +2_5V_INTREPID 5%
1/16W
SM1 RP9 35 11 9 RAM_CKE<1>
3
22 6 RAM_CKE<2>
1 MEM_ADDR<12> RAM_ADDR<12> 11 35 11 9
R208 35 9 35
10K
1%
RP17
22
5%
1/16W
SM1
35 11 9 RAM_CKE<3>
INT_2_5V_COLD INT_2_5V_COLD INT_2_5V_COLD INT_2_5V_COLD
1/16W
MF
402 2
35 9 MEM_BA<0> 2 7 RAM_BA<0> 11 35
R247
1 1
R257
10K
1
R260 1
R265 INT - DDR/BOOTROM
BA
5%
RP17 10K 10K 10K
A INT_MEM_VREF 9 38
1/16W
SM1
1
22 8
5%
1/16W
MF
5%
1/16W
MF
5%
1/16W
MF
5%
1/16W
MF NOTICE OF PROPRIETARY PROPERTY
A
MEM_BA<1> RAM_BA<1>
35 9 11 35
2 402 2 402 2 402 2 402
R2021 C249 1 RP17 5% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
10K 0.1uF 1/16W
SM1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1%
1/16W
20%
10V 3
22 6
CERM 2 35 9 MEM_WE_L RAM_WE_L 11 35
MF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
CNTL
402 2 402 5%
1/16W R162 II NOT TO REPRODUCE OR COPY IT
MEM_CAS_L
SM1
1
22 2 RAM_CAS_L
35 9 11 35
5%
R176 1/16W
35 9 MEM_RAS_L 1
22
5%
2
MF
402 RAM_RAS_L 11 35
APPLE COMPUTER INC.
D 051-6653 C
1/16W
MF
402
SCALE
NONE
SHT
9 OF
44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BIT 0..15 BIT 16..31 BIT 32..47 BIT 48..63

+2_5V_INTREPID +2_5V_INTREPID
D 38
10 9+2_5V_INTREPID
16 15
38 16 15 10 9 +2_5V_INTREPID
38 16 15 10 9 38 16 15 10 9
D
1 C734 1 C764
1 C757 1 C758 1 C730 1 C741 1 C733 1 C732
1 C726 0.1uF 0.1uF
1 C742 1 C727 1 C745 0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20% 20% 20% 0.1uF
20%
0.1uF
20%
0.1uF
20% 10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM
2 10V 2 10V
CERM 2 10V
CERM 2 10V 2 10V 2 10V 402 402 402 402 402 402
CERM 402 402 CERM CERM CERM
402 402 402 402
CRITICAL CRITICAL
E8
F3
F8
E8
F3
F8
CRITICAL
E8
F3
F8
CRITICAL
E8
F3
F8
VDD VDD
VDD G1 DA11 C10 G1 DA11 C10
VDD 35 11 RAM_DATA_B<32> DB0* RAM_DATA_A<41> 11 35 35 11 RAM_DATA_B<48> DB0* RAM_DATA_A<57> 11 35
35 11 RAM_DATA_B<16> G1 DB0* DA11 C10 RAM_DATA_A<25> 11 35
35 11 RAM_DATA_B<0> G1 DB0* DA11 C10 RAM_DATA_A<9> 11 35 35 11 RAM_DATA_B<33> J1 DB1* DA12 A10 RAM_DATA_A<42> 11 35 35 11 RAM_DATA_B<49> J1 DB1* DA12 A10 RAM_DATA_A<58> 11 35
RAM_DATA_B<17> J1 DA12 A10 RAM_DATA_A<26>
35 11 RAM_DATA_B<1> J1 DB1* DA12 A10 RAM_DATA_A<10> 11 35
35 11
RAM_DATA_B<18> K2
DB1*
U27 A8 RAM_DATA_A<27>
11 35
35 11 RAM_DATA_B<34>
K2 DB2* U18 DA13 A8 RAM_DATA_A<43> 11 35 35 11 RAM_DATA_B<50> K2 DB2* U16 DA13 A8 RAM_DATA_A<59> 11 35
35 11 RAM_DATA_B<2> K2 DB2* U28 DA13

CBTV4020
A8 RAM_DATA_A<11> 11 35
35 11
RAM_DATA_B<19> J4
DB2*
DB3*
CBTV4020
DA13
DA14 A7 RAM_DATA_A<28>
11 35
35 11 RAM_DATA_B<35>
J4 DB3*
CBTV4020
BGA DA14 A7 RAM_DATA_A<44> 11 35 35 11 RAM_DATA_B<51> J4 DB3*
CBTV4020
BGA DA14 A7 RAM_DATA_A<60> 11 35
RAM_DATA_B<3> J4 A7 RAM_DATA_A<12>
35 11 BGA 11 35
K5 A5 K5 A5
35 11 DB3* BGA DA14 11 35 35 11 RAM_DATA_B<36> DB4* DA15 RAM_DATA_A<45> 11 35 35 11 RAM_DATA_B<52> DB4* DA15 RAM_DATA_A<61> 11 35
35 11 RAM_DATA_B<20> K5 DB4* DA15 A5 RAM_DATA_A<29> 11 35
35 11 RAM_DATA_B<4> K5 DB4* DA15 A5 RAM_DATA_A<13> 11 35 35 11 RAM_DATA_B<37>
K7 DB5* DA16 B4 RAM_DATA_A<46> 11 35 35 11 RAM_DATA_B<53> K7 DB5* DA16 B4 RAM_DATA_A<62> 11 35
35 11 RAM_DATA_B<21> K7 DB5* DA16 B4 RAM_DATA_A<30> 11 35
35 11 RAM_DATA_B<5> K7 DB5* DA16 B4 RAM_DATA_A<14> 11 35 35 11 RAM_DATA_B<38>
K8 DB6* DA17 A2 RAM_DATA_A<47> 11 35 35 11 RAM_DATA_B<54> K8 DB6* DA17 A2 RAM_DATA_A<63> 11 35
35 11 RAM_DATA_B<22> K8 DB6* DA17 A2 RAM_DATA_A<31> 11 35
35 11 RAM_DATA_B<6> K8 DB6* DA17 A2 RAM_DATA_A<15> 11 35 35 11 RAM_DATA_B<39>
K10 DB7* DA18 B1 RAM_DQS_A<5> 11 35 35 11 RAM_DATA_B<55> K10 DB7* DA18 B1 RAM_DQS_A<7> 11 35
35 11 RAM_DATA_B<23> K10 DB7* DA18 B1 RAM_DQS_A<3> 11 35
35 11 RAM_DATA_B<7> K10 DB7* DA18 B1 RAM_DQS_A<1> 11 35 35 11 RAM_DQS_B<4>
H10 DB8* DA19 D1 RAM_DQM_A<5> 11 35 35 11 RAM_DQS_B<6> H10 DB8* DA19 D1 RAM_DQM_A<7> 11 35
35 11 RAM_DQS_B<2> H10 DB8* DA19 D1 RAM_DQM_A<3> 11 35
35 11 RAM_DQS_B<0> H10 DB8* DA19 D1 RAM_DQM_A<1> 11 35 35 11 RAM_DQM_B<4>
F10 DB9* 35 11 RAM_DQM_B<6> F10 DB9*
35 11 RAM_DQM_B<2> F10 DB9*
35 11 RAM_DQM_B<0> F10 DB9* 35 11 RAM_DATA_B<40>
D10 DB10* 35 11 RAM_DATA_B<56> D10 DB10*
35 11 RAM_DATA_B<24> D10 DB10*
35 11 RAM_DATA_B<8> D10 DB10* 35 11 RAM_DATA_B<41>
B10 DB11* 35 11 RAM_DATA_B<57> B10 DB11*
35 11 RAM_DATA_B<25> B10 DB11* DH0 F2 MEM_DATA<32> 9 35 DH0 F2 MEM_DATA<48> 9 35
35 11 RAM_DATA_B<9> B10 DB11* DH0 F2 MEM_DATA<16> 9 35 35 11 RAM_DATA_B<42>
A9 DB12* 35 11 RAM_DATA_B<58> A9 DB12*
A9 DH0 F2 MEM_DATA<0> 9 35 35 11 RAM_DATA_B<26> A9 DB12* DH1 H2 MEM_DATA<33> 9 35 DH1 H2 MEM_DATA<49> 9 35
35 11 RAM_DATA_B<10> DB12* DH1 H2 MEM_DATA<17> 9 35 35 11 RAM_DATA_B<43>
B7 DB13* 35 11 RAM_DATA_B<59> B7 DB13*
B7 DH1 H2 MEM_DATA<1> 9 35 35 11 RAM_DATA_B<27> B7 DB13* DH2 J2 MEM_DATA<34> 9 35 DH2 J2 MEM_DATA<50> 9 35
35 11 RAM_DATA_B<11> DB13* DH2 J2 MEM_DATA<18> 9 35 35 11 RAM_DATA_B<44>
A6 DB14* 35 11 RAM_DATA_B<60> A6 DB14*
A6 DH2 J2 MEM_DATA<2> 9 35 35 11 RAM_DATA_B<28> A6 DB14* DH3 J3 MEM_DATA<35> 9 35 DH3 J3 MEM_DATA<51> 9 35
35 11 RAM_DATA_B<12> DB14* DH3 J3 MEM_DATA<19> 9 35 35 11 RAM_DATA_B<45>
A4 DB15* 35 11 RAM_DATA_B<61> A4 DB15*
DH3 J3 A4 DH4 J5 DH4 J5
C 35 11
35 11
RAM_DATA_B<13>
RAM_DATA_B<14>
A4
A3
DB15*
DB16*
DH4 J5
MEM_DATA<3> 9
MEM_DATA<4> 9
35
35
35 11
35 11
RAM_DATA_B<29>
RAM_DATA_B<30> A3
DB15*
DB16*
DH4 J5
DH5 J6
MEM_DATA<20> 9 35
MEM_DATA<21> 9 35
35
35
11 RAM_DATA_B<46>
11 RAM_DATA_B<47>
A3
A1
DB16*
DB17*
DH5 J6
MEM_DATA<36> 9 35
MEM_DATA<37> 9 35
35 11
35 11
RAM_DATA_B<62>
RAM_DATA_B<63>
A3
A1
DB16*
DB17*
DH5 J6
MEM_DATA<52> 9 35
MEM_DATA<53> 9 35 C
A1 DH5 J6 MEM_DATA<5> 9 35 35 11 RAM_DATA_B<31> A1 DB17* DH6 J8 MEM_DATA<38> 9 35 DH6 J8 MEM_DATA<54> 9 35
35 11 RAM_DATA_B<15> DB17* J8 C1 DH6 J8 MEM_DATA<22> 9 35 35 11 RAM_DQS_B<5>
C1 DB18* J9 35 11 RAM_DQS_B<7> C1 DB18* J9
DH6 MEM_DATA<6> 9 35 35 11 RAM_DQS_B<3> DB18* DH7 MEM_DATA<39> 9 35 DH7 MEM_DATA<55> 9 35
35 11 RAM_DQS_B<1> C1 DB18* DH7 J9 MEM_DATA<23> 9 35 35 11 RAM_DQM_B<5>
E1 DB19* 35 11 RAM_DQM_B<7> E1 DB19*
DH7 J9 MEM_DATA<7> 9 35 35 11 RAM_DQM_B<3> E1 DB19* DH8 H9 MEM_DQS<4> 9 35 DH8 H9 MEM_DQS<6> 9 35
35 11 RAM_DQM_B<1> E1 DB19* DH8 H9 MEM_DQS<2> 9 35
DH8 H9 MEM_DQS<0> 9 35 DH9 F9 MEM_DQM<4> 9 35 DH9 F9 MEM_DQM<6> 9 35
F9 DH9 F9 MEM_DQM<2> 9 35 E9 E9
DH9 MEM_DQM<0> 9 35 DH10 MEM_DATA<40> 9 35 DH10 MEM_DATA<56> 9 35
E9 DH10 E9 MEM_DATA<24> 9 35
C9 C9
DH10 MEM_DATA<8> 9 35 DH11 MEM_DATA<41> 9 35 DH11 MEM_DATA<57> 9 35
C9 F1 DH11 C9 MEM_DATA<25> 9 35 35 11 RAM_DATA_A<32> F1 DA0 B9 35 11 RAM_DATA_A<48> F1 DA0 B9
F1 DH11 MEM_DATA<9> 9 35 35 11 RAM_DATA_A<16> DA0 DH12 MEM_DATA<42> 9 35 DH12 MEM_DATA<58> 9 35
35 11 RAM_DATA_A<0> DA0 B9 H1 DH12 B9 MEM_DATA<26> 9 35 35 11 RAM_DATA_A<33> H1 DA1 B8 35 11 RAM_DATA_A<49> H1 DA1 B8
H1 DH12 MEM_DATA<10> 9 35 35 11 RAM_DATA_A<17> DA1 DH13 MEM_DATA<43> 9 35 DH13 MEM_DATA<59> 9 35
35 11 RAM_DATA_A<1> DA1 B8 K1 DH13 B8 MEM_DATA<27> 9 35 35 11 RAM_DATA_A<34>
K1 DA2 B6 35 11 RAM_DATA_A<50> K1 DA2 B6
K1 DH13 MEM_DATA<11> 9 35 35 11 RAM_DATA_A<18> DA2 DH14 MEM_DATA<44> 9 35 DH14 MEM_DATA<60> 9 35
35 11 RAM_DATA_A<5> DA5 B2 J7 DH17 B2 MEM_DATA<31> 9 35 35 11 RAM_DATA_A<38>
J7 DA6 C2 35 11 RAM_DATA_A<54> J7 DA6 C2
J7 DH17 MEM_DATA<15> 9 35 35 11 RAM_DATA_A<22> DA6 DH18 MEM_DQS<5> 9 35 DH18 MEM_DQS<7> 9 35
35 11 RAM_DATA_A<6> DA6 C2 K9 DH18 C2 MEM_DQS<3> 9 35 35 11 RAM_DATA_A<39>
K9 DA7 E2 35 11 RAM_DATA_A<55> K9 DA7 E2
DH18 MEM_DQS<1> 9 35 35 11 RAM_DATA_A<23> DA7 DH19 MEM_DQM<5> 9 35 DH19 MEM_DQM<7> 9 35
35 11 RAM_DATA_A<7> K9 DA7 DH19 E2 MEM_DQM<3> 9 35 35 11 RAM_DQS_A<4>
J10 DA8 35 11 RAM_DQS_A<6> J10 DA8
DH19 E2 MEM_DQM<1> 9 35 35 11 RAM_DQS_A<2> J10 DA8
35 11 RAM_DQS_A<0> J10 DA8 35 11 RAM_DQM_A<4>
G10 DA9 35 11 RAM_DQM_A<6> G10 DA9
35 11 RAM_DQM_A<2> G10 DA9
35 11 RAM_DQM_A<0> G10 DA9 35 11 RAM_DATA_A<40>
E10 DA10 SEL E3 MEM_MUXSEL_MSB 9 10 35 35 11 RAM_DATA_A<56> E10 DA10 SEL E3 MEM_MUXSEL_MSB 9 10 35
35 11 RAM_DATA_A<24> E10 DA10 SEL E3 MEM_MUXSEL_LSB 9 10 35
35 11 RAM_DATA_A<8> E10 DA10 SEL E3 MEM_MUXSEL_LSB 9 10 35 GND GND
GND
C5
C6
D2
D9
G2
G9
H5
H6
C5
C6
D2
D9
G2
G9
H5
H6
GND
C5
C6
D2
D9
G2
G9
H5
H6
C5
C6
D2
D9
G2
G9
H5
H6
B B
SEL = LOW; HOST = B PORT; A PORT = 100OHM TO GND
SEL = HIGH; HOST = A PORT; B PORT = 100OHM TO GND
16BIT 2:1 DDR MUXES

A
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
10 44 OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+2_5V_MAIN +2_5V_MAIN +2_5V_MAIN +2_5V_MAIN
NC 403 NC 401
DDR_VREF 1A
VREF0
2A DDR_VREF DDR_VREF 1B 2B DDR_VREF NOTE: The SODIMM connector footprint has a through-hole slot
CRITICAL VREF1 VREF0
CRITICALVREF1
38 11 11 38 38 11 11 38
3A
VSS0 VSS1
4A 3B
VSS0 VSS1
4B on the PCB for additional mounting
35 10 RAM_DATA_A<0> 5A
DQ0
J25 DQ4
6A RAM_DATA_A<4> 10 35 35 10 RAM_DATA_B<0> 5B
DQ0
J25 DQ4
6B RAM_DATA_B<4> 10 35
RAM_DATA_A<1> 7A F-RT-SM 8A RAM_DATA_A<5> RAM_DATA_B<1> 7B F-RT-SM 8B RAM_DATA_B<5> 10

35 10 DQ1 DQ5 10 35 35 10 DQ1 DQ5 35
9A (2 OF 2) 10A 9B (1 OF 2) 10B
VDD0 VDD1 VDD0 VDD1
DDR-SO-DIMM-DUAL
DDR-SO-DIMM-DUAL
RAM_DQS_A<0> 11A 12A RAM_DQM_A<0> 10 35 RAM_DQS_B<0> 11B 12B RAM_DQM_B<0> 10 35
35 10 DQS0 DM0 35 10 DQS0 DM0
35 10 RAM_DATA_A<2>
13A DQ2 DQ6
14A RAM_DATA_A<6> 10 35 35 10 RAM_DATA_B<2>
13B DQ2 DQ6
14B RAM_DATA_B<6> 10 35
15A 16A 15B 16B
VSS2 VSS3 VSS2 VSS3
RAM_DATA_A<3> 17A 18A RAM_DATA_A<7> RAM_DATA_B<3> 17B 18B RAM_DATA_B<7> 10
35 10 DQ3 DQ7 10 35 35 10 DQ3 DQ7 35
10 RAM_DATA_A<8>
19A 20A RAM_DATA_A<12> RAM_DATA_B<8> 19B 20B RAM_DATA_B<12> 10
35 DQ8 DQ12 10 35 35 10 DQ8 DQ12 35
+2_5V_MAIN
21A 22A 21B 22B
D 35 10 RAM_DATA_A<9> 23A
VDD2
DQ9
VDD3
DQ13
VDD2
DQ9
VDD3
DQ13
24B RAM_DATA_B<13> 10 35
D
35 10 RAM_DQS_A<1>
25A
27A
DQS1 DM1
26A
28A
RAM_DQM_A<1> 10 35 35 10 RAM_DQS_B<1>
25B
27B
DQS1 DM1
26B
28B
RAM_DQM_B<1> 10 35 DDR VREF
VSS4 VSS5 VSS4 VSS5 1
R299 ONE 0.1UF PER SLOT
RAM_DATA_A<10> 29A 30A RAM_DATA_A<14> 10 RAM_DATA_B<10> 29B 30B RAM_DATA_B<14> 10
35 10 DQ10 DQ14 35 35 10 DQ10 DQ14 35 1K
RAM_DATA_A<11> 31A 32A RAM_DATA_A<15> 10 RAM_DATA_B<11> 31B 32B RAM_DATA_B<15> 10 1%
35 10 DQ11 DQ15 35 35 10 DQ11 DQ15 35
1/16W
33A 34A 33B 34B MF
VDD4 VDD5 VDD4 VDD5
35A 36A 35B 36B 2 402
35 9 SYSCLK_DDRCLK_A0 CK0 VDD6 35 9 SYSCLK_DDRCLK_B0 CK0 VDD6 DDR_VREF 11 38
9 SYSCLK_DDRCLK_A0_L
37A 38A 9 SYSCLK_DDRCLK_B0_L
37B 38B
35 CK0* VSS6 35 CK0* VSS6
39A 40A 39B 40B 1
VSS7 VSS8 VSS7 VSS8 R303 1 C397 1 C403
RAM_DATA_A<16> 41A KEY
42A RAM_DATA_A<20> RAM_DATA_B<16> 41B KEY
42B RAM_DATA_B<20> 10
1K 0.1uF 0.1uF
35 10 DQ16 DQ20 10 35 35 10 DQ16 DQ20 35 1% 20% 20%
1/16W
35 10 RAM_DATA_A<17> 43A
DQ17 DQ21
DQ17 DQ21
44B RAM_DATA_B<21> 10 35 MF 2 10V
CERM 2 10V
CERM
45A 46A 45B 46B 2 402 402 402
VDD7 VDD8 VDD7 VDD8
RAM_DQS_A<2> 47A 48A RAM_DQM_A<2> 10 RAM_DQS_B<2> 47B 48B RAM_DQM_B<2> 10 35
35 10 DQS2 DM2 35 35 10 DQS2 DM2
10 RAM_DATA_A<18>
49A 50A RAM_DATA_A<22> 10 RAM_DATA_B<18>
49B 50B RAM_DATA_B<22> 10
35 DQ18 DQ22 10 35 35 DQ18 DQ22 35
51A 52A 51B 52B
VSS9 VSS10 VSS9 VSS10
35 10 RAM_DATA_A<19> 53A DQ19 DQ23
54A RAM_DATA_A<23> 10 35 35 10 RAM_DATA_B<19> 53B DQ19 DQ23
54B RAM_DATA_B<23> 10 35
10 RAM_DATA_A<24>
55A 56A RAM_DATA_A<28> 10 10 RAM_DATA_B<24>
55B 56B RAM_DATA_B<28> 10
35 DQ24 DQ28 35 35 DQ24 DQ28 35
57A 58A 57B 58B
VDD9 VDD10 VDD9 VDD10
35 10 DQ25 DQ29 10 35 35 10 DQ25 DQ29 35
RAM_DQS_A<3> 61A 62A RAM_DQM_A<3> 10 RAM_DQS_B<3> 61B 62B RAM_DQM_B<3> 10 35

35 10 DQS3 DM3 35 35 10 DQS3 DM3
63A 64A 63B 64B
35 10 DQ26 DQ30 10 35 35 10 DQ26 DQ30 35

35 10
69A
71A
DQ27
VDD11
DQ31
VDD12
70A
72A
10 35 35 10
69B
71B
DQ27
VDD11
DQ31
VDD12
70B
72B
35
DDR BYPASS
NC RFU0 RFU1 NC NC RFU0 RFU1 NC
C NC
73A
75A
RFU2 RFU3
74A
76A
NC NC
73B
75B
RFU2 RFU3
74B
76B
NC +2_5V_MAIN SLOT "A" C
SLOT "A" NC
NC
77A
79A
81A
VSS13
RFU4
RFU6
VSS14
RFU5
RFU7
78A
80A
82A
NC
NC
SLOT "B" NC
NC
77B
79B
81B
VSS13
RFU4
RFU6
VSS14
RFU5
RFU7
78B
80B
82B
NC
NC
LOWER SLOT NC
NC
83A
85A
87A
VDD13
RFU8
RFU10
VDD14
RFU9
RFU11
84A
86A
88A
NC
NC
UPPER SLOT NC
NC
83B
85B
87B
VDD13
RFU8
RFU10
VDD14
RFU9
RFU11
84B
86B
88B
NC
NC
1 C404
10uF
20%
2 6.3V
1 C128
10uF
20%
2 6.3V
CERM
CERM
FACTORY SLOT NC
NC
89A
91A
93A
VSS15
RFU12
RFU13
VSS16
VSS17
VDD15
90A
92A
94A
CUSTOMER SLOT NC
NC
89B
91B
93B
VSS15
RFU12
RFU13
VSS16
VSS17
VDD15
90B
92B
94B
805 805
RAM_CKE<1> 95A
VDD16 VDD17
96A RAM_CKE<0> 9 RAM_CKE<3> 95B
VDD16 VDD17
96B RAM_CKE<2> 9
1 C169 1 C391 1 C211 1 C356 1 C127
35 9 CKE1 CKE0 35 35 9 CKE1 CKE0 35
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
NC 97A RFU14 RFU15
98A NC NC 97B RFU14 RFU15
98B NC 20% 20% 20% 20% 20%
99A 100A 99B 100B 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
35 11 9 RAM_ADDR<12> A12 A11 RAM_ADDR<11> 9 11 35 35 11 9 RAM_ADDR<12> A12 A11 RAM_ADDR<11> 9 11 35 402 402 402 402 402
9 RAM_ADDR<9>
101A 102A RAM_ADDR<8> 9 RAM_ADDR<9>
101B 102B RAM_ADDR<8>
35 11 A9 A8 9 11 35 35 11 A9 A8 9 11 35
103A 104A 103B 104B
RAM_ADDR<7> 105A 106A RAM_ADDR<6> RAM_ADDR<7> 105B 106B RAM_ADDR<6>
35 11 9 A7 A6 9 11 35 35 11 9 A7 A6 9 11 35

35 11 9 A5 A4 9 11 35 35 11 9 A5 A4 9 11 35

35 11 9 A3 A2 9 11 35 35 11 9 A3 A2 9 11 35
9 RAM_ADDR<1>
111A 112A RAM_ADDR<0> 9 RAM_ADDR<1>
111B 112B RAM_ADDR<0> +2_5V_MAIN
35 11 A1 A0 9 11 35 35 11 A1 A0 9 11 35
35 11 9 RAM_ADDR<10>
113A
115A
VDD18
A10_AP
VDD19
BA1
114A
116A RAM_BA<1> 9 11 35 35 11 9 RAM_ADDR<10>
113B
115B
VDD18
A10_AP
VDD19
BA1
114B
116B RAM_BA<1> 9 11 35
SLOT "B"
9 RAM_BA<0>
117A 118A RAM_RAS_L 9 9 RAM_BA<0>
117B 118B RAM_RAS_L 9
35 11 BA0 RAS* 11 35 35 11 BA0 RAS* 11 35
9 RAM_WE_L
119A 120A RAM_CAS_L 9 9 RAM_WE_L
119B 120B RAM_CAS_L 9
35 11
9 RAM_CS_L<0>
121A
WE* CAS*
122A RAM_CS_L<1>
11 35 35 11
9 RAM_CS_L<2>
121B
WE* CAS*
122B RAM_CS_L<3>
11 35
1 C157 1 C174
35
123A
S0* S1*
124A
9 35 35
123B
S0* S1*
124B
9 35
10uF 10uF
20%
NC RFU16 RFU17 NC NC RFU16 RFU17 NC 20% 6.3V
125A 126A 125B 126B 2 6.3V
CERM
2 CERM
VSS20 VSS21 VSS20 VSS21 805
B 35 10 RAM_DATA_A<32>
RAM_DATA_A<33>
127A
129A
DQ32 DQ36
128A
130A
RAM_DATA_A<36> 10
RAM_DATA_A<37> 10
35 35 10 RAM_DATA_B<32>
RAM_DATA_B<33>
127B
129B
DQ32 DQ36
128B
130B
RAM_DATA_B<36> 10
RAM_DATA_B<37> 10
35
805
B
35 10 DQ33 DQ37 35 35 10 DQ33 DQ37 35
131A 132A 131B 132B
RAM_DQS_A<4> 133A
VDD20 VDD21
134A RAM_DQM_A<4> 10 35 RAM_DQS_B<4> 133B
VDD20 VDD21
134B RAM_DQM_B<4> 10 35
1 C383 1 C150 1 C156 1 C132 1 C140
35 10 DQS4 DM4 35 10 DQS4 DM4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RAM_DATA_A<34> 135A 136A RAM_DATA_A<38> 10 RAM_DATA_B<34> 135B 136B RAM_DATA_B<38> 10 20% 20% 20% 20% 20%
35 10 DQ34 DQ38 35 35 10 DQ34 DQ38 35
137A 138A 137B 138B 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
VSS22 VSS23 VSS22 VSS23 402 402 402 402 402
35 10 DQ35 DQ39 35 35 10 DQ35 DQ39 35
35 10 RAM_DATA_A<40> 141A DQ40 DQ44

142B RAM_DATA_B<44> 10 35
143A 144A 143B 144B
35 10 DQ41 DQ45 35 35 10 DQ41 DQ45 35
10 RAM_DQS_A<5>
147A 148A RAM_DQM_A<5> 10 35 10 RAM_DQS_B<5>
147B 148B RAM_DQM_B<5> 10 35
35 DQS5 DM5 35 DQS5 DM5
149A 150A 149B 150B
35 10 DQ42 DQ46 35 35 10 DQ42 DQ46 35

35 10 DQ43 DQ47 35 35 10 DQ43 DQ47 35
155A 156A 155B 156B
157A 158A SYSCLK_DDRCLK_A1_L 9 157B 158B SYSCLK_DDRCLK_B1_L 9
VDD26 CK1* 35 VDD26 CK1* 35
159A 160A SYSCLK_DDRCLK_A1 9 35 159B 160B SYSCLK_DDRCLK_B1 9 35
VSS26 CK1 VSS26 CK1
161A 162A 161B 162B
35 10 RAM_DATA_A<48> 163A DQ48 DQ52
164B RAM_DATA_B<52> 10 35

35 10 DQ49 DQ53 35 35 10 DQ49 DQ53 35
167A 168A 167B 168B
35 10 DQS6 DM6 35 10 DQS6 DM6
35 10 DQ50 DQ54 35 35 10 DQ50 DQ54 35
173A 174A 173B 174B
35 10
35 10
RAM_DATA_A<51>
RAM_DATA_A<56>
175A
177A
VSS29
DQ51
DQ56
VSS30
DQ55
DQ60
176A
178A
RAM_DATA_A<55> 10
RAM_DATA_A<60> 10
35
35
35 10
35 10
RAM_DATA_B<51>
RAM_DATA_B<56>
175B
177B
VSS29
DQ51
DQ56
VSS30
DQ55
DQ60
176B
178B
RAM_DATA_B<55> 10
RAM_DATA_B<60> 10
35
35
DDR SODIMM CONNS
A 179A
181A
VDD29 VDD30
180A
182A
179B
181B
VDD29 VDD30
180B
182B NOTICE OF PROPRIETARY PROPERTY
A
35 10 RAM_DATA_A<57> DQ57 DQ61 RAM_DATA_A<61> 10 35 35 10 RAM_DATA_B<57> DQ57 DQ61 RAM_DATA_B<61> 10 35

35 10 DQS7 DM7 35 10 DQS7 DM7 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
185A 186A 185B 186B PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
VSS31 VSS32 VSS31 VSS32 AGREES TO THE FOLLOWING
35 10 DQ58 DQ62 35 35 10 DQ58 DQ62 35
RAM_DATA_A<59> 189A 190A RAM_DATA_A<63> 10 RAM_DATA_B<59> 189B 190B RAM_DATA_B<63> 10 +3V_MAIN
+3V_MAIN 35 10 DQ59 DQ63 35 +3V_MAIN 35 10 DQ59 DQ63 35
191A 192A 191B 192B
VDD31 VDD32 VDD31 VDD32 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
INT_I2C_DATA0 193A 194A INT_I2C_DATA0 193B 194B
39 23 13 11 6 SDA SA0 39 23 13 11 6 SDA SA0
INT_I2C_CLK0 195A 196A INT_I2C_CLK0 195B 196B SIZE DRAWING NUMBER REV.
39 23 13 11 6
197A
SCL
VDDSPD
SA1
SA2
198A ADDR=0XA0(WR)/0XA1(RD) 39 23 13 11 6
197B
SCL
VDDSPD
SA1
SA2
198B ADDR=0XA2(WR)/0XA3(RD) D 051-6653 C
NC 199A 200A NC NC 199B 200B NC APPLE COMPUTER INC.
RFU18 RFU19 RFU18 RFU19
NC 404 NC 402
SCALE
NONE
SHT
11 44OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AGP PULL-UPS/PULL DOWNS

R197
4.7
38 14 12 8 +1_5V_INTREPID_PLL 1 2 +1_5V_INTREPID_PLL5 38
5% +3V_GPU 19 20 21 38
R167 C270 1 1/16W

MF
38 14 12 8 +1_5V_INTREPID_PLL 1
4.7 2 +1_5V_INTREPID_PLL6 38
0.22uF 402
38 21 20 19 16 15 12 +1_5V_AGP 20%
5% 6.3V 2
1/16W CERM
R272 C190 1 MF
402
402 R334
10K
0.22uF
D 35 24
39
CLK33M_AIRPORT
NO STUFF
1
33 2 20%
6.3V 2
CERM
19 12 AGP_BUSY_L 1
5%
2
D
5% 402 1/16W
C362 1 1/16W
MF NOTE: Designs using AGP slot should R308 MF
402
12PF
5% 402 1
R245 use 52-ohm a resistor here. 10K
50V 12 STOP_AGP_L 1 2
CERM 2 J11 60.4 5%
402 1% V14
VDD15A_6 1/16W 1/16W
R230
33 39 24 12 AIRPORT_PCI_REQ_L AR17 PCI_REQ_0 (PLL4)
PCIAD_0 AM10 PCI_AD<0> 9 17 18 24 37 39 MF VDD15A_5 MF
402
1 2 AR16 AR8 2 402 (PLL5)
OMIT
35 18 CLK33M_CBUS 18 12 CBUS_PCI_REQ_L PCI_REQ_1 PCIAD_1 PCI_AD<1> 9 17 18 24 37 39
NO STUFF
C311 1 5% 17 12 NEC_PCI_REQ_L AT17 PCI_REQ_2 PCIAD_2 AK12 PCI_AD<2> 9 17 18 24 37 39
AN19
U51 AT33 AGP_REQ_L
+1_5V_AGP 12 15 16 19 20 21
38
12PF
1/16W
MF
AT16
OMIT PCIAD_3 AJ8 PCI_AD<3> 9 17 18 24 37 39
12 STOP_AGP_L STP_AGP
AJ24 AGPPVT
INTREPID-REV2.1AGPREQ AM29 AGP_GNT_L
12 19 37
5%
50V
402 39 24 AIRPORT_PCI_GNT_L
AN18
PCI_GNT_0 U51
PCIAD_4 AN10 PCI_AD<4> 9 17 18 24 37 39
INT_AGPPVT
AB20 AGPVREF0
BGA
(3 OF 9)
AGPGNT 12 19 37
CERM 2 18 CBUS_PCI_GNT_L PCI_GNT_1INTREPID-REV2.1 PCIAD_5 AT8 PCI_AD<5> 9 17 18 24 37 39

38 19 12 INT_AGP_VREF
AGPAD0 CRITICAL AR19 AGP_AD<0>
402 19 37
NEC_PCI_GNT_L AN17 PCI_GNT_2 BGA AB21 AGPVREF1
R273 17
(7 OF 9) PCIAD_6 AN11 PCI_AD<6> 9 17 18 24 37 39 AGPAD1 AM19 AGP_AD<1> 19 37
35 17 CLK33M_NEC 1
22 2 35 CLK33M_AIRPORT_UF AR18 PCI_CLK0 CRITICAL PCIAD_7 AH13 PCI_AD<7> 9 17 18 24 37 39 AGPAD2 AT20 AGP_AD<2> 19 37 RP34
10K
NO STUFF 35 CLK33M_CBUS_UF AH18 PCI_CLK1 PCIAD_8 AK13 PCI_AD<8> 9 17 18 24 37 39 19 12 AGP_BUSY_L
AT19 AGP_BUSY AGPAD3 AR20 AGP_AD<3> 4 5
5% PCI/ROM 19 37
37 19 12 AGP_REQ_L
C372 1 1/16W
MF 35 CLK33M_NEC_UF AT18 PCI_CLK2 INTERFACE PCIAD_9 AR9 PCI_AD<9> 9 17 18 24 37 39 CLK66M_AGP_1_5V_TPAK28 AGP_CLK Vout = AGPIO (1.5V) AGPAD4 AT21 AGP_AD<4> 19 37
5%
12PF 402 35 INT_PCI_FB_OUT AM18 PCI_CLK_OUT VOUT = 3.3V PCIAD_10 AR10 PCI_AD<10> 9 17 18 24 37 39 35 INT_AGP_FB_INAK27 AGP_FB_IN Vin = Vcore (1.5V) AGPAD5 AN20 AGP_AD<5> 19 37
1/16W R553
5% SM1
50V AJ19 AT9 AK25 AGP_FB_OUT Vout = AGPIO (1.5V) AGPAD6 AR21 10K 2
CERM 2
402
35 INT_PCI_FB_IN PCI_CLK_IN VIN = 1.5V PCIAD_11
AR11
PCI_AD<11> 9 17 18 24 37 39
PCI_AD<12> 9 17 18 24 37 39
R246
0 2
35 INT_AGP_FB_OUT
AN21
AGP_AD<6>
AGP_AD<7>
19 37
37 19 12 AGP_GNT_L 1
AT14 PCIAD_12 1 AGPAD7 19 37 5%
PCI_PAR PCI_PAR
R318 1/16W
37 24 18 17
AM12 AM21
R264 24 18 17
39
12 PCI_FRAME_L AN16 PCI_FRAME
PCIAD_13 PCI_AD<13> 9 17 18 24 37 39
5% AGPAD8 AGP_AD<8> 19 37 MF
402
1
33 2
39 37
PCI_TRDY_L AT15 PCIAD_14 AN12 PCI_AD<14> 9 17 18 24 37 39 1/16W
MF AGPAD9 AT22 AGP_AD<9> 19 37
AGP_FRAME_L 1
10K 2
24 18 17 12 PCI_TRDY AK11 AR22 37 19 12
39 37 PCIAD_15 PCI_AD<15> 9 17 18 24 37 39 402 AGPAD10 AGP_AD<10> 19 37
5% 24 18 17 12 PCI_IRDY_L AH16 PCI_IRDY 5%
1/16W 39 37 PCIAD_16 AT11 PCI_AD<16> 9 17 18 24 37 39 AGPAD11 AN22 AGP_AD<11> 1/16W
MF 24 18 17 12 PCI_STOP_L AR15 PCI_STOP AGP_FB_CLK IS ROUTED THE SAME LENGTH AS CLK66M_GPU_AGP 19 37
MF R317
402 PCIAD_17 AT10 PCI_AD<17> 9 17 18 24 37 39 AM22 AGP_AD<12> 402
39
24 18 17
37
12 PCI_DEVSEL_L AM17 PCI_DEVSEL AN13
AGPAD12
AN23
19 37
12 AGP_DEVSEL_L 1
10K 2
39 37 PCIAD_18 PCI_AD<18> 9 17 18 24 37 39 AGP AGPAD13 AGP_AD<13> 19 37
37 19
PCI FEEDBACK CLOCK MATCHES
LONGEST PCI CLOCK ROUTE 24 PCI_CBE<0> AR14 PCI_CBE_0 AM13 PCI_AD<19> 9 17 18 24 37 39 INTERFACES AR23 AGP_AD<14> 5%
18 17 PCIAD_19 AGPAD14 19 37 1/16W
1
R244 37
37 24 18 17 PCI_CBE<1> AK16 PCI_CBE_1 PCIAD_20 AR12 PCI_AD<20> 9 17 18 24 37 39 AGPAD15 AT24 AGP_AD<15> 19 37 RP34 MF
402
47 10K
C 5%
MF
PLACE NEAR
1/16W INTREPID
37 24 18 17
37 24 18 17
PCI_CBE<2>
PCI_CBE<3>
AM16
AJ15
PCI_CBE_2
PCI_CBE_3
PCIAD_21
PCIAD_22
AJ11
AT12
PCI_AD<21> 17 18 24 37 39
PCI_AD<22> 17 18 24 37 39
AGPAD16
AGPAD17
AM23
AR24
AGP_AD<16>
AGP_AD<17>
19 37
19 37
37 19 12 AGP_IRDY_L 1
5%
8
C
2 402
35 CLK66M_GPU_AGP_UF AK17 ROM_OVRLY_EN
PCIAD_23 AM11
AR13
PCI_AD<23> 17 18 24 37 39 AGPAD18 AT25
AR25
AGP_AD<18> 19 37
1/16W
SM1 RP34
10K
PCIAD_24 PCI_AD<24> 9 17 18 24 37 39 AGPAD19 AGP_AD<19> 19 37
12 INT_ROM_CS_L AM9 ROM_CS 37 19 12 AGP_TRDY_L 2 7
PCIAD_25 AK15 PCI_AD<25> 9 17 18 24 37 39 AGPAD20 AM24 AGP_AD<20> 19 37
INT_ROM_OE_L AR7 ROM_OE 5%
R252 12
INT_ROM_RW_L AN9 ROM_WE

PCIAD_26 AH15 PCI_AD<26> 9 17 18 24 37 39 AGPAD21 AN25 AGP_AD<21> 19 37
R316 1/16W
35 19 CLK66M_GPU_AGP1
33 2
12
PCIAD_27 AN14 PCI_AD<27> 9 17 18 24 37 39 AGPAD22 AL24 AGP_AD<22> 19 37 10K
SM1
AT13 PCI_AD<28> 9 17 18 24 37 39 AR26 AGP_AD<23> 37 19 12 AGP_STOP_L 1 2
5% PCIAD_28 AGPAD23 19 37
1/16W AK14 PCI_AD<29> 9 17 18 24 37 39 AT26 AGP_AD<24> 5%
MF PCIAD_29 AGPAD24 19 37 1/16W
402
PCIAD_30 AN15 PCI_AD<30> 9 17 18 24 37 39 AGPAD25 AM25 AGP_AD<25> 19 37
MF
402
R552
AM15 PCI_AD<31> 9 17 18 24 37 39 AN26 AGP_AD<26> AGP_RBF_L 1
10K 2
(PLL4) PCIAD_31 AGPAD26 19 37 37 19 12
VSSA_6 AGPAD27 AM26 AGP_AD<27> 19 37 5%
1/16W
J10
AGPAD28 AR27 AGP_AD<28> 19 37 RP34 MF
AGPAD29 AT27 AGP_AD<29> 3
10K 6
402
19 37
19 12 AGP_WBF_L
AGPAD30 AR28 AGP_AD<30> 19 37
5%
AN27 1/16W
AGPAD31 AGP_AD<31> 19 37
SM1 R314
AM20 AGP_CBE<0> AGP_PIPE_L 1
10K 2
AGPCBE_0 19 37 12
AGPCBE_1 AT23 AGP_CBE<1> 19 37 5%

AN24 1/16W
AGPCBE_2 AGP_CBE<2> 19 37
R254 MF
402
AGPCBE_3 AL25 AGP_CBE<3> 19 37
AGP_AD_STB<0> 1
10K 2
37 19 12
AGP I/O REFERENCE AGPPAR AT29 AGP_PAR 19 37 5%

1/16W
R255
AGPFRAME AN28 AGP_FRAME_L MF
PCI PULL-UPS (PLACE CLOSE TO INTREPID AGP BALLS)
AGPTRDY AR29 AGP_TRDY_L
12 19 37
12 19 37
37 19 12 AGP_AD_STB<1>
402
1
10K 2
+3V_SLEEP 38 21 20 19 16 15 12 +1_5V_AGP AGPIRDY AT28 AGP_IRDY_L 12 19 37 5%
1/16W
RP33 AGPSTOP AM28 AGP_STOP_L
10K AGPDEVSEL AM27 AGP_DEVSEL_L
12 19 37
R239 MF
402
B 39 37 24 18 17 12 PCI_FRAME_L 4 5
1 AT32
12 19 37
37 19 12 AGP_SB_STB 1
10K 2 B
5%
RP33 R225 AGP_SBA0 AGP_SBA<0> 19 37 5%
1/16W
1/16W
SM1 1K AGP_SBA1 AR32 AGP_SBA<1> 19 37 MF
2
10K 7
1%
1/16W AGP_SBA2 AM31 AGP_SBA<2> 402
39 37 24 18 17 12 PCI_DEVSEL_L MF
19 37
402 2 AGP_SBA3 AN31 AGP_SBA<3> 19 37

5%
RP36
10K
1/16W
SM1 INT_AGP_VREF 12 19 38
AGP_SBA4 AR31 AGP_SBA<4> 19 37
4 5 AGP_SBA5 AT31 AGP_SBA<5>

39 37 24 18 17 12 PCI_IRDY_L 19 37
5%
RP36 R219 1
1 C291 AGP_SBA6 AM30 AGP_SBA<6> 19 37
R253
1/16W
SM1 1K 0.22uF AGP_SBA7 AN30 AGP_SBA<7> 19 37
10K
3
10K 6
1%
1/16W 20% 37 19 12 AGP_AD_STB_L<0> 1 2
12 PCI_TRDY_L
39 37 24 18 17
MF 2 6.3V
CERM AGP_SB_STB_P AH25 AGP_SB_STB 12 19 37 5%
5% 402 2 402 1/16W
RP36 1/16W AGP_SB_STB_N AG25 AGP_SB_STB_L 12 19 37 MF R256
SM1 402 10K 2
2
10K 7 AGP_ST0 AN29 AGP_ST<0> AGP_AD_STB_L<1> 1
39 37 24 18 17 12 PCI_STOP_L 19 37 19 12
5% AGP_ST1 AT30 AGP_ST<1> 19 5%

1/16W
1/16W AGP_ST2 AR30
SM1 RP33 AGP_ST<2> 19
R235
10K
MF
402
1
10K 8
SIMPLY PROVIDING REFERENCE TO CHIP AK20 AGP_AD_STB<0> 12 19 37 AGP_SB_STB_L 1 2
39 24 12 AIRPORT_PCI_REQ_L BECAUSE SINGLE AGP PWR PLANE AND CLOSE PROXIMITY OF CHIPS AGP_AD_STB0_P 37 19 12
AGP_AD_STB0_N AK19 AGP_AD_STB_L<0> 12 19 37 5%

5% 1/16W
RP36 1/16W
SM1 19 12 AGP_WBF_L AK30 AGP_WBF AGP_AD_STB1_P AK21 AGP_AD_STB<1> 12 19 37 MF
402
1
10K 8 AGP_AD_STB1_N AK22 AGP_AD_STB_L<1> 12 19 37
18 12 CBUS_PCI_REQ_L
5% AGPPIPE AJ29 AGP_PIPE_L 12
1/16W
SM1 +3V_MAIN SERIES RESISTORS FOR BOOTROM CONTROL SIGNALS AGPRBF AK24 AGP_RBF_L 12 19 37
VSSA_5
(PLL5)
RP33 PLACE CLOSE TO INTREPID SIDE V13
17 12 NEC_PCI_REQ_L 3
10K 6 INTREPID AGP/PCI
A 5%
1/16W R277 NOTICE OF PROPRIETARY PROPERTY
A
SM1
INT_ROM_CS_L 1
22 2 ROM_CS_L
12 9 39
5% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1/16W
MF R282 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
INT_ROM_OE_L
402
1
22 2 ROM_OE_L I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
12 9 39
5% II NOT TO REPRODUCE OR COPY IT

NEC USB2 REQ REMAINS ON +3V_MAIN 1/16W
BECAUSE THIS CHIP IS POWERED DURING SLEEP R278 MF
402
INT_ROM_RW_L 1
22 2 ROM_RW_L
12 9 39 SIZE DRAWING NUMBER REV.
5%
1/16W
MF
402 APPLE COMPUTER INC.
D 051-6653 C
SCALE
NONE
SHT
12 44
OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TEST PULL-UPS/DOWNS +3V_MAIN
CLKENET_LINK_TX RP35
V5 UIDE_DATA<0> 24 37
35 26
2
10K 7
OMIT ATA_D0 39 13 JTAG_ASIC_TDI
T1
U51 ATA_D1 UIDE_DATA<1> 24 37 R145 RP35 5%
ATA_D2 U1 UIDE_DATA<2> 24 37 10 1/16W
INTREPID-REV2.1 ATA_D3 U2 UIDE_DATA<3> 24 37
37 26 ENET_PHY_TX_EN 1 2 37 ENET_LINK_TX_EN
JTAG_ASIC_TMS 1
10K 8
SM1
BGA 5% 39 26 13
(5 OF 9) ATA_D4 V4 UIDE_DATA<4> 24 37 1/16W
MF 5%
CRITICAL V2 1/16W
ATA_D5 UIDE_DATA<5> 24 37
R149 402 OMIT SM1 R269
ATA_D6 W1 UIDE_DATA<6> 24 37 10 H9 TX_CLK U51 INT_TDO 2
10K 1
V1 UIDE_DATA<7> 24 37 37 26 ENET_PHY_TX_ER 1 2 37 ENET_LINK_TX_ER 26 14 13
ATA_D7
W2 UIDE_DATA<8> 24 37 5%
A7 TX_EN INTREPID-REV2.1 HW_PLL<BIT 0> 5%
1/16W
ATA_D8 1/16W A5 TX_ER BGA
D ATA_D9 W8
W4
UIDE_DATA<9> 24 37 MF
402
ENET_LINK_TXD<0> H10 TXD_0
(4 OF 9) MF
402
NO STUFF
D
ATA_D10 UIDE_DATA<10> 24 37 37 13
CRITICAL
UATA100 W5 UIDE_DATA<11> 24 37 37 13 ENET_LINK_TXD<1> E9 TXD_1 R630
ATA_D11
Y2 UIDE_DATA<12> 24 37 37 13 ENET_LINK_TXD<2> D8 TXD_2 1
10K 2
ATA_D12
Y1 ENET_LINK_TXD<3> A6 TXD_3 RESET U5 INT_RESET_L
ATA_D13 UIDE_DATA<13> 24 37 37 13
MISC 9 29 5%
ENET_LINK_TXD<4> B7 1/16W
W7 TXD_4
ATA_D14
Y8
UIDE_DATA<14> 24 37
UIDE_DATA<15> 24 37
37 13
37 13 ENET_LINK_TXD<5> G10 TXD_5

PURESET T2 INT_PU_RESET_L 25 29 R270
10K
MF
402
ATA_D15 1 2
ENET_LINK_TXD<6> D9 39 13 INT_TST_PLLEN_PD
37 13 TXD_6 L4 FW_LINK_DATA<0>
ATA_A0 Y5 UIDE_ADDR<0> 24 37 37 13 ENET_LINK_TXD<7> E10 TXD_7
PHY_DATA0 27 37 5%
1/16W
M4 FW_LINK_DATA<1>
ATA_A1 AB1 UIDE_ADDR<1> 24 37
CLKENET_LINK_RX J12 RX_CLK
PHY_DATA1
P7 FW_LINK_DATA<2>
27 37 MF
402 RP35
10K
ATA_A2 Y7 UIDE_ADDR<2> 24 37 35 26 PHY_DATA2 27 37
3 6
ENET_RX_DV C4 RX_DV N5 FW_LINK_DATA<3> 39 26 13 JTAG_ASIC_TCK
PHY_DATA3
37 26 27 37
ATA_VREF Y15 UIDE_REF D2 RX_ER K1 5%
26 ENET_RX_ER FW_LINK_DATA<4>
38
37 PHY_DATA4 27 37
1/16W
ATA_RST Y4 UIDE_RST_L 24 37
ENET_LINK_RXD<0> D3 PHY_DATA5 K2 FW_LINK_DATA<5> 27 37
R263
1K
SM1
UDMA - STOP ATA_WR AA1 UIDE_DIOW_L 24 37 37 26 RXD_0 GB ETHERNET L2
PHY_DATA6 FW_LINK_DATA<6> JTAG_ASIC_TRST_L 1 2
UDMA - HOSTDMARDY/HSTROBE ATA_RD AA2 UIDE_DIOR_L 24 37 R224
82 2
37 26 ENET_LINK_RXD<1> E7 RXD_1
PHY_DATA7 N4 FW_LINK_DATA<7>
27 37
27 37
39 26 13
5%
AA5 26 ENET_LINK_RXD<2>
D6 RXD_2 1/16W
UIDE_IOCHRDY 24 37 1 HD_DMARQ
UDMA - DEVICEDMARDY/DSTROBE ATA_CHRDY
ATA_CS0 AA4 UIDE_CS0_L 24 37 5%
24 37
37
37 26 ENET_LINK_RXD<3>
B4 RXD_3 PHY_LPS M1 FW_PHY_LPS 27
R186 MF
402 RP35
10K
1/16W A4
FIREWIRE
P5 1
22 2 4 5
AB2 UIDE_CS1_L 24 37 MF 37 26 ENET_LINK_RXD<4> RXD_4 PHY_CTL0 FW_LINK_CNTL<0> 27 37 FW_PHY_LREQ 27 37 39 13 INT_JTAG_TEI
ATA_CS1
AC1 402 26 ENET_LINK_RXD<5>
D7 L1 FW_LINK_CNTL<1> 27 5% 5%
ATA_DMACK UIDE_DMACK_L 24 37 37 RXD_5 PHY_CTL1 37
ATA_DMARQ AC2 37 UIDE_DMARQ R205 37 26 ENET_LINK_RXD<6>

G9 RXD_6 PHY_LREQ M2 37 FW_LINK_LREQ
1/16W
MF R259 1/16W
SM1
AA8 82 2 26 ENET_LINK_RXD<7>
E8 T7 CLKFW_LINK_PCLK 27
402
INT_TST_MONIN_PD 1
1K 2
ATA_INTRQ 37 UIDE_INTRQ 1 HD_INTRQ 37 RXD_7 FWR_PCLK 35 39 13
5%
24 37
R160
10 35 26 CLKENET_LINK_GBE_REF
L13 GBE_REFCLK R195
22
5%
1/16W
1/16W H12
MF 35 26 CLKENET_PHY_GTX 1 2 35 CLKENET_LINK_GTX GTX_CLK FWR_LCLK U14 35 CLKFW_LINK_LCLK 1 2 CLKFW_PHY_LCLK 27 35 MF
402
+3V_MAIN 402 E6
NO_TEST=TRUE CS_CE1 AD1 CSLOT_CE1_L_SPN 5%
1/16W
37 26 ENET_CRS CRS FW_LINKON N2 FW_LKON 27 5%
1/16W
NO_TEST=TRUE CS_CE2 AB4 CSLOT_CE2_L_SPN MF
402
37 26 ENET_COL
C5
B5
COL FW_PINT N1 FW_PINT 27 37 MF
402
I2C PULL-UPS
26 ENET_MDIO
NO_TEST=TRUE CS_IORD AB5 CSLOT_IORD_L_SPN 1
R232 NO STUFF
Keep C847 stub short 1
37 MDIO +3V_MAIN
NO_TEST=TRUE CS_IOWR AD2 10K C847 26 ENET_MDC
B6 MDC RP32
C CARDSLOT
NO_TEST=TRUE CS_OE AC4
CSLOT_IOWR_L_SPN
CSLOT_OE_L_SPN
5%
1/16W
10pF
5%
37
39 23 13 11 6 INT_I2C_CLK0
2.2K
2 7
C
NO_TEST=TRUE CS_WE AE1 CSLOT_WE_L_SPN
MF 2 50V
CERM
2 402 402 39 13 JTAG_ASIC_TDI AK8 TDI 5%
CS_WAIT AE2 CSLOT_IOWAIT_L_PU
26 14 13 INT_TDO
AT5 TDO
1/16W
SM1 RP32
CS_WAIT IS AN INPUT 39 26 13 JTAG_ASIC_TCK
AP5 TCK 2.2K
1 8
39 23 13 11 6 INT_I2C_DATA0
39 26 13 JTAG_ASIC_TMS
AR5 TMS
AC5 EIDE_DATA<0> 24 37 5%
IDEDD0
AD4
39 26 13 JTAG_ASIC_TRST_L
AN6 TRSTN TEST IICCLK_0 AN2 INT_I2C_CLK0 6 11 13 23 39 RP32 1/16W
SM1
IDEDD1 EIDE_DATA<1> 24 37
39 13 INT_JTAG_TEI
AH10 TEI IICDATA_0 AN1 INT_I2C_DATA0 6 11 13 23 39
2.2K
4 5
AF1 EIDE_DATA<2> 24 37 AM7 39 25 14 13 INT_I2C_CLK1
IDEDD2 39 13 INT_TST_MONIN_PD TST_MONIN
IDEDD3 AG1 EIDE_DATA<3> 24 37 AK10 5%
39 INT_TST_MONOUT_TP TST_MONOUT IICCLK_1 AK5 INT_I2C_CLK1 1/16W
IDEDD4 AF2 EIDE_DATA<4> 24 37
13 INT_TST_PLLEN_PD
AR6 TST_PLLEN IICDATA_1 AM3 INT_I2C_DATA1
13 14 25 39
SM1 RP32
IDEDD5 AH1 EIDE_DATA<5> 24 37
39 13 14 25 39
2.2K
3 6
39 25 14 13 INT_I2C_DATA1
IDEDD6 AD5 EIDE_DATA<6> 24 37 5%
IDEDD7 AG2 EIDE_DATA<7> 24 37 1/16W
SM1
IDEDD8 AE4 EIDE_DATA<8> 24 37
IDEDD9 AE5 EIDE_DATA<9> 24 37 ENET_TXD SERIES TERMINATION
IDEDD10 AF4 EIDE_DATA<10> 24 37
IDEDD11 AH2 EIDE_DATA<11> 24 37
IDEDD12 AD7 EIDE_DATA<12> 24 37 RP16
22
IDEDD13 AG4
AJ1
EIDE_DATA<13> 24 37
EIDE_DATA<14> 24 37
37 26 ENET_PHY_TXD<0> 4 5 ENET_LINK_TXD<0> 13 37
ADDR
BUS I2C-0 I2C-1 I2C-2 PMU
IDEDD14 5% (MAIN) (MAIN) (SLEEP) (SLEEP)
IDEDD15 AJ2 EIDE_DATA<15> 24 37
1/16W
SM1 RP10 A0-WR RAM - LOWER
22 N/A N/A N/A
IDE IDEA0 AF5 EIDE_ADDR<0> 24 37
A1-RD J25 - PG 11
IDEA1 AE7
AK1
EIDE_ADDR<1> 24 37
RP10 5%
1/16W
SM1
A2-WR RAM - UPPER N/A N/A N/A
IDEA2 EIDE_ADDR<2> 24 37
1
22 8 A3-RD J25 - PG 11
NO_TEST=TRUE AG5 CSLOT_ADDR3_SPN 37 26 ENET_PHY_TXD<2> ENET_LINK_TXD<2> 13 37
IDEA3
B NO_TEST=TRUE IDEA4 AH4 CSLOT_ADDR4_SPN 5% AC-WR N/A N/A DASH MODEM
N/A B
NO_TEST=TRUE IDEA5 AL1 CSLOT_ADDR5_SPN
1/16W
SM1 RP10 AD-WR J14 - PG 25
NOT USING CARDSLOT INTERFACE 22
NO_TEST=TRUE IDEA6 AK2
AH5
CSLOT_ADDR6_SPN
CSLOT_ADDR7_SPN
AE-WR BOOTBANG EEPROM N/A N/A N/A
NO_TEST=TRUE
NO_TEST=TRUE
IDEA7
IDEA8 AF7 CSLOT_ADDR8_SPN RP10
5%
1/16W
SM1
AF-RD U51 - PG 6
NO_TEST=TRUE IDEA9 AG7 CSLOT_ADDR9_SPN 37 26 ENET_PHY_TXD<4> 2

22 7 ENET_LINK_TXD<4> 13 37
84-WR J3000LMU N/A N/A N/A
IDECHRDY AK4 EIDE_IOCHRDY 24 37 5% 85-RD (LMU on -RUXPG Brd.)
23
IDECS0 AB7 EIDE_CS0_L 24 37

1/16W
SM1 RP16 5C-WR FAN CONTROLLER
N/A
IDECS1 AM1 EIDE_CS1_L 24 37 37 26 ENET_PHY_TXD<5> 3
22 6 ENET_LINK_TXD<5> 13 37 5D-RD N/A U52 - PG 25 N/A
IDERST AJ4 EIDE_RST_L 24 37 RP16 5%
1/16W 6A-WR N/A N/A SNAPPER SOUND
N/A
IDEWR AM2 EIDE_WR_L 24 37
37 26 ENET_PHY_TXD<6> 1
22 8
SM1
ENET_LINK_TXD<6> 13 37
6B-RD J2 - PG 25
IDERD AL2
AG8
EIDE_RD_L 24 37
5% D2-WR N/A CLOCK SLEW SSCG
N/A N/A
IDEDMACK
AH7
EIDE_DMACK_L 24 37 1/16W
SM1 RP16 D3-RD U30 - PG 14
IDEDMARQ EIDE_DMARQ 24 37
2
22 7
IDEINTRQ AA7 EIDE_INT 24 37
37 26 ENET_PHY_TXD<7> ENET_LINK_TXD<7> 13 37
ADDR LSB INDICATES READ (’1’) OR WRITE (’0’) MODES
5%
1/16W
SM1
JTG_RSTN_L TST_TEI_H JTG_TDO_H JTG_TDI_H TST_PLLEN_H ANALYZER_CLK

1
(I/O) (I/O) DESCRIPTION
R207 1 X X X X X JTAG MODE
1K
1%
1/16W
MF
2 402
0 0
EXTPLL
SHUTDOWN
(OUTPUT)
DDR_
TPDENABLE
(OUTPUT)
0 (OUTPUT) NORMAL OPERATION INT - ENET/FW/UATA
A
0 0 (OUTPUT) 0(I) 1 SELECTED
PLL OUTPUTS VIEW PLLS (SOFTWARE) EIDE/I2C
0 0
HWPLL_
TESTSEL5
(INPUT)
1(I) SELECTED
1
PLL OUTPUTS VIEW PLLS (HARDWARE) NOTICE OF PROPRIETARY PROPERTY
A
0 1 0(I) 0(I) MEMWE SYNC/MEM
BYPASS
DATA
ATPG NORMAL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
0 1 0(I) 1(I) 0 X(I) ATPG IDDQ I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0 1 0(I) 1(I) 1 X(I) TEST TRI-STATE III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
FUNCTIONAL TEST WITHOUT
0 1 1(I) 0(I) 0 X(I) POSTSCALAR BYPASS SIZE DRAWING NUMBER REV.
0 1 1(I) 0(I) 1 X(I) FUNCTIONAL

POSTSCALAR
TEST WITH
BYPASS APPLE COMPUTER INC.
D 051-6653 C
0 1 1(I) 1(I) X X(I) FUNCTIONAL TEST IDDQ SCALE
NONE
SHT
13 44 OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+2_5V_MAIN
NO STUFF
+1_5V_INTREPID_PLL 8 12 38
-> 1.55V OUTPUT
R240
4.7 2
USB PORT ASSIGNMENTS
R568 1 +1_5V_INTREPID_PLL8 38
0 5%
1
5%
2
U49
LT1962-ADJ C392 1 R574
18.7K
1 C337 1
0.22uF
1/16W
MF
402
PORT A - PORT D/UNUSED
1/16W
MF MSOP 0.01uF
20% 1% 20%
6.3V 2
R181
10K
+1_8V_MAIN
603 38 LTC1962_INT_VIN 8 IN OUT 1
16V
CERM 2
1/16W
MF CERM
402
R280
4.7 14 USB_DAM 2 1
402 2
R565 NC 7 NC 402 1 C723 1 2 +1_5V_INTREPID_PLL4 38 5%
1/16W R183
0 ADJ 2 LT1962_INT_ADJ 10uF 5% MF 10K
1 2 C721 1 NC 6 NC 2 6.3V
20%
C389 1 1/16W
MF 14 USB_DAP 402 2 1
5% 1uF CERM
0.22uF 402
1/16W 20% BYP 3 LT1962_INT_BYP R567 1 805 R156 5%
1/16W
D
MF
603
10V
CERM 2
603
5 SHDN GND 4 68.1K
1%
20%
6.3V 2
CERM
402
R279 14 USB_DBM 2
10K 1
MF
402 D
1/16W 4.7 2
+3V_SLEEP
R148 MF
402
1 +1_5V_INTREPID_PLL3 38
5%
1/16W R157
10K
10K 2 PCI INTERRUPTS 2 5% USB_DBP
MF
402 2 1
1/16W 14
1 CBUS_INT_L 14 18
C388 1 MF
402 R164 5%
5%
1/16W R746 0.22uF 10K
1/16W
MF
20% 2 1
MF 10K 2 6.3V 2 USB_DCM 402
402 1 AIRPORT_PCI_INT_L CERM R243 14
+3V_MAIN 5%
14 24 39 402
1
4.7 2 +1_5V_INTREPID_PLL2
5%
1/16W R165
R158 1/16W TABLE_5_HEAD
38 +3V_MAIN
USB_DCP
MF
402 2
10K 1
10K 2 MF PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 5% 14
402 1/16W
1 NEC_PCI_INT_L 14 17 TABLE_5_ITEM
C386 1 MF
402
R182 5%
1/16W
5%
1/16W
359S0086 1 IC,CY28512-2 U31 CRITICAL SSCG 0.22uF 1
USB_DDM 2
10K 1
MF
402
20%
14
MF 6.3V 2
+3V_MAIN 402 GPIO/EXTINT PULLUPS +3V_MAIN CERM R201 5%
R180
+2_5V_MAIN
402 4.7 L13 1/16W
MF 10K
R187 1 2 +1_5V_INTREPID_PLL1 38
FERR-EMI-100-OHM 14 USB_DDP 402 2 1
2
10K 1 USB_PWREN_EF_L
5%
1/16W
SM 5%
5%
14
C387 1 MF
402
1/16W
MF
R191 1/16W 1 0.22uF 2 402
MF 1 20% +3V_INTREPID_USB
10K 1 6.3V 2 38
2
5%
402 USB_OC_EF_L 14
SSCG
L15 L14
SSCG CERM
402 PORT E/BLUETOOTH
1/16W RP11 400-OHM-EMI
R174
VDD15A_1 AA16
VDD15A_2 AJ12
VDD15A_3 AJ17
VDD15A_4 AJ18
VDD15A_8 AG29
MF
10K 400-OHM-EMI SM-1
402 1 C235 1 C246 1 C256 22
VDDU33_1 T8
VDDU33_2 U8
7 2 USB_OC_AB_L SM-1
14 USB_DEP 1 2 BT_USB_DP
RP11 0.01uF 0.1uF 10uF 37 14 25 37 39
PCI_
(PLL1)
PCI_
(PLL2)
PCI_
(PLL3)
PCI_
(PLL7)
(PLL9)
5% 2 20% 20% 20% 5%
6
10K 3
1/16W
SM1 2 2 16V
CERM 2 10V
CERM 2 6.3V
CERM R179 1/16W
USB_PWREN_CD_L 14 402 402 805 MF
MAIN_RESET_L +3V_CG_PLL_MAIN 22 402
5%
1/16W
RP8 39 29 24 19 18 17
SSCG SSCG 37 14 USB_DEM 1 2 BT_USB_DM 25 37 39
10K 1 C402 C399
1 5%
SM1 5 4 USB_PWREN_AB_L 14 SSCG
1uF 0.1uF OMIT
1/16W
MF
R1781 1
R175
RP11 5% 1 C400 20% 20% 402 15K 15K
2 10V 10V U51 SCCTXDA AF9 COMM_TXD_L 5% 5%
C
C 5
10K 4
1/16W
SM1
USB_OC_CD_L 14
NO STUFF
R2861 1
R287
SSCG 0.1uF
20%
2 10V
CERM
603
2 CERM
402 SSCG INTREPID-REV2.1 SCCRTSA AN3 COMM_RTS_L
25 39
25 39
1/16W
MF
402 2
1/16W
MF
2 402
5% RP8 0 10K CERM
402
R450 CRITICAL (6 OF 9)
BGA
SCCDTRA AF10 COMM_DTR_L 25 39
1/16W 10K 5% 5% 0
SM1 8 1 INT_EXTINT14_PU
1/16W 1/16W
+2_5V_CG_MAIN
5%
1/16W
SCCRXDA AG11 COMM_RXD 25 39
14 MF MF
402 2 2 402 MF
402 SCCGPIOA AG9 COMM_GPIO_L 25 39
RP5 5% SSCG CG_FSEL 1 2 CG_FSEL_INT G5 VCORE A/B SEL
SCCTRXCA AT4 COMM_TRXC
3
10K 6
1/16W
SM1
INT_EXTINT8_PU 14 SSCG NO STUFF
1 C394
0.1uF
14
33 14 INT_GPIO1_PU
E1
GPIO0
GPIO1
GENERAL
PURPOSE
VIA
MISO SCCTXDB AR4 PMU_FROM_INT

25 39
29
PORT F/MODEM
R288 1 2
R295 25 COMM_SHUTDOWN
J7
R192
VDD1 10
VDDA 12
VDDQ 18
20% GPIO2 I/O’S
5%
RP6 2 10V
39
REQ* AL5 PMU_REQ_L
VDD0 1
VDDC 5
SCCRTSB 14 29
1/16W
SM1 10K 10K 10K CERM
402
39 25 COMM_RESET_L
F2 GPIO3 AG10 PMU_TO_INT USB_DFP 1
22 2 MODEM_USB_DP
4 5 5% 5% J8 MOSI SCCRXDB 29 37 14 25 37 39
COMM_RING_DET_L 14 25 29 39 1/16W 1/16W 27 FW_PHY_PD GPIO4 AP4
MF MF ACK* SCCGPIOB PMU_ACK_L 5%
RP11 5%
1/16W
402 2 1 402 39 25 SND_HP_MUTE_L
H5 GPIO5
SCK SCCTRXCB AM5 PMU_CLK
29
R188 1/16W
MF
10K SM1 CRITICAL 25 SND_AMP_MUTE_L
L9 GPIO6
29
22 402
8 1 INT_GPIO15_PU 14 U31 SSCG
14 INT_GPIO9_PU
H4 GPIO9 USB_VD0_P L8 USB_DAP
37 14 USB_DFM 1 2 MODEM_USB_DM 25 37 39
5% RP6 CY28512D R293 14 SND_HW_RESET_L

J5 USB_VD0_N L7 USB_DAM
14
5%
1/16W
1/16W 10K INT_REF_CLK_OUT 20 CLKIN TSSOP 33 39 25 GPIO11 14
1 1
SM1 2 7 PMU_INT_NMI 14 29
35 14
OMIT CPU0 16 CG_CLKOUT1 2 INT_REF_CLK_IN 14 35
14 INT_GPIO12_PU
K8 GPIO12
MF
402 R189 R193
CG_FSEL 3 FSEL INTERNAL 250K PULL-UP 5% USB_VD1_P G2 USB_DBP 14 15K 15K
RP6 5%
1/16W
14
1/16W
OUTPUT IMPEDANCE ~18-20 OHMS 14 INT_GPIO15_PU
F1 GPIO15
USB_VD1_N G1 USB_DBM
5%
1/16W
5%
1/16W
3
10K 6 SM1 INT_I2C_CLK1 9 SCLK
MF
402 26 INT_ENET_RST_L
K7 GPIO16
14
MF MF
PMU_INT_L 14 29
39 25 13
J4 402 2 2 402
USB_PRTPWR0 USB_PWREN_AB_L 14
F33
5%
1/16W R250 39 25 13 INT_I2C_DATA1 8 SDATA 39 29 25 14 COMM_RING_DET_L EXTINT0
USB_PWRFLT0 K4 USB_OC_AB_L 14
SM1 1
10K 2 PMU_REQ_L 14
29 14 PMU_INT_L E34 EXTINT1
29 CG_ADDRSEL 14 ADDRSEL INTERNAL 250K PULL-DOWN C33
19 AGP_ATI_INT_L EXTINT2 USB_VD2_P H2 USB_DCP
RP7 5%
1/16W 17 RESET* 14 INT_EXTINT3_PU
D34 EXTINT3 USB_VD2_N H1 USB_DCM
14
RP13
10K MF CG_RESET_L SSCG
2 B33
14
4
47 5
7 2 402 INT_GPIO12_PU 14
13 PD* R292 PLACE NEAR INTREPID TO
39 25 SND_LIN_SENSE_L EXTINT4
USB_VD3_P M7 USB_DDP
INT_I2S0_SND_TO_DAC 25 39
5%
RP7
14 CG_SYSCLK_EN
5%
75 MINIMIZE OVERSHOOT 26 ENET_ENERGY_DET
A33 EXTINT5
USB_VD3_N M8 USB_DDM
14
5%
1/16W
RP13
1/16W
SM1 10K CG_LOCK 2 LOCK OPEN DRAIN OUTPUT 1/16W 39 24 14 AIRPORT_PCI_INT_L
E31 EXTINT6 USB 14
SM1 3
47 6
MF INTERRUPTS INT_I2S0_SND_LRCLK 25 39
6 3 INT_EXTINT13_PU 402 1 14 CBUS_INT_L
G30 EXTINT7 USB_PRTPWR1 J2 USB_PWREN_CD_L
14
SSCG
R284 NC 4 ODSEL INTERNAL 250K PULL-UP SSCG
18
D31 J1
14
RP13 5%
RP4 5%
R142
14 INT_EXTINT8_PU EXTINT8 POWERBOOK SPARE USB_PWRFLT1 USB_OC_CD_L 14
47 1/16W
7 VSS0
19 VSS1
11 VSSA
6 VSSC
15 VSSQ
1/16W NO STUFF SM1

B 5
10K 4
SM1
INT_EXTINT16_PU
38
14 VCORE_VGATE 1
0 2 2
R296 VCORE_VGATE 1
0 2
29 14 PMU_INT_NMI
14 INT_EXTINT10_PU
C32
B32
EXTINT9
USB_VD4_P K5 USB_DEP 14 37
1 8 INT_I2S0_SND_SCLK 25 39
B
14 33
5% 10K 38 33 14 EXTINT10 CBUS_REG_L
USB_VD4_N L5 USB_DEM
5%
1/16W RP13
5%
1/16W RP5 1/16W
MF
5%
1/16W
5%
1/16W
14 INT_EXTINT11_PU
E30 EXTINT11 CBUS_IREQ_L
14 37
SM1
2
47 7
SM1
1
10K 8 402 MF MF 14 INT_EXTINT12_PU
J9 EXTINT12 USB_VD5_P P8 USB_DFP 14 37
INT_I2S0_SND_MCLK 25 35 39
INT_EXTINT11_PU 14 1 402 402 F4
14 INT_EXTINT13_PU EXTINT13 USB_VD5_N N8 USB_DFM 14 37
5%
1/16W
RP6 5%
1/16W 14 INT_EXTINT14_PU
D1 EXTINT14 M5
SM1
1
10K 8
SM1 NO STUFF
SND_HP_SENSE_L E2 EXTINT15
USB_PRTPWR2 USB_PWREN_EF_L 14
INT_EXTINT10_PU 39 25
N7 USB_OC_EF_L
5%
14
R467 14 INT_EXTINT16_PU
H7 EXTINT16
USB_PWRFLT2 14
SOFT_MODEM
1/16W RP4 SYSTEM_CLK_EN 1 0 G4 RP47
29 14 2 17 14 NEC_PCI_INT_L EXTINT17
SM1 10K AUD_DTO R4 INT_I2S0_SND_TO_DAC_UF 0K
NO STUFF 5 MPIC_CPU_INT_L
D30
6 3 INT_EXTINT12_PU 14 R457 1/16W
5% CG_SYSCLK_EN CPU_INT R7 INT_I2S0_SND_FROM_ADC 25
1 8 INT_MOD_DTO 25
RP8 5% J9 CLK18M_INT_EXT 35 INT_TDO 1 0 MF

2 402
14
PMU_PME_L AJ7 PCIPME

AUD_DTI
T5 INT_I2S0_SND_LRCLK_UF
39
5%
1/16W U.FL-R_SMT 26 13 39 29 24 17 AUD_SYNC SOFT_MODEM1/16W
7
10K 2
SM1 F-ST-SM
3 NO STUFF 5% AT6 PROCSLEEPREQ
29 INT_PROC_SLEEP_REQ_L AUD_BITCLK P2 INT_I2S0_SND_SCLK_UF RP47 SM1
INT_GPIO9_PU 14 1/16W
AN8 PENDPROCINT R5 0K
5% RP8 R134
0
MF
402
29 INT_PEND_PROC_INT AUD_CLKOUT INT_I2S0_SND_MCLK_UF 2 7 INT_MOD_SYNC 25
1/16W 1 U4 XTAL_IN AUDIO/I2S R2 5%
SM1
6
10K 3
1 2 35 CLK18M_INT_XIN MOD_DTO 14 INT_MOD_DTO_UF
1/16W
INT_GPIO1_PU 14 33 5% NO STUFF CLK18M_INT_XOUT V15 XTAL_OUT T4 INT_MOD_DTI SM1 SOFT_MODEM
NO STUFF 35 MOD_DTI
(SIGNAL FROM MODEM)
R153 5% 2 1
R113
1/16W
MF R144 29 14 SYSTEM_CLK_EN AN7 STOPXTAL MOD_SYNC R1 14 INT_MOD_SYNC_UF
14 25
RP47
0K
1
10K 2 1/16W
SM1 INT_EXTINT3_PU 14 51
402 10M CLOCKS
V8 14 INT_MOD_BITCLK_UF 3 6 INT_MOD_BITCLK 25
2 1 MOD_BITCLK
USB_MODEM 5% AT7 WATCHDOG P1
5% INT_WATCHDOG_L 14 INT_MOD_CLKOUT_UF
1/16W RP15 1/16W
MF 5%
1/16W 1
R143
29 MOD_CLKOUT SOFT_MODEM 5%
RP47 1/16W
MF
402 2
10K 7 INT_MOD_DTO_UF
2 402 MF
402 0 R218 +3V_SLEEP 0K 5 SM1
14
5% INT_REF_CLK_OUT1
0 2 INT_REF_CLK_OUT_UF U15 BUF_REF_CLK_OUT
4 INT_MOD_CLKOUT 25
USB_MODEM 5% CRITICAL 1/16W 35 14 35
RP15 1/16W
SM1 Y2 MF
2 402
5% 35 14 INT_REF_CLK_IN
K9 SS_REF_CLK_IN 5%
1/16W
3
10K 6 18.432M 1/16W
MF SM1
INT_MOD_CLKOUT_UF 1 2
14
CLK18M_XTAL_IN 35
402 IICCLK_2 AL4
2
IIC
R258 2R241
5%
1/16W
SM1
USB_MODEM C152 1
8X4.5MM-SM
1 C151
HWPLL_
TESTMUXSEL SIGNAL NAME
IICDATA_2 AH8
5%
1K 1K
5%
INT - USB/GPIOS/I2S
A RP15 22pF 22pF 5 MOD_BITCLK_B_H
(PLL1) 1/16W
MF
1/16W
MF A
(PLL2)
(PLL3)
(PLL7)
AH29 VSSA_8
(PLL9)
R9 VSSU_1
R8 VSSU_2
10K 5% 5% 1 402 1 402 NOTICE OF PROPRIETARY PROPERTY
AA15 VSSA1
AJ13 VSSA2
AJ16 VSSA3
AK18 VSSA4
4 5 INT_MOD_DTI 50V 2 50V
USB_MODEM
14 25 CERM 2
402
CERM
402 4 MOD_CLKOUT_B_H
5%
1/16W
SM1
RP15
10K 3 MOD_DTO_B_H
1 8 INT_MOD_SYNC_UF INT_I2C_CLK2 25 39
14
USB_MODEM
R206 5%
1/16W
CRYSTAL LOAD CAPACITANCE IS 16PF 2 MOD_SYNC_B_H INT_I2C_DATA2 25 39
1
10K 2 SM1 INT_MOD_BITCLK_UF
TABLE_ALT_HEAD
1 MOD_DTI_B_H III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

14
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
5%
1/16W R166
PART NUMBER
0 JTG_TDO_H SIZE DRAWING NUMBER REV.
MF
051-6653 C
TABLE_ALT_ITEM
100K2
402 1 SND_HW_RESET_L 14 25 39
197S0004 197S0035 Y2 Alt. for Siward Part
PART # QTY DEVICE PACKAGE DESCRIPTION VALUE VOLT. WATT. TOL. REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_11_HEAD
APPLE COMPUTER INC.

D
5%
1/16W SCALE SHT
14 44 OF
TABLE_11_HEAD
MF 116S1104 1 RES RES-0402-V2 RESISTOR 10K 1/16W 5% R292 NO_SSCG

402 NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+2_5V_SLEEP +2_5V_MAIN
INT_2_5V_COLD INT_2_5V_HOT
1 1 +1_5V_AGP
R276 R274 38 21 20 19 16 12
0 0
5% 5% +1_5V_MAIN +3V_MAIN
1/10W 1/10W
FF FF
805 2 805 2
MAXBUS_SLEEP
D
38 33 16 8 7 6 5
+2_5V_INTREPID D
AD20
AE20
AE23
AF22
AH19
AH22
AH28
AJ21
AJ23
AL19
AL22
AL28
AL30
AN32
AP19
AP22
AP25
AP28
AP31
AR33
AR34
AA11
AA12
AC12
AC13
AC14
AD21
AE15
AE17
AF25
AL10
AB3
AB6
F30
AE3
AE6
AH3
AH6
AK6
F7
F9
G3
G6
AA25 AGP_IO_VDD VDD3.3 AL13
C12 AA29
AL16
C15 OMIT AB25
AL3 TABLE_5_HEAD
C18 AB27 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
C21 U51 AB31
AL7 TABLE_5_ITEM
C24
INTREPID-REV2.1 AB34
AM4 343S0305 1 IC,ASIC,INTREPID,REV2.1,974 BGA,FAST U51 CRITICAL ?
BGA AN5
C27 (8 OF 9) AC25 OMIT
AA21 AP10
C30 CRITICAL AC27
AA24
U51 AP13
INTREPID-REV2.1
C9 AC28
AB13 BGA AP16
F12 AE31
AB15 (9 OF 9) K3
F15 AE34 CRITICAL
AB17 K6
F18 AF28
AB19 N24
F21 AH30
AC17 N3
F24 AH34
AC19 N6
F27 VDD1.8/CPUVIO AK34
AC23 P13
M15 AP35
AD13 P14
M16 C35
AD15 POWER R22
M19 G31
AD22 T12
M22 G34
P15 T18
M23 K31
P18 T3
N18 K34
P20 VDD3.3 T6
N21 VDD2.5 N28
P21 VDD1.5 U12
N23 N31
R17 W12
P16 N34
C P19 N36
P25
R20
T13
W13
W3
C
U17 W6
POWER/GROUND P28
U18 AP2
R25
U24 AP7
R27
V16 AR3
T25
V19 B3
T28
V20 C2
T29
V22 C6
T31
W16 D32
T34
W24 D5
U25
Y13 B34
U28
Y18 E4
L24 V25
M14 V29
M17 W25
M18 W31
M20 W34
M21 Y27
M24 Y29 AD28
M28 E33 AD3
M3 AD31
M31 AN33 AD34
M32 AN4 AD6
M34 AP1 AE14
GROUND
M6 AP12 AE16
M9 AP15 AE18
B N15
N25
AP18
AP21
AE19
AE21 U19
B
P12 AP24 AE22 U22
P17 AP27 AE28 U27
P22 AP3 AG21 U29
P29 AP30 AG23 V10
P4 AP33 AG24 V12
R14 VSS AP34 AG3 V17
R16 AP36 AG30 V18
R18 AP6 AG34 VSS V21
R19 VSS AP9 AG6 V24
R21 AR2 AH20 V3
R23 AR35 AH21 V31
R24 AT3 AH23 V34
R26 AT34 AH27 V6
R29 B2 VSS W11
R3 B35 AK3 W14
R31 C1 AK7 W23
R34 C10 AL12 W26
R6 C13 AL15 Y11
T11 C16 AL18 Y12
T14 C19 AL21 Y14
T23 C22 AL27 Y16
T24 C25 AL31 Y19
A
T27
U10
C28
C3
AL34
AL6
Y23
Y24 Intrepid Power
U16 C31
C34
AL9 Y25
A
AGP_IO_VSS
J6
J34
J31
J3
G7
F6
F34
F31
F3
F28
F25
F22
F19
F16
F13
F10
D4
D33
C7
C36
A3
A34
AA20
AA27
AA3
AA31
AA34
AA6
AB11
AB12
AB14
AB16
AB18
AB24
AB28
AB29
AC11
AC15
AC16
AC18
AC20
AC22
AC26
AD12
AD23
AD25
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
15 44 OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+1_5V_MAIN
24 Balls 30 Balls
33 15 8 7 6 5MAXBUS_SLEEP
38
INTREPID MAXBUS DECOUPLING 4 X 10UF (0805)
28 X 0.22UF (0402) INTREPID CORE DECOUPLING 4 X 10UF (0805)
29 X 0.22UF (0402)
C148 1 C142 1 1 C182 1 C178 1 C141 1 C145 1 C214 1 C163 1 C164 1 C225 1 C160 1 C159 C324 1 C325 1 1 C299 1 C279 1 C262 1 C292 1 C248 1 C302 1 C300 1 C290 1 C272 1 C259
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
805 805 402 402 402 402 402 402 402 402 402 402 805 805 402 402 402 402 402 402 402 402 402 402
D C144 1 C146 1 1 C204 1 C166 1 C205 1 C223 1 C229 1 C181 1 C207 1 C208 1 C183 1 C180 C201 1 C200 1 1 C301 1 C278 1 C226 1 C238 1 C250 1 C263 1 C224 1 C222 1 C261 1 C227 D
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
805 805 402 402 402 402 402 402 402 402 402 402 805 805 402 402 402 402 402 402 402 402 402 402
1 C165 1 C206 1 C147 1 C149 1 C179 1 C162 1 C161 1 C213 1 C271 1 C310 1 C288 1 C260 1 C303 1 C287 1 C258 1 C236 1 C289
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20% 20%
0.22uF 0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20% 20%
0.22uF 20%
0.22uF 20%
0.22uF
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
+3V_MAIN
57 Balls
4 X 10UF (0805)
INTREPID 3.3V DECOUPLING 40 X 0.22UF (0402)
38 21 20 19 15 12 +1_5V_AGP C378 1 C376 1 1 C170 1 C358 1 C268 1 C327 1 C342 1 C215 1 C352 1 C171 1 C158 1 C309
21 Balls 10uF
20%
10uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
INTREPID AGP I/O DECOUPLING 4 X 10UF (0805)
21 X 0.22UF (0402)
6.3V 2
CERM
805
6.3V 2
CERM
805
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
C C381 1 C380 1 1 C367 1 C319 1 C330 1 C363 1 C366 1 C332 1 C361 1 C320 1 C328 1 C364 C377 1 C375 1 1 C175 1 C357 1 C351 1 C350 1 C286 1 C176 1 C189 1 C167 1 C371 1 C359 C
10uF
20%
10uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
10uF
20%
10uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
6.3V 6.3V 2 6.3V 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 6.3V 6.3V 6.3V 2 6.3V 2 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 2 6.3V 6.3V
CERM 2 CERM 2 CERM 2 CERM CERM CERM CERM CERM CERM CERM 2 CERM 2 CERM CERM 2 CERM 2 CERM CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 CERM
805 805 402 402 402 402 402 402 402 402 402 402 805 805 402 402 402 402 402 402 402 402 402 402
C382 1 C379 1 1 C365 1 C329 1 C345 1 C346 1 C373 1 C344 1 C331 1 C312 1 C354 1 C347 1 C285 1 C283 1 C269 1 C221 1 C234 1 C247 1 C257 1 C343 1 C313 1 C228
10uF
20%
10uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
805 805 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
1 C321 1 C360 1 C308 1 C318 1 C237 1 C317 1 C341 1 C177 1 C212 1 C349 1 C184
0.22uF
20% 20%
0.22uF 0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20% 20%
0.22uF 20%
0.22uF 20%
0.22uF 0.22uF
20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402 402
44 Balls
38 15 10 9 +2_5V_INTREPID INTREPID DDR DECOUPLING 4 X 10UF (0805)
46 X 0.22UF (0402)
C314 1 C322 1 1 C304 1 C266 1 C172 1 C281 1 C243 1 C253 1 C334 1 C241 1 C348 1 C192 +2_5V_MAIN
B 10uF
20%
6.3V 2
10uF
20%
6.3V 2
0.22uF
20%
2 6.3V
0.22uF
20%
2 6.3V
0.22uF
20%
2 6.3V
0.22uF
20%
2 6.3V
0.22uF
20%
2 6.3V
0.22uF
20%
2 6.3V
0.22uF
20%
2 6.3V
0.22uF
20%
2 6.3V
0.22uF
20%
2 6.3V
0.22uF
20%
2 6.3V
INTREPID/MAIN 2.5V DECOUPLING
10 X 0.22UF (0402)
B
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
805 805 402 402 402 402 402 402 402 402 402 402
C191 1 C202 1 1 C306 1 C252 1 C275 1 C297 1 C240 1 C218 1 C274 1 C369 1 C368 1 C168
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 1 C770 1 C139 1 C335 1 C735 1 C245 1 C736 1 C739 1 C395 1 C374 1 C385
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 2
CERM
6.3V 2
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
805 805 402 402 402 402 402 402 402 402 402 402 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
402 402 402 402 402 402 402 402 402 402
1 C265 1 C251 1 C216 1 C254 1 C305 1 C186 1 C219 1 C315 1 C264 1 C294
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
6.3V
2 CERM 2 6.3V 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 2 6.3V 6.3V
2 CERM
402
CERM
402 402 402 402 402 402 402
CERM
402 402
Place these 2.5V Decoupling Caps near the Edge of +2.5V_MAIN and +2.5V_INTREPID split
1 C323 1 C273 1 C242 1 C203 1 C333 1 C217 1 C230 1 C293 1 C231 1 C296
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
1 C239 1 C316 1 C185 1 C282 1 C295 1 C280

Intrepid Decoupling
A 0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20% NOTICE OF PROPRIETARY PROPERTY
A
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
APPLE COMPUTER INC.

D 051-6653 C
SCALE SHT OF
NONE
16 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+3V_NEC_VDD 17 38
TABLE_ALT_HEAD
1 C749 1 C746 1 C761 1 C750 PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS:
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
TABLE_ALT_ITEM
197S0608 197S0038 Y1 Alt. for Siward Part

2 10V
CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
402 402 402 402 +3V_MAIN
FERR-EMI-100-OHM
L7
1 C756 1 C748 1 C769 1 C752 1 2 38 NEC_AVDD
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20% SM
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM C760 1 C751 1 C173 1
402 402 402 402 0.1uF 0.1uF 10uF
1
R172 20%
10V
20%
10V
20%
6.3V 2 Y1’s LOAD CAPACITANCE = 16 pF
0 CERM 2 CERM 2 CERM R613 D
D 1 C747 C197 1 C765 1 C768
0.1uF 10uF 0.1uF 0.1uF
5%
1/16W
MF
402 402 805
CRITICAL 43.2
1 2 NEC_USB_DAM 25 37 39
20% 20% 20% 20% 2 603 Y1 1%
2 10V
CERM
6.3V
CERM 2 10V
CERM 2 10V
CERM 30.0000M 1/16W
402 805 402 402 1 2 NEC_XT2_R MF
402
38 17 +3V_NEC_VDD 8X4.5MM-SM Low/Full/High Speed (External)
1 C759 1 C136 1R124
27pF 27pF 100 R612
P12
A13
A12
L13
J13
H13
F13
D13
G12
N10
N12
H3
M4
C8
P2
P3
A3
E2
N8
H4
D7
5% 5% 5% 43.2
2 50V
CERM 2 50V
CERM 1/16W 1 2 NEC_USB_DAP 25 37 39
M5 402 402 MF
39 37 24 18 12 9 PCI_AD<0> 1%
AD0 2 402 1/16W
VDD_PCI
VDD
AVDD
39 37 24 18 12 9 PCI_AD<1>
P5 AD1 XT1/SCLK L9 NEC_XT1 MF
N5 402
XT2 P8
39 37 24 18 12 9 PCI_AD<2> AD2 NEC_XT2
39 37 24 18 12 9 PCI_AD<3>
P4 AD3
39 37 24 18 12 9 PCI_AD<4>
N4 AD4 RSDM1 M14 NEC_USB_RSDM1
39 37 24 18 12 9 PCI_AD<5>
M3 AD5 DM1 M13 (NEC_USB_DAM)
CRITICAL
39 37 24 18 12 9 PCI_AD<6>
N3 AD6 DP1 L14 (NEC_USB_DAP)
39 37 24 18 12 9 PCI_AD<7>
M1 AD7 U17 RSDP1 K13 NEC_USB_RSDP1
39 37 24 18 12 9 PCI_AD<8>
L2
L1
AD8 NEC_uPD720101_USB2
FBGA K14 NEC_USB_RSDM2
39 37 24 18 12 9 PCI_AD<9> AD9 RSDM2
39 37 24 18 12 9 PCI_AD<10>
K2 AD10 DM2 K12 (NEC_USB_DBM) R609
43.2
39 37 24 18 12 9 PCI_AD<11>
L3 AD11 DP2 J14 (NEC_USB_DBP) 1 2 NEC_USB_DBM 25 37 39
39 37 24 18 12 9 PCI_AD<12>
K1 AD12 RSDP2 J12 NEC_USB_RSDP2 1%
K3 1/16W
39 37 24 18 12 9 PCI_AD<13> AD13 MF
J2 402
39 37 24 18 12 9 PCI_AD<14> AD14 RSDM3 H11 NC
39 37 24 18 12 9 PCI_AD<15>
J1 AD15 DM3 G11 Low/Full/High Speed (External)
39 37 24 18 12 9 PCI_AD<16>
F2 AD16 DP3 G13
39 37 24 18 12 9 PCI_AD<17>
E3 AD17 RSDP3 G14 NC R610
43.2
C 39 37 24 18 12 9 PCI_AD<18>
39 37 24 18 12 9 PCI_AD<19>
E1
D3
AD18
RSDM4 F12 NC
1
1%
2 NEC_USB_DBP 25 37 39 C
AD19 1/16W
39 37 24 18 12 9 PCI_AD<20>
D1 AD20 DM4 F14 MF
402
39 37 24 18 12 PCI_AD<21>
D2 AD21 DP4 E12
39 37 24 18 12 PCI_AD<22>
C2 AD22 RSDP4 E14 NC
39 37 24 18 12 PCI_AD<23>
C1 AD23
39 37 24 18 12 9 PCI_AD<24>
B4 AD24 RSDM5 E13 NC
39 37 24 18 12 9 PCI_AD<25>
A4 AD25 DM5 D14
39 37 24 18 12 9 PCI_AD<26>
B5 AD26 DP5 C13
39 37 24 18 12 9 PCI_AD<27> (PCI_AD<27>) C4 AD27 RSDP5 C14 NC +3V_MAIN
PCI_AD<28> A5 R614
39 37 24 18 12 9
C5
AD28
9.09K Tie to GND (NEC_AVSS_F) at ball N11
39 37 24 18 12 9 PCI_AD<29> AD29 RREF P11 NEC_RREF 1 2 NEC_AVSS_F 17
39 37 24 18 12 9 PCI_AD<30>
B6 AD30 1%
1/16W 7 8
39 37 24 18 12 9 PCI_AD<31>
A6 AD31 MF
402 +3V_NEC_VDD 17 38 RP43 RP43
PCI_CBE<0> M2 CBE0
RP43 10K 10K
37 24 18 12
10K 5%
1/16W
5%
1/16W
R6361 37 24 18 12 PCI_CBE<1>
J3 CBE1 OCI1 B12 NEC_LUSB_OCI 17
3 6
R607 SM1 SM1
22 37 24 18 12 PCI_CBE<2>
F1 CBE2 OCI2 B11 NEC_RUSB_OCI 17 5% 2 1
5%
1/16W 12 PCI_CBE<3>
C3 CBE3 OCI3 B10 NEC_OCI<3> RP43 1/16W
SM1 NEC_LUSB_OCI 1
0 2 NEC_LUSB_OCI_UF
MF
37 24 18
A10 4
10K 5
17 25 39
402 2 OCI4 NEC_OCI<4> 5%

1/16W
PCI_PAR J4 PAR OCI5 B9 NEC_OCI<5> 5% MF
39 37 24 18 12
PCI_FRAME_L F3 1/16W R606 402 R608

39 37 24 18 12 FRAME SM1
1
10K 2 NEC_RUSB_OCI 1
0 2 NEC_RUSB_OCI_UF
39 37 24 18 12 PCI_IRDY_L F4 IRDY PPON1 C12OUT NEC_LUSB_PPON 25 39
17 25 39
G1 A11OUT 5% 5%
12 PCI_TRDY_L TRDY PPON2 NEC_RUSB_PPON
39 37 24 18
12 PCI_STOP_L
G3 C11OUT NEC_PPON3_TP
25 39
R615 1/16W
MF
1/16W
MF
39 37 24 18 STOP PPON3 1K
2 1
402 402
NEC_IDSEL B3 IDSEL PPON4 C10OUT NEC_PPON4_TP NO STUFF NO STUFF
A9 OUT 5% 1 C743 1 C744 B
B 39 37 24 18 12 PCI_DEVSEL_L
12 NEC_PCI_REQ_L
G2
C6
DEVSEL
REQ
PPON5 NEC_PPON5_TP 1/16W
MF
R632
0.1uF
20%
0.1uF
20%
Series Rpaks required to RP45 12 NEC_PCI_GNT_L
D6 GNT
NC1 P6 NEC_NC<1> 402
1K 2 10V
CERM 2 10V
CERM
facilitate NAND-tree testing 47 H2 NC2 M6 NEC_NC<2> 2 1 402 402
5% 18 PCI_PERR_L PERR
1 8 OD
H1 5%
18 PCI_SERR_L SERR 1/16W
OD MF
14 NEC_PCI_INT_L 2 7 NEC_PCI_INTA_L C7 INTA 402
OD
3 6 NEC_PCI_INTB_L B7 INTB NEC documentation indicates that NCs must be tied high.
OD
4 5 NEC_PCI_INTC_L A7 INTC
IPD
1/16W 35 12 CLK33M_NEC
A8 PCLK NTEST1 M8 NC
SM1
IPD
17 NEC_IO_RESET_L B8 VBBRST SMC M7 NC
NEC_CRUN_L N6 CRUN
OD
17 NEC_PME_L
D9 PME
R6171 17 NEC_MAIN_RESET_L
C9 VCCRST TEB N7
IPD
NC
4.7K NEC_SMI_L_TP
OD
L6 SMI AMC P7
IPD
NEC_AMC_TP
5%
1/16W
MF IPD
402 2 TEST L8 NC
17 NEC_LEGC L7 LEGC
NANDTEST M10 NEC_NANDTESTEN_TP

M9
RP44 SRCLK NC
N11 AVSS(R)
47 SRDTA N9 NEC_NANDTESTOUT_TP
5% SRMOD P9 IPD NC
IO_RESET_L 1 8 NEC_IO_RESET_L 17 VSS
29 26 23
AVSS
39 29 24 14 PMU_PME_L 2 7 NEC_PME_L 17
USB 2.0
P10
N14
H14
B14
N13
B13
M11
L12
H12
D12
J11
F11
P13
M12
B1
N1
A2
B2
N2
G4
D8
39 29 24 19 18 14 MAIN_RESET_L 3 6 NEC_MAIN_RESET_L 17 R798

0
A 17 NEC_LEGC 4
1/16W
5
17 NEC_AVSS_F 1
5%
2
A
SM1 1/16W
MF
603 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
APPLE COMPUTER INC.

D 051-6653 C
SCALE SHT OF
NONE 17 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+3V_SLEEP
1
R756
0
5%
1/16W
MF
2 603
PCI1510 PULL-UPS 38 +3V_SLEEP_PCCARD

+3V_MAIN
1 C60 1 C776 1 C789 1 C791 1 C784
10uF
20%
10uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
+3V_SLEEP_PCCARD
2 6.3V
CERM 2 6.3V
CERM
6.3V
2 CERM 2 6.3V
CERM 2 6.3V
CERM
+5V_MAIN MAKE SURE VCC AND VPP ARE WIDE PLANE/TRACES
D
805 805 402 402 402
U4 TO MINIMIZE INDUCTANCE! D
R718 34
SLEEP_L_LS5 TPS2211
26 20
NC 9 10 +VPP_CBUS_SW
10K 33 32 V_12 SSOI AVPP 18 38
1 2 PCI_PERR_L 5
5%
17 18
1 C782 1 C783 1 C778 1 C775 6
V_5_1
11 +VCC_CBUS_SW
R714 1/16W 0.22uF 0.22uF 0.22uF 0.22uF R7261 V_5_2 AVCC0 18 38
MF 20% 20% 20% 20% 3 12

10K 2 402 6.3V
2 CERM 2 6.3V 2 6.3V 2 6.3V
CERM 0 V_3_1 AVCC1
1 PCI_SERR_L CERM CERM 5% 4 13
17 18
402 402 402 402 1/16W V_3_2 AVCC2
5% MF
1/16W
MF R722 R7211 402 2 1
VCCD0 C40 1 1 C37
402 10K 10K 2 0.1uF 0.1uF
1 2 CBUS_SUSPEND_PU 18 5% VCCD1 20%
10V
20%
1/16W 15
VPPD0 CERM 2 2 10V
CERM
5% MF 402 402
14
1/16W 402 2
MF +2_5V_SLEEP VPPD1
402 TPS2211_SHTDWN_L 16
A7 C13 D5 E1 M1 N7 N11
SHTDWN
7 8 NC
GND OC
1 C786 VCC
1 C787 0.22uF 0.1UF ARE USED TO INCREASE ESD DISCHARGES OF UP TO 10KV
4.7uF 20% NC H10 CLK_48_RSVD/NC CRITICAL CLAMP FOR PC-CARD VCCCB B11
20%
2 6.3V 2 6.3V CLAMP FOR PCI VCCP L3
CERM
805
CERM
402 PCI1510_VR_EN_L D4 VR_EN* U8
L8 VR_PORT PCI1510GGU
BGA
VCCD0* N13 CBUS_VCCD0_L
VCCD1* L12 CBUS_VCCD1_L
39 37 24 17 12 9 PCI_AD<0> N8 AD0
39 37 24 17
39 37 24 17
12 9 PCI_AD<1>
12 9 PCI_AD<2>
M7
L7
AD1
AD2
VPPD0
VPPD1
K9
M11
CBUS_VPPD0
CBUS_VPPD1
PC CARD/CARDBUS CONNECTOR
39 37 24 17 12 9 PCI_AD<3> N6 AD3
CD1*/CCD1* L13 CBUS_DET_1_L 18 39
39 37 24 17 12 9 PCI_AD<4>
K4 AD4 CRITICAL
CD2*/CCD2* B5 CBUS_DET_2_L 18 39
39 37 24 17 12 9 PCI_AD<5> M6 AD5
IORD*/CAD13 F12 CBUS_IORD_L 18 J5
39 37 24 17 12 9 PCI_AD<6>
L6 AD6 C11
QT500806-L111
C 39 37 24 17
39 37 24 17
12 9 PCI_AD<7>
12 9 PCI_AD<8>
N5
N4
AD7
AD8
IOWR*/CAD15
OE*/CAD11 G10
CBUS_IOWR_L 18
CBUS_OE_L 18
M-ST-SM1
84 81 C
CE1*/CC/BE0* H13 CBUS_CE1_L 18
39 37 24 17 12 9 PCI_AD<9>
M2 AD9
VS1*/CVS1 B2 CBUS_VS1 18
2 1 CBUS_DATA<3> 18
39 37 24 17 12 9 PCI_AD<10> M5 AD10 VS2*/CVS2 A9 CBUS_VS2 18 39 18 CBUS_DET_1_L 4 3 CBUS_DATA<4> 18
39 37 24 17 12 9 PCI_AD<11> L4 AD11 WE*/CGNT* D13 CBUS_WE_L 18 18 CBUS_DATA<11> 6 5 CBUS_DATA<5> 18
39 37 24 17 12 9 PCI_AD<12> N3 AD12 RDY/IREQ*/CINT* A6 CBUS_READY 18 18 CBUS_DATA<12>
8 7 CBUS_DATA<6> 18
39 37 24 17 12 9 PCI_AD<13> K5 AD13 RESET/CRST* D8 CBUS_RESET_L 18 18 CBUS_DATA<13>
10 9
39 37 24 17 12 9 PCI_AD<14> L5 AD14 REG*/CC/BE3* A8 CBUS_REG_L 18 12 11 CBUS_DATA<7> 18
39 37 24 17 12 9 PCI_AD<15>
M4 AD15 BVD1/CSTSCHG/STSCHG*/RI* C6 CBUS_BVD1_L 18 18 CBUS_DATA<14> 14 13 CBUS_CE1_L 18
39 37 24 17 12 9 PCI_AD<16> J4 AD16 BVD2/SPKR*/CAUDIO D6 CBUS_BVD2_L 18 18 CBUS_DATA<15> 16 15 CBUS_ADDR<10> 18
39 37 24 17 12 9 PCI_AD<17>
H1 AD17 INTEGRATED PULL-UP WP/IOIS16*/CCLKRUN* A5 CBUS_WP_L 18 18 CBUS_CE2_L 18 17 CBUS_OE_L 18
39 37 24 17 12 9 PCI_AD<18>
H3 AD18 CE2/CAD10* G13 CBUS_CE2_L 18 18 CBUS_VS1
20 19
PCI_AD<19> (PCI_AD<19>) H2
39 37 24 17 12 9 AD19 INPACK/CREQ* B8 CBUS_INPACK_L 18 22 21 CBUS_ADDR<11> 18
39 37 24 17 12 9 PCI_AD<20> G2 AD20 WAIT/CSERR* B6 CBUS_WAIT_L 18 18 CBUS_IORD_L 24 23 CBUS_ADDR<9> 18
39 37 24 17 12 PCI_AD<21> G4 AD21 18 CBUS_IOWR_L 26 25 CBUS_ADDR<8> 18
39 37 24 17 12 PCI_AD<22> F1 AD22 A0/CAD26 C7 CBUS_ADDR<0> 18
18 CBUS_ADDR<17> 28 27 CBUS_ADDR<13> 18
39 37 24 17 12 PCI_AD<23>
C3 AD23 A1/CAD25 D7 CBUS_ADDR<1> 18
18 CBUS_ADDR<18>
30 29
39 37 24 17 12 9 PCI_AD<24> F3 AD24 A2/CAD24 B7 CBUS_ADDR<2> 18
32 31 CBUS_ADDR<14> 18
39 37 24 17 12 9 PCI_AD<25> E2 AD25 A3/CAD23 D10 CBUS_ADDR<3> 18
CBUS_ADDR<19>
18 34 33 CBUS_WE_L 18
39 37 24 17 12 9 PCI_AD<26>
F4 AD26 A4/CAD22 B12 CBUS_ADDR<4> 18
18 CBUS_ADDR<20>
36 35 CBUS_READY 18
39 37 24 17 12 9 PCI_AD<27> B1 AD27 A5/CAD21 C8 CBUS_ADDR<5> 18
CBUS_ADDR<21> 38 37 +VCC_CBUS_SW 18 38
39 37 24 17 12 9 PCI_AD<28> D2 AD28 A6/CAD20 C9 CBUS_ADDR<6> 18 TI REFERENCE SCHEMATIC DID NOT HAVE BULK ON +VCC_CBUS_SW
38 18 +VCC_CBUS_SW 40 39
39 37 24 17 12 9 PCI_AD<29> E4 AD29 A7/CAD18 A12 CBUS_ADDR<7> 18
42 41 +VPP_CBUS_SW 18 38
39 37 24 17 12 9 PCI_AD<30> D3 AD30 A8/CC/BE1* E11 CBUS_ADDR<8> 18
+VPP_CBUS_SW 44 43 CBUS_ADDR<16> 18
R7191 39 37 24 17 12 9 PCI_AD<31>
E3 AD31 A9/CAD14 F11 CBUS_ADDR<9> 18 1 C796 1 C800 38 18
18 CBUS_ADDR<22>
46 45 CBUS_ADDR<15> 18
22 A10/CAD9 G11 CBUS_ADDR<10> 18 2.2uF
20% 20%
2.2uF
5% 37 24 17 12 PCI_CBE<0> K6 C/BE0* 18 CBUS_ADDR<23>
48 47 CBUS_ADDR<12> 18
B 1/16W
MF
402 2
37 24 17 12 PCI_CBE<1> M3
J2
C/BE1*
A11/CAD12 G12
A12/CC/BE2* D9
CBUS_ADDR<11> 18
CBUS_ADDR<12> 18
2 10V
CERM
805
2 10V
CERM
805 18 CBUS_ADDR<24> 50
52
49
51
B
37 24 17 12 PCI_CBE<2> C/BE2* CBUS_ADDR<7> 18
A1 A13/CPAR E12 CBUS_ADDR<13> 18
54 53
37 24 17 12 PCI_CBE<3> C/BE3* 18 CBUS_ADDR<25> CBUS_ADDR<6> 18
A14/CPERR* D12 CBUS_ADDR<14> 18
39 37 24 17 12 PCI_PAR N1 PAR A15/CIRDY* C10 CBUS_ADDR<15> 18 R724 18 CBUS_VS2 56 55 CBUS_ADDR<5> 18
K1
47 18 CBUS_RESET_L
58 57 CBUS_ADDR<4> 18
39 37 24 17 12 PCI_IRDY_L IRDY A16/CCLK B13 CBUS_ADDR_16_UF 1 2 CBUS_ADDR<16> 18
60 59
18 CBUS_WAIT_L
18 17 PCI_SERR_L L2 SERR A17/CAD16 F10 CBUS_ADDR<17> 18 5%
1/16W 62 61 CBUS_ADDR<3> 18
CBUS_PCI_IDSEL F2 IDSEL A18/RSVD E13 CBUS_ADDR<18> 18 MF
402 18 CBUS_INPACK_L 64 63 CBUS_ADDR<2> 18
18 17 PCI_PERR_L K3 PERR A19/CBLOCK* A13 CBUS_ADDR<19> 18
18 CBUS_REG_L
66 65 CBUS_ADDR<1> 18
39 37 24 17 12 PCI_FRAME_L
J1 FRAME A20/CSTOP* E10 CBUS_ADDR<20> 18
18 CBUS_BVD2_L
68 67 CBUS_ADDR<0> 18
39 37 24 17 12 PCI_STOP_L L1 STOP A21/CDEVSEL* D11 CBUS_ADDR<21> 18
18 CBUS_BVD1_L
70 69
39 37 24 17 12 PCI_TRDY_L J3 TRDY A22/CTRDY* C12 CBUS_ADDR<22> 18
72 71
R723
47 39 37 24 17 12 PCI_DEVSEL_L
K2 DEVSEL A23/CFRAME* A10 CBUS_ADDR<23> 18
CBUS_DATA<8> 74 73
CBUS_DATA<0>
CBUS_DATA<1>
18
18 18
39 29 24 19 17 14 MAIN_RESET_L 1 2 CBUS_PCI_RESET_LG3 PRST A24/CAD17 B10 CBUS_ADDR<24> 18
76 75
18 CBUS_DATA<9> CBUS_DATA<2> 18
5% 12 CBUS_PCI_REQ_L C2 REQ A25/CAD19 B9 CBUS_ADDR<25> 18
1/16W 18 CBUS_DATA<10> 78 77 CBUS_WP_L 18
MF 12 CBUS_PCI_GNT_L
C1 GNT
402 D0/CAD27 A4 CBUS_DATA<0> 18 39 18 CBUS_DET_2_L
80 79
35 12 CLK33M_CBUS G1 PCLK
D1/CAD29 C4 CBUS_DATA<1> 18
D2/RSVD A3 CBUS_DATA<2> 18 83 82
RP1
10K
NC M9 SPKROUT D3/CAD0 K11 CBUS_DATA<3> 18
5% NC M8 RI_OUT/PME D4/CAD1 K12 CBUS_DATA<4> 18
1/32W N10 SUSPEND D5/CAD3 J13
25V 18 CBUS_SUSPEND_PU CBUS_DATA<5> 18
D6/CAD5 J10 CBUS_DATA<6> 18
5 6 CBUS_MFUNC1_PD 14 CBUS_INT_L K7 MFUNC0 H12
18
N9 D7/CAD7 CBUS_DATA<7> 18
10 4 CBUS_MFUNC2_PD 18 CBUS_MFUNC1_PD MFUNC1 C5
18
D8/CAD28 CBUS_DATA<8> 18
A
7
3
9
CBUS_MFUNC3_PD
CBUS_MFUNC4_PD
CBUS_MFUNC5_PD
18
18
18
18 CBUS_MFUNC2_PD
18 CBUS_MFUNC3_PD
18 CBUS_MFUNC4_PD
L9
K10
M10
MFUNC2
MFUNC3
MFUNC4
D9/CAD30
D10/CAD31
D11/CAD2
B4
B3
M12
CBUS_DATA<9> 18
CBUS_DATA<10> 18
CBUS_DATA<11> 18
CARDBUS A
8 18 CBUS_MFUNC5_PD N12 MFUNC5 NOTICE OF PROPRIETARY PROPERTY
CBUS_MFUNC6_PD 18
D12/CAD4 J11 CBUS_DATA<12> 18
2 18 CBUS_MFUNC6_PD
L10 MFUNC6
D13/CAD6 K13 CBUS_DATA<13> 18 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 J12 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
L11 D14/RSVD CBUS_DATA<14> 18 AGREES TO THE FOLLOWING
GRST H11
SM D15/CAD8 CBUS_DATA<15> 18 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
GND II NOT TO REPRODUCE OR COPY IT
A2 A11 D1 F13 H4 K8 M13 N2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.

D 051-6653 C
18 44
SCALE SHT OF
NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
39 38 20 GPU_VCORE
60-OHM-EMI
1
L22
2 GPU_VCORE_VDDCI 19 38
+3V_SLEEP
EXT_TMDS
L78
SIL1162 DVI-Compliant Transmitter Ext. TMDS source termination
+3V_GPU SI_TMDS_CLK_STM
SM 38 21 20 19 12 400-OHM-EMI EXT_TMDS
1 C476 1 C457 1 C458 1 C490 1 C442 1 C530 1 2 +3V_SI_AVCC EXT_TMDS
+3V_SLEEP EXT_TMDS
R827 C865
0.01uF 0.01uF CRITICAL
300 2 0.1uF
0.01uF
20%
0.01uF
20%
10uF
20%
0.01uF
20% 20% 20% R3231 U47 SM-1 EXT_TMDS
1 C856 C858 C860 1
EXT_TMDS
1
EXT_TMDS
L80 TMDS_CLKP 1 1 2 TMDS_CLKN
2 16V 2 16V 2 6.3V 2 16V 2 16V
CERM 2 16V
CERM 10K 10uF 100pF 100pF 400-OHM-EMI 37 22 19
5%
19 22
37
CERM CERM CERM CERM 402 402 5% RAGE_MOBILITY EXT_TMDS 20% 5% 5% 20%
402 402 805 402 1/16W 1 2 1/16W
MF M11-CSP64 L79 2 6.3V
CERM 2 50V
CERM
50V
2 CERM MF 10V
CERM
402 2 64MB SM-1 402
B26 A17 400-OHM-EMI 805 402 402 NO STUFF NO STUFF
402
BGA +3V_SI_VCC C875 1 1 C877
+1_5V_AGP A26 (2 OF 6) B16 1 2 +3V_SI_PLLVCC
CRITICAL
38 21 20 19 16 15 12
EXT_TMDS EXT_TMDS EXT_TMDS EXT_TMDS EXT_TMDS EXT_TMDS 470pF 470pF
B25 ATI_64MB A16 SM-1
EXT_TMDS 1C855 C857 C859
1 1 1 C861 C862 1 C863
1 10%
50V
10%
2 50V
D
ATI_64MB
U47 M2
P3 CRITICAL R3131
1
R338
20K
A25
C22
B14
A14
1C854
10uF
10uF
20%
6.3V
100pF
5%
50V
100pF
5%
100pF
5%
2 50V
100pF
5%
2 50V
20%
10uF
6.3V EXT_TMDS C864
CERM 2
SI_TMDS_D0_STM
EXT_TMDS 402
CERM
402 D
RAGE_MOBILITY 47 5% 20% 2 CERM 2 CERM 2 50V
CERM CERM CERM 2 CERM
R828
M11-CSP64 A21 U47
RAGE_MOBILITY
1%
1/16W
MF
1/16W
MF
D21
C21
B13
A13
2 6.3V
CERM
805 402 402 402 402
39 37
805
TMDS_DP<0> 1
300 2 0.1uF
1 2 TMDS_DN<0> 19
64MB B19 402 2 2 402 805 19
22
22 37 39
BGA M11-CSP64 D20 D13 5%

(6 OF 6)
M15 64MB PLL NOISE SHOULD BE LESS THAN 100mV PEAK-TO-PEAK 1/16W 20%
AB30 AD31 MF 10V
N15 AGP_AD<31> BGA AD_STB0 N29 AGP_AD_STB<0> C20 C13 CERM
NO 402
37 12 12 37
AB27 (1 OF 6) STUFF NO STUFF
402
P15 AGP_AD<30> AD30 ATI_64MB AD_STB1 W29 AGP_AD_STB<1> D22 D12 NO STUFF EXT_TMDS
37 12 12 37
MAIN_RESET_L R8351 R818
NO STUFF EXT_TMDS EXT_TMDS C871
1 1C873
28
46
40
34
AVCC 22
1
R15 12 AGP_AD<29>
AA29 AD29 AD_STBB0 M28 AGP_AD_STB_L<0> 12 C23 C12 1 1 1
R823 R825 R837
VCC 3
VSS
37
37 10K
EXT_TMDS 4.99K 470pF 470pF
PVCC1
PVCC2
AVCC
VCC
T15 12 AGP_AD<28>
AB28 AD28 AD_STBB1 Y29 AGP_AD_STB_L<1> 12 D23 D10 5% 10K 10K 10K 10% 10%
T12
37
12 AGP_AD<27>
AA30 AD27 AGP_BUSYB AG28 AGP_BUSY_L
37
A27 C10 R832 1/16W 5% 5% 5% 1%
1/16W
50V
CERM 2 2 50V
CERM SI_TMDS_D1_STM
37 12 47
MF 1/16W
402 2 MF
1/16W
MF
1/16W
MF MF 402 402 EXT_TMDS EXT_TMDS
T13 37 12 AGP_AD<26>
AA27 AD26 AGPREF K30 38 12 INT_AGP_VREF B27 D9 1 2
402 2 2 402 2 402 2 402
R829 C866
27 MSEN 48 0.1uF
T14 12 AGP_AD<25>
Y30 K29 GPU_AGP_TEST 5% 20 SI_I2C_CLK SCL/DK1 SI_MSEN
37 AD25 AGPTEST
C412 1 H2 C9 1/16W
MF SI_I2S_DATA 26 TMDS_DP<1> 1
300 2 1 2 TMDS_DN<1>
W16 12 AGP_AD<24>
AA28 AD24 AGP8X_DETB U25 AGP8X_DET_PU 20 SDA/DK0 EXT_TMDS1 39 37 22 19 19 22
V16
37
12 AGP_AD<23>
W30 AD23
0.01uF
20%
H1 B12 402
SI_A2 24 CTL3/A2 R826 5%
37 39
37 16V
CERM 2
J2 A12 NO STUFF
25 330 1/16W 20%
10V
U16 37 12 AGP_AD<22>
W27 AD22 SUS_STAT AJ28 AGP_SUS_STAT_L_PU 402 J1 B11 R833
47
SI_RST_L ISEL/RST* 5%
1/16W
MF
402
NO STUFF
CERM
NO 402
STUFF
T16 12 AGP_AD<21>
V30 AD21 (PLACE C408 CLOSE TO AGPREF PIN) 47 PD* MF
R16
37
12 AGP_AD<20>
V28 AD20
ST0 AF30 AGP_ST<0> 12 1 C408 K4 A11 1 2 SI_PD_L
44 EDGE/HTPLG
402 2 C876 1 1C878
37
ST1 AF28 AGP_ST<1> 12 0.1uF K3 B9 5%
1/16W
SI_HPD TXC+ 33 SI_TMDS_CLKP 19 36 470pF 470pF
R17 12 AGP_AD<19>
V29 AD19 10% 10%
37
ST2 AE29 AGP_ST<2>
20% L4 A9 MF
U58
EXT_TMDS TXC- 32 SI_TMDS_CLKN SI_TMDS_D2_STM50V 2 50V
2 10V
19 36
12 402 GPU_DVOD<0> 18 D0 2 CERM
R18 37 12 AGP_AD<18>
V27 AD18 CERM M3 B8
36 19
402 EXT_TMDSCERM
402
R19 37 12 AGP_AD<17>
U30 AD17 SBA7 AC28 AGP_SBA<7> 12 37
402
L3 A8
36 19 GPU_DVOD<1> 17 D1 SIL1162 TX0+ 36 SI_TMDS_DP<0> EXT_TMDS
R830 C867
37 12 AGP_AD<16>
U28 AD16 SBA6 AB29 AGP_SBA<6> 12 37 VSS VSS 36 19 GPU_DVOD<2> 16 D2 TSSOP TX0- 35 SI_TMDS_DN<0> 19 36 300 0.1uF
M4 C7 15
39
37 22 19 TMDS_DP<2> 1 2 1 2 TMDS_DN<2> 19 22 37 39
R27 AC27 GPU_DVOD<3> D3
12 AGP_AD<15> AGP_SBA<5> 36 19
U6 37 AD15 SBA5 12 37
N2 D7 TX1+ 39 SI_TMDS_DP<1> 19 36
GPU_DVOD<4> 14 D4 5%
AE15 12 AGP_AD<14>
R29 AD14 SBA4 AC30 AGP_SBA<4> 36 19 1/16W 20%
37 12 37
+3V_GPU 12 19 20 21 38 N1 C6 GPU_DVOD<5> 13 TX1- 38 SI_TMDS_DN<1> 19 36 MF 10V
VDDCI F18 37 12 AGP_AD<13>
P28 AD13 SBA3 AD27 AGP_SBA<3> 12 37
36 19 D5 402 CERM
N4 D6 10 NO STUFF 402
NO STUFF
P30 AD30 GPU_DVOD<6> D6 TX2+ 42 SI_TMDS_DP<2> 19 36
P25 37 12 AGP_AD<12>
P27
AD12 SBA2
AE28
AGP_SBA<2> 12 37 1
R335 N3 C4
36 19
GPU_DVOD<7> 9 D7 TX2- 41 SI_TMDS_DN<2> 19 36

1 1 C872 C874
37 12 AGP_AD<11> AD11 SBA1 AGP_SBA<1> 12 37 20K G30 D4
36 19
470pF 470pF
P29 AD29 5% GPU_DVOD<8> 8 D8 10% 10%
12 AGP_AD<10> AGP_SBA<0> 36 19 50V
AD10 SBA0 2 50V
C 38 19 GPU_VCORE_VDDCI
37
37 12 AGP_AD<9>
N28
N30
AD9 RBFB AE30 AGP_RBF_L
12 37
12 37
1/16W
MF
2 402
G28
B30
C3
D3
36 19 GPU_DVOD<9>
GPU_DVOD<10>
7
6
D9
D10
CERM 2
402
CERM
402 EXT_TMDS
C
37 12 AGP_AD<8>
M30
AD8
STP_AGPB AG29 AGP_STP_L D26 A5
36 19
GPU_DVOD<11> 5 D11
RP56
37 12 AGP_AD<7> AD7 AC29 AGP_SB_STB D16 B5
36 19 22
M27 SB_STB 12 37 GPU_DVOD_DE 19 DE 36 19 SI_TMDS_CLKP
1 4 TMDS_CLKP 19
37 12 AGP_AD<6>
M29
AD6
SB_STBS AD28 AGP_SB_STB_L R336
12 37
B15 A4
36 19
GPU_DVO_HSYNC 20 HSYNC (SET TO LOW SWING MODE) 36 19 SI_TMDS_CLKN

2 3 TMDS_CLKN 19
22 37
37 12 AGP_AD<5> AD5 AD24 ATI_RSTB_MSK 1

0 2 D11 B4
36 19
EXT_SWING 30 SI_EXT_SWING_SET
22 37
L28 RSTB_MSK GPU_DVO_VSYNC 21 VSYNC +1_8V_GPU 19 20 21 38 5%

12 AGP_AD<4>
36 19
37 AD4 B10 A2 EXT_TMDS 1/16W
+3V_GPU 5% 12 2
38 21 20 19 12
37 12 AGP_AD<3>
L30 AD3 1/16W 36 19 GPU_DVO_CLKP IDCK+ VREF SI_VREF_IDCK_N 19 EXT_TMDS SM1
RP52
L27 DBI_LO Y25 ATI_DBI_LO_PU MF D5 B2 SI_VREF_IDCK_N 11 IDCK-
1
R838
37 12 AGP_AD<2> AD2 402 19 22
R337 1 DBI_HI Y27 B3 1K
49 THRML
ATI_DBI_HI_PU 38 A1 1
SI_TMDS_DP<0> 4 TMDS_DP<0>
12 AGP_AD<1>
L29
PGND
PGND
AGND
AGND
AGND
20 36 19 19 22 37 39
37 AD1 G3 1%
10K 16
+1_5V_AGP B1
PAD
GND
GND
GND
K28 12 NO STUFF NO STUFF EXT_TMDS 1/16W 2
SI_TMDS_DN<0> 3 TMDS_DN<0>
12 AGP_AD<0>
36 19 19 22 37 39
MAIN_RESET_L IS TOGGLED FOR SLEEP 5% AD0
1/16W
37 15
19
21
E1 E4 R8191 1
R824 R836 1 MF
2 402 5%
MF
AGP_CBE<3> W28 CBEB3 U1 E3 10K 10K 10K Place C879 close 1/16W EXT_TMDS
402 2 to SI pin#2
RP57
29
45
31
43
37
1
23
4
37 12
5% 5% 5% SM1
R309 12 AGP_CBE<2>
U29 CBEB2 V3 F3 1/16W 1/16W 1/16W EXT_TMDS EXT_TMDS
22
MAIN_RESET_L1
47 2
37
12 AGP_CBE<1>
R30 CBEB1 AB1 F4
MF
402 2
MF
2 402
MF
2 402
C879 1 1
R839 SI_TMDS_DP<1>1 4 TMDS_DP<1>
39 29 24 19 18 17 14 37
N27 R325 1 1
R324 AC3
0.1uF
20% 1K 36 19 19 22 37 39
5% 37 12 AGP_CBE<0> CBEB0 H3
10V 1% 36 19 SI_TMDS_DN<1>2 3 TMDS_DN<1> 19 22 37 39
1/16W 47K 47K CERM 2 1/16W
38 21 20 19 12 +3V_GPU MF
402 CLK66M_GPU_AGP AG30 PCICLK
5%
1/16W
5%
1/16W
J30 H4 RP49 RP51 402 MF 5%
35 12
J29 J3 0KEXT_TMDS 0KEXT_TMDS 2 402 EXT_TMDS 1/16W
R3881 37 12 AGP_FRAME_L
U27 FRAMEB
MF
402 2
MF
2 402 H30 J4 5% 5% RP53 SM1
1K 37 12 AGP_IRDY_L
T30 IRDYB 36 20 ATI_DVOD<1>1 8 GPU_DVOD<1> 19 36 36 20 ATI_DVOD<10>1 8 GPU_DVOD<10> 19 36 22
H29 C1 36 19 SI_TMDS_DP<2>1 4 TMDS_DP<2> 19 22 37 39
1% 37 12 AGP_TRDY_L
T28 TRDYB 36 20 ATI_DVOD<0>
2 7 GPU_DVOD<0> 19 36 36 20 ATI_DVOD<11>2 7 GPU_DVOD<11> 19 36
1/16W F30 C2 36 19 SI_TMDS_DN<2>
2 3 TMDS_DN<2> 19 22 37 39
MF 37 12 AGP_STOP_L T27 STOPB 36 20 ATI_DVOD<3>
3 6 GPU_DVOD<3> 19 36 36 20 ATI_DVOD<8> 3 6 GPU_DVOD<8> 19 36
402 2 F29 D1 5%
37 12 AGP_DEVSEL_L
T29 DEVSELB 36 20 ATI_DVOD<2>
4 5 GPU_DVOD<2> 19 36 36 20 ATI_DVOD<9> 4 5 GPU_DVOD<9> 19 36 1/16W
E30 D2 SM1
37 12 AGP_PAR
R28 PAR 1/16W 1/16W INT_TMDS
E29 F1
37 12 AGP_REQ_L
AF29 REQB J28 F2
SM1 SM1 RP58
12 AGP_GNT_L
AF27 GNTB RP50 RP60 0
R3971 37
14 AGP_ATI_INT_L AH29 INTAB

J27 G1 0KEXT_TMDS 0KEXT_TMDS 36 20 GPU_TMDS_CLKN 1 4 TMDS_CLKN 19 22 37
1K H28 G2 5% 5% 36 20 GPU_TMDS_CLKP 2 3 TMDS_CLKP 19 22 37
1% 38
19 GPU_MEM_IO AGP_ATI_RESET_LAH30 RSTB ATI_DVOD<7>1 8 GPU_DVOD<7> 1
ATI_DVO_HSYNC 8 GPU_DVO_HSYNC 19 36
1/16W H27 R1 36 20 19 36 36 20 5%
B MF
402 2
21
12 AGP_WBF_L AE27 WBF F28 R2 36 20 ATI_DVOD<6>2 7 GPU_DVOD<6> 19 36 36 20
2
ATI_DVO_VSYNC 7 GPU_DVO_VSYNC 19 36 INT_TMDS 1/16W
RP54 SM1
B
R3731 AGP_ATI_VREFG AK3 VREFG F27 T1 36 20 ATI_DVOD<5>3 6 GPU_DVOD<5> 19 36 36 20 ATI_DVOD_DE 3 6 GPU_DVOD_DE 19 36
0
1K AGP_ATI_VREF D8 MVREF E28 T2 36 20 ATI_DVOD<4>4 5 GPU_DVOD<4> 19 36 36 20 ATI_DVO_CLKP4 5 GPU_DVO_CLKP 19 36
36 20
1
GPU_TMDS_DN<0> 4 TMDS_DN<0> 19 22 37 39
1% 1/16W 1/16W
1/16W A10 E27 V1 36 20
2
GPU_TMDS_DP<0> 3 TMDS_DP<0> 19 22 37 39
MF C19 SM1 SM1
402 2 C5 D30 V2 5%
P2
PLACE VERF VOLTAGE DIVIDER
CLOSE TO ATI M11 VREF PIN B18
A3
G4
D29
C30
VSS VSS W1
W2 +3V_SLEEP
27M OSC
(PLACE THE OSCILLATOR AND R304 AND R305
1/16WINT_TMDS
SM1
RP59
P4
L16 0
R3651 C516 1 C508 1
A19
E2 C29 T3
FERR-EMI-100-OHM
CLOSE TO ATI PIN AJ29)
36 20 GPU_TMDS_DN<1>1 4 TMDS_DN<1> 19 22 37
1K 0.1uF 10uF U2 A30 T4 36 20 GPU_TMDS_DP<1>2 3 TMDS_DP<1>
39
19 22 37
1% 20% 20% R3 1 2 +3V_ATI_OSC_SLEEP 39
1/16W 10V 6.3V 2 V4 A29 U3 38 5%
MF CERM 2 CERM A18 SM NO STUFF INT_TMDS 1/16W
402 2 402 805
R4
AB2 A28 U4
R304 1 C409 1 1 C401 RP55 SM1
AC4 B28 W3 0.1uF 4.7uF 0
D19 100K CRITICAL 14 20% 20%
P1 VSS VSS B23 D28 W4
SPREAD SPECTRUM SUPPORT 5% VCC
10V
CERM 2
6.3V 36 20 GPU_TMDS_DN<2>
2 CERM 1 4 TMDS_DN<2> 19 22 37 39
K2 C28 Y3 1/16W 402 805 2 3
G29 MF GPU_TMDS_DP<2> TMDS_DP<2> 19 22 37 39
G27
A23 D27 Y4 S0=1;S1=M => -1.5% DOWN-SPREAD 402 2 G1 GPU_SS 5%
B29
K1 C27 Y1 GPU_SS
27MHZ R305 1/16W
SM1
B22 D25 Y2
+3V_SLEEP
L66 1
OSC
SM 8 1
0 2 ATI_CLK27M_OSC_SS 19
+1_8V_GPU C26 ATI_OSC_OE OE OUT 35 ATI_CLK27M_OSC 35
38 21 20 19
L2 C25 AA1 FERR-EMI-100-OHM 5%
C16 1/16W
A15
A22 D24 AA2 1 2 +3V_ATI_SS
38 GND R3151 MF
402
L1 C24 AC1 SM GPU_SS GPU_SS 7 287
C11 1% (PLACE R315 CLOSE TO OSC)
D18 AC2 1 C384 C390
1 1/16W
ATI_MEMIO_LO
1
ATI_MEMIO_HI
1 D+ AC10 GPU_THERM_DP 25
C18 AD1 10uF 0.1uF MF
402 2
R370 R371 D- AC11 GPU_THERM_DM 25
20%
2 6.3V
20%
2 10V
GPU_SS 7 CRITICAL
4.7K 4.7K GPU_MEM_IO 19 21 38 D17
AD2 CERM
805
CERM
402 VDD ATI_CLK27M_IN 20 35
5% 5% E8 AA3
1/16W 1/16W TEST_YCLK C17 U30
A
MF
402 2
MF
2 402
ATI_MEMVMODE0 B7 MEMVMODE0
TEST_MLCK
MEMTEST
J6
C8
(PULL-UP to GPU_MEM_IO)
ATI_MEMTEST
D15
C15
AA4
AB3 NO STUFF GPU_SS
1
SOI
CY25811 R320
162
1%
1
M11 AGP INTERFACE
A
B6 MEMVMODE1 AC22 NC AB4 1 19
1 ATI_CLK27M_OSC_SS XIN/CLKIN 1/16W
ATI_MEMVMODE1 PLLTEST D14 R289 35
R297 NC 8 XOUT SSCLK 5 ATI_SSCLK_UF 35
MF NOTICE OF PROPRIETARY PROPERTY
ATI_MEMIO_HI ATI_MEMIO_LO 1 C14
AD3 0 0 GPU_SS
402 2
R375 1 1
R376 R372 AD4 5%
1/16W
5%
1/16W 1
R285 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
45.3 B17 MF MF NC 6 FRSEL PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
4.7K 4.7K 1% AE3 402 2 2 402 33 AGREES TO THE FOLLOWING
5% 5% FOR 2.5 VDDR1 1/16W AE4 3 5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W 1/16W MF CY25811_S1 S1 1/16W
MF MF MEMVMODE0=1.8V 2 402 4 MF II NOT TO REPRODUCE OR COPY IT
402 2 2 402 MEMVMODE1=GND CY25811_S0 S0 2 402
NO STUFF NO STUFF VSS III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
FOR 1.8 VDDR1 1 1
MEMVMODE0=GND R290 R298 2 ATI_SSCLK_IN 20
MEMVMODE1=1.8V
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
0 0 35 SIZE DRAWING NUMBER REV.

5% 5%
PART NUMBER
TABLE_ALT_ITEM
1/16W
MF
402 2
1/16W
MF
APPLE COMPUTER INC.
D 051-6653 C
197S0318 197S0048 G1 Alt. for Siward Part 2 402
SCALE SHT OF
NONE 19 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ATI_64MB CRITICAL
CRITICAL +1_5V_AGP CRITICAL
Int.TMDS Termination U47
38 21 20 19 16 15 12
L17
RAGE_MOBILITY
Q23 FERR-220-OHM F12
ATI_64MB
U47 G7
TERMINATION NETWORK SHOULD BE CONNECTED AS SHOWN
M11-CSP64
SI3446DV 1 2 +1_5V_GPU_VDD15 (500mA) L6 G8
CMF LINE SHOULD BE ROUTED AS 4MIL SURFACE 1 TSOP 38 RAGE_MOBILITY
TRACE SO THAT IT MAY BE CUT BETWEEN CAPS 64MB 0805 T6 M11-CSP64 G9
GPU_TMDS_CLK_CMF BGA 2
AB6 64MB G10
INT_TMDS INT_TMDS ATI_DVOD<0>
36 19
AJ5 ZV_LCDDATA0
(3 OF 6)
ROMCSB AE5 NC 5 1 C448 1 C443 1 C435 1 C482 1 C411 F17 VDD15 BGA G11
R374 R377 ATI_DVOD<1>
36 19
AK5 ZV_LCDDATA1 6 3 GPU_CORE_OK 20 21
0.01uF
20%
0.01uF
20%
0.01uF
20%
0.01uF
20%
10uF
20%
(5 OF 6)
2
49.9 1 2
49.9
1 GPU_TMDS_CLKN 19 20 36 19 ATI_DVOD<2> AG6 R AK28 22 GPU_R 16V
2 CERM 16V
2 CERM 2 16V 2 16V 6.3V
2 CERM
G25 G12
36 20 19 GPU_TMDS_CLKP ZV_LCDDATA2 4 CERM CERM R25 G13
36 +GPU_VDD15_UF 20 38 402 402 402 402 805
1% 1% 36 19 ATI_DVOD<3>
AH6 ZV_LCDDATA3 G AK27 22 GPU_G
1/16W 1/16W AB25 G14
MF MF 36 19 ATI_DVOD<4>
AJ6 ZV_LCDDATA4
402 402 AK6 B AK26 22 GPU_B 1 C407 AJ3
G15
INT_TMDS INT_TMDS 36 19 ATI_DVOD<5> ZV_LCDDATA5 NO STUFF NO STUFF NO STUFF
1000pF G16
C536 1 1 C522 36 19 ATI_DVOD<6>
AG7 ZV_LCDDATA6
1
R346 1R342 1R341 10% 1 C505 1 C532 1 C529 1 C526 AF25
D 470pF
10%
50V
470pF
10%
2 50V
36 19 ATI_DVOD<7>
AH7
AJ7
ZV_LCDDATA7
VSYNC AG27
V2SYNC AG25 NC
ATI_VSYNC 75
1%
22
75
1%
75
1%
2 25V
X7R
402
0.01uF
20%
0.01uF
20%
0.01uF
20%
0.01uF
20%
AG4
AH4
G17
G18 D
CERM 2 CERM 36 19 ATI_DVOD<8> ZV_LCDDATA8 1/16W
MF
1/16W
MF
1/16W
MF 2 16V 2 16V 2 16V 2 16V G19
402 402 AK7 CERM CERM CERM CERM
36 19 ATI_DVOD<9> ZV_LCDDATA9 HSYNC AG26 ATI_HSYNC 2 402 22 2 402 2 402 402 402 402 402 AF5
G20
36 19 ATI_DVOD<10>
AG8 ZV_LCDDATA10 H2SYNC AG24 NC F6
G21
36 19 ATI_DVOD<11>
AH8 ZV_LCDDATA11 G6
INT_TMDS
R367
GPU_TMDS_D0_CMF
INT_TMDS
R369
38 21 19 +1_8V_GPU
38 21 20 19 12 +3V_GPU
NC AJ8
NC AK8
ZV_LCDDATA12
ZV_LCDDATA13
RSET AK25
R2SET AJ24
ATI_RSET
ATI_R2SET 39 38 20 19 GPU_VCORE GPU VCORE - 1.2V(PUT ALL CAPs BELOW ATI ASIC)
H6
P6
G22
G23
G24
75 75 NC AG9 ZV_LCDDATA14 1 1 AD26
36 20 19 2
GPU_TMDS_DP<0> 1 2 1 GPU_TMDS_DN<0> 19 20 36
NC AH9 ZV_LCDDATA15
R332 R333 V6
H7
1% 1%
INT_TMDS
1
EXT_TMDS
1 Y_G AK23 GPU_Y 715 499 1 C484 1 C485 1 C440 1 C441 1 C445 1 C446 1 C449 1 C434 H8
1/16W
MF
1/16W
MF
R389 R840 NC AJ9 ZV_LCDDATA16
C_R AK24
22
GPU_C 1/16W
1% 1%
1/16W 10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF W6
H23
402 402 10K 10K NC AK9 ZV_LCDDATA17
22
MF MF 20% 20% 20% 20% 20% 20% 20% 20% AC6
5% 5% COMP_B AK22 402 2 2 402 6.3V 6.3V 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 6.3V H24
INT_TMDS INT_TMDS 22 GPU_COMP 2 CERM 2 CERM 2 CERM CERM CERM CERM 2 CERM 2 CERM
C515
1 1 C507 1/16W
MF
1/16W
MF NCAG10 ZV_LCDDATA18 805 805 402 402 402 402 402 402
AD6
J7
1
470pF 470pF 402 2 2 402 NCAH10 ZV_LCDDATA19 R359 1R356 1R360 AE6
J24
10%
50V
10%
50V AJ10
ZV_LCDDATA20_PU ZV_LCDDATA20 75 75 75 F7
CERM 2 2 CERM 1% 1% 1% K7
402 402 NCAK10 ZV_LCDDATA21 DIGON AE13 FP_PWR_EN 1/16W 1/16W 1/16W F10
NCAG11 ZV_LCDDATA22 BLON AF13
22
22 INV_ON_PWM
MF
2 402
MF
2 402
MF
2 402
1 C452 1 C451 1 C494 1 C498 1 C509 1 C510 1 C512 1 C513 AE10
K24
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF L7
NCAH11 ZV_LCDDATA23 20% 20% 20% 20% 20% 20% 20% 20% F11
HPD1 AF11 GPU_HPD 22
6.3V
2 CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
6.3V
2 CERM AE11
L24
ATI_DVO_VSYNC AJ4 ZV_LCDCNTL0 402 402 402 402 402 402 402 402 M7
GPU_TMDS_D1_CMF 36 19
+3V_GPU 12 19 20
F13 VDDC
36 19 ATI_DVO_HSYNC AK4 ZV_LCDCNTL1 21 38 M24
INT_TMDS INT_TMDS 1 F14
R362 R355 36 19 ATI_DVOD_DE
AH5 ZV_LCDCNTL2 R779 AE14
N7
75 75 AG5 10K N24
36 20 19 2
GPU_TMDS_DP<1> 1 2 1 GPU_TMDS_DN<1> 19 20
36
36
19 ATI_DVO_CLKP ZV_LCDCNTL3 5%
1/16W R3661 R3681 1 C524 1 C525 1 C528 1 C531 1 C533 1 C477 1 C486 1 C495 AF14
P7
1% 1% ATI_AGP_FBSKEW<0> AJ2 MF 10K 10K 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF W26
20 GPIO0 20% P24
1/16W 1/16W AK2 2 402 5% 5% 20% 20% 20% 6.3V 20% 20% 20% 20%
MF MF 20 ATI_AGP_FBSKEW<1> GPIO1 AUXWIN AJ27AUXWIN_PU 1/16W
MF
1/16W
MF 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
2 CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
AF15
R7
402
INT_TMDS
402
INT_TMDS R378 20 ATI_X1CLK_SKEW<0>
AK1 GPIO2 402 2 402 2 402 402 402 402 402 402 402 402 AE17
R24
C487
1 1 C497 1
1K 2 AH3 AC25
20 ATI_X1CLK_SKEW<1> GPIO3
470pF 470pF AH2 DDC1DATA AH28 GPU_DVI_DDC_DATA 22
AE18
T7
C 10%
50V
CERM 2
402
10%
2 50V
CERM
402
5%
1/16W
MF
402
20 ATI_BUS_CFG<0>
20 ATI_BUS_CFG<1>
AJ1
GPIO4
GPIO5
DDC1CLK AH27 GPU_DVI_DDC_CLK 22
38 21 20 19 12 +3V_GPU F23
T24
U7
C
20 ATI_BUS_CFG<2>
AF4 GPIO6 DDC2DATA AE12 LVDS_DDC_DATA 22 39
F24
U24
ATI_GPIO7_SPN AH1 GPIO7 DDC2CLK AF12 LVDS_DDC_CLK 22 39
AE24
M10 Power Shut down Sequencing NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF V7
AG3 1 F25
ATI_GPIO8_PD
AF3
GPIO8
DDC3DATA AH26 SI_I2S_DATA 19
R384 1R387 1R386 1R382 1R383 1R385 1R381 M25
V24
GPU_TMDS_D2_CMF ATI_GPIO9_SPN GPIO9 +2_5V_SLEEP 10K 10K 10K 10K 10K 10K 10K
38 21 20 19 12 +3V_GPU
AG2 DDC3CLK AH25 SI_I2C_CLK 19 5% 5% 5% 5% 5% 5% 5% N25
W7
ATI_GPIO10_SPN GPIO10 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W VSS W24
INT_TMDS INT_TMDS NO STUFF MF MF MF MF MF MF MF
R350 R340 R380 1 ATI_GPIO11_SPN AF2 GPIO11 TXOUT_U0N AH18 LVDS_U0N 22 37
DP5 2 402 2 402 2 402 2 402 2 402 2 402 2 402
W25
Y7
2
GPU_TMDS_DP<2> 1
75 2
75 1 GPU_TMDS_DN<2>10K ATI_GPIO12_SPN AG1 GPIO12 TXOUT_U0P AG18 LVDS_U0P 22 37 BAS16TWXW11 XW9 (GPIO0) ATI_AGP_FBSKEW<0> 20
V25
36 20 19 Y24
5% ATI_GPIO13_SPN AF1 GPIO13 TXOUT_U1N AH19 LVDS_U1N SM SOT-363 SM (GPIO1)
1% 1% 1/16W 22 37 ATI_AGP_FBSKEW<1> 20 AA7
1/16W 1/16W AE2 +1_8V_ATI_PVDD1 38 1 6 +2_5V_SLEEP_NECK1
MF MF
MF
402 2 22 HPD_PWR_SNS_EN GPIO14 TXOUT_U1P AG19 LVDS_U1P 38 21
22 37
2 1 2 (GPIO2) ATI_X1CLK_SKEW<0> 20 AA24
402 402 20 GPU_VCORE_CNTL_L AE1 GPIO15 TXOUT_U2N AH20 LVDS_U2N 22 37 (GPIO3)
INT_TMDS INT_TMDS 38 +1_8V_PVDD_NECK
ATI_X1CLK_SKEW<1> 20 AB7
C479
1 1 C469 35 19 ATI_SSCLK_IN
M1 GPIO16 TXOUT_U2P AG20 LVDS_U2P 22 37
DP5 (GPIO4) ATI_BUS_CFG<0> 20 AB24
470pF 470pF TXOUT_U3N AH22 LVDS_U3N_TP(NO ICT TEST)
XW12
BAS16TW +1_5V_AGP_NECK 38 (GPIO5) ATI_BUS_CFG<1> 20 AC7
10% 10%
50V 2 50V ATI_TMDS_DN<0> AJ13 TX0M TXOUT_U3P AG22 LVDS_U3P_TP(NO ICT TEST) SM SOT-363
CERM 2 CERM 37 20
39 38 2 5
(GPIO6) ATI_BUS_CFG<2> 20 AC8
402 402 AK13 19 GPU_VCORE
20 ATI_TMDS_DP<0> TX0P TXCLK_UN AH21 CLKLVDS_UN 1 2
37
AJ14 TXCLK_UP AG21
22 37 20
XW4 NO STUFF
1
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF AC23
INT_TMDS
R765
37 20 ATI_TMDS_DN<1> TX1M CLKLVDS_UP 22 37
38 GPU_VCORE_NECK
SM R393 1R396 1R395 1R391 1R392 1R394 1R390 AC24
0 37 20 ATI_TMDS_DP<1>
AK14 TX1P TXOUT_L0N AK16 LVDS_L0N 22 37 39 1 2 +1_5V_AGP DP5 20 21 38
12 15 10K
5% 5%
10K 10K
5%
10K
5%
10K
5%
10K
5%
10K
5% AD7
36 20 19 21
GPU_TMDS_DN<0> ATI_TMDS_DN<0> 20 37 37 20 ATI_TMDS_DN<2>
AJ15 TX2M TXOUT_L0P AJ16 LVDS_L0P 22 37 39
SM
BAS16TWXW5
SOT-363
16 19
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF AD8
INT_TMDS
5% 20 ATI_TMDS_DP<2>
AK15 TX2P TXOUT_L1N AK17 LVDS_L1N
1/16W R767 37
.
22 37 39
38 20 +GPU_VDD15_UF 1 2 3 4 2 402 2 402 2 402 2 402 2 402 2 402 2 402 AD9
MF 20 ATI_TMDS_CLKN
AJ12 TXCM TXOUT_L1P AJ17 LVDS_L1P
INT_TMDS 20 19 GPU_TMDS_DP<0> 4021
0 2 ATI_TMDS_DP<0> 20 37 37 22 37 39
AD10
AK12 TXOUT_L2N AK18
R760 36
5%
37 20 ATI_TMDS_CLKP TXCP LVDS_L2N 22 37 39
38 +GPU_VDD15_NECK AD11
0 TXOUT_L2P AJ18 LVDS_L2P
ATI_TMDS_DN<1>1/16W
22 37 39
1
GPU_TMDS_DN<1> 2 AD12
20 19
36 INT_TMDS MF20 37 ATI_CLK27M_IN AJ29 XTALIN TXOUT_L3N AK20 LVDS_L3N_TP(NO ICT TEST)
402 35 19
AD13
36
20 19
B
5%
1/16W
MF
4021
GPU_TMDS_DP<1>
5%
1/16W
R762
0 2 ATI_TMDS_DP<1> 20 37
INT_TMDS
0 2
R764
R351
2
1K
5%
NC AJ30 XTALOUT
AH24 TESTEN
1 ATI_TESTEN
TXOUT_L3P AJ20
TXCLK_LN AK19
TXCLK_LP AJ19
LVDS_L3P_TP
CLKLVDS_LN
CLKLVDS_LP
(NO ICT TEST)
22 37 39
22 37 39
+PBUS
GPU VCORE SUPPLY WHEN VCORE_CNTL HIGH => 1.2V
AD14
AD15
AD16
B
MF36 1
GPU_TMDS_DN<2> ATI_TMDS_DN<2> 20 37 1/16W NC AJ26 SSIN SSOUT AJ25 NC AD17
40219
20 MF 1.2V = 0.8V * (1 + R329 / (R328//R330)) AD18
5%INT_TMDS 402
1/16W
MF
R766 B24 VSS VSS A20 WHEN VCORE_CNTL LOW => 1.0V AD19
4021 0 2 ATI_TMDS_DP<2> 20 1.0V = 0.8V * (1 + R329 / R330)
INT_TMDS 20 19 GPU_TMDS_DP<2> B20 VSS VSS B21 AD20
R761
36
5%
37
A24 VSS AD21
1
0 2
1/16W 1
R327 1
R331 1
R326 C706 1 C708 1
20 19
36
GPU_TMDS_CLKN ATI_TMDS_CLKN MF20 37
402 Place all TMDS 10 ohms 1M 1 576K 5 4.7uF 4.7uF AD22
5%INT_TMDS 5% 5% 1% 20% 20%
R3291 AD23
1/16W
MF
R763 close to GPU 1/16W 1/16W 1/16W 25V
CERM 2
25V
CERM 2 4.99K
402 0 MF MF MF
CRITICAL 1206 1206
20 19 GPU_TMDS_CLKP 1 2 ATI_TMDS_CLKP 20 37 2 402 2 603 2 402 1%
1/16W
36
5%
1/16W +5V_MAIN
Q48 MF
402 2
MF 38 1778_VCC 4 SI7860DP GPU_VCORE 19 20 38 39
402 SO-8-PWRPK CRITICAL 39 38 20 1778_VFB
NO STUFF 38 1778_VIN 1 GPU_PWRMSR
C466 D12
3
1 1
R5591 R5561
1
R343 R352 1
4.7UF
4.7uF 1N914
1 2 3 R328
0 63.4K +5V_MAIN 18.2K
1
100K 100K 20% SOT23 38 GPU_VCORE_SW 1%
5% 1% 2 10V
5%
1/16W
5%
1/16W DP7 DP7 1/16W
MF
1/16W
MF
CERM
1206 C431 1
3
L64 1/16W
MF
R3301
MF
402 2
MF
402 2
BAS16TW BAS16TW 2 402 2 402 0.1uF R358 38
2.1uH-11A CRITICAL +5V_MAIN 2 402
20K
C704
1778_BST_RC
SOT-363 SOT-363 1778_GND

21 20 6 1 2 5 SLEEP_L_LS5
20 38
20% 1
2.2 2 SM
1
22uF
1
C705 HIGH_VCORE_DIVD 1%
15 12
19 16
+1_5V_AGP GPU_VCORE_PWR_SEQ 18 26 32 33 34 25V
CERM 2 20%
330uF 1/16W
MF
38
603 5% 20%
1
R357 1/16W 2 10V 2 6.3V 402 2
R5581
3 DP7 100K
9 11 10 MF
603
CERM
1210 TANT
CASE-D4
GPU_PWRMSR
1
GPU_PWRMSR
R361
10K GPU_VCORE_SEQ_L 1 Q51 BAS16TW
SOT-363
5%
1/16W
EXT INT VIN
VCC VCC
C481 1 CRITICAL R7861 C846
0.1uF
1
1.82K
5%
2N3904 MF U32 2 CRITICAL 100K 1%
1/16W
MF
402 2 3 SM
3 4 DCDC_EN 28 32 33
2 402 LTC1778
SSOP
0.1uF
20% D29 C707
330uF
1
C711
330uF
1 5%
1/16W
20%
10V
CERM 2
1/16W
MF
2 1 RUN/SS 25V SM MF 402 2 402
1778_SHDN_L ION 7 38 1778_ION CERM 2 20% 20% 402 2
GPU_VCORE_SEQ 1 Q52 CRITICAL 603 MBRS130LT3 6.3V
TANT
2 6.3V 2
TANT HIGH_VCORE
5 ITH GPU_VCORE_CNTL_RC
2N3904 38 1778_ITH B00ST 16 1778_BST 5 6 7 8 1 CASE-D4 CASE-D4
A SM TG 15
38
1778_TG GPU_VCORE_CNTL
M11 CORE PWR/LVDS/TMDS A
R555 1 2 R3391 38 1778_VRNG 3 VRNG
SW 14
38
CRITICAL GPU_PWRMSR
3
33K 20K Q49 6
Q25
5% 1%
1/16W 38 1778_FCB 4 FCB
IRF7832
R549
10K D
Q25
D
2N7002DW THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1/16W MF
MF 402 2 BG 12 38 1778_BG 4
SO-8 20 1
GPU_VCORE_CNTL_L 2 2N7002DW 5 G
SOT-363 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 2 NO STUFF 21 S
20 GPU_CORE_OK 2 PGOOD NO STUFF 5% 2 SOT-363
G S
38 1778_ITH_RC 1 C465 R344 1R353
1 VFB 8 1778_VFB 39
20 38
C838 1 1/16W
MF 4
220pF 0 0 1 C480 SGND PGND 0.001uF 1 2 3 402 II NOT TO REPRODUCE OR COPY IT

C455 1 5% 5% 5%
0.1uF 6 13 20% NO STUFF 1
470pF 2 25V
CERM
1/16W
MF
1/16W
MF 20%
50V
CERM 2 C712 1
10% 402 OMIT
50V 2 402 2 402 2 10V 402 0.1uF
CERM 2 CERM XW6 20%
38
402
20 1778_GND
402
1
SM
2
10V
CERM 2
D 051-6653 C
SCALE
NONE
SHT
20 44
OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(150mA MAX)
U34
+2_5V_SLEEP
MM1571J
SOT-25A
L20
FERR-220-OHM
GPU PLL - 1.8V +2_5V_SLEEP
(150mA MAX)
U60
1
CRITICAL
5 +1_8V_ATI_PVDD 1 2 +1_8V_GPU_PLL (21mA)
MM1571J
SOT-25A FERR-220-OHM
L75
VIN VOUT 38 21 20 38
CRITICAL
0402 1 5 1 2
C830 1 21 20 GPU_CORE_OK
3 CONT NOISE 4 ATI_PVDD_BYP 1
R787 1 C418 1 C414 1 C413 VIN VOUT 38 +1_8V_ATI_TPVDD +1_8V_GPU_TP_PLL
0 10uF 0.1uF 0.01uF 1

0402
1uF
20%
GND
1 C553 5% 20% 20% 20%
2 16V C833 1 21 20 GPU_CORE_OK 3 CONT NOISE 4 ATI_TPVDD_BYP R788
10V 2 1/16W 2 6.3V
CERM 2 10V
CERM CERM 1uF 0
+2_5V_SLEEP CERM 2 0.01uF MF 402 GND 5%
603 20%
16V 2 402
805 402 20%
10V
CERM 2
2 1 C834 1/16W
MF
2 CERM 0.01uF
L23 402 1_8V_PVDD_STD 20 19 +1_8V_GPU 603 20% 2 402
2 16V
38 21
FERR-220-OHM CERM 1_8V_TPVDD_STD
1 2 (140mA) +2_5V_GPU_A2VDD
1 C552 L19 402
1 C835
21 38
10uF FERR-220-OHM
D 0402 20%
2 6.3V
CERM
1 2 38 +1_8V_GPU_AVDD (AVDD+VDDDI=75mA)
AK29 PVDD
AF23 AVDD0
PVSS AK30
AVSSQ AF22
10uF
20% D
1 C459 1 C460 1 C461 805 0402 AF24 AVDD1 2 6.3V
CERM
38 21 19 GPU_MEM_IO 805
10uF 0.01uF 0.01uF A2VSSQ AJ22
20% 20% 20% 1 C427 1 C453 1 C450 +2_5V_GPU_A2VDD AVSSN0 AE22
2 6.3V 2 16V 2 16V 10uF 0.01uF 0.01uF 38 21 A2VDD0
CERM
805
CERM
402
CERM
402 20% 20% 20% A2VDD1 AVSSN1 AE23 L31
FERR-220-OHM
2 6.3V
CERM 2 16V
CERM 2 16V
CERM 38 21 +1_8V_GPU_AVDDQ A2VDDQ
805 402 402 A2VSSN0 AE19 1 2
21
+1_8V_GPU 38 21 +1_8V_GPU_VDDDI AH23 VDD1DI A2VSSN1 AE20 0805
19
20
38 38 21 20 19 16 15 12 +1_5V_AGP AF20 VDD2DI
L21 VSS1DI AG23
FERR-220-OHM +2_5V_GPU_MCLK VDDRH0 VSS2DI AF19
L18 AGP 4X I/O - 1.5V
38 21
1 2 (2mA) +1_8V_GPU_AVDDQ 21 FERR-10-OHM-500MA VDDRH1

VSSRH0 F20 MEMORY I/O
38
0402 K25
1 2 38 +1_5V_AGP_GPU (20mA) VSSRH1 M6
1 C464 1 C463 SM L25
F5 (1200mA) GPU_MEM_IO_FLT
10uF
20%
0.01uF
20%
1 C438 1 C444 1 C423 1 C424 1 C422 T25
G5
38
2 6.3V 2 16V 0.1uF 0.1uF 0.1uF 0.1uF 10uF Y28

CERM
805
CERM
402
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 6.3V K27
H5 1 C551 1 C421 1 C456 1 C488 1 C517
CERM
402
CERM
402
CERM
402
CERM
402
CERM
805 AA25
J5 10uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
K5 2 6.3V 2 10V 10V
2 CERM 2 10V 2 10V
21
19 +1_8V_GPU K26 CERM CERM CERM CERM
20 L5 805 402 402 402 402
38 L26
L24 M26
M5
FERR-220-OHM N5
1 2 (AVDD+VDDDI=75mA) +1_8V_GPU_VDDDI
1 C439 1 C447 1 C425 1 C417 N26
P5
21 38
0.01uF 0.01uF 0.01uF 0.01uF P26 1 C546 1 C545 1 C544 1 C543 1 C541
0402 20% 20% 20% 20% R5
16V
2 CERM 2 16V
CERM 2 16V
CERM 2 16V
CERM
R26 VDDP
T5
0.1uF
20% 20%
0.1uF 0.1uF
20%
0.1uF
20% 20%
0.1uF
1 C478 1 C462 1 C454 402 402 402 402 T26
U5 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
10uF
20%
0.01uF
20%
0.01uF
20% U26 402 402 402 402 402
V5
2 6.3V
CERM 2 16V
CERM 2 16V
CERM
+2_5V_SLEEP V26
W5
C 805 402 402
L25 MEMORY CORE - 2.5V
Y26
AA26
Y5 C
+2_5V_SLEEP
FERR-220-OHM AA5 1 C436 1 C437 1 C540 1 C547 1 C542
AB26 VDDR1
1 2 38 +2_5V_GPU_MEMCORE (1800mA)
AC26
AB5 0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.01uF
20%
0805 AC5 2 10V 2 10V 2 10V 2 10V 2 16V
L28 1 C470 1 C539 1 C475 1 C419 1 C483 ATI_64MB AD5
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
FERR-220-OHM CRITICAL
1 2
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
10uF
20%
G26
0402
+2_5V_GPU_MCLK 21 38
2 10V
CERM
10V
2 CERM 2 10V
CERM 2 10V
CERM 2 6.3V
CERM
U47 K6
402 402 402 402 805 E5 RAGE_MOBILITY R6
1 C511 1 C527 1 C472 E6 M11-CSP64 Y6
10uF 0.01uF 0.01uF 64MB
20% 20% 20% E12 BGA AA6
6.3V
2 CERM 16V
2 CERM 2 16V E13 (4 OF 6) F8
CERM
805 402 402 1 C471 1 C538 1 C504 1 C420 E18 VDDM F9
0.01uF 0.01uF 0.01uF 0.01uF E19 F15
20% 20% 20% 20%
2 16V 2 16V 2 16V 2 16V E20 F16
CERM CERM CERM CERM
402 402 402 402 E26 F21
F26 F22 +1_8V_GPU 19 20
38 21 20 +1_8V_ATI_PVDD
GPU_MEM_IO E7
H25 1.8V DVO POWER (EXT.TMDS) EXT_TMDS
21 38
38 21 19
J25
L32 H26 L81
+1_5V_SLEEP +1_8V_SLEEP
FERR-220-OHM LVDS PLL - 1.8V E9
J26
FERR-10-OHM-500MA
1 2 38 +1_8V_GPU_PNLPLL (40mA) E10 AF6 +1_8V_GPU_DVO 1 2
0402 E11 AE7 SM
1
R275 R363 1
1 C493 1 C468 E14 VDDR4 AF7 1 C535 C519 C534 1 1 1 C521 R843 INT_TMDS
1
0 0 10uF 0.01uF E15 AE8 10uF 0.1uF 0.1uF 0.1uF
5% 20% 20% 20% 20% 0
5%
1/10W 1/10W 20%
6.3V
20%
16V E16 VDDR1 AF8 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 5% +3V_GPU 12 19 20 21
FF FF 2 CERM 2 CERM 805 402 402 402 1/16W
2 805
805 2
+1_8V_ATI_PVDD
805 402 E17 AE9 MF
2 603
L33
38
38 21 20 FERR-10-OHM-500MA
B +1_5V_AGP 12 15 16 19 20 21 38
+1_8V_GPU 19 20 21 38
L30
E21
E22
AF9
AF10 38 +3V_GPU_FLT 2 1 B
1.5V 1.8V FERR-220-OHM
1 2
MEMORY PLL - 1.8V
38 +1_8V_GPU_MEMPLL 38 21 +1_8V_GPU_TP_PLL
E23
E24
VDDR3 AD25
AE25 1 C550 1 C518 1 C520 1 C430
10uF 0.1uF 0.1uF 0.1uF
SM
0402 E25 AE26 20% 20% 20% 20%

1 C537 1 C523
1 C831 1 C832 AF26 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
10uF 0.01uF 10uF
20% 20%
0.01uF 805 402 402 402
2 6.3V 2 16V
20%
2 6.3V
CERM
805
20%
2 16V
CERM
402
CERM
805
CERM
402 AK21 LPVDD LPVSS AJ21 1 C880 1 C881 1 C426
3.3V IO SUPPLY
(Max Current varies, depends on usage)
AK11 TPVDD TPVSS AJ11
+1_8V_SLEEP +2_5V_SLEEP
A7 MPVDD
0.1uF 0.1uF 0.1uF
+2_5V_SLEEP (20mA) MPVSS A6 20% 20% 20%
2 10V
CERM 2 10V
CERM 2 10V
CERM
ATI_MEMIO_HI L26 AE16 AH16 402 402 402
ATI_MEMIO_LO
R312 1 1
R319 FERR-10-OHM-500MA LVDS - 2.5V LVDDR_18 LVSSR0
1.8V 5%
1/10W
0 0
5%
1/10W
2.5V 1
SM
2 38 +2_5V_GPU_PNLIO (350mA)
AF16
AG16
AF17
LVDDR_18
LVDDR_25
LVSSR1
LVSSR2
AG17
AH17
AF18
EXT_TMDS
+1_8V_GPU 19 20 21 38
FF
805 2
FF
2 805
LVDDR_25 LVSSR3 R842
0
1 C499 1 C500 1 C473 AG12 TXVDDR0 DVOVMODE AH12 ATI_DVOVMODE 1 2
GPU_MEM_IO 19 21 38 10uF 0.01uF 0.01uF AG13 AH13 5%
20% 20% 20% TXVDDR1 TXVSSR1 INT_TMDS
2 6.3V 2 16V 2 16V 1/16W
CERM
805
CERM
402
CERM
402
AG14 TXVDDR2 TXVSSR2 AH14 R8411 MF
402
38 21 20 19 +1_8V_GPU AG15 TXVDDR3 TXVSSR3 AH15 0
5%
1/16W
MF
402 2
L29 LVDS/TMDS - 1.8V

+3V_SLEEP FERR-220-OHM
1 2 38 +1_8V_GPU_PNLIO (180mA)
0402
C514 C492 C496 C489
M11 POWER
A 1
R379
0
1
10uF
20%
1
0.1uF
20%
1
0.1uF
20%
1
0.1uF
20% TABLE_5_HEAD

A
5%
1/10W 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
FF 805 402 402 402 TABLE_5_ITEM

2 805 338S0158 1 IC,ATI,M11-CSP128,GRAPHICTLR,667BGA U47 CRITICAL ATI_128MB PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
+3V_GPU 12 19 20 21 38 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
3.3V
TABLE_ALT_HEAD
1 C491 1 C501 1 C506 PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS: II NOT TO REPRODUCE OR COPY IT
0.1uF
20%
0.01uF
20%
0.01uF
20% TABLE_ALT_ITEM
2 10V
CERM
16V
2 CERM 2 16V
CERM
338S0183 338S0154 ATI_64MB U47 ATI M11 64MB A16 SIZE DRAWING NUMBER REV.
GPU POWER SOURCES - 1.5V, 1.8V, 2.5V & 3.3V

402 402 402
338S0182 338S0158 ATI_128MB U47 ATI M11 128MB A16
TABLE_ALT_ITEM
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
21 44 OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power key detect path when
system is shutdown or asleep..
DDC_CLK is isolated from
VGA SYNC BUFFERS
+3V_MAIN
OMIT
DVI DDC CURRENT LIMIT
EXTERNAL VIDEO (DVI) INTERFACE NV17M DURING SHUTDOWN. WHEN
power key on remote device
is pressed, 5V will be driven
into DDC_CLK. Since host rails
will be low, TP0610 will turn
on, driving SOFT_PWR_ON_L low.
DVI POWER SWITCH
5
74AHC1G32 L38
FERR-60-OHM-0.1A (55mA requirement per DVI spec)
As host rails rise, TP0610
will turn off, as will remote
1 device path into DDC_CLK.
20 ATI_VSYNC SM
4 ATI_VSYNC_BUF
1 2 VGA_VSYNC 22
+5V_SLEEP CRITICAL F2 L42
400-OHM-EMI
+5V_DDC_SLEEP 22 38 39 Isolation will be disabled as well.
DVI_TURN_ON_BASE
SOFT_PWR_ON_L 23 29
2
U40 0402
39
0.5AMP-13.2V Q38 33 39
32 1 2 38 +5V_DDC_SLEEP_UF 1 2 TP0610
SM R473 R460 6
3
SM
SM-1
DVI_DDC_CLK_UF2 3 DVI_TURN_ON2
680 1 DVI_TURN_ON_ILIM 1
10K 2 2 Q35
Isolation required for DVI power switch
39 22
S D MMDT3904
SOT-363
PLACE L1002 & L1003 CLOSE TO DVI CONNECTOR 5% 5%
1/16W 1/16W
+3V_MAIN
CRITICAL
L47 D19
SM
3V LEVEL SHIFTERS G MF
402 R459 1 MF
402
1
D
CRITICAL
J22
90-OHM-300mA
2012H
SYM_VER-1
1 2 DDC_CLK_ISO
+3V_SLEEP
1
330
5%
1/16W
Pulldown prevents
3904 from turning
D
OMIT MF on when DVI monitor
QH1112 1 4 TMDS_DN<2> +5V_DDC_SLEEP 402 2 has active, self-
74AHC1G32
5 L36
FERR-60-OHM-0.1A
F-RT-TH 36 MBR0530 1
R476
39 38 22
powered DDC clock
pullup.
ATI_HSYNC 1 4.7K
20 SM CRITICAL 33 31 R4781 1
R480
2
U39 4 ATI_HSYNC_BUF
1
0402
2 VGA_HSYNC 22 39 L45
90-OHM-300mA CHGND1
2 3 TMDS_DP<2> 19 37 39 4.7K
5%
5%
1/16W
MF 10K +3V_SLEEP
2012H CRITICAL 5 5%
32
39 37 19
2
TMDS_DN<0> 36 3 TMDS_CONN_DN<0>
17 1 TMDS_CONN_DN<2> L46
1/16W
MF 2 402 Q39 1/16W
MF
R479 2N7002DW
36
3 402 2 G
90-OHM-300mA 2 402
TMDS FILTERING 1
TMDS_DP<0> 36 4 TMDS_CONN_DP<0>
18
36
36
9 TMDS_CONN_DN<1>
2012H
2 TMDS_CONN_DP<2> SYM_VER-1 1
SOT-363
100 2 DVI_DDC_CLK3 D S 4 GPU_DVI_DDC_CLK 20
PLACE CLOSE TO CONNECTOR SYM_VER-1

19
36 10 TMDS_CONN_DP<1>
3
1 4 TMDS_DN<1> 39
19
37 5%
1/16W
1 Power key detect path 1
R485
1 C668
0.1uF
1 C654 MF R474 when system is running.
HPD normally driven to 68.1K 20%
402
11 2 3 TMDS_DP<1> 39
19 100pF 10K 3.3V. When power key 1% 2 10V
CERM
2 5% on remote device pressed,1/16W
L37 (TMDS_DN<5>) NC 20 4 NC (TMDS_DN<4>)
37 5%
2 25V
Q39 1/16W
MF
HPD will be driven to 5V. MF
COMPARATOR ENABLED BY NV17MAP
402 2
402
370-OHM
SM
12 NC (TMDS_DN<3>) CERM
201 R477 2N7002DW G
2 402 GPIO.
SOT-363
SYM_VER-1
(TMDS_DP<5>) NC 21 5 NC (TMDS_DP<4>) 100 6 D S 1
HPD_PWR_SW_BASE
37 19 TMDS_CLKP 1 4 TMDS_CONN_CLKP 22 36 39 13 NC (TMDS_DP<3>)
1 2 DVI_DDC_DATA GPU_DVI_DDC_DATA 20 HPD_4V_REF
4
2 U42
22 6 39 22 DVI_DDC_CLK_UF
5%
1/16W LMC7211 R475 3
14
MF 1
R481 SM
1 10K 2 5 Q35
37 19 TMDS_CLKN 2 3 TMDS_CONN_CLKN 22 36 39
(+5V_DDC SLEEP) 1 C655 402
100K R472 1
MMDT3904
TMDS_CONN_CLKP 23 7 39 DVI_DDC_DATA_UF 100pF 5 5% 10K 2 5% SOT-363
39 36 22
15 5% Q40 1/16W 39 22 DVI_HPD_UF 1 DVI_HPD_DIV 3 1/16W
MF 4
2 25V MF
39 36 22 TMDS_CONN_CLKN 24 8 VGA_VSYNC 22 39
CERM
201 R4692N7002DW
SOT-363
G
2 402 1%
1/16W
5 402
ANALOG FILTERING 16 39 22 DVI_HPD_UF 1
100 2 DVI_HPD 3 D S 4 GPU_HPD
MF
402 R4841 HPD_PWR_SW
20
100K
PLACE CLOSE TO CONNECTOR VGA_B C3 C1 VGA_R
5%
1/16WNOTE: Pulldown for DVI_HPD provided by DVI power switch interface R482 1 1%
1/16W 1
39 22
C5B C5A
22 39
MF
402
10K MF R470
1%
1/16W
402 2 330
L50 L49 39 22 VGA_HSYNC C4 C2 VGA_G 22 39 MF
HPD_REF_EN_L
5%
1/16W
0.068uH 0.068uH 402 2 MF
C667 1 1 C653 2 402
C 20 GPU_B
1
SM
2 GPU_B_FILTR 1
SM
2 VGA_B 22 39
34 32 0.01uF
20%
50V
5%
100pF 6 C
35 CERM 2 2 25V
C642 1 1 C641 1
R462 603
CERM
201
D Q40
4.7pF 3.3pF 75 2N7002DW
5% 0.25% 1% 2 SOT-363
50V PLACE NEAR C5A & C5B HPD_PWR_SNS_EN G S
L44 CERM 2
402
L43 2 50V
CERM
1/16W
MF CHGND2 R464
20
0.068uH 0.068uH 402

2 402 0 1
GPU_G 1 2 GPU_G_FILTR 1 2
VGA_G
2 1 R4831
20
SM
22 39
5% 470K
SM 1/16W 5%
MF 1/16W
1 402 MF
C635 1 1 C634 R458 CHGND2 402 2
4.7pF 75
5%
3.3pF
0.25% 1% R463
50V 50V 1/16W 0
L41 CERM 2
402 L40 2 CERM
402
MF
2 402
2 1
20 GPU_R
1
0.068uH
2 GPU_R_FILTR 1
0.068uH
2 VGA_R 22 39
5%
1/16W
MF
402
INVERTER INTERFACE
SM
C632 1
4.7pF
5%
50V
CERM 2
SM
1 C631
3.3pF
0.25%
50V
1
R456
75
1%
1/16W
PLACE NEAR 3, 11 & 19 CHGND1
LCD INTERFACE
LVDS INTERFACE
+PBUS
402
2 CERM
402
MF
2 402
L73
FERR-1K-OHM-EMI
2 39 38 1 +14V_INV
+3V_MAIN CRITICAL
+5V_MAIN SM
LCD POWER SWITCH C548 1 J14 Q76
0.001uF CHGND4 G-501973 +5V_INV_UF_SW
S-VIDEO/COMP OUT INTERFACE R347

38
+3V_LCD_SW 38 20% F-RT-SM
34
FDG6324L
C474
50V
CERM 2
SC70-6
L74
1 402 3 400-OHM-EMI CRITICAL
2200pF L27 1
Place GND shorts at 100K 1 2 4
FERR-250-OHM R7501 4 S2 D2 2 1 2 1 C812 J4
B graphics controller
5%
1/16W
MF 5% 3 6 1 2 +3V_LCD
2
3
100K
5%
1/16W
SM-1 0.001uF
20% 5
SM-2MT
B
XW15 L54 2 402 50V
CERM 5 SM
39 38
(LVDS DDC POWER) 4 MF G2 1 C813 2 50V

CERM
SM FERR-10-OHM-500MA R354 603 402 2 6 10uF 402 1
100K 2
C503 1 NC 5
FP_PWR_EN_L
20%
1 2 38 GPU_TV_GND1 1 2 TV_GND1 38 39 1 2 LCD_PWREN_L 1 6 2 6.3V
CERM 2
SM 5% TSOP
0.001uF
20%
22 20
39
LVDS_DDC_CLK
6 805 3
1/16W 50V LVDS_DDC_DATA 7 39 38 +5V_INV_SW
MF SI3443DV CERM 2
22 20
39 4
C657 1 LCD_DIGON_L 402
Q29 402 37 20 LVDS_L0N 8 D1
Q76
0.01uF
20% 3 CHGND4
39
37 20 LVDS_L0P 9
FDG6324L
1 C815
L53 50V
39
10 FP_PWR_EN 5 G1 0.001uF 6
3.3uH CERM 2
603 D Q28
+3V_SLEEP
LVDS_L1N 11
22 20
S1
SC70-6
L72
400-OHM-EMI
20%
2 50V
CERM
1 2 2N7002 37 20
39
12 1 402
20 GPU_Y 1 SM 37 20 LVDS_L1P 1 2 39 BRIGHT_PWM
22 20 FP_PWR_EN G S 39
0603 13 SM-1 39 INV_GND
+3V_MAIN
C656 1
CRITICAL TV_C 39 2 R543 R544 1 1 C701 1 39 37 20 LVDS_L2N 14
C816 1 1 C19
C663 1
560pF J21 100K 100K 0.001uF
20% 39 37 20 LVDS_L2P 15
0.001uF 0.001uF 1
560pF
10% 10% MINIDIN 5%
1/16W
5%
1/16W 50V 16 20% 20%
50V L57 50V RT-TH CERM 2 50V 50V
CERM 2 CERM 2 MF MF 402 17 CERM 2 2 CERM
402 3.3uH 402
MH11773-WMR8A 402 2 402 2 39 37 20 CLKLVDS_LN
18 C22 1 402 402 L1
GPU_C 1 2 4 3 TV_Y
39 37 20 CLKLVDS_LP
0.1uF FERR-250-OHM
20 39 LVDS_DDC_CLK 20 22 19 20% SM
0603 2 1 39 10V
LVDS_DDC_DATA 20 22 39 LVDS_U0N 20 CERM 2
C661 1 5 TV_COMP
37 20 402 5 NC7S32
560pF
C660 1 39
100K pull-ups are for 37 20 LVDS_U0P 21 20 INV_ON_PWM 1
A SC70 CHGND3 2
560pF 8 9 no-panel case (development) 22 4
10%
50V
CERM 2 L55 10%
50V 10 11 Panel has 2K pull-ups 23 2
U2 Y BRIGHT_PWM_UF
402 3.3uH CERM 2

402 NO STUFF
37 20 LVDS_U1N
LVDS_U1P 24
B INVERTER EXPECTS ACTIVE HIGH SIGNAL
37 20
3
20 GPU_COMP 1 2 1 C702 25
CHGND1 0.001uF
A C664 1
0603
C658 1
20%
50V
CERM 2
37 20
37 20
LVDS_U2N
LVDS_U2P
26
27 VIDEO CONNECTORS
560pF
10%
560pF
10%
402
CLKLVDS_UN
28
29 NOTICE OF PROPRIETARY PROPERTY
A
XW14
50V
CERM 2 L56 50V 2 37 20
R753
402 FERR-10-OHM-500MACERM
402 37 20 CLKLVDS_UP 30
SM
1
0 2
1 2 38 GPU_TV_GND2 1 2 TV_GND2 38 39 CHGND4 AGREES TO THE FOLLOWING
33
SM 5%
C549 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 1/16W

0.001uF MF II NOT TO REPRODUCE OR COPY IT
C659 1 116S1331 2 DISCRETE,RES,33OHM,0402 L36,L38 VGA_BUFFER_RES
TABLE_5_ITEM
2 1
402
0.01uF
20% C819
50V 20% 0.01uF SIZE DRAWING NUMBER REV.
Place GND shorts at CERM 2 50V
graphics controller
603 CERM
402
CHGND4 1
20%
2
APPLE COMPUTER INC.
D 051-6653 C
50V
CHGND1 CERM
603 CHGND3
SCALE
NONE
SHT
22 44
OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LMU/RIGHT SENSOR CONNECTOR +3V_MAIN
SLEEP LED TOP CONTACT ZIF KEYBOARD CONN
CONN,TOP CONTACT ZIF,0.8MM PITCH,30P,SM
1 Apple Part #: 518S0079
R758 +5V_MAIN SMK Part #: CFP0630-0301 CRITICAL
0
5% J11
1/16W
MF
CFP0630
F-RT-SM
2 603 31
38 +3V_MAIN_LMU R6161 R611 1
+3V_MAIN
2.2K 100 39 29 KBD_Y<7> 1
5%
CRITICAL 1/16W
MF
5%
1/16W Q22 39 29 KBD_Y<6> 2
D
D J19
54102
402 2 MF
402 2
2N3906
SM
1
2
(GND)
39 29 KBD_Y<5>
3
4
F-ST-SM SLEEP_LED_L SLEEP_LED_I 29 NUMLOCK_LED_L
1 2 39 29 KBD_Y<4>
5
Q58 39 29 KBD_Y<3>
6
29 26 17 IO_RESET_L 3 4 ST7_SLEEP_LED_H 23 39
R154 2N3906
SM
2
3
39 29 KBD_Y<2>
7
39 13 11 6 INT_I2C_DATA0 5 6 PMU_LID_CLOSED_L 23 29 39
SLEEP_LED_SW_L 1
4.7K2 1 NUMLOCK_LED
7 8 39 29 KBD_Y<1>
8
39 13 11 6 INT_I2C_CLK0 LMU_DETECT 23 39
5% 39 29 KBD_Y<0>
9
9 10 1/16W
MF 10
11 12 3 39 29 23 KBD_X<9>
39 34 32 29 25 SLEEP PMU_SLEEP_LED 23 39
3 402 R3001 39 29 23 KBD_X<8> 11
23 KBD_LED1_OUT 13 14 LUX_ALS_GAIN_SW 23 SLEEP_LED_UF 200
KBD_LED2_OUT 15 16 LUX_ALS_OUT 23
D Q18 +3V_MAIN 5%
1/16W 39 29 23 KBD_X<7>
12
23
17 18 2N7002DW MF 39 29 23 KBD_X<6>
13
5 SOT-363 1 402 2
ST7_SLEEP_LED_H G S 14
39 29 23 KBD_X<5>
39 23
NC 19 20 NC
NOTE: KEEP FERRITE CLOSE TO CAP Q19 39 29 23 KBD_X<4>
15
4 L68 2N3906 2
CRITICAL SM 39 KBD_NUMLOCK_LED 16
400-OHM-EMI 1
SM J8 29 CAPSLOCK_LED_L
1 (GND) 17
SM-2MT R577 39 29 23 KBD_X<3>
18
3 0 19
2 3 5% 39 29 23 KBD_X<2>
1/16W 20
MF 39 29 23 KBD_X<1>
SLEEP_LED 1 CAPSLOCK_LED 2 402
39
39 29 23 KBD_X<0>
21
SLEEP_LED_DGND 2
NO STUFF
R223 1 R6031 39 29 23 KBD_SHIFT_L
22
+3V_PMU +3V_MAIN R228 C766 1

200 0 39 29 23 KBD_OPTION_L
23
2
0 1 470pF
10%
4 5%
1/16W
5%
1/16W 39 29 23 KBD_COMMAND_L 24
50V MF MF 25
23 KBD_CONTROL_L
5% CERM 2 402 2 402 2 39 29
1/16W 603 23 KBD_FUNCTION_L
26
MF 39 29
1 1 402 39 KBD_CAPSLOCK_LED 27
R754 R173 +3V_MAIN
100K 10K 39 KBD_JIS 28
5% 5% 1
C 1/16W 1/16W CRITICAL R7891R138 39 KBD_INTL 29
C
MF
402 2
MF
402 2
U21 0
5%
0
5% 39 29 23 KBD_ID
30
5 74LVC1G125 1/16W 1/16W
39
2 4 MF MF
PMU_SLEEP_LED ST7_SLEEP_LED_H
2 402 2 402 32
23 23 39
3 1 SOT23-5
CHGND5
6 39 23 LMU_DETECT
D Q18 1
2N7002DW R198 100K
2 SOT-363 5%
29 PMU_SLEEP_LED_L G S
1/16W
MF
1 402 2
+3V_PMU
R569
39 29 23 KBD_ID
100K
1 2
5%
1/16W
MF
402
RP42
10K
LEFT LIGHT SENSOR CONNECTOR 5%
1/32W
CRITICAL
J2
TRACKPAD/PWR BTN CONN 39 29 23
39 29 23
KBD_X<0>
KBD_X<1>
1
2
25V
5
10
SM-2MT 39 29 23 KBD_X<2> 3
5 +3V_PMU 4
39 29 23 KBD_X<3>
+5V_SLEEP 6
L8 R163 39 29 23 KBD_X<5>
B
B 39 38 +3V_MAIN
LUX_ALS_GAIN_SW
1
2
400-OHM-EMI CRITICAL 39 38 +3V_HALL_EFFECT 2
22 1
39 29 23 KBD_X<7> 7
8
23
2 1 39 29 23 KBD_X<6>
3 +5V_TPAD_SLEEP 5%
23 LUX_ALS_OUT
SM-1
39 38
J10 1/16W 39 29 23 KBD_X<4> 9
4 1 C199 M-ST-5087
SM
C188 1 MF
402 SM
0.001uF 0.001uF
6 L10
400-OHM-EMI
20%
2 50V
1 10 20%
50V L9
400-OHM-EMI
CERM 23 KBD_LED1_OUT
2 9 KBD_LED2_OUT CERM 2 RP40
402 23 402
29 TPAD_TXD 1 2 39 TPAD_F_TXD 3 8 39 LID_CLOSED_L 1 2 PMU_LID_CLOSED_L 23 29 39
10K
5%
SM-1 39 TPAD_F_RXD 4 7 23 PWR_BUTTON_L SM-1 1/32W
1 C210 5 6 C198 1 25V
L12 0.001uF
20%
0.001uF
20% L11 39 29 23 KBD_CONTROL_L 1 5
400-OHM-EMI 2 50V
CERM
50V
CERM 2 400-OHM-EMI 39 29 23 KBD_SHIFT_L 2 10
402 402
29 TPAD_RXD 1 2 1 2 SOFT_PWR_ON_L 22 29 33 39 39 29 23 KBD_OPTION_L 3
SM-1 SM-1 39 29 23 KBD_FUNCTION_L 4
1 C233 C220 1 NC 6
0.001uF 0.001uF KBD_X<8> 7
20%
2 50V
20%
50V
CERM 2
D9
SOT23
39 29 23
39 29 23 KBD_X<9> 8
CERM 402
402 15V 9
39 29 23 KBD_COMMAND_L
2
Connect caps to pin 5 via trace Connect caps, DZ1 to pin 6 via trace 3 SM
1
NC
DEBUG HELPERS KEYBOARD PULLUPS

NO STUFF
R185
470K
1
5%
2 PWR_BUTTON_L 23 KEYBOARD/TPAD/SLEEP LED
A 1/16W
MF
603
PLACE "POWER BUTTON" IN SILK NEAR RESISTOR
A
NO STUFF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R190
470K
1 2 PMU_RESET_BUTTON_L 29 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5% II NOT TO REPRODUCE OR COPY IT
1/16W PLACE "PMU RESET" IN SILK NEAR RESISTOR
MF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
603
PLACE ON TOP SIDE NEAR FRONT EDGE OF BOARD SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6653 C
23 44
SCALE SHT OF
NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
WIRELESS INTERFACE HARD DRIVE INTERFACE (UATA100)
+3V_SLEEP
+5V_HD_SLEEP 32 38
PLACE SERIES R CLOSE TO INTERPID
+3V_SLEEP 3V_HD_LOGIC 5V_HD_LOGIC
RP19 R5731 1
R570
NO STUFF CRITICAL 33 0 0
5% 5%
R7391 J6 37 13 UIDE_DATA<11> 4 5 HD_DATA<11> 24 37 1/16W
MF
1/16W
MF CRITICAL
10K QT510806-L111 RP18 5% 402 2 2 402 J12 D
D 5%
1/16W
MF
F-ST-SM1
84 81 37 13 UIDE_DATA<3> 2
33 7
1/16W
SM1 HD_DATA<3> 24 37
M-SM
EIDE SERIES TERMINATION 402 2

2 1
5%
1/16W
RP18
33
37 24 HD_RESET_L 1
2
50
49
39 29 19 18 17 14 MAIN_RESET_L SM1 1 8
PLACE TERMINATORS NEAR INTREPID 39 RF_DISABLE_L 4 3 CLK33M_AIRPORT 12 35 39
37 13 UIDE_DATA<1> HD_DATA<1> 24 37
37 24 HD_DATA<7> 3 48 HD_DATA<8> 24 37
NO STUFF NO STUFF
AIRPORT_PCI_REQ_L 6 5
PCI_AD<18> 9 12 17 18 24 37 39
RP18
33
5%
1/16W
SM1
37 24 HD_DATA<6> 4
5
47
46
HD_DATA<9> 24 37
8 7
RP26 C808 1 1 C805PCI_AD<31> AIRPORT_PCI_GNT_L 12 39
37 13 UIDE_DATA<2> 4 5 HD_DATA<2> 24 37
HD_DATA<5> 6 45 HD_DATA<10>
33 100pF
5%
100pF
5%
10 9 PMU_PME_L 14 17 29 39
5% RP18 37 24
7 44
24 37
1 8 12 11 1/16W HD_DATA<4> HD_DATA<11>

37 13 EIDE_DATA<8> EIDE_OPTICAL_DATA<8> 24
39
37 50V
CERM 2 2 50V
CERM
AIRPORT_PCI_INT_L 14 39 2
R737 SM1 3
33 6
37 24
8 43
24 37
UIDE_DATA<0> HD_DATA<0>
RP27 5% 402 402 12 9 PCI_AD<29> 14 13 PCI_AD<30> 9 12 17 18 37 39 22 37 13 24 37
EIDE_DATA<10> 1
33 8
1/16W
SM1 EIDE_OPTICAL_DATA<10>
39 37 18 17
37 18 17 12 9
39
PCI_AD<27> 16 15 5%
1/16W
RP19
33
5%
1/16W
37 24 HD_DATA<3> 9
10
42
41
HD_DATA<12> 24 37
37 13 24 37 39 HD_DATA<2> HD_DATA<13>
PCI_AD<25> 18 17 PCI_AD<28> 9 12 17 18 37 39 MF 3 6 SM1 37 24 24 37
5% RP26 39 37 18 17 12 9
20 19 PCI_AD<26> 9 12 17 18 37 39
1 402 37 13 24 37
11 40
37 13 EIDE_DATA<9>
1/16W
SM1 2
33 7 EIDE_OPTICAL_DATA<9> 24 37 39 37 18 17 12 PCI_CBE<3> 22 21 PCI_AD<24> 9 12 17 18 37 39
5%
1/16W
RP19
33 37 24 HD_DATA<1> 12 39 HD_DATA<14> 24 37
1
RP30 5% 24 23 AIRPORT_IDSEL R196 37 13 UIDE_DATA<5> SM1 2 7 HD_DATA<5> 24 37 37 24 HD_DATA<0> 13 38 HD_DATA<15> 24 37
1/16W 10K 14 37
2
33 7
SM1 39 37 18 17 12 PCI_AD<23> 26 25
1/16W
5% RP19 5%
1/16W 15 36
37 13 EIDE_DATA<11> EIDE_OPTICAL_DATA<11> 24 37 39
39 37 18 17 12 PCI_AD<21> 28 27 PCI_AD<22> 12 17 18 37 39 MF 1
33 8
SM1 37 13 HD_DMARQ HD_DIOW_L 24 37
5% RP24 39 37 18 17 12 9 PCI_AD<19> 30 29 PCI_AD<20> 9 12 17 18 37 39
402 2 37 13 24 37
37 24 HD_DIOR_L 16 35 HD_IOCHRDY 24 37
37 13 EIDE_DATA<12>
1/16W
SM1 2
33 7 EIDE_OPTICAL_DATA<12> 24 37 39
32 31 PCI_PAR 12 17 18 37 39
5%
1/16W
RP21
33
17 34
SM1 2 7 HD_DMACK_L 18 33 HD_INTRQ 13
PCI_AD<17> 34 33 PCI_AD<18> 9 12 17 18 24 37 39 UIDE_DATA<6> HD_DATA<6> 37 24 37
RP30 5% 39 37 18 17 12 9 37 13 24 37
HD_ADDR<1> 19 32 HD_ADDR<2>
EIDE_DATA<14> 3
33 6
1/16W
SM1 EIDE_OPTICAL_DATA<14>
36
38
35
37
PCI_AD<16> 9 12 17 18 37 39 RP21
33
5%
1/16W
37 24
20 31
24 37
37 13 24 37 39
37 18 17 12 PCI_CBE<2> SM1
UIDE_DATA<8> 1 8 HD_DATA<8>
5% RP27 PCI_IRDY_L 40 39 PCI_FRAME_L 12 17 18 37 39
37 13 24 37
37 24 HD_ADDR<0> 21 30 HD_CS1_L 24 37
1/16W
SM1 4
33 5
39 37 18 17 12
42 41 PCI_TRDY_L 12 17 18 37 39
5%
1/16W
RP23 37 24 HD_CS0_L 22 29
44 43 SM1 3
33 6 23 28
AIRPORT_CLKRUN_L PCI_STOP_L 12 17 18 37 39 UIDE_DATA<9> HD_DATA<9>
RP30 5%
1/16W
39
46 45
37 13 24 37
24 27
4
33 5
SM1
48 47
PCI_DEVSEL_L 12 17 18 37 39
RP21 5%
1/16W +HD_LOGIC_SLEEP 25 26
EIDE_DATA<15> EIDE_OPTICAL_DATA<15> PCI_CBE<1> 33 SM1 38
C
37 13
5% RP26
24 37 39 37 18 17 12
39 37 18 17 12 9 PCI_AD<14> 50 49 PCI_AD<15> 9 12 17 18 37 39 37 13 UIDE_DATA<10> 3 6 HD_DATA<10> 24 37 C

1/16W
SM1 3
33 6
52 51 PCI_AD<13> 9 12 17 18 37 39 5%
1/16W
RP23 R5791 1
R578
PCI_AD<12> 54 53 PCI_AD<11> 9 12 17 18 37 39 SM1 33 10K
RP24 5%
39 37 18 17 12 9
37 13 UIDE_DATA<14> 2 7 HD_DATA<14> 24 37 20K 5%
PCI_AD<10> 56 55 5%
EIDE_DATA<1> 3
33 6
1/16W
SM1 EIDE_OPTICAL_DATA<1> 24
39 37 18 17 12 9
ROM_RW_TP_L 58 57 PCI_AD<9> 9 12 17 18 37 39
RP25
33
5%
1/16W
1/16W
MF
1/16W
MF
37 13 37 39 9
4 5 SM1 402 2 2 402
UIDE_ADDR<0> HD_ADDR<0> 24
5% RP24 39 37 18 17 12 9 PCI_AD<8> 60 59 PCI_CBE<0> 12 17 18 37 37 13 37
1/16W
SM1 1
33 8 39 37 18 17 12 9 PCI_AD<7> 62 61 ROM_OE_TP_L 9 5%
1/16W
RP25
64 63 PCI_AD<6> 9 12 17 18 37 39 SM1 2
33 7
37 13 UIDE_CS0_L HD_CS0_L 24 37
RP27 5%
1/16W PCI_AD<5> 66 65
37 13 EIDE_DATA<3> 2
33 7
SM1
EIDE_OPTICAL_DATA<3> 24 37 39
39 37 18 17 12 9
9 ROM_ONBOARD_CS_TP_L 68 67 PCI_AD<4> 9 12 17 18 37 39 RP25

33
5%
1/16W
SM1
PCI_AD<3> 70 69 PCI_AD<2> 9 12 17 18 37 39 UIDE_ADDR<1> 1 8 HD_ADDR<1> 24
5% RP24 39 37 18 17 12 9 37 13 37
ANY SEQUENCING REQUIREMENT BETWEEN
1/16W
SM1 33 72 71 PCI_AD<0> 9 12 17 18 37 39 5% RP23
37 13 EIDE_DATA<6> 4 5 EIDE_OPTICAL_DATA<6> 24 37 39
39 37 18 17 12 9 PCI_AD<1> 74 73
UIDE_DATA<15>
1/16W
SM1 4
33 5 HD_DATA<15>
+5V_HD_SLEEP AND +3V_SLEEP
RP27 5% ROM_CS_TP_L 76 75 NC 37 13 24 37
3
33 6
1/16W
SM1
9
NC 78 77 NC RP21 5%
1/16W
37 13 EIDE_DATA<7> EIDE_OPTICAL_DATA<7> 24 37 39 33
5% RP26 R7471 NC 80 79 37 13 UIDE_DATA<13> 4 5 SM1
HD_DATA<13> 24 37
1/16W 33 10K 5% RP25
SM1 4 5 5% 1/16W
37 13 EIDE_DATA<4> EIDE_OPTICAL_DATA<4> 24 37 39 1/16W
MF
83 82 SM1 3
33 6
RP30 5%
1/16W
402 2
37 13 24 37
37 13 EIDE_DATA<5> 1
33 8
SM1
EIDE_OPTICAL_DATA<5> 24 37 39
RP23
33
5%
1/16W
SM1
UIDE_ADDR<2> 1 8 HD_ADDR<2> 24
5%
1/16W
RP28
33
37 13
5%
37
37 13 EIDE_CS0_L SM1 4 5 EIDE_OPTICAL_CS0_L 24 37 39 OPTICAL DRIVE INTERFACE (EIDE) +5V_SLEEP

1/16W
SM1 R214
33
RP28 5%
1/16W 37 13 UIDE_CS1_L 2 1 HD_CS1_L 24 37
3
33 6 SM1 5%
37 13 EIDE_ADDR<1> EIDE_OPTICAL_ADDR<1> 24 37 39 1/16W
1
RP28 R759 MF
B 37 13 EIDE_ADDR<2>
5%
1/16W
SM1 1
33 8 EIDE_OPTICAL_ADDR<2> 24 37 39
0
5%
402
B
1/10W
FF
RP28 5%
1/16W 2 805
+5V_SLEEP
2
33 7
SM1 38 +5V_SLEEP_OPT PLACE PULLUP RESISTORS CLOSE TO INTREPID
37 13 EIDE_ADDR<0> EIDE_OPTICAL_ADDR<0> 24 37 39
NO STUFF NO STUFF
5% 1 1
1
R234
1/16W
SM1 R541 R540 1R546 +3V_SLEEP
10K 100K 10K 10K

5% CRITICAL 5% 5%
5% 1/16W 1/16W 1/16W
1/16W
MF
MF
402 2
J13 MF MF
M-SM 2 402 2 402
2 402
NC 1 50 EIDE_OPTICAL_RST_L 24 37 39
1
2 49
R2031 R213 R2041
39 37 24 EIDE_OPTICAL_DATA<8> 3 48 EIDE_OPTICAL_DATA<7> 24 37 39 10K 10K 10K
5% 5%
4 47 1/16W 5%
R266 39 37 24 EIDE_OPTICAL_DATA<9> EIDE_OPTICAL_DATA<6> 24 37 39 1/16W
MF MF 1/16W
EIDE_CS1_L 1
33 2 EIDE_OPTICAL_CS1_L
39 37 24 EIDE_OPTICAL_DATA<10>
5 46 EIDE_OPTICAL_DATA<5> 24 37 39 402 2 2 402 MF
402 2
37 13 24 37 39
5%
1/16W R237 7 44 R199
MF
402 82 EIDE_OPTICAL_DATA<12> 8 43 EIDE_OPTICAL_DATA<3> 24 UIDE_RST_L 1
33 2 HD_RESET_L
39 37 24 37 39 37 13 24 37
37 13 EIDE_DMARQ 1 2 EIDE_OPTICAL_DMA_RQ 24 37 39
9 42 EIDE_OPTICAL_DATA<2> 24 37 39 5%
R238
5%
1/16W
MF
1/16W
MF
402
R229
22
EIDE_DMACK_L 1
22 2
402
EIDE_OPTICAL_DMAACK_L 24
11 40 EIDE_OPTICAL_DATA<0> 24 37 39 37 13 UIDE_DMACK_L 1 2 HD_DMACK_L 24 37
37 13 37 39
12 39 5%
5%
1/16W
MF R262 39 37 24 EIDE_OPTICAL_DMA_RQ 13 38 EIDE_OPTICAL_WR_L 24 37 39 R200
22
1/16W
MF
402
EIDE_RD_L
402
1
22 2 EIDE_OPTICAL_READ_L 24
39 37 24 EIDE_OPTICAL_READ_L
14 37 EIDE_OPTICAL_IOCHRDY 24 37 39 37 13 UIDE_DIOR_L 1 2 HD_DIOR_L 24 37
37 13 37 39
39 37 24 EIDE_OPTICAL_DMAACK_L
15 36 EIDE_OPTICAL_INT 24 37 39 5%
R268
5%
1/16W
MF
16 35 EIDE_OPTICAL_ADDR<1> 24 37 39
1/16W
MF
402
R215
22 INTERNAL I/O CONNECTORS
A 37 13 EIDE_WR_L 1
22 2
402
EIDE_OPTICAL_WR_L 24 37 39
39 37 24
39 37
EIDE_OPTICAL_ADDR<2>
24 EIDE_OPTICAL_CS1_L
17
18
34
33
EIDE_OPTICAL_ADDR<0> 24 37
EIDE_OPTICAL_CS0_L 24 37 39
39 37 13 UIDE_DIOW_L 1
5%
2 HD_DIOW_L 24 37

A
5% 1/16W
1/16W
MF R251
82
19 32
1
R542 R216
MF
402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
37 13 EIDE_IOCHRDY
402
1 2 EIDE_OPTICAL_IOCHRDY 24 37 39
R5451 20 31
10K 82 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
5%
20K 21 30
5% 37 13 UIDE_IOCHRDY 1 2 HD_IOCHRDY 24 37
5% 1/16W I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
R217
82
1/16W
MF
1/16W
MF
NC 22 29 NC MF
5%
1/16W II NOT TO REPRODUCE OR COPY IT
1 2
402 402 2 23 28 2 402 1 C284 MF
37 13 EIDE_INT EIDE_OPTICAL_INT 24 37 39 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
5%
24 27
5%
10pF
1/16W
MF R242 25 26
2 50V
CERM
33
37 13 EIDE_RST_L
402
1
5%
2 EIDE_OPTICAL_RST_L 24 37 39
402
APPLE COMPUTER INC.
D 051-6653 C
1/16W
MF
402 IOCHRDY - UATA100 REQUIRES PULL-UP TO 3.3V
SCALE
NONE
SHT
24 44 OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LEFT I/O & AUDIO BOARD (LIO) +5V_MAIN
USB MODEM/SOFT MODEM RIGHT USB BOARD

1
CRITICAL R751 +5V_MAIN +3V_MAIN +5V_MAIN
J3 100K
5% PLACE NEAR CONNECTOR PINS 15 PLACE NEAR CONNECTOR PINS 16
QT500406-L111 1/16W
M-ST-SM1 MF NO STUFF
+5V_MAIN NO STUFF
41 42 2 402 CRITICAL
1 C698 1 C696 1 C689 1 C692 J17
39 25 SND_AMP_MUTE
10uF
20%
0.1uF 10uF 0.1uF QT500166-L010
+3V_MAIN 1 2 20% 20% 20%
Place it near J3 2 6.3V 2 10V 2 6.3V 2 10V M-ST-SM1
D 39 29
39 29
ADAPTER_DET
CHARGE_LED_L
3
5
4
6
Q77
3
D
CERM
805
CERM
402
CERM
805
CERM
402 2 1 D
39 17 NEC_LUSB_PPON 7 8 NEC_USB_DAM 17 37 39
1
C848
150uF 2N7002DW
4
6
3
5
9 10
SOT-363 5
39 17 NEC_LUSB_OCI_UF NEC_USB_DAP 17 37 39 20% S G SND_AMP_MUTE_L 14 8 7
11 12 2 6.3V
TANT +3V_MAIN
SMD-1 4 10 9
BT_USB_DM 13 14 SLEEP
39 37 14
BT_USB_DP 15 16 39 INT_I2S0_SND_SCLK
23 29 32 34 39
25 SND_AMP_MUTE_CTRL
1
R752 +5V_MAIN
39 37 17 NEC_USB_DBM 12 11 NEC_RUSB_OCI_UF 17 39
39 37 14 14
100K +3V_MAIN 39 37 17 NEC_USB_DBP 14 13 NEC_RUSB_PPON 17 39
17 18 INT_I2S0_SND_FROM_ADC 14 6 5%
39 1/16W SOFT_MODEM 16 15
MF
39 35 14 INT_I2S0_SND_MCLK 19
21
20
22
SND_HW_RESET_L
INT_I2C_CLK2
14 39
Q77
2N7002DW
D
2 402 R778 1 1
R530
14 25 39
SOT-363 10K 10K CRITICAL
39 14 INT_I2S0_SND_LRCLK 23 24 INT_I2C_DATA2 14 25 39 S G 2 INT_PU_RESET_L 13 29 5%
1/16W
5%
1/16W
MF
J15
QT500166-L010
39 14 INT_I2S0_SND_TO_DAC 25 26 MF
27 28 1 402 2 2 402 M-ST-SM1
39 14 SND_HP_SENSE_L SND_HP_MUTE_LO 25
29 30 +3V_MAIN_AUD USB_MODEM INT_MOD_DTO 1 2 INT_MOD_SYNC 14
39 14 SND_LIN_SENSE_L SND_AMP_MUTE 25 39
32 38 14
31 32 INT_MOD_CLKOUT 3 4 INT_MOD_DTI 14
+5V_MAIN_AUD
R776 14
5 6 INT_MOD_BITCLK
33 34 32 38
PREVENTS POWER-ON POP AND COMM_SHUTDOWN1 0 14
NO STUFF
35
37
39
36
38
40
GENERATES ACTIVE HIGH SPKR MUTE
+3V_MAIN
14
39
5%
1/16W
MF
402
2
39 25 14
39
14
COMM_SHUTDOWN_PU
COMM_RESET_L
INT_I2C_DATA2
7
9
11
8
10
12
MODEM_USB_DM 14 37 39
MODEM_USB_DP 14 37 39
SERIAL DEBUG INTERFACE
NO STUFF 39 25 14 INT_I2C_CLK2 13 14 COMM_RING_DET_L 14 29 39
+5V_MAIN
1 C818 43 44 C817 1 15 16
0.001uF 0.001uF
20% 20%
50V
2 CERM 50V
CERM 2 1
R768 1
402 402
100K
R769
5% 100K
1/16W 5% NO STUFF
MF 1/16W CRITICAL
MF
C828 1 1 C829 2 402 2 402
USB MODEM I2C ADDR ASSIGNED VIA FLEX CABLE J28
OMIT 0.1uF 0.1uF SND_HP_MUTE_LO M-ST-5087
C 20% 20% 25
C
XW30
1
SM
2 38 AUD_GND
10V
CERM 2
402
2 10V
CERM
402
Q78
2N7002DW
SOT-363
3
D
+3V_MAIN
FAN INTERFACE 39 14
39 14
COMM_TXD_L
COMM_TRXC
1
2
3
SM
10
9
8
COMM_DTR_L
COMM_RTS_L
14 39
14 39
5 4 7
4
S G SND_HP_MUTE
R806
FAN CONTROLLER +3V_SLEEP
39 14 COMM_GPIO_L
5 6
COMM_RXD 14 39
6 1
10 2 ADT7460_VCC
Q78 D 5%
1/16W
2N7002DW MF
SOT-363 2 402
S G SND_HP_MUTE_L 14 39
C849 1 1 C763
1uF 0.1uF 1
1 1
R770 10%
6.3V 2
20%
2 10V
R633 R7491 1
R774R4541 1
R773
SND_AMP_MUTE_CTRL 100K CERM
603
CERM
402
10K
5%
10K 10K 10K 10K
25
5% 5% 5% 5% 5%
PLACE CLOSE TO CPU 1/16W
MF 3
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
MAIN1 PREVENTS POWER-ON POP AND 2 402 VCC 2 402 402 2 2 402 402 2 2 402
+3V_PMU_AVCC
PROPAGATES ACTIVE LOW HP MUTE U53
38 29
THERM1_M_DP 15
37 25
KEEP STUFFING RESISTORS CLOSE TO ADT7460 CONTROLLER ADT7460_VCORE_MON14 +2.5V/ QSOP PWM1/ FAN1_PWM_L 25
5
SMBALERT# XTO 1
3 6 FAN1_TACH R817
ADT7460 TACH1
25 39
INT_I2C_DATA1 16 SDA
39 14 13 100K
1 Q59 39 14 13 INT_I2C_CLK1 1 SCL CRITICAL PWM2/ 5 FAN2_PWM_L +3V_MAIN 5%
1/16W
2N3904 37 25 SMBALERT# MF
SM R703 C868 1 THERM1_DP 13 D1+ TACH2
7 FAN2_TACH 25 39 2 402
2 0
37 25 THERM1_M_DM 37 25 THERM1_M_DP 1 2 THERM1_DP 25 37 1000pF THERM1_DM 12 D1- PWM3/ 8 ADT7460_ADR_ENABLE_L
10% THERM_L_OC 29
5%
1/16W
25V
X7R 2
ADR ENABLE#
11 4
R704
0
MF
402 37 25
402
10
D2+ TACH3 ADT7460_TACH3_TP 1
R808
1 2
D2- 100K
THERM1_M_DM THERM1_DM 25 37 TACH4/ 9 3
PLACE IN BETWEEN 3/5/1.5/2.5V PWR SUPPLY 37 25
ADR SELECT/ ADT7460_THERM_L 25 5%
B MAIN2
5%
1/16W
MF
C869 1 THERM2_DP THERM#
1/16W
MF
2 402
D Q83 B
402 1000pF THERM2_DM GND 2N7002DW
10% 5 SOT-363
25V 2 THERM_INV G S
THERM2_M_DP
37 25
R686
0
X7R
402
2
3 37 25 THERM2_M_DP 1 2 THERM2_DP 25 37
37 25
R8071 4
5%
100K
5%
1 Q46 R687 1/16W
MF
1/16W
MF 6
2N3904 0 402 402 2 1 C850
2
SM
37 25 THERM2_M_DM 1 2 THERM2_DM 25 37
D
Q83 0.1uF
2N7002DW 20%
37 25 THERM2_M_DM 5%
1/16W
MF
402
CPU FAN GPU FAN 25 ADT7460_THERM_L
2 G S
SOT-363 10V
2 CERM
402
+5V_SLEEP +5V_SLEEP +5V_SLEEP 1
PLACE UNDERNEATH UPPER RAM

NO STUFF NO STUFF
ALTERNATE1 1
R771 1
R547CRITICAL 1
R772 CRITICAL
10K 0 J1 10K J18
THERM1_A_DP 5% 5% SM04B-SSR 5%
37 25
1/16W
MF
1/10W M-RT-SM
FF 1/16W SM04B-SSR
5 MF M-RT-SM
3 2 402 2 805 2 402 5
1 Q61 KEEP STUFFING RESISTORS CLOSE TO ADT7460 CONTROLLER +FAN_PWR 1

39 38 25
+FAN_PWR 1
2N3904 39 25 FAN1_TACH 2 39 38 25
2
SM 39 25 FAN2_TACH
2 NO STUFF NO STUFF FAN1_PWM 3
FAN2_PWM 3
37 25 THERM1_A_DM
R701
0
R700
0 6
4
4
37 25 THERM1_A_DP 1 2 THERM1_DP 25 37 6 CPU_THERM_DP 1 2 THERM1_DP 25 37 3
5% 5%
D Q79
2N7002DW
6
D
Q79 6 FAN/MODEM/SOUND/BACKUP BATT.
PLACE CLOSE TO BATTERY CHARGER/VCORE 1/16W NO STUFF 1/16W
C669
A ALTERNATE2
NO STUFF
R702
MF
402 R705
MF
402 25 FAN1_PWM_L 2 G S
SOT-363 1
4.7uF FAN2_PWM_L 5 G S
2N7002DW
SOT-363
1 C814
4.7uF NOTICE OF PROPRIETARY PROPERTY
A
0 0 20% 25
37 25 THERM1_A_DM 1 2 THERM1_DM 25 37 6 CPU_THERM_DM 1 2 THERM1_DM 25 37 1 2 6.3V
CERM
20%
805 4 2 6.3V
CERM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
37 25 THERM2_A_DP 5% 5% NO STUFF
1/16W NO STUFF 1/16W 805 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
3
MF
402 R688 MF
402 R659 AGREES TO THE FOLLOWING
0 GPU_THERM_DP 1
0 2 THERM2_DP 25
THERM2_A_DP 1 2 THERM2_DP 25 19 37
1 Q67 37 25
5%
37
5%
2N3904 NO STUFF 1/16W NO STUFF
1/16W
MF
SM MF 402
2 R689 402 R661 SIZE DRAWING NUMBER REV.
37 25 THERM2_A_DM
37 25 THERM2_A_DM 1
0
5%
2 THERM2_DM 25 37 19 GPU_THERM_DM 1
5%
0 2 THERM2_DM 25 37
APPLE COMPUTER INC.
D 051-6653 C
1/16W 1/16W
MF
402
MF
402
SCALE
NONE
SHT
25 44 OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+3V_MAIN
Ethernet routing priority:
1. Decoupling caps
2. TX SERIES TERMINATION - LOCATE NEAR LINK
3. RX SERIES TERMINATION - LOCATE NEAR PHY
C680 1
10uF
20%
LTC3405_SW 38
NO STUFF 6.3V 2 All differential signals should be close,
1 CERM
R513 805
4
VIN
parallel, matched lengths, with minimum
0 CRITICAL via count, and short if possible
5%
1/16W U45 L60
MF
402 2
LTC3405
SOT23-6
3.3uH Must maintain 50-ohms trace impedance on all
1 3 1 2 MDI pairs and all RJ45 pairs
3405_MODE RUN CRITICAL SW +1_0V_MARVELL 38
D 6 MODE VFB 5
1
R506C675 1
SM1
1
R504 Sandwich each RJ54 pair between chassis grounds D
1
GND 665K 22pF 49.9K
R507 2 1%
1/16W 5% 1%
1/16W
5%
0 MF 50V
CERM 2 MF 1 C674
1/16W 2 402 R2A 402 2 402 10uF
MF R2B 20%
402 2 3405_VFB 2 6.3V
CERM
805
VOUT = 0.8V*(1+R2EQV/R1) 1R503

PLACE ALL SERIES RES CLOSE TO PHY 182K
R423 R2EQV = R2A||R2B 1%
1/16W
MF
0 2 402
35 13 CLKENET_LINK_TX 1 2 35 CLKENET_PHY_TX
R1
5%
1/16W
MF R421 4
TX_CLK CTRL10 51 NC
35 13 CLKENET_LINK_RX
402
1
0 2 35 CLKENET_PHY_RX
5% 2 1
RX_CLK
R445 1/16W
MF 6
0 402
35 13 CLKENET_LINK_GBE_REF 1 2 35 CLKENET_PHY_GBE_REF 22
125CLK 10 1 C594 1 C601 1 C608 1 C619 1 C603 1 C599
5% 15 0.1uF
20%
0.01uF
20%
0.1uF
20%
0.01uF
20%
0.1uF
20%
0.01uF
20%
+2_5V_MAIN
1/16W NO STUFF
MF DVDD 57 2 10V 2 16V 2 10V 2 16V 2 10V 2 16V
402 C851 1 C852 1 13 ENET_PHY_TXD<0>
11 CRITICAL 62
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
10pF 10pF 37 TXD0 1
5%
50V 2
5%
50V 37 13 ENET_PHY_TXD<1>
12
TXD1 U43 67 R442
Keep C851 & C852 Stubs short CERM
402
CERM 2
402 37 13 ENET_PHY_TXD<2>
14
TXD2 88E1111 71 PLACE CAPS (IN ORDER) ON PINS 1, 6, 10/15, 57/62, 67/71, 85 0
5%
13 ENET_PHY_TXD<3>
16 85 1/16W
37 TXD3 BCC MF
13 ENET_PHY_TXD<4>
17 2 603
37
TXD4
13 ENET_PHY_TXD<5>
18 5 38 26 +2_5V_MARVELL
37 TXD5
13 ENET_PHY_TXD<6>
19 21
37 TXD6
C 37 13 ENET_PHY_TXD<7>
20
TXD7
VDDO 88
96
1 C597
0.1uF
1 C612
0.01uF
1 C623
0.1uF
1 C600
0.01uF
1 C598
0.1uF
1 C595
10uF
1 C646
0.1uF
1 C648
0.1uF
1 C645
0.1uF
1 C647
0.1uF
C
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
37 13 ENET_PHY_TX_EN 9
TX_EN 2 10V
CERM 2 16V
CERM 2 10V
CERM 2 16V
CERM 2 10V
CERM 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
13 ENET_PHY_TX_ER
7 52 402 402 402 402 402 805 402 402 402 402
37 TX_ER
VDDOH 66
8 72 PLACE CAPS (IN ORDER) ON PINS 5, 21/26, 48/52, 66/72, 88, 96 PLACE CAPS AT CONNECTOR PINS 5 & 6
35 13 CLKENET_PHY_GTX GTX_CLK CRITICAL
26
FERR-EMI-600-OHM
L35 J23
ENET_LINK_RXD<0> 95 VDDOX 48 38 +2_5V_MARVELL_AVDD MJ-R0016
37 13
RXD0 2 1 F-RT-TH
37 13 ENET_LINK_RXD<1> 92 RXD1 SM
13 ENET_LINK_RXD<2>
93 32
37
13 ENET_LINK_RXD<3>
91
RXD2
35
1 C614 1 C616 1 C618 1 C602 1 C592 PRIMARY
1CT:1CT
37
90
RXD3
36
0.1uF
20%
0.01uF
20%
0.1uF
20%
0.01uF
20%
10uF
20%
13
13 ENET_LINK_RXD<4>
37
RXD4 AVDD 2 10V 16V
2 CERM 10V
2 CERM 16V
2 CERM 6.3V
2 CERM 11 75 OHM
13 ENET_LINK_RXD<5>
89 40 CERM
37 RXD5 402 402 402 402 805
ENET_LINK_RXD<6> 87 45
38 26 +2_5V_MARVELL 37 13
RXD6
13 ENET_LINK_RXD<7>
86 78 PLACE CAPS (IN ORDER) ON PINS 32/35, 36/40, 45 & 78 5 ENET_CTAP
37
RXD7
6 ENET_CTAP 1CT:1CT
ENET_RX_DV 94 29 MDI_P<0> 1 MDI_0+ SECONDARY
37 13 RX_DV MDI0+ 39 37
75 OHM
ENET_RX_ER 3 31 MDI_M<0> 2 MDI_0- J1
37 13 RX_ER MDI0- 39 37
33 MDI_P<1> 3 MDI_1+ J2
MDI1+ 39 37
R431 1 R4301 R4321 37 13 ENET_CRS 84

CRS MDI1- 34 39 37 MDI_M<1> 4 MDI_1- J3
10K 10K 1.5K ENET_COL 83 39 MDI_P<2> 7 MDI_2+ 1CT:1CT J4
5% 5% 5% 37 13 COL MDI2+ 39 37
1/16W 1/16W 1/16W 41 8 MDI_2- J5

MF MF MF MDI2- 39 37 MDI_M<2>
402 2 402 2 402 2 25 42 9 MDI_3+ 75 OHM J6
37 13 ENET_MDC MDC MDI3+ 39 37 MDI_P<3>
24 43 10 MDI_3- J7
R422 37 13 ENET_MDIO MDIO MDI3- 39 37 MDI_M<3>
INT_ENET_RST_L1
1K 2
J8
14
B 5%
1/16W
D15 14 ENET_ENERGY_DET 23 INT-/
LED_LINK10
LED_LINK100
76
74
LED_LINK10
LED_LINK100
R4331
49.9
R4351
49.9
R4371
49.9
R4391
49.9
12
14
1CT:1CT RJ45
CABLE SIDE
B
MF INT+ 1% 1% 1% 1% 75 OHM
402 1N914 73 NC 1/16W 1/16W 1/16W 1/16W
LED_LINK1000 MF MF MF MF
IO_RESET_L 3 1 ENET_RST_L 28 70 NC 402 2 402 2 402 2 402 2 RJ45
29 23 17 RESET LED_DUPLEX CHIP SIDE
69 LED_RX_SPN
SOT23 LED_RX
27 68 NC 1 1 1 1
ENET_COMA COMA LED_TX R434 R436 R438 R440
49.9 49.9 49.9 49.9
1% 1% 1% 1%
3 C611 1 CONFIG0 65 (000) 1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF CHGND1 SHIELD 1000PF, 2000V
D
Q32 2.2uF
20% NC 82 S_IN+ CONFIG1 64 (000) 2 402 2 402 2 402 2 402
2N7002DW 10V
CERM 2 NC 81 S_IN- CONFIG2 63 (111)
AC_IN 5 G S
SOT-363 6 805 61 SEE CONFIG TABLES MDI0_PD MDI1_PD MDI2_PD MDI3_PD
30 29 28 CONFIG3 (110)
(BELOW)
D
Q32 NC 77 CONFIG4 60 (111)
4
2N7002DW NC 75
S_OUT+
CONFIG5 59 (101)
1 C622 1 C613 1 C615 1 C617
2 SOT-363 S_OUT-
58
0.01uF
20% 20%
0.01uF 0.01uF
20%
0.01uF
20%
SLEEP_L_LS5 G S (000)
34 33 32 20 18 CONFIG6 2 16V 2 16V 2 16V 2 16V
NC 79 CERM CERM CERM CERM
1 S_CLK+ 402 402 402 402
NC 80 S_CLK- TDI
44 INT_TDO 13 14
50 JTAG_ASIC_TDO_TP PLACE RESISTORS CLOSE TO PHY
TDO 39
PLACES PHY IN "COMA" MODE WHEN ENET_HSDACP 37 49 JTAG_ASIC_TCK 13

HSDAC+ TCK 39
ASLEEP ON BATTERY (SAVES POWER) ENET_HSDACM 38 46 JTAG_ASIC_TMS 13

HSDAC- TMS 39
47 JTAG_ASIC_TRST_L
TRST 13 39
CLK25M_ENET_XIN
CLK25M_ENET_XOUT
55
54
XTAL1
XTAL2
RSET 30 ENET_RSET MARVELL 88E1111
NO STUFF 56 NC
SEL_OSC
R425 ENET_VSSC 53
VSSC SEL_2.5V 13
1
20K 2
GND 10/100/1000 ETHERNET
A 5%
1/16W 1
NO STUFF NO STUFF 97 A
MF
402 R441 R424 R429 1 1 1
R428 1
R427 NOTICE OF PROPRIETARY PROPERTY
PUT CRYSTAL CIRCUIT CLOSE TO PHY 0 CONFIG DEFINITIONS
5% 49.9 49.9 10K 4.99K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
CRITICAL 1/16W 1% 1% 5% 1% CONFIG INPUTS PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MF 1/16W 1/16W 1/16W 1/16W
Y5 2 402 MF
402 2
MF
402 2
MF MF PIN BIT[2:0] AGREES TO THE FOLLOWING
SM-3 2 402 2 402 VDDO 111 PIN BIT[2] BIT[1] BIT[0] I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1 3 CLK25M_XTAL_IN II NOT TO REPRODUCE OR COPY IT
LED_LINK10 110 CONFIG<0> PHYADR[2] PHYADR[1] PHYADR[0]
25.0000M LED_LINK100 101 CONFIG<1> ENA_PAUSE PHYADR[4] PHYADR[3]
C604 1 C624 1 LED_LINK1000 100 CONFIG<2> ANEG[3] ANEG[2] ANEG[1] SIZE DRAWING NUMBER REV.
27pF 27pF
5%
50V
CERM 2
402
5%
50V
CERM 2
402
LED_DUPLEX
LED_RX
011
010
CONFIG<3> ANEG[0] ENA_XC DIS_125
CONFIG<4> MODE[2] MODE[1] MODE[0] APPLE COMPUTER INC.
D 051-6653 C
LED_TX 001 CONFIG<5> DIS_FC DIS_SLEEP MODE[3]
Y6 LOAD CAPACITANCE IS 16PF VSS 000 CONFIG<6> SEL_BDT INT_POL 75/50 OHM
SCALE
NONE
SHT
26 44OF
8 7 6 5 4 3 .
2 1
8 7 6 5 4 3 2 1
D25 165MA MAX LOAD
SC-59 CRITICAL 38 28 27 +3V_FW 1
38 28 27 +FW_PWR_OR 1 U37
LM2594
CRITICAL
L59 +1_95V_FW_DVDD 27
+5V_SLEEP 3 38 LM2594_IN 7 SM 4 220uH L34 1
R414
38
VIN FB 1 2 400-OHM-EMI 10
8
2 VOUT SM-1 5%
1/16W
SM-3
GND ON/OFF MF 1 C585
SDM20E40C +3V_FW_UF 2
2 603 1 C587 1 C684 2.2uF
6 5 38
38 +1_95V_FW_DVDD_PORT1
0.1uF
20%
0.1uF
20% 20%
C665 2 10V 2 10V 2 10V
1
10uF
2 C670
100uF
1
CERM CERM CERM
805
N20P20%
50V
D16
SM 20%
1 C588 1 C589 402
PHY PINS 72,76
402
2 CERM
MBR0540SMD-3
POLY
10V 2 2.2uF
20%
0.1uF
20%
2320
D 1 2 10V
CERM
805
2 10V
CERM
402 D
PHY PIN 64
R418 +1_95V_FW_PLLVDD 27 38
1
1 2 38 +3V_FW_AVDD_PORT2
1 1
U44 5% C593 R415 R416
PHY PIN 61
VOUT = 1.22*(1+R2/R1)+ IADJ*R2 1/16W 3.3 3.3
LTC1761ES5-BYP IADJ = 30NA AT 25C MF
603
1uF 5% 5%
SOT-23-1 1 2 1/16W 1/16W
SYM_VER2 MF MF
1 IN OUT 5 +1_95V_FW_PLLVDD 27 38 603 2 2 603
20%
CRITICAL 10V
CERM
FWPLL_BYP 3 BYP ADJ 4 R426 603 +1_95V_FW_PLL500VDD 38
R496
1 1
1 2 38 +3V_FW_AVDD_PORT1
GND +1_95V_FW_PLL400VDD 38
FW_PLL_ADJ
C671 1 16.2K 5% C606
PHY PIN 50
2.2uF 1 C610 2 1%
1/16W
1 C609 1/16W
MF 1uF
20% 0.01uF MF 10uF
10V
CERM 2 20% 2 402 20% 603 1 2 C586 C678
805 2 16V 2 6.3V
CERM 1uF 1uF
CERM R2 805 20% 1 2 1 2
402 10V
R420
1
CERM
603 20% 20% +1_95V_FW_DVDD 27
PHY PIN 25
PHY PIN 28
R495 1 2 38 +3V_FW_AVDD_PORT0 10V 10V
R419
38
27.4K2 CERM
603
CERM
603 1
1 5% C596
PHY PIN 40
1%
1/16W
1/16W
MF
603
1uF
1
5%
2
R519
22
MF 1 2 1/16W 37 27 FW_PHY_CNTL<0> 1 2 FW_LINK_CNTL<0> 13 37
402 R1 MF
603 5%
20% 1/16W
R413
10V
CERM +1_95V_FW_DVDD_RX0
R520 MF
402
603
38
22
+1_95V_FW_DVDD 1
1 2 38 +3V_FW_AVDD C591 R417
1
37 27 1
FW_PHY_CNTL<1> 2 FW_LINK_CNTL<1> 13 37
27 38 5%
CRITICAL 5% C584 0.1uF 38 +1_95V_FW_DVDD_TX0 1 2 1/16W
PHY PIN 21
C U38 1 C621 1R443
1/16W
MF 1uF 1 2 1 C590 5%
1/16W
MF
402 R518 C
603 1 2 0.1uF MF 22
LT1962-ADJ 0.01uF
20% 16.2K 20%
10V 20% 603 35 27 CLKFW_PHY_PCLK 1 2 CLKFW_LINK_PCLK 13 35
MSOP
8 IN OUT 1 2 16V
1%
1/16W 20% CERM 2 10V
CERM 5%
CERM
402 MF 1 C620 10V
CERM
402 402 1/16W
MF
2 402 10uF 1 603 PHY PIN 38 402
NC 7 NC R2 20% R509 PHY PIN 38
C625 1 ADJ 2 FW_CORE_ADJ 2 6.3V
CERM 1 1K
2.2uF NC 6 NC 805 R505 5%
1/16W
20%
FW_CORE_BYP 1
1K MF 1 C681 1 C683 1 C677 1 C676 1 C682 DSx Strap Options
10V
CERM 2
BYP 3 R444 5%
1/16W 2 402 10uF 0.1uF 0.1uF 0.1uF 0.1uF
805 5 SHDN GND 4 27.4K MF
R497 1 1
R508
20% 20% 20% 20% 20% 0 = Bilingual port
1% 2 402 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
1/16W 1K 0 805 402 402 402 402 1 = A-only port
37 RX0
MF
R515 1 5% 5%
31 TX0
2 402 1/16W 1/16W
R1 1K MF
402 2
MF 2
R516
2 402
24
39
44
51
57
63
65
71
18
69
70
29
30
5% PHY PINS 4,14
6
1/16W
MF 10K
402 5%
2 AVDD DVDD DVDD PLL PLL 1/16W
MF
3.3 1.8 3.3 VDD VDD 1 402
33 DS0 1.8 3.3
FW_PORT1_SEL 32 CRITICAL 5 CLKFW_PHY_PCLK 27
DS1 PCLK 35
35 13 CLKFW_PHY_LCLK 7
LCLK U36 PINT
1 FW_PINT 13 37
TSB81BA3A
13 FW_PHY_LPS 80
LPS PQFP CNA
79 NC
R4881 1
R487
1 C605C607 1 R4921 1
R491
(SYM_VER1) 56.2 56.2 1uF
20%
1uF 20% 56.2 56.2
FW_PHY_LREQ 3 1% 1%
37 13
LREQ 9 FW_PHY_CNTL<0> 27
1% 1% 2 10V
CERM
10V
CERM 2 1/16W 1/16W
+FW_PWR_OR PWR CLASS = 100
SN0201029PFP CTL0
10 FW_PHY_CNTL<1> 27
37 1/16W
MF
402 2
1/16W
MF
2 402
603 603 MF
402 2
MF
2 402
38 28 27
FW_PC_PU 66 CTL1 37
(MAY PROVIDE POWER, OR PC0

MAY REQUIRE UP TO 3W) FW_PC_PD 67
PC1 1MA (MAX) BUS HOLDERS
(DS2)C/LKON 2 FW_LKON 13
68
R5021 (PC0 IS MSB, PC2 IS LSB) PC2
402K
B 1%
1/16W
MF
14 FW_PHY_PD 77
PD
TPA0+
TPA0-
46
45
(FW_TPA0P)
(FW_TPA0N)
FW_TPO0P 28
39
FW_TPO0N 28
37
37
(FWB-RX)
B
39
402 2
FW_BMODE 74 53 (FW_TPA1P) FW_TPA1P 28 37
BMODE TPA1+ (FW_TPA1N) (FWA-RX)
52 FW_TPA1N 28 37
TPA1-
FW_CPS 34
CPS 59 NC
TPA2+
FW_LINK_DATA<0> 1 8 FW_PHY_DATA<0> 11 58 NC
37 13
FW_LINK_DATA<1> 2
RP38
22 7
37
37 FW_PHY_DATA<1> 12
D0 TPA2-
37 13
5% D1 42 (FW_TPB0P) FW_TPI0P 28 37
37 13 FW_LINK_DATA<2> 3 1/16W 6 37 FW_PHY_DATA<2> 13 TPB0+ 39
SM1 D2 41 (FW_TPB0N) FW_TPI0N 28 (FWB-TX)
37 13 FW_LINK_DATA<3> 4 5 37 FW_PHY_DATA<3> 15 TPB0- 39
37
D3
FW_LINK_DATA<4> 1 8 FW_PHY_DATA<4> 16 49 (FW_TPB1P) FW_TPB1P 28
37 13
37 13 FW_LINK_DATA<5> 2
RP37
22 7
37
37 FW_PHY_DATA<5> 17
D4 TPB1+
48 (FW_TPB1N) FW_TPB1N 28
37
37
(FWA-TX)
5% D5 TPB1-
37 13 FW_LINK_DATA<6> 3 1/16W 6 37 FW_PHY_DATA<6> 19
SM1 D6 56 FW_TPB2_PD 38 28 27 +3V_FW
37 13 FW_LINK_DATA<7> 4 5 37 FW_PHY_DATA<7> 20 TPB2+
D7 55 NO STUFF
TPB2- CRITICAL4 TABLE_ALT_HEAD
FW_PHY_RESET_L 75
RESETZ TPBIAS0
47 FW_BIAS0 VCC
R4121 PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS:
54 FW_BIAS1
100K TABLE_ALT_ITEM
TPBIAS1 5% 197S0011 197S0052 G2 Alt. for Siward Part

FW_INPUT_PD 35
SE TPBIAS2
60 NC G2 1/16W
MF
R510
47
98.304MHZ
OSC
402 2
1 3 SM-A 1 FW_OSC_EN
R517 36
SM XI
27 35 FW_XI 1 2 35 FW_OSC
OUT OE
1K XO
26 NC 5%
1/16W
5% 78 GND
1/16W FW_TESTM MF
MF TESTM 402 R4941 1
R493 R4901 1
R489
23 FW_R0
2 402 R0 2
56.2 56.2 56.2 56.2
FW_VREG_PD 73 VREG_PD 22 FW_R1 1 1% 1% 1% 1%
R1 R511
A 0.22uF
C679 1 R514
1K
1
R500 1
THRML
PAD
AGND DGND PLLGND 5%
100
1/16W 1 C583
1/16W
MF
402 2
1/16W
MF
2 402
1/16W
MF
402 2
1/16W
MF
2 402 FIREWIRE PHY
470 1
R501 R4861 MF
A
81
21
40
43
50
61
62
4
14
38
64
72
76
25
28
20% 5% 5% 2 402
0.22uF
20%
6.3V 1/16W 1K 1K 6.3V FWB_TPB0 FWB_TPB1 NOTICE OF PROPRIETARY PROPERTY
CERM 2 MF 1/16W
MF 5% 5% 2 CERM
402 402 2 1 1
402 2 1/16W
MF
1/16W
MF
402 R499 R498 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2 402 402 2 C673 4.99KC672 4.99K
1%
220pF
5%
1%
1/16W 220pF
5% 1/16W
25V MF 25V MF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

CERM 2 402 CERM 2 402 II NOT TO REPRODUCE OR COPY IT
402 402
CAPACITOR IN CONJUCTION WITH III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
INTERNAL PULLUP PROVIDES
RESET PULSE WHEN PHY FIRST
RECEIVES POWER R512 SIZE DRAWING NUMBER REV.
6.34K
2
1%
1
APPLE COMPUTER INC.
D 051-6653 C
1/16W SCALE SHT OF
MF
402 NONE
27 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PORT POWER SWITCH 38 27 +3V_FW

+PBUS CRITICAL 28 +3V_FW_ESD
Q34 L39
NDS9407
R451
10K
400-OHM-EMI D20 D23
F3 SOI CRITICAL
1 2 +3V_FW_ESD_ILIM 1 2 BAV99DW
SOT-363
BAV99DW
SOT-363
1.5A-24V 8 D24 5% SM-1
5 2
1 2 38 +FW_PBUS 3 SMB 1/16W
7 MF
C630 1 C637 1
3
SM
2
6 38 +FW_SW 1 2 38 27 +FW_PWR_OR 402
D21 3 6
1 0.1UF 0.001UF 1N5227B
1 5 20% 20% 4 1
R448 C639 1 B340B 10V
CERM 2
50V
CERM 2
1 SOT23
D
D +3V_PMU
470K
5% 0.01UF
20% 4
402 402
D20
1/16W 16V D23
MF
402 2 CERM 2
402 C638 1
0.01UF
BAV99DW
SOT-363 BAV99DW
SOT-363
1 C633
PORT 0
R4471
100K
FW_GATE_EN
20%
16V
CERM 2
2
6 3
5
0.01UF
20%
16V
1394a/b
5%
1/16W
MF
DP6
BAS16TW F1
1
402
1 4
2 CERM
402 (BILINGUAL)
402 2 R4611
SOT-363
POWER_UP1 6 330K
5%
1.5AMP-33V
SM
514S0058
1/16W CRITICAL
MF
3 402 2 J20
2
D
Q33 FW_GATE_EN_RC CRITICAL 1394B
F-RT-SM
5
2N7002DW
SOT-363
L76
90-OHM-300mA
15
INT-SHIELD
32 29 PMU_POWER_UP_L G S 6 2012H 13
38 +FW_PWR1 SYM_VER-1
11
4 D
Q33 39 37 27 FW_TPO0P 4 1
2N7002DW 37 FW_TPAO0P 4 TPA
DP6 FW_POWER_UP 2 G S
SOT-363
1 1 (AREF) 39 FW_TPO0R 5 TPA(R)
BAS16TW 27 FW_TPO0N
3 2 37 FW_TPAO0N 3 TPA*
SOT-363 1
39 37
CRITICAL
6
33 32 20 DCDC_EN 4 3 L58 L51 L77 38 FW_VGND0
7
VG
FERR-250-OHM FERR-250-OHM 90-OHM-300mA
2012H
NC SC
SM SM 39 38 +FW_VP0 8
DP6 4
SYM_VER-1
1 2
VP
R446 BAS16TW 39 37 27 FW_TPI0P 37 FW_TPBI0P TPB

SOT-363 2 2 (BREF) (TPI0R) 9
AC_IN 2
10K 1 AC_IN_FW_CNTL2 5
TPB(R)
30 29 26 37 FW_TPBI0N 1 TPB*
FW_TPI0N 3 2
5% 39 37 27
10
1/16W
MF 12
C 402
R7771
470K
C650
0.01uF
1 14
INT-SHIELD
C
5% 20%
1/16W 16V
MF CERM 2
402 2 402
2 NO STUFF
R466 1 C651
1
R465 NO STUFF 0
1 C649 C652 1 5% 0.01uF
1M 0.1uF 0.01uF
1/10W 20%
5% 20% 20%
FF 2 16V
CERM
1/16W 1 805
MF 2 50V
CERM
16V
CERM 2
402
2 402 805 402
ENABLES PORT POWER WHEN CHGND1
MACHINE IS RUNNING OR WHEN ASLEEP ON AC
CHGND1
AREF NEEDS TO BE ISOLATED FROM

ALL LOCAL GROUNDS PER 1394B SPEC
SO WHEN A BILINGUAL DEVICE IS
+3V_FW_ESD
PLUGGED TO A BETA-ONLY DEVICE,
28
THERE’S NO DC PATH BETWEEN THEM
D22 D18 (TO AVOID GROUND OFFSET ISSUE)
BAV99DW BAV99DW BREF SHOULD BE HARD CONNECTED TO
SOT-363 SOT-363
5 2 LOGIC GROUND FOR SPEED SIGNALING
AND CONNECTION DETECTION CURRENTS
3 6 PER 1394B V1.33
4 1
C640 1
D22 D18
0.01UF 1 C644
B 20%
16V
CERM 2
402
BAV99DW
SOT-363
BAV99DW
SOT-363
20%
0.01UF B
2 5 2 16V
CERM
402
6 3
1 4
PORT 1
1394a ONLY
L52
260-OHM-330MA
514-0057
SM1 CRITICAL
37 27 FW_TPA1P 4 SYM_VER-2 3 J24
1394A
F-RT-TH
37 27 FW_TPA1N 1 2
39 37 FW_TPO1P 6
L48 TPO
260-OHM-330MA 39 37 FW_TPO1N 5
4
SM1
3
TPO#
37 27 FW_TPB1P SYM_VER-2
4
39 37 FW_TPI1P
TPI
39 37 FW_TPI1N 3
37 27 FW_TPB1N 1 2 TPI#
39 38 +FW_VP1 1
VP
CLEAR OUT ALL PLANES UNDER TRANSFORMERS 38 FW_VGND1 2
VGND
A
1
R471
0
5%
1/10W
FF
1
20%
2 16V
C662C666 1
0.01uF
CERM
0.01uF
20%
16V
CERM 2
7 8 9 10
FIREWIRE PORTSA
2 805 402 402 NOTICE OF PROPRIETARY PROPERTY
CHGND1 AGREES TO THE FOLLOWING
APPLE COMPUTER INC.

D 051-6653 C
SCALE SHT OF
NONE 28 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+3V_PMU +3V_PMU
R595 RP41
10K
470K
1 2 CHARGE_LED_L
29 PMU_EPM 4 5
25 29 39
+3V_PMU 5%
R583
5%
1/16W
R602
1/16W
SM1 RP41
10K
MF
402 4.7
+3V_PMU_AVCC 25 29 38
3
10K 6
1 2 PMU_POWER_UP_L 1 2 29 23 PMU_RESET_BUTTON_L
28 29 32
5% 5% TABLE_5_HEAD 5%
1/16W
1/16W
MF
402
R582
10K C255 1 C729 1 C724 1 1/16W
MF
402
C731 1 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
R261 SM1
1 2 SOFT_PWR_ON_L 22 23 29 33 39
10uF 0.1uF 0.1uF 0.1uF 341S1008 1 IC,PMU,V81B U29
TABLE_5_ITEM
PMU_POWERUP_OK 2
100K1
20% 20% 20% 20% 29
5% 6.3V 2 10V 10V 10V
1/16W CERM CERM 2 CERM 2 CERM 2 5%
805 402 402 402 1/16W
D
MF
402 MF
402 D
CPU_VCORE_HI_OC/PMU_AP should
R560
100K
14 60 97 have a pulldown for coming out of
reset. MLB will have a pull-up
to +3V_MAIN or +3V_SLEEP, which
1 2 MAIN_RESET_L 14 17 18 19 24 29 39 VCC AVCC will act as our pulldown since R591
5%
both are off during PMU reset.
PMU_BATT1_DET_L_PU 2
470K1
RP39 1/16W
MF
OMIT
(PMU_AP) 29
5%
4
100K 5 402
39 23 KBD_Y<0> 86
P00_D0 P50_WRL_WR
44 CPU_VCORE_HI_OC 7 33 1/16W
IO_RESET_L 17 23 26 29
39 23 KBD_Y<1> 85
P01_D1 U29 P51_WRH_BHE
43
INT_RESET_L 9 13 29
MF
402 R589
5% 42 470K1
1/16W
SM1
RP39
100K
39 23 KBD_Y<2> 84
P02_D2 M16C62
FLAS
P52_RD 41
MAIN_RESET_L 14 17 18 19 24 29 39 39 30 29 PMU_BATT_DET_L 2
39 23 KBD_Y<3> 83 NC 5%
3 6 SLEEP P03_D3 P53_BCLK 1/16W
23 25 29 32 34 39
39 23 KBD_Y<4> 82
P04_D4 P54_HLDA
40
PMU_INT_NMI 14 RP41 MF
5% 39 10K 402
RP39 R597 81
1/16W 39 23 KBD_Y<5> PMU_EPM 29 PMU_NMI_BUTTON_L 2 7
100K SM1 P05_D5 P55_HOLD 38 29
1 8 INT_RESET_L NUMLOCK_LED_L1
2.2K2 39 23 KBD_Y<6> 80
P06_D6 P56_ALE INT_PU_RESET_L 13 25 29
5%
9 13 29 23 37
5% 5%
39 23 KBD_Y<7> 79
P07_D7 P57_RDY_CLKOUT PMU_CPU_HRESET_L 6 39
1/16W
SM1 RP41
1/16W RP39 1/16W
78 36 1
10K 8
SM1 MF PMU_NUMLOCK_LED_L PMU_ACK_L PMU_NMI_L
100K
2 7
402
77
P10_D8 P60_CTS0_RTS0 35
14 29
INT_SUSPEND_REQ_L 8 29 PMU_CAPSLOCK_LED_L PMU_CLK 14 5%

R596 P11_D9 P61_CLK0 34 1/16W
76
R587
5%
1/16W 2.2K 29 25
39
CHARGE_LED_L
P12_D10 P62_RXD0 33
PMU_FROM_INT 14
R584 SM1
1K SM1 23 CAPSLOCK_LED_L1 2 29 28
32
PMU_POWER_UP_L 75
P13_D11 P63_TXD0 PMU_TO_INT 14
PMU_SMB_DATA
7.15K1
2
2 1 74 32 30 29
PMU_BYTE 29 5%
1/16W
NC P14_D12 P64_CTS1_RTS1_CTS0_CLKS1 PMU_REQ_L 14
1%
73 31
5% MF 39 SOFT_PWR_ON_L PMU_LID_CLOSED_L 1/16W
1/16W
R586 402
33 29 23 22
P15_D13_INT3 P65_CLK1 30
23 29 39
MF
MF
402 10K 1 39 25 14 COMM_RING_DET_L 72
P16_D14_INT4 P66_RXD1 29
PMU_RESET_BUTTON_L 23 29 402
R585
2 PMU_CNVSS 29 14 INT_WATCHDOG_L 71
P17_D15_INT5 P67_TXD1 PMU_NMI_BUTTON_L 29
PMU_SMB_CLK
7.15K1
2
30 29
5% 28
1/16W 39 23 KBD_X<0> 70 TPAD_RXD 23 29 1%
MF P20_A0_D0 P70_TXD2_SDA_TA0OUT 27 1/16W
402 39 23 KBD_X<1> 69 TPAD_TXD 23 29 MF
P21_A1_D1_D0 P71_RXD2_SCL_TA0IN_TB5IN 26 402
KBD_X<2> 68 SYSTEM_CLK_EN +3V_SLEEP
39 23
P22_A2_D2_D1 P72_CLK2_TA1OUT_V 25
14
R599
KBD_X<3> 67 CPU_CLK_EN
C
39 23
39 23 KBD_X<4> 66
P23_A3_D3_D2
P24_A4_D4_D3
P73_CTS2_RTS2_TA1IN_V
P74_TA2OUT_W
24
23
PMU_CHARGE_V
8
30 29 PMU_I2C_CLK 2
10K 1 C
KBD_X<5> 65 PMU_CHRG_BATT_0 5%
39 23
P25_A5_D5_D4 P75_TA2IN_W 22
30
1/16W
R598
39 23 KBD_X<6> 64 NC (CHARGE_I) MF
P26_A6_D6_D5 P76_TA3OUT 21 402 10K
39 23 KBD_X<7> 63 NC 29 PMU_I2C_DATA 2 1
P27_A7_D7_D6 P77_TA3IN
20 5%
UNDERVOLTAGE RESET CIRCUIT 39 23
39 23
KBD_X<8>
KBD_X<9>
61
59
P30_A8_D7
P31_A9
P80_TA4OUT_U
P81_TA4IN_U
19
PMU_SLEEP_LED_L
CPU_SMI_L
23
5
1/16W
MF
402
+3V_PMU 58 18
IO_RESET_L POWER_VALID
29 26 23 17
P32_A10 P82_INT0 17
29
+5V_SLEEP
57
39 23 KBD_COMMAND_L
P33_A11 P83_INT1 16
PMU_PME_L 14 17 24 29 39
R563
39 29 23 KBD_CONTROL_L 56
P34_A12 P84_INT2 INT_PEND_PROC_INT 14
TPAD_RXD 2
10K 1
1 15 29 23
R267 39 29 23 KBD_SHIFT_L 55
P35_A13 P85_NMI 9
PMU_NMI_L 29 Keep crystal subcircuit close to PMU.
5%
1K 39 29 23 KBD_OPTION_L 54
P36_A14 P86_XCOUT CLK32K_PMU_XOUT 1/16W
MF R564
5% 8
1/16W 39 23 KBD_FUNCTION_L 53
P37_A15 P87_XCIN CLK32K_PMU_XIN
TPAD_TXD
402
2
10K 1
MF 29 23
2 402 14 PMU_INT_L 52
P40_A16 P90_TB0IN_CLK3
5
PMU_BATT0_DET_L R588
1K
NO STUFF
5%
39
33 +3V_PMU_RESET 39 23 KBD_ID 51
P41_A17 P91_TB1IN_SIN3
4 PMU_BATT1_DET_L_PU 29 1 2 PMU_BATT_DET_L 29 30 39
R248 1/16W
MF
50 3 1
10M 2 402
7 CPU_PLL_STOP_OC
P42_A18 P92_TB2IN_SOUT3 NC 5%
1/16W
2
C370 1 NC 49
P43_A19 P93_DA0_TB3IN NC MF 5% +3V_MAIN
0.1uF 39 34 32 29 25 23 SLEEP 48
P44_CS0 P94_DA1_TB4IN
1 INT_PROC_SLEEP_REQ_L 14
402 1/16W
MF 1
R249 R576
20%
10V 4 47 100
PMU_POWERUP_OK
402
0 POWER_VALID 2
100K1
CERM 2 P45_CS1 P95_ANEX0_CLK4 29 29
402 VCC 8 INT_SUSPEND_ACK_L 46
P46_CS2 P96_ANEX1_SOUT4
99
NC R600 CRITICAL
5%
1/16W 5%
U26 98 1K MF 1/16W
R575
MAX6804 29 8 INT_SUSPEND_REQ_L 45
P47_CS3 P97_ADTRG_SIN4 PMU_OOPS 29 1
5%
2 AC_IN 26 28 30
Y3
SM-2
2 402
PMU_PME_L
MF
402
2
10K 1
SOT143 95 39 29 24 17 14
39 29 PMU_KB_RESET_L 3 MR* RSET* 2 P100_AN0 93

THERM_L_OC 25 1/16W
MF
32.768K CLK32K_PMU_XOUT_UF
5%
P101_AN1 92
PMU_AC_IN 402 1 3
R562 1/16W
MF
GND 29 PMU_BYTE 6
BYTE P102_AN2 PMU_AC_DET 29
PMU_LID_CLOSED_L 2
100K1 402
11 91 2 4 39 29 23
1 CLK10M_PMU_XOUT
XOUT P103_AN3 NC 5%
CLK10M_PMU_XIN 13 90 PMU_I2C_CLK 1 C339 1 C340 1/16W
B
B NO STUFF PMU_RESET_L 10
XIN
RESET
P104_AN4_KI0
P105_AN5_KI1
89
88
PMU_I2C_DATA
29
29
12pF
5%
12pF
5%
MF
402
R580 38 29 25 +3V_PMU_AVCC 96
VREF P106_AN6_KI2 PMU_SMB_CLK 29 30 2 50V
CERM 2 50V
CERM
87 402 402
1
10M 2
29 PMU_CNVSS 7 CNVSS P107_AN7_KI3 PMU_SMB_DATA 29 30
5% VSS AVSS
1/16W
R5811 MF
402
0 12 62 94
5% Y3’S LOAD CAPACITANCE IS 12.5PF R594
1/16W
MF Keep crystal subcircuit close to PMU. PMU_OOPS 1
10K 2
402 2 CRITICAL 29
Y4 Y5’S LOAD CAPACITANCE IS 12PF +3V_PMU 5%

CLK10M_PMU_XOUT_UF
10.0000M
1 2
A29 ADAPTER DETECTION 1/16W
MF
402
R561
100K
29 25 13 INT_PU_RESET_L 1 2
38 31 +4_85V_RAW
8X4.5MM-SM TABLE_ALT_HEAD
5%
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 1/16W
C406 1 C728 1 PART NUMBER 2
R592 1
MF
402
12pF
5%
12pF
5%
TABLE_ALT_ITEM
100K R348 1
R364
50V
CERM 2
50V
CERM 2
197S0604 197S0041 Y4 Alt. for Siward Part 1% 52.3K 100K
PMU KEYBOARD RESET CIRCUIT 402 402
1/16W
MF
1%
1/16W
1 C467 5%
1/16W
1 402 MF 0.1uF MF
+3V_PMU 2 402 20%
2 402
ADAPTER_DET 25 39 2 10V
CERM
402
1
R593 A29_DETECT 30
5 NC7S32 100K
1 1%
39 33 29 23 22 SOFT_PWR_ON_L SC70 1/16W
A MF 3
4
U20 Y
PMU_KB_RESET_IN1
+3V_PMU 2 402 2 U33 D
Q30
A
39 29 23 KBD_CONTROL_L
2
B
3
+3V_PMU 29
1
PMU_AC_DET
R590
402K
4 LMC7211
SM
1 A29_DET_L 1 G S
2N7002
SM PMU A
C277 1 1
5 NC7S32
SC70
ADAPTER IDs 1%
3 2
0.1uF
20%
A
4 PMU_KB_RESET_L ADAPTER ID RANGE PIN VOLTAGE
1/16W
MF 5 R345
+3V_PMU
10V
CERM 2 2
U25Y 29 39
Q11 (65W) 1.65-2.31V 2.007-2.066V

2 402 A29_DET_REF 4.7M
1 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
402 B AGREES TO THE FOLLOWING
5%
3 A29 (45W) 2.31-2.97V 2.558-2.661V R349
1 1/16W
MF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5 NC7S32 127K 402
1 AIRLINE 0.33-0.99V 0.589-0.663V 1%
39 29 23 KBD_SHIFT_L SC70 1/16W
A MF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
4
2
U24 Y
PMU_KB_RESET_IN2
2 402
39 29 23 KBD_OPTION_L
B
3 KEEP CAP CLOSE TO ALL 3 OR GATES
APPLE COMPUTER INC.
D 051-6653 C
29 44
SCALE SHT OF
NONE
8 7 6 5 4 3 2 1
.
8 7 6 5 4 3 2 1
+BATT
DC POWER INPUT BACKFEED +PBUS CURRENT LIMIT BATTERY SWITCH-OVER CIRCUIT

(POWER JACK, ETC. ON SEPARATE BOARD)
DC INRUSH LIMITER PROTECTION C798 1 1
38 +ADAPTER_SW R728 0.1uF F5 F4
CRITICAL
Q68 Q69 2
1K 1 IAC_RC_COMP 1 2 +24V_PBUS 5AMP-125V 5AMP-125V
+PBUS
J27 SI4435DY SI4435DY 1%
SM-2 SM-2
87438-0433 SOI SOI 1/16W 20%
10V
M-RT-SM MF
8 8 402 +3V_PMU CERM 2 2
1 3 S3 D4 D4 S3 3 402
39 38 31 +ADAPTER 7 7 +ADAPTER_SENSE
2 2 S2 D3 D3 S2 2
6 6
3 1 C35 R212 C11 1 1 D2 D2 1 1 C36 C794 1
D 4 0.1uF
10% 330K 0.1uF
S1
GATE
D1 5 5 D1
GATE
S1
CRITICAL
8 0.01uF
20% 0.1uF PLACE R383 CLOSE TO LTC1625
38 30 +BATT_24V_FUSE 38 +BATT_14V_FUSE
D
2 50V
X7R
5%
1/16W
20%
50V 2 50V
CERM CRITICAL 20%
10V
603-1 MF CERM 2 4 4 R7321 V+ 603 1
R745 CERM 2 CRITICAL
ROUTE LTC1625_ITH CAREFULLY
402 1 805
47K U3 +24V_PBUS
42.2K 402
Q6 CRITICAL
2 AC_ENABLE_GATE
5%
1/16W
MAX4172
TSSOP
0.1%
1/16W LTC1625_ITH SI4435DY Q7
R51 MF 1
RS+ RS-
2 FF
U55 DP1
SOI SUD45P03
20K +3V_PMU 402 2 2 603 2 LMC7111 8
TO-252
1% 7 NC
R727 IAC_FB 4 BAS16TW R119 3 S3 D4
D4
1/16W BKFD_PROT_GATE 3 PG SOT23-5 SOT-363
MF 2 NC NC1 10K 150 7
R29 D3
S
2 S2
1 402 NC 4
NC2 OUT
6 MAX4172_OUT 2 1 1 6 1 2 1 1625_COMP 31 6
470K 1
C803 1 R734 1 D2
G
GND 1% 1% S1
1
5% 5
1/16W 0.1uF 68K 1/16W 3 1/16W D1
C801 1 1
R15 MF 5% MF MF GATE
R402 R161 0.01uF 10K 1 402
20%
10V
CERM 2
1/16W
MF 5
CRITICAL 402 5 402
R716 1 R7101
97.6K 100K 20% 1 ADAPTER_I_REG 4 47K
1% 1% 16V
CERM 2
5%
1/16W AC_ENABLE_L 402 402 2 R77 Place close to RS- 47K 5%
1/16W 1/16W MF 2.21K 5% 1/16W
MF
402 1
MF
402 2
402
2 402
BKFD_PROT_EN_L
0.1%
1/16W
1 C826 CURRENT_THRESHOLD
1/16W
MF MF
402 2
3 MF 0.01uF
20% CRITICAL CRITICAL 1
CRITICAL 402 2
2 U1 D Q1 6 603 2
2 50V
CERM R7361 1
R738 R742 BATT_14V_GATE
38 31 1V20_REF 4 LMC7211 AC_IN 2N7002DW D 603 42.2K 82.5K +3V_PMU 51.1K BATT_24V_GATE
26 28 29 30 0.1%
SM
1 5 G S
SOT-363 0.1%
1/16W
0.1%
1/16W 1/16W
FF R7111
AC_IN 2 G
FF
603 2
FF
2 603 2 603 R7171 10K
AC_DIV 3 4
30 29 28 26 S
A29_CURRENT_ADJ
1
R744 OVER_18V_ADJ
10K 5%
1/16W
5%
5 R41 Q9 1 100K AC_IN_L
1/16W DP1 MF
402 2
2N7002DW 5% 3 30 MF
BAS16TW
R422 R302 1
1M 2 SOT-363 PLACE U24 NEXT TO R382
6 1/16W
MF
402 2
SOT-363
BAS16TW
AC_IN_L 30
10K 57.6K D
Q2 2 402
D
Q74 1 BATT_24PBUS_EN 5 2
R102 BATT_14PBUS_EN
SOT-363
4
5%
DP1
1% 1%
1/16W 1/16W 1/16W
MF 6
2N7002DW 2N7002DW 158K
MF MF SOT-363 AC_GTR_18V5 G S SOT-363
402 1 402 1 402 30 29 A29_DETECT 2 G S 1% 3
1/16W
Q1 D
MF
3
2N7002DW 2
R22 CRITICAL 1 6
4 2 402
D
Q9
SOT-363
S G 2 470K R61 2N7002DW
5% 0.0252 D
Q74 C809 1 5 SOT-363
C 1
1/16W
MF
1 402
1
1% 2
2N7002DW
SOT-363
1uF
20%
10V
AC_IN_L_RC G S
4
C
1 R821
1W
MF 1
R87
30 1772_ACOK_L G S
CERM 2
603
C118 1
R57 1
D4 4.7
2512
4.7 1
10uF
20%
100K 5% 5% 6.3V 2
GREATER THAN 13.1V DETECT 1%
1/16W
1N914
SOT23
1/16W
MF 1772_CSSP
1/16W
MF 37
CERM
805 WHEN AC IS IN, P-CHANNEL FETS ARE QUICKLY (DIODE) TURNED OFF
MF 3 402 2 2 402
402 2 37 1772_CSSN WHEN AC IS NOT PLUGGED, P-CHANNEL FETS ARE ON
R725 D6 RC TIME IS 480K*10UF @ +3V_PMU
33 1N914 1772_BST_ESR
+3V_PMU SWITCHER VOLTAGE CONTROL SWITCHER CURRENT CONTROL R49 1 1 C67 C71 1 1 C95 38 1772_LDO 1 2 1 3
PMU SELECTS BETWEEN TWO VOLTAGES CHARGE DISABLED BY PMU OR INPUT VOLTAGE <18V 12.7K 0.47uF 0.47uF 5% +24V_PBUS
1uF 20%
50V
20% 1/8W SOT23
CHARGE THROTTLED BY LOW BATTERY VOLTAGE 1% 20%
CERM 2 2 50V R521 FF 1
R96
1/16W 2 50V
CERM 1206
CERM
1206 1206
MF
402 2 1210 100K 4.7
5% 5%
1/16W C97 1 1/16W
R731 R621 1
R58 27 26 MF
402 2 0.1uF MF
2 603
27.4K 10K 10K CSSP CSSN
20%
25V
1% 1% 1% 1 DCIN CERM 2
1/16W 1/16W 1/16W 1772_DCIN CELLS 16 1772_CELLS
MF
402 2
MF
402 2
MF
38
U6
LDO 2
603 C96 1 5 6 7 8 1 C112 1 C117 1 C113 1 C115 1 C116
2 402 1772_ACIN 11 ACIN 0.1uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF
OD OUTPUT LOW - WHEN AC GREATER THAN 18V 30 1772_ACOK_L 12 ACOK MAX1772 DLOV 22 1772_DLOV
20%
50V 2 50V
20% 20%
2 50V
20%
50V
20%
50V
20%
50V
QSOP 38
CERM 2 CRITICAL CERM CERM 2 CERM 2 CERM 2 CERM
(+3V_PMU) 13 RFIN BST 25 1772_BST 805

Q70 1812 1812 1812 1812 1812
15 VCTL IRF7805
1772_VCTL DHI 24 1772_DHI 4
SM
14 ICTL CRITICAL
1772_ICTL
1 LX 23 38 1772_LX CRITICAL
R74 1772_ICHG 10 ICHG DLO 21 1772_DLO L70 +BATT_RSNS 38 +BATT_24V_FUSE 30 38
4.12K R7331 R7311 28 IINP

1 2 3
10uH R715
1% 1772_IINP PGND 20 (GND)
1/16W 20K 1K 0.05
MF
402 2
1%
1/16W
1%
1/16W R561 7 CCV CSIP 19 37 1772_CSIP
1 2 1 2
MF MF 1K 1772_CCV SM1 1%
CSIN 18 1772_CSIN 1W
B R591
BATTV_HIGH
402 2 402 2 1%
1/16W
MF
1772_CCI 6 CCI
37
5 6 7 8 2 MF
2512
1 C780 1 C795 C790
B
100K
BATT_LOW_L 402 2 1772_CCS 5 CCS BATT 17
C98 1 1 C99 D36 4.7uF
20% 4.7uF 1
4.7uF 1
C779
5% 6
1 REF CLS GND
1 C41 0.1uF 0.1uF CRITICAL SM
MBRS140T3 2 25V
20%
2 25V 33uF
1/16W
MF D
Q4 R75 6 3 R551 C43 1 1 C42 4 3 8 9
1uF 20%
25V
20% Q64 CERM
1206 CERM
20%
2 25V 20%
2 25V 1206 CERM
2N7002DW 5.23K 1K
402 2 20% 1 2 25V
0.01uF 0.01uF 2 10V CERM 2 CERM IRF7811W 1206
SOT-363
1%
1/16W
D
Q71 D
Q71 1%
1/16W 20% 20% CERM 603 603 4
R720 1
R713 1
C777 1 C792 1 ELEC
SM1
BATTV_LOW 2 G S MF 2N7002DW
SOT-363
2N7002DW
SOT-363
MF 16V
CERM 2 2 16V
CERM
603 NO STUFF SO-8
1 1 4.7uF 4.7uF C785 1
2 402 2 G S 5 G S
402 2 402 402 1C853 5% 5% 20% 20% 4.7uF
25V
3 1
1772_CCV_RC 1772_REF R541 1000pF1 2 3
1/16W
MF
1/16W
MF
25V
CERM 2 CERM 2
20%
25V
CERM 2
1 4 1 10K 1 XW1 10%
2 25V
603 2 603 2 1206 1206
1206
D
Q4 R83 1%
1/16W R94 SM X7R
2N7002DW
SOT-363
1K
1%
1 C24 C23 1 MF
402 2
100K
5%
1 2 402
29 PMU_CHARGE_V 5 G S 1/16W 0.1uF 1uF 1772_CLS 1/16W
MF 20% 20% MF
2 402 2 10V
CERM 10V 402 2
4 +3V_PMU
402 CERM 2 R531
603
4.12K
1%
1/16W
MF
R7411 +3V_PMU
402 2
100K 6
38 1772_GND
5%
1/16W +BATT
MF
402 2
D
Q72 38 +BATT_VSNS
2N7002DW
SOT-363
CHARGE_DISABLE 2 G S 1 C799 R7291 1
R740 BATTERY 2
1
0.1uF
20% 100K 499K R471 CONNECTOR L6
3
2 10V
CERM
1%
1/16W
1%
1/16W 6.34K
1%
L5 FERR-50-OHM
D
Q72 402 MF
402 2
MF 1/16W CRITICAL FERR-EMI-100-OHM
2 402 J26 SM 1 2
2N7002DW
SOT-363
U57 2
4
MF
402 2
87438-0833 SM
LMC7211
A
29 PMU_CHRG_BATT_0 5 G S
BATT_LOW 1
SM BATT_DIV
A29_CLS_ADJ M-RT-SM
1
1
L4 BATTERY CHARGER
4
3
1V65_REF
D
3
Q2 2 39 38+BATT_POS
FERR-EMI-100-OHM
1 2 NOTICE OF PROPRIETARY PROPERTY
A
3 (BATT_IN_PD) PMU_SMB_CLK
5 2N7002DW SM
29
SOT-363 4 BATT_CLK THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

R7301 1
R735 1 C807 30 29 A29_DETECT 5 G S
5
39
39 BATT_DATA
V = CELLS X (4.096 + (0.4096 * V / V )) 100K 100K 0.047uF
BATT VCTL REFIN 1%
1/16W
1%
1/16W 10% 4 6 PMU_BATT_DET_L 29 39
FERR-EMI-100-OHM
L3 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
For 4.15V cells, VCTL = 0.123 REFIN MF MF 2 16V

CERM 7 39 38 BATT_NEG II NOT TO REPRODUCE OR COPY IT
402 2 2 402
For 4.20V cells, VCTL = 0.245 REFIN
402
8 L2 1 2 PMU_SMB_DATA III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
FERR-50-OHM SM
29
ICHG = (0.2048/R ) *ICTL

(V / V ) 1 2 SIZE DRAWING NUMBER REV.
_62 REFIN
SM
APPLE COMPUTER INC.
D 051-6653 C
30 44
SCALE SHT OF
NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
Q15
FDG6324L
+5V_MAIN SC70-6
3
4 S2 D2 2 1625_EXTVCC 38
1
R130 G2
470K 6
5%
1/16W
MF
402 2
D 1625_ENABLE_L
D
6
1625_ENABLE 5 G1
D1
S1
Q15
CRITICAL
FDG6324L
SC70-6
1 C134
0.1uF
20%
12.8V PBUS SUPPLY
1 2 10V
CERM
402
PBUS HOLD-UP CAPS
+24V_PBUS
CONNECT LTC1625 TK PIN AT TOP-SIDE FET
KEEP VIN/TK LOOP SHORT
5 6 7 8
+3V_PMU
1625_INTVCC
C754 1 C154 1 C155 1
2
38
2.2uF 2.2uF 2.2uF
R127 NO STUFF CRITICAL 20%
50V
20%
50V
20%
50V
1 1
R120 Q17 CERM 2
1812
CERM 2
1812
CERM 2
1812
1
C804
5%
1/16W 0 1 IRF7805 100uF
R6901 C772 1 MF
603 1
5%
1/16W
1625_TG 4
SM 1 C755 1 C153 1 C753
20%
2 35V
97.6K 0.1uF MF EXTVCC D7 2.2uF 2.2uF 2.2uF
ELEC
SM-1
1%
1/16W
20%
10V
CERM 2
2 402 U13 SM 20% 20% 20%
MF 402 16
LTC1625
10
1 2 1625_BST_ESR 1 2 3 2 50V
CERM 2 50V
CERM 2 50V
CERM
402 2 38 1625_VIN VIN SSOP BG 1812 1812 1812
2 U14 15 TK CRITICAL TG 13 1
R122 1 C135
1V20_REF 4 LMC7211 MBR0540
38 30
SM D8 2 SYNC VOSENSE 7 2.2
5% 0.22uF CRITICAL
1 1625_RUNSS 3 11
3 1
1625_COMP 5
RUN/SS INTVCC
ITH
1/16W
MF
20%
2 25V
CERM
L69 +PBUS
30
2 603
3
1625_DIV 3 1N914
SOT23 1625_FCB 4 12 1625_BST
805
FCB BOOST
C 5 R663 8 14 C
2
VPROG SW 38 1625_VSW
R6731 1M C131 1
10K
1 2
R1072 4700pF SGND PGND 8.0uH-6.8A
SM1
1%
1/16W
1%
1/16W C137 1 4.99K 5%
25V 6 9 5 6 7 8
1 C771 1
R108
MF MF 0.1uF 1%
1/16W CERM 2 4.7uF
20% 158K
402 2 402 603 1%
20%
50V
MF
402 1 1 CRITICAL 2 25V
CERM 1/16W
CERM 2
805
R118 Q16 1206 MF
2 402
0
5% IRF7811W C806 1
COMP_RC 1 C124 1/16W
MF
1625_BG 4
SO-8 2 220uF
470pF 20%
10%
2 50V
2 402 NO STUFF D32
SM
25V 2
ELEC
SM
WHEN +24V_PBUS IS BELOW ~13.1V, CERM
603 1 C119 1 C138 1 2 3 MBRS140T3 1
R109
1625 IS SHUT-OFF C121 1 4.7uF 0.0047uF 1 C767 1
4700pF 20% 10% 4.7uF 16.2K
5% OMIT 1%
25V 2 10V
CERM 2 25V
CERM
20%
25V 1/16W
CERM 2 CERM 2 MF
603 XW3
SM
1206 402
1206 2 402
38 1625_SGND 1 2
1625_VFB
B PMU SUPPLY B
+5V_MAIN
D10
SM 3V_PMU_VTAP
NC
BACKUP BOOTSTRAP SYSTEM FROM

ADAPTER OR BATTERY
6
1
MBR0520LT
2
6
BATTERY +ADAPTER 1
R39
390 2 38 +ADAPTER_ILIM 1
D1
SM
2 38 +ADAPTER_OR_BATT 8
PLUS5VTAP
U23
LP2951
SOI 1
+4_85V_RAW 29 38
D11
1
SM
2
+4_6V_BU 32 38
8
VTAP
U22
LP2951
SOI-3.3V 1
+3V_PMU
39 38 30
IN OUT IN OUT
CRITICAL 5% 2 5 2 5 NC
1/4W SENSE ERR R233
1 SENSE ERR
J16 FF
1210
MBR0540 3
SHUT FDBK 7
R604 1
1
MBR0520LT 3
SHUT FDBK 7 1
R231
SM-2MT +PBUS +BATT
GND 294K 1 C276 5% GND 1
4 D3 1%
1/16W 470pF
10%
1/16W
MF
5%
1/16W
+24V_PBUS 1N914 4 MF
402 2 2 50V 2 603 4 MF
1
INPUT TO AND OUTPUT
1 3 CERM 2 603
2
FROM BATTERY
1 C244 C737 1 FB_4_85V_BU
603
+4_85V_ESR 38
3V_PMU_SENSE
OUTPUT FROM BATTERY
SOT23 0.1uF 0.1uF +3V_PMU_ESR
3 20%
2 50V
20%
10V
1 C740 38
CERM CERM 2 0.1uF

+PBUS
805 402 R6051 1 C336 20%
5 D2 100K
1% 2.2uF 2 10V
CERM
1 C326
SM 1/16W 20% 402 10uF
1 2 MF 2 10V
CERM
20%
6.3V
402 2 805 2 CERM
805
MBR0540
A
12.8V REGULATOR
A
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
31 44
OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V/5V MAIN SUPPLY

+24V_PBUS
C558 1 C559 1 C561 1 C560 1 8 7 6 5 5 6 7 8 1 C582 1 C581 1 C580 1 C579

D 2.2uF
20%
50V
2.2uF
20%
50V
2.2uF
20%
50V
2.2uF
20%
50V
2.2uF
20%
2.2uF
20%
2.2uF
20%
2.2uF
20% D
CERM 2 CERM 2 CERM 2 CERM 2 CRITICAL CRITICAL 2 50V
CERM 2 50V
CERM 2 50V
CERM 2 50V
CERM
1812 1812 1812 1812 38 3707_INTVCC 1812 1812 1812 1812
Q41 Q45
IRF7805 IRF7805
SM
4
R4051 1
R406 1 C574 3V_TG 4
SM
+5V_MAIN 5V_RSNS 0 100K 4.7uF
20%
38
CRITICAL 5% 1% CRITICAL 3V_RSNS 38
R411 1 1/16W 1/16W 2 10V 1
R399
CRITICAL L61 D14 1
1M MF MF CERM
1206 1M
1
D13 L62 CRITICAL +3V_MAIN
R522 4.7uH 3 2 1
SM 5%
402 2 2 402 5% SM
1 2 3
4.7uH R538
0.0052
1 2 1 MBR0540 1/16W +5V_MAIN 1/16W MBR0540 1 2 1
0.0052
MF MF
OMIT IHLP-5050 2 402 2 2 402 2 IHLP-5050
1% 1% OMIT
XW31
SM C687 1 1/4W
FF 2 8 7 6 5
5V_BOOST_ESR NC 3V_BOOST_ESR 5 6 7 8 2
1/4W
FF 1 C700 CRITICAL XW32
22uF 1206 1206 22uF SM
25 +5V_MAIN_AUD1 2 CRITICAL 20% D26 22 21 24 10 D28 20%
1
C703 1 2 +3V_MAIN_AUD
38
C685 1 10V
CERM 2 MBRS140T3
SM CRITICAL
C575 1
1
R409 EXT INT VIN 3.3 R4021 1 C564 CRITICAL SM
MBRS140T3
10V
2 CERM 330uF 25 38
330uF 1210
Q42 4.7 VCC VCC VOUT 4.7 Q47 1210 20%
2 6.3V
20% 1 0.22uF 0.22uF 1 TANT
6.3V
TANT 2 1
R521 1 IRF7811W 20%
25V
5%
1/16W U35 5%
1/16W 20%
2 25V
IRF7811W CASE-D4
CASE-D4
10 R523 SO-8
4
CERM 2 MF
2 603
LTC3707 MF
603 2 CERM
4
SO-8 R5371 R5391
1 C686 5% 10
5%
NO STUFF 805 5V_TG 27 TG1 SSOP TG2 16 805 NO STUFF 10
5% 5%
10 C699 1
22uF
20%
1/16W
MF 1/16W C839 1 5V_BOOST 25 BOOST1 BOOST2 18 3V_BOOST 1 C840 1/16W 1/16W 22uF
20%
MF 3 2 1 0.001uF 0.001uF 1 2 3 MF MF
2 10V
CERM 2 402 2 402 20% 38 5V_SW 26 SW1 SW2 17 38 3V_SW 20% 402 2 402 2 10V
CERM 2
1210 50V 5V_BG 23 BG1 BG2 19 3V_BG 2 50V 1210
CERM 2 CRITICAL CERM
402 402
+5V_MAIN 2 SNS1+ SNS2+ 14
37 5V_SNSP 37 3V_SNSP
37 5V_SNSM 3 SNS1- SNS2- 13 37 3V_SNSM
+3V_MAIN
C576 5V_VOSNS 4 VOSNS1 VOSNS2 12 3V_VOSNS C565
0.001uF 5V_ITH 8 ITH1 ITH2 11 3V_ITH
0.001uF
C8 1 C114 1 C415 1 1 2
5V_RUNSS 1 RUN/ RUN/ 15
1 2
0.1uF
20%
0.1uF
20%
0.1uF
20% NO STUFF SS1 SS2 NO STUFF
C 10V
CERM 2
10V
CERM 2
10V
CERM 2
R4081 1 C573
20%
50V 7 FCB
3V_RUNSS
1 C569
20%
50V C568 1
1
R401 C
402 402 402 113K
1% 180pF CERM
402 C571 1 C577 1 3707_FSET 5 FREQSET PGOOD 28
0.0022uF
CERM
402 180pF 63.4K
1%
C555 1 C416 1 C353 1
1/16W 5% 0.0022uF 0.047uF 1 C566 10% 5% 1/16W 0.1uF 0.1uF 0.1uF
MF 2 50V
CERM
10%
50V
10%
16V
6 STBYMD
0.1uF 2 50V
50V
CERM 2 MF 20%
10V
20%
10V
20%
10V
402 2 402 CERM 2 CERM 2 20% CERM 402 2 402 CERM 2 CERM 2 CERM 2
C123 1 C554 1 C7 1 402 402 3707_FCB
SGND PGND 2 10V
CERM
402 402 402 402
0.1uF
20%
0.1uF
20%
0.1uF
20%
5V_ITH_RC
3707_STBY 9 20 402 3V_ITH_RC
10V 10V 10V
CERM 2 CERM 2 CERM 2 C627 1 C126 1 C143 1
402 402 402 R4101 R4041 1 C570 C572 1
1
R407 C567 1
1
R403 1
R400 0.1uF 0.1uF 0.1uF
21.5K
1%
15K
1% 100pF 0.01uF 100K
1% 100pF 12K
5%
20K
1%
20%
10V
20%
10V
20%
10V
5% 20% 5% CERM 2 CERM 2 CERM 2
C557 1 C562 1 C629 1 1/16W
MF
1/16W
MF 2 50V
CERM
16V
CERM 2
1/16W
MF 50V
CERM 2
1/16W
MF
1/16W
MF 402 402 402
0.1uF 0.1uF 0.1uF 402 2 402 2 402 402 2 402 402 2 402 2 402
20% 20% 20%
10V 10V 10V
CERM 2 CERM 2 CERM 2 38 3707_SGND
C556 1 C563 1 C628 1
402 402 402 5V START TO TURN ON ~12.5MS AFTER DCDC_EN_L
0.1uF
20%
0.1uF
20%
0.1uF
20%
3V START TO TURN ON ~25MS AFTER DCDC_EN_L 3 10V 10V 10V
3V_5V_OK 34 CERM 2 CERM 2 CERM 2
DISTRIBUTE CAPS ALONG TOP EDGE AND FAN CUT-OUT
DIODE WILL ENSURE DCDC_EN_L IS QUICKLY DISCHARGED DURING SHUT-DOWN
R524
D
Q43 2 402 402 402
2N7002 XW13 1 C578 THIS SIGNAL IS OPEN COLLECTOR TO GND WHEN POWER IS NOT GOOD
POWERDOWN DELAY IS AROUND 4MS-15.6MS
DCDC_EN_L 1
1M 2 LTC3707_START_RC 1 G S
SM SM 220pF 220PF IS USED TO QUIET NOISE ON PGOOD ONCE INTERNAL OPEN DRAIN IS DISENGAGED
+4_6V_BU 31 38 34 32
DISTRIBUTE CAPS ALONG TOP EDGE AND FAN CUT-OUT
5%
5%
1/16W 2
1 2 25V
CERM
1 MF 402
R533 402
470K
5%
1/16W
MF
2 402 D27 1 C688
DCDC_EN 20 28 33 3 1
20%
0.01uF +3V_MAIN +3V_SLEEP
R534 1N914 2 16V
CERM +5V_MAIN
PMU_POWER_UP_L
100K
1 2 34 32 DCDC_EN_L
6 SOT23 402
29 28
5%
D Q44 R294 4
B 1/16W
MF
402 3 2 G S
2N7002DW
SOT-363
NO STUFF SLEEP 1
100K2 3 6 +3V_SLEEP LOADS B
1 SLEEP_L_LS5_NET 34 39 34 32 29 25 23
D Q44 R548 5% 5
1) CPU PLL CONFIG CONTROL
2N7002DW 1 C694 1 DCDC_EN TRUTH TABLE 100K
5%
1/16W
MF NO STUFF 2
2) INTREPID - I2C PULLUPS & OSCILLATOR
SOT-363 402
39 34 32 29 25 23 SLEEP 5 G S 0.01uF
20% +3V_SLEEP 1/16W
MF
6
NO STUFF R572 C7131
100uF
1 1
3) MAP31 - 3V RAIL (IF USING D3COLD)
2 16V
CERM
PMU_POWER_UP_LSLEEP DCDC_EN DCDC_EN_L State 2 402 D
Q50 100K 20%
TSOP
SI3443DV
+5V_MAIN 5% 4) GRAPHIC CHIP SPREAD SPECTRUM CHIP
4 402 2N7002DW 1/16W 10V
0 0 1 0 Run +3V_SLP_OK_L2 G S
SOT-363 MF
402 2
POLY
SMD-3 2 Q21 5) LVDS DDC PULL-UPS
6) DVI LEVEL SHIFTERS & PULLUPS & HPD
1 (2.99V) 1 1 0 Sleep NO STUFF C398
+5V_MAIN
1 0 0 1 Shutdown
1
R551 1
2200pF 7) BOOT BANGER
C432 100K 3 NO STUFF R3011 3V_SLEEP_PWREN_L 2 1 8) HARD DRIVE (IF USING 3V LOGIC)
5%
0.01uF +3V_PMU +3V_PMU +4_6V_BU +3V_PMU VOLTAGE 1/16W D
Q50 100K 9) WIRELESS
1 2 MF 5% 5% 10) PMU - I2C PULLUPS
2 402 2N7002DW 1/16W
MF 6
50V
CERM
5 SOT-363 402 2 NO STUFF 603
20% +3V_SLP_ON G S
16V
CERM
D Q20
2N7002DW
402 4 4
R321
100K
+5V_HD_SLEEP 24 38
SLEEP LEVEL SHIFTER (3V -> 5V) SLEEP_NET_INV 2 G S
SOT-363
32 SLEEP_LS5 1 2 5V_HD_PWREN 3 6 +5V_MAIN NO STUFF
5% 5
1
R550 SLEEP_NET 3 1
1/16W +5V_SLEEP LOADS 470K NO STUFF
MF 1 C428 2 1
C709 5% D Q20
402 10uF 1 100uF 1/16W
MF R291 2N7002DW
20%
6.3V TSOP 20% 1) FAN
2 402 1
100K2 5 SOT-363
2 CERM SI3443DV 2 10V SLEEP G S
805 POLY
SMD-3
2) Headphone amplifier R3061 R3071 39 34 32 29 25 23
Q26 3) OPTICAL DRIVE 100K

5%
100K
5%
5%
1/16W
MF
4
4) DVI 1/16W 1/16W 402
MF MF
C433 5) TRACKPAD 402 2 402 2
A
0.1uF
1 2 SLEEP_L_LS5 18 20 26 33 34
SLEEP_LS5 32
3.3V/5V REGULATOR
20%
10V SLEEP_L_LS5_EN_L 6 SLEEP_LS5_EN_L 3 NOTICE OF PROPRIETARY PROPERTY
A
CERM +5V_SLEEP
R322 402 4
R311
D
Q24 R310
D
Q24 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
100K2 2N7002DW 2N7002DW PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1 5V_SLEEP_PWREN 3 6
SLEEP 1
100K2 2 G S
SOT-363
1
100K2 5 G S
SOT-363 AGREES TO THE FOLLOWING
39 34 32 29 25 23
5% 5 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W 5% 5%
MF
402
1 C429 2 1
C710 1/16W
MF
1 1/16W
MF 1 C410 4 II NOT TO REPRODUCE OR COPY IT
10uF
20%
1 100uF 402 402 0.01uF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TSOP 20% 20%
2 6.3V
CERM SI3443DV 2 10V
POLY 2 16V SIZE DRAWING NUMBER REV.
805 CERM
SMD-3
Q27 402
APPLE COMPUTER INC.

D 051-6653 C
32 44
SCALE SHT OF
NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.250V->0.975V 1.50Ghz +3V_MAIN
NOTE: When U15 MUX is removed => NO SW Support,
R794,R795,R796&R797 have to be stuffed
VCORE POWER SEQUENCING 1.200V->0.975V
(value without offset)
1.33Ghz
R794
CPU core follows CPU I/O voltage
VCORE_FAST<1>1
0 2 VCORE_VID<1>
CPU_BTR&CPU_BST 33 33
(approx. 7ms delay) NO STUFF NO STUFF CPU_BTR
NO STUFF 1NO STUFF 1NO STUFF 1NO STUFF 1 1 1 1 1
NO STUFF 1 C130 5%
+5V_MAIN R125 R135
1 R635 R672 R757 R137 R631 R662
470K 0 0 470K 470K 0 0
R676
10K
0.1uF
20%
1/16W
MF
402
R796
0
470K 5% 5% 5% 5% 5% 5% 5% 5%
16
2 10V 33 VCORE_FAST<2> 1 2 VCORE_VID<2> 33
TABLE_5_HEAD
5% 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W CERM PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
1/16W
MF MF MF MF MF MF MF MF MF VCC 402 5% CAP,AL,POLY,8.2uF,20%,16V,V CASE,SMD
R795 1/16W
TABLE_5_ITEM
2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 U15 MF 126S0036 7 C51,C52,C77,C78,C91,C92,C111CRITICAL
1 1 1 PI3B3257 0 402
R101 R106 R111 VCORE_SLOW<1> 2
A1 QSOP Y1
4 VCORE_VID<1> 33
VCORE_FAST<3>1 2 VCORE_VID<3> 33
100K 100K 100K 3
SYM_VER-2 5%
5%
1/16W
5%
1/16W
1%
1/16W
33 VCORE_FAST<1>
B1NO STUFF 1/16W
MF R797
D 38 16 15 8 7 6 5 MAXBUS_SLEEP MF
402 2
MF
402 2 DP2 MF
2 402
VCORE_SLOW<2>
33 VCORE_FAST<2>
5
6
A2 Y2 7 VCORE_VID<2>
33
33
VCORE_FAST<4>
402
1
0 2 VCORE_VID<4> 33 D
BAS16TW 11
B2
9
5% CPU_VCORE_SLEEP
CPU_VCORE_PWR_SEQ SOT-363 VCORE_SLOW<3> VCORE_VID<3> 33 1/16W 39 38 33 6 5
6 1
A3 Y3 MF
33 VCORE_FAST<3> 10 402
B3
14 12
3
VCORE_SLOW<4>
A4 Y4 VCORE_VID<4> 33
C101 1 C12 1 C74 1 C100 1 C16 1
R675 33 VCORE_FAST<4> 13
B4 10uF 10uF 10uF 10uF 10uF
R991 CPU_VCORE_SEQ_L
0 SEL = 0; Y1=A1 20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
10K 1 Q8 33 29 7 1
CPU_VCORE_HI_OC 2 VCORE_MUX_SEL 1
SEL CERM CERM CERM CERM CERM
5%
1/16W 2N3904 5% VCORE_MUX_EN 15
OE
SEL = 1; Y1=B1 805 805 805 805 805
MF 3 SM 1/16W
402 2 2 MF CPU_BTR&CPU_BST
402 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF CPU_BTR&CPU_BST CPU_BST GND +PBUS
1 1 1 1 1 1 1 1 1 NO STUFF
CPU_VCORE_SEQ 1 Q5 R123 R129 R647 R671 R126 R139 R634 R660 R121 8
2N3904 0 470K 470K 470K 470K 470K 470K 0 1K C90 1 C57 1 C21 1 C6 1 C15 1
SM 5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W 5% Keep trace fat (40-100 mils) and short!! 10uF 10uF 10uF 10uF 10uF
2 MF MF MF MF MF MF MF MF 1/16W 20% 20% 20% 20% 20%
MF OMIT OMIT OMIT OMIT 6.3V 6.3V 6.3V 2 6.3V 6.3V 2
2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 CRITICAL CRITICAL CRITICAL CRITICAL CERM 2 CERM 2 CERM CERM 2 CERM
<D4> <D3> <D2> <D1> <D4> <D3> <D2> <D1> 805 805 805 805 805
C77
10uF
1
C91
10uF
1
C78
10uF
1
C52
10uF
1
DP2 +5V_MAIN 20% 20% 20% 20%
BAS16TW 16V 2 16V 2 16V 16V 2
SOT-363 TANT TANT TANT 2 TANT
34 32 26 20 18 SLEEP_L_LS5 5 2
CASE-D CASE-D CASE-D CASE-D
C83 1 C63 1 C3 1 C5 1 C14 1
CRITICAL
10uF
20%
10uF
20%
10uF
20%
10uF
20%
10uF
20%
OMIT OMIT OMIT 6.3V 2 6.3V 6.3V 2 6.3V 2 6.3V 2
DP2 PLACE C423 CLOSE 1
TO PINS 15 & 13!! D5 CRITICAL CRITICAL CRITICAL CERM
805
CERM 2
805
CERM
805
CERM
805
CERM
805
BAS16TW SM C92 1
C111 1
C51 1
SOT-363
DCDC_EN 4 3 R861 1 C93 2
MBR0530 10uF
20%
10uF
20%
10uF
20%
32 28 20
20 1uF 16V 2 16V 2 16V 2
VCORE_BOOST
5% 20% TANT TANT TANT
1/16W 2 10V
CERM
CASE-D CASE-D CASE-D
C76 1 C106 1 C105 1 C4 1 C13 1
MF 603
402 2 10uF
20%
10uF
20%
10uF
20%
10uF
20%
10uF
20%
NO STUFF 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2
38 VCORE_VCC CERM CERM CERM CERM CERM
C R80 5 5
805 805 805 805 805
C
0 38
33 29 7 CPU_VCORE_HI_OC1 2
R851 C84 1 7 15 CRITICAL
5% 1 0 VCC VDD
CRITICAL
1/16W
MF R91 5%
1/16W
1uF
20% Q62 Q65
402 27.4K MF 10V
CERM 2
U7 SI7860DP SI7860DP XW29
1%
1/16W
402 2 603 MAX1717 (VCORE_VPLUS)
4
SO-8-PWRPK 4 SO-8-PWRPK CRITICAL SM
R81 MF
402 2
QSOP NO STUFF
L71 VCORE_VSENSE
1 2
INT_GPIO1_PU 1
0 2
5 VCORE_SHDN_L 2 SKP/SDN V+ 1
R71 1 C65 1.2uH-18.3A Keep trace fat and short!!
14
(VCORE_SNS) 5 FBS 2.2 0.0047uF 1 2 3 Keep trace fat and short!!
3
10% 1 2 3
5%
1/16W 38 VCORE_ILIM 10 ILIM
BST 22 VCORE_BST2 1
2 25V
CERM
R743 (VCORE=1.385V for EVTB)
MF DH 24 5% 0.001
2
402 (VCORE_GNDSNS)
11 GNDS 1/16W 402 CPU_VCORE_SLEEP 5 6 33 38 39
MF SM1
+3V_MAIN 33 VCORE_AB_SEL 16 A/B 603 1%
CRITICAL 38 VCORE_DH
1 C64 5 6 7 8 5 6 7 8 5 6 7 8
1W
MF
CPU_BTR&CPU_BST
VCORE_REF 9 0.1uF 2512
1 38 REF 20%
R66 2 25V
CERM CRITICAL CRITICAL CRITICAL CRITICAL
0 603 CRITICAL CRITICAL
C802
5%
1/16W
38 VCORE_TON 8 TON LX 23 38 VCORE_LX Q60 Q63 Q66 C797 C774 330uF
MF 6 14 4 IRF7832 4 IRF7832 4 IRF7832 CRITICAL 330uF 330uF 20%
2 402 38 VCORE_CC CC DL 38 VCORE_DL SO-8 SO-8 SO-8 2 20% 20% 2.5V-ESR9V
2.5V-ESR9V 2.5V-ESR9V
<D0> VCORE_VID<0> 21 D0 GND 13 VCORE_GND
R901 D33 POLY
CASE-D2E
POLY
CASE-D2E
POLY
CASE-D2E
38
2.2 B540C
33 VCORE_VID<1> 20 D1 C841 1 1 2 3 C842 1 1 2 3 C843 1 1 2 3 5%
1/4W 1 SM
19 0.001uF 0.001uF 0.001uF MF CRITICAL CRITICAL CRITICAL
33 VCORE_VID<2> D2 FB 4 VCORE_FB
39 38 20%
C781 C793
MAX1717 VID INPUTS ARE 3.3-5V TOLERANT 33 VCORE_VID<3> 18 D3 TIME 3 VCORE_TIME
50V
CERM 2
20%
50V
CERM 2
20%
50V
CERM 2
1210 2
NO STUFF C788 330uF 330uF
17
38
402 402 402 CPU_VCORE_SNUB R72 330uF 20% 20%
33 VCORE_VID<4> D4 VGATE 12 VCORE_VGATE 14 38
100
20%
2.5V-ESR9V 2.5V-ESR9V 2.5V-ESR9V
VGATE PULLUP PROVIDED BY INTREPID
1 2 POLY POLY POLY
CASE-D2E CASE-D2E CASE-D2E
NO STUFF NO STUFF
1
R65 C66 1 R671 R951 1 C94 C80 1 XW28 C79 5%
470K 0.01uF 178K 12.7K 1uF 220pF R691 C70 1 SM
0.0022uF 1 1/16W
MF
5% 20% 1% 1% 20% 5%
25V 390K 0.001uF 1 2 10%
402
1/16W 16V 1/16W 1/16W 2 10V
CERM CERM 2 5% 20% 50V
CERM 2 MF MF 1/16W
XW2 XW27
B MF
2 402 402 402 2 402 2 603 402 MF
402 2
50V
CERM 2
402 SM
CERM
603 2
SM B
38 VCORE_GNDA 1 2 1 2
Note:No stuff R67 to set skip mode of VCore
Connect MAX1717 GND pin 13
(R93 CPU_BTR BOM OPTION SEE BOM TABLE)
+3V_MAIN GROUND SENSE VOLTAGE DIVIDER to GND at bottom-side FET Keep trace fat and short!!
CPU_BST
OUTPUT VOLTAGE 1
R93
3K
CPU_BTR&CPU_BST
1
R98
This allows for an offset to the ground sense to adjust the output voltage.
VREF = 2.0V, HENCE VOFFSET = 2.0V*0.85*(Rb / Ra) AND VCORE = VDAC + VOFFSET.
PLACE THIS SHORT AT
PIN OF 1000uF CAP
R7901 5%
1/16W 158K (Ra) NOTE: Ra NO STUFFED FOR NO OFFSET CASE CLOSEST TO CPU
VDAC 100K MF
2 402
1%
1/16W
D3 D2 D1 D0 NO STUFF
5%
1/16W MF
2 402 (CPU Vcore value with offset)
D4=0 D4=1 R792 MF
402 2
VCORE_OFFSET_DIV
TABLE_5_HEAD
2.00 1.275 0 0 0 0 33 VCORE_AB_SEL 1

0 2 VCORE_AB_SEL_OPT 6
Q82
VCORE_GNDDIV 33 38
1.50Ghz 1.280V->0.990V 114S2003 1 RES,MF,1/16W,2K OHM,1%,0402,SMD R97 ? CPU_BTR
TABLE_5_ITEM
1.95 1.250 0 0 0 1
5%
1/16W
MF
402 1
VCORE_AB_SEL_INV
R791
0 2 2 G
D
S
2N7002DW
SOT-363
1
CPU_BST
R97
3K
1.33Ghz 1.220V->0.990V 114S5903 1 RES,MF,1/16W,5.9K OHM,1%,0402,SMD R93 ? CPU_BTR
TABLE_5_ITEM
1.90 1.225 0 0 1 0 5% 5%
(Rb)
3 1/16W 1 1/16W (R93&R97 CPU_BTR BOM OPTION SEE BOM TABLE)
1.85 1.200 0 0 1 1 MF
402
MF
2 402
1.80 1.175 0 1 0 0
D Q82
2N7002DW 38 33 VCORE_GNDSNS
5 SOT-363 38 VCORE_SNS
1.75 1.150 0 1 0 1 G S
1.70 1.125 0 1 1 0 ROUTE AS DIFFERENTIAL PAIR

4
Fmax Test Connections
1.65 1.100 0 1 1 1
1.60 1.075 1 0 0 0 FOR V-STEP: 2.05K2
NO STUFF
R706
A
1.55
1.50
1.050
1.025
1
1
0
0
0
1
1
0 D<4..0> Hi/Fast
A/B_ =
Lo/Slow
38 33 VCORE_GNDDIV1
1%
1/16W
MF
NO STUFF
J7
M-ST-SM-52465-1217
VCORE SUPPLY A
402 1 12 NOTICE OF PROPRIETARY PROPERTY
1.45 1.000 1 0 1 1 <= 1K PU 1 0 NO STUFF
R708 VCORE_GNDDIV_TEST 2 11
VCORE_D0
VCORE_D1
>= 100K PU 1 1
1.40 0.975 1 1 0 0 VCORE_GNDSNS1
100 2 VCORE_GNDSNS_TEST 3 10 VCORE_D2
>= 100K PD 0 1 38 33
4 9
1.35 0.950 1 1 0 1 <= 1K PD 0 0 1%
1/16W
39
MF 29 23
29 +3V_PMU_RESET
5 8
VCORE_D3
22 SOFT_PWR_ON_L VCORE_D4
1.30 0.925 1 1 1 0 When A/B_ is high (fast): D4-D0 read as-is 402 39
NC (RFU) 6 7
NO CPU NO CPU 1 1 1 1 When A/B_ is low (slow): <=1K-ohm -> 0 SIZE DRAWING NUMBER REV.
>=100K-ohm -> 1
If all pull-ups are >=100K and all APPLE COMPUTER INC.
D 051-6653 C
pull-downs are <=1K,A V =B V .
SCALE
NONE
SHT
33 44 OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+1_5V_SLEEP LOADS
1.5V/2.5V SWITCHER
1) AGP I/O - IF USING D3COLD
2) MAXBUS I/O - IF 1.5V INTERFACE
M11 Power Shut down Sequencing
+1_5V_MAIN +1_5V_SLEEP
+3V_SLEEP
+2_5V_SLEEP
Q53 +1_5V_MAIN LOADS
+5V_MAIN DP4
SI3446DV XW8
SM
BAS16TW
SOT-363
XW21
SM
1 TSOP
1) INTREPID CORE 1 38 1
2 +2_5V_SLEEP_NECK2 6 +3V_SLEEP_NECK1 2
2
D 5
+2_5V_MAIN LOADS
+1_8V_SLEEP
DP4 D
6 3 1_5V_SLEEP_EN_L XW10 BAS16TW
BAS16TW
34
R117 1 R177 SM SOT-363
SOT-363
2
1) MAP31 - FBCORE/FBIO IF USING D3HOT
DP3
4
100K 2
20 1 MAX1715_VCC 1 2
238 +1_8V_SLEEP_NECK 5
5%
38 2) GIGABIT ETHERNET - AVDDL
C717 1 1 C718 1/16W
MF
5% 3) DDR SODIMMS - CORE/IO +1_5V_SLEEP
10uF 1000pF 1/16W 1 C194 DP4
5
402 2
20%
6.3V 2
10%
2 25V
NO STUFF MF
402
1 C195 2.2uF 4) DDR MUXES
XW23 BAS16TW
CERM
805
X7R
402
1
R227 2.2uF
20%
20%
10V SM SOT-363
3V_5V_OK 2 CERM
34 32
0 2 10V 1 3
238 +1_5V_SLEEP_NECK 4
DP3 5%
1/16W
CERM
805
NO STUFF 805
BAS16TW MF 1
R226
SOT-363
2 402 0
6 1
+5V_MAIN 3 5%
1/16W
BAS16TW
MAX1715_TON MF
Q10 38
SOT-363
D
3
2 402
DP3
R184 2N7002 +2_5V_SLEEP LOADS
DCDC_EN_L 1
330K2 MAX1715_ON_RC1 G S
SM
R1161 R1151
32
38 2_5V_ILIM 38 1_5V_ILIM +PBUS 1) FBCORE/FBIO IF USING D3COLD
4
100K 5%
5% 100K 1/16W
MF
1 C133 2 U48
1/16W 5%
1/16W 402QUICK SHUT-DOWN 0.01uF R2101 1
R211 +PBUS +2_5V_MAIN SI6467BDQ +2_5V_SLEEP
MF DIODE PROVIDE PROVIDE TSSOP
402 2 MF POWER DOWN DELAY 1.5MS TO 3.5MS 20% 158K 158K
402 2 2 16V
CERM 1% 1%
2 3 6 7
402 1/16W 1/16W
1 5 8
1_5V_SLEEP_EN_L 34 MF MF 21 20
402 2 2 402
3
VCC VDD
MAX1715_GND 34 U19 MAX1715_SKIP 38
D Q11 +PBUS
38
MAX1715 CRITICAL CRITICAL
2N7002DW QSOP 1 C338 1 C355 C715 1
4
5 SOT-363
34 SLEEP_L_LS5_INV G S 3 ILIM1 V+ 4 4.7uF
20%
4.7uF
20%
10uF
20%
12 ILIM2 NC_15 15
6 4
NC 2 25V
CERM 2 25V
CERM
6.3V 2
CERM
32 SLEEP_L_LS5_NET CRITICAL CRITICAL 10 ON1 NC_23 23 NC 1206 1206 805
C R114
D
Q11 C232 1 C209 1 R171 11 ON2 NC_28 28 NC R170 C
2N7002DW
33 100K SOT-363 4.7uF 4.7uF 4.7 4.7
26
18 SLEEP_L_LS51 2 2 G S 20%
25V
20%
25V
38 1_5V_BOOST 1 2 38 1_5V_BST 25 BST1 BST2 18 38 2_5V_BST 1 2 38 2_5V_BOOST
R557 C716
20
32 5% CERM 2 CERM 2 5% CRITICAL 5% 100K 1000pF
26 DH2 17
1/16W
MF
1 C129 1 1206 1206 1/16W
MF DH1 1/16W
MF 39 34 32 29 25 23 SLEEP 1 2 2_5V_SLEEP_PWREN_L 1 2
402 1000pF 8 7 6 5 1 C196 603
27 16
603 5 6 7 8 5%
10%
2 25V 0.1uF LX1 LX2 1 C193 NO STUFF 1/16W
MF
NO STUFF
C714 1
10%
25V
X7R 20% 24 DL2 19 0.1uF R554 402 1000pF X7R
402 CRITICAL 2 25V
CERM
DL1 20% CRITICAL
100K 402
Q56 603 +1_5V_MAIN 2 25V
CERM Q55 34 SLEEP_L_LS5_INV 1 2
10%
25V
5 TON PGND 22 MAX1715_GND 603 X7R 2
IRF7805 4 1_5V_DH +2_5V_MAIN 38 2_5V_DH 4 IRF7805 5%
1/16W
402 +2_5V_MAIN
+1_5V_MAIN SM 38
1 SM
OUT1 OUT2 14 MF
402
CRITICAL 7 CRITICAL
L67 NC PGOOD
4.7uH 38 MAX1715_REF 9 REF SKIP 6 L65
3 2 1 1 2 3 4.7uH
1 2 38 1_5V_LX 1_5V_FB 2 FB1 FB2 13 1 2
34
38
38 2_5V_LX
SM4 1
1 NO STUFF AGND THRML R468 SM4
R212 R2211 8 29 15.4K
1%
5.11K 8 7 6 5
0 1/16W 5 6 7 8
1% MF
1/16W 5% 2 402 CRITICAL
MF CRITICAL 1/16W
C738 2 402 Q57 MF
Q54 1 C725 1
C393 1
C405 1
C396
1 1
C307 1
C267 1_5V_FB 34 38
402 2 2_5V_FB 2
10uF 150uF 150uF 150uF
10uF
20%
150uF
20%
150uF
20% 2
IRF7811W
SO-8
4 38 1_5V_DL 1 1
38 2_5V_DL 4 IRF7811W
SO-8
D30
SM
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
TANT
20%
2 6.3V
2 6.3V
CERM 2 6.3V
TANT 2 6.3V
TANT
1
R222 D31 NO STUFF 1 C298 R220 R601 NO STUFF MBRS130LT3 CERM
805
TANT
SMD-1 SMD-1 TANT
SMD-1
805 10K SM 0 10K
SMD-1 SMD-1
1% MBRS130LT3 3 2 10.001uF
C844
1 OMIT 1uF
20% 5% 1% 1 C845 1 2 3
1
1/16W 1 2 10V
1/16W 1/16W 0.001uF
2
MF
402
20%
50V 2 XW25
SM
CERM
603
MF
402 2
MF
2 402
20%
2 50V
CERM CERM
402 1 2 38 34 MAX1715_GND 402
B B
+1_8V_MAIN +1_8V_SLEEP
+3V_MAIN
1.8V SWITCHER +1_8V_MAIN LOADS
1) INTREPID PLLS
39 34 32 29 25 23 SLEEP
R566
1
100K2
5%
4
3 6
5
1/16W
+1_8V_MAIN MF 2
CRITICAL 402
1 +1_8V_SLEEP LOADS
LTC3411_VCC L63 C719 1 TSOP
SI3447DV 1) MPC7447 - MAXBUS I/O - IF 1.8V INTERFACE
34 38
2.2uH 10uF
R531 20%
6.3V U50 2) CPU JTAG & MaxBus Pull-ups
C695 1 1
10 2 LTC3411_VCC 38 1_8V_SW 1 2 CERM 2
NO STUFF 38 34
805 3) CPU PLL Config Straps
1
R398 10uF SM1
1M
20%
6.3V 2
1 5%
R526 1R5271/16W CRITICAL 7 6 R5291 C722
5% CERM
805 10K MF 1M 402 C693 1 1000pF
1/16W 5% 5% SVIN PVIN 10pF 887K 1_8V_SLEEP_PWREN_L 2 1
MF 1/16W 1/16W 1%
2 402 MF MF U46 5%
50V 1/16W
R535 (BURST MODE)
2 402 2 402 LTC3411
MSOP
CERM 2
402
MF
402 2 .
10%
25V
324K 1 NO STUFF X7R
LTC3411_EN_L 2 38 LTC3411_SHDN 1 SHDN/RT SW 4 NO STUFF
C720 1 402
1%
1/16W LTC3411_SYNC 2 SYNC/MODE VFB 9 1_8V_VFB R571 1000pF
MF
38 38
1
SLEEP_L_LS5_INV
100K2 10%
25V 2
402 34
X7R
8 PGOOD ITH 10 38 LTC3411_ITH 5% 402
1/16W
3 PGND SGND 1
R532 1 C697 MF
402
D Q31
2N7002 NO STUFF (CONTINUOUS MODE)
5 3
1%
16.2K 22uF
20% 1.5V/1.8V/2.5V SUPPLIES
2 10V
A 34 32 3V_5V_OK 1 G S
SM 1
R536 R525C690 1 1
1/16W
MF
2 402
R528
698K
1 CERM
1210
A
10K 1M 1uF 1%
2 (PULSE MODE) 5% 5% 20% LTC3411_ITH_RC 38 1/16W
1/16W 1/16W 10V
MF MF CERM 2 MF
402 2
2 402 603
2 402 1 C691 AGREES TO THE FOLLOWING
5%
1000pF OMIT I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
2 25V II NOT TO REPRODUCE OR COPY IT

CERM
603 XW17
SM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
38 LTC3411_GND 1 2 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
34 44 OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GROUP SIG_NAME PROPAGATION_DELAY MAX_VIAS MAX_EXPOSED_LENGTH STUB_LENGTH NET_SPACING_TYPE NO_TEST PULSE_PARAM
CLOCK LINE CONSTRAINTS
GROUP SIG_NAME PROPAGATION_DELAY MATCHED_DELAY MAX VIAS MAX EXPOSED LENGTH STUB_LENGTH NET_SPACING_TYPE PULSE PARAM
INTREPID SYSCLK_CPU_UF
SYSCLK_CPU
L:S::150 MIL
(200)
10 MIL SPACING 167.0 MHz::: 8
L:S:2650 MIL:2750 MIL 5 250.0000 10 MIL SPACING 167.0 MHz:::

CLOCKS INT_CPUFB_OUT L:S::150 MIL 5 250.0000 10 MIL SPACING 167.0 MHz:::
5 8
INT_CPUFB_OUT_SHORT L:S:700 MIL:850 MIL 5 250.0000 10 MIL SPACING 167.0 MHz::: 8
STUB_LENGTH OF 200 MILS NEEDED WHEN WE CONVERT TO 14.2 INT_CPUFB_OUT_NORM L:S:500 MIL:600 MIL 5 250.0000 10 MIL SPACING 167.0 MHz::: 8
INT_CPUFB_IN_NORM L:S:500 MIL:600 MIL 5 250.0000 10 MIL SPACING 167.0 MHz::: 8

(200)
GROUP 0 MEM_DATA<7..0> L:S:1602:1700 7 500 167 MHZ 9 10 INT_CPUFB_LONG
DIGITAL SIGNALS
I261 L:S:1050 MIL:1150 MIL 5 250.0000 10 MIL SPACING 167.0 MHz::: 8
D I262 MEM_DQM<0>
MEM_DQS<0>
L:S:1602 MIL:1700
L:S:1602 MIL:1700
MIL7
MIL7
500.0000
500.0000
(200)
(200)
167.0 MHz::: 9 10
167.0 MHz::: 9 10
INT_CPUFB_IN L:S:700 MIL:800 MIL 5 250.0000 (200) 10 MIL SPACING 167.0 MHz::: 8 D
I263
TOTAL
(200) LENGTH CONTROLLED BY SPREADSHEET
I264 RAM_DATA_A<7..0> L:S:1903:2000 7 500 167 MHZ 10 11
SYSCLK_DDRCLK_A0_UF L:S:300 MIL:350
DDRCLK_A0_UF
MIL SYSCLK_DDRCLK_A0_UF:G:L:S:0 MIL:25
4 MIL (200) 10 MIL SPACING 167.0 MHz::: 9
RAM_DQM_A<0> L:S:1903 MIL:2000 MIL7 500.0000 (200) 167.0 MHz::: 10 11
I265 SYSCLK_DDRCLK_A0_L_UFL:S:300 MIL:350 (200)
(200) DDRCLK_A0_UF
4 MIL 10 MIL SPACING 167.0 MHz::: 9
I266 RAM_DQS_A<0> L:S:1903 MIL:2000 MIL7 500.0000 167.0 MHz::: 10 11
SYSCLK_DDRCLK_A1_UF L:S:300 MIL:350
DDRCLK_A1_UF
RAM_DATA_B<7..0> L:S:2000:2100 7 500 (200) 167 MHZ 10 11
I267 SYSCLK_DDRCLK_A1_L_UFL:S:300 MIL:350 (200)
(200) DDRCLK_A1_UF
I268
RAM_DQM_B<0> L:S:2000 MIL:2100 MIL7 500.0000 167.0 MHz::: 10 11
SYSCLK_DDRCLK_B0_UF L:S:300 MIL:350
DDRCLK_B0_UF
MIL SYSCLK_DDRCLK_B0_UF:G:L:S:0 MIL:25
RAM_DQS_B<0> L:S:2000 MIL:2100 MIL7 500.0000 (200) 167.0 MHz::: 10 11
I269 SYSCLK_DDRCLK_B0_L_UFL:S:300 MIL:350 (200)
(200) DDRCLK_B0_UF
GROUP 1 MEM_DATA<15..8>
MEM_DQM<1>
L:S:1344:1660 7 500
(200)
167 MHZ 9 10
SYSCLK_DDRCLK_B1_UF L:S:300 MIL:350
DDRCLK_B1_UF
L:S:1344 MIL:1660 MIL7 500.0000 167.0 MHz::: 9 10 (200)
(200) SYSCLK_DDRCLK_B1_L_UFL:S:300 MIL:350
DDRCLK_B1_UF
MEM_DQS<1> L:S:1344 MIL:1660 MIL7 500.0000 167.0 MHz::: 9 10
TOTAL LENGTH CONTROLLED BY SPREADSHEET SYSCLK_DDRCLK_A0 L:S:2900 MIL:3000
DDRCLK_A0
MIL SYSCLK_DDRCLK_A0:G:L:S:0 MIL:25
7 MIL 250.0000 (200) 10 MIL SPACING 167.0 MHz:::
9 11
RAM_DATA_A<15..8> L:S:1905:2000 7 500 (200) 167 MHZ 10 11
SYSCLK_DDRCLK_A0_L L:S:2900 MIL:3000
DDRCLK_A0
7 MIL 250.0000 (200) 10 MIL SPACING 167.0 MHz::: 9 11
SYSCLK_DDRCLK_A1 L:S:2900 MIL:3000
DDRCLK_A1
RAM_DQS_A<1> L:S:1905 MIL:2000 MIL7 500.0000 (200) 167.0 MHz::: 10 11
SYSCLK_DDRCLK_A1_L L:S:2900 MIL:3000
DDRCLK_A1
RAM_DATA_B<15..8> L:S:2004:2412 7 500 (200) 167 MHZ 10 11
SYSCLK_DDRCLK_B0 L:S:3100 MIL:3200
DDRCLK_B0
MIL SYSCLK_DDRCLK_B0:G:L:S:0 MIL:25
RAM_DQM_B<1> L:S:2004 MIL:2412 MIL7 500.0000 (200) 167.0 MHz::: 10 11
SYSCLK_DDRCLK_B0_L L:S:3100 MIL:3200
DDRCLK_B0
SYSCLK_DDRCLK_B1 L:S:3100 MIL:3200
DDRCLK_B1
MEM_DATA<23..16> (200)
GROUP 2 I270
MEM_DQM<2>
L:S:1435:1500 7 500
(200)
167 MHZ 9 10
SYSCLK_DDRCLK_B1_L L:S:3100 MIL:3200
DDRCLK_B1
I271 L:S:1435 MIL:1500 MIL7 500.0000 167.0 MHz::: 9 10
MEM_DQS<2> L:S:1435 MIL:1500 MIL7 500.0000 (200) 167.0 MHz::: 9 10 (200)
I272
TOTAL LENGTH CONTROLLED BY SPREADSHEET I260 INT_REF_CLK_OUT_UF L:S::400 MIL 10 MIL SPACING 49.92 MHz::: 14
RAM_DATA_A<23..16> L:S:1707:1800 7 500 (200) 167 MHZ 10 11
I274 I256 INT_REF_CLK_OUT L:S:1000 MIL:1150 MIL 5 250.0000 (200) 10 MIL SPACING 49.92 MHz::: 14
RAM_DQM_A<2> L:S:1707 MIL:1800 MIL7 500.0000 (200) 167.0 MHz::: 10 11 (200)
I273 I257 INT_REF_CLK_IN L:S:1900 MIL:2000 MIL 5 250.0000 10 MIL SPACING 167.0 MHz::: 14
RAM_DQS_A<2> L:S:1707 MIL:1800 MIL7 500.0000 (200) 167.0 MHz::: 10 11 (200)
I275 CLK66M_GPU_AGP_UF L:S::150 MIL 10 MIL SPACING 66.00 MHz::: 12
RAM_DATA_B<23..16> L:S:1900:2000 7 500 (200) 167 MHZ (200)
I277 10 11 CLK66M_GPU_AGP L:S:1800 MIL:1900 MIL 6 400.0000 10 MIL SPACING 66.00 MHz::: 12 19
RAM_DQM_B<2> L:S:1900 MIL:2000 MIL7 500.0000 (200) 167.0 MHz::: 10 11 (200)
I276 INT_AGP_FB_OUT L:S::150 MIL 10 MIL SPACING 66.00 MHz::: 12
RAM_DQS_B<2> L:S:1900 MIL:2000 MIL7 500.0000 (200) 167.0 MHz::: 10 11 (200)
I278 INT_AGP_FB_IN L:S:1450 MIL:1550 MIL 6 500.0000 10 MIL SPACING 66.00 MHz::: 12
(200)
GROUP 3 MEM_DATA<31..24> L:S:1233:1485 7 500 167 MHZ 9 10 CLK33M_CBUS_UF (200)
C
C MEM_DQM<3> L:S:1233 MIL:1485 MIL7 500.0000 (200)
(200)
167.0 MHz::: 9 10 CLK33M_CBUS
L:S::250
L:S:5000
MIL
MIL:6000 MIL 9 500.0000 (200)
10
10
MIL
MIL
SPACING
SPACING
33.00
33.00
MHz::: 12
MHz::: 12 18
MEM_DQS<3> L:S:1233 MIL:1485 MIL7 500.0000 167.0 MHz::: 9 10 CLK33M_AIRPORT_UF (200)
TOTAL LENGTH CONTROLLED BY SPREADSHEET L:S::250 MIL 10 MIL SPACING 33.00 MHz::: 12
RAM_DATA_A<31..24> L:S:1700:2165 7 500 (200) 167 MHZ (200)
10 11 CLK33M_AIRPORT L:S:9500 MIL:10500 MIL 6 500.0000 10 MIL SPACING 33.00 MHz::: 12 24 39
RAM_DQM_A<3> L:S:1700 MIL:2165 MIL7 500.0000 (200) 167.0 MHz::: 10 11 (200)
I259 CLK33M_NEC_UF L:S::250 MIL 10 MIL SPACING 33.00 MHz::: 12
RAM_DQS_A<3> L:S:1700 MIL:2165 MIL7 500.0000 (200) 167.0 MHz::: 10 11 (200)
I258 CLK33M_NEC L:S:4000 MIL:6000 MIL 7 500.0000 10 MIL SPACING 33.00 MHz::: 12 17
RAM_DATA_B<25..24> L:S:1907:2356 7 500 (200) 167 MHZ (200)
10 11 INT_PCI_FB_OUT L:S::300 MIL 10 MIL SPACING 33.00 MHz::: 12
RAM_DATA_B<26> L:S:1907 MIL:2356 MIL7 (200) 167.0 MHz::: 10 11 (200)
I279 INT_PCI_FB_IN L:S:6500 MIL:7500 MIL 7 500.0000 10 MIL SPACING 33.00 MHz::: 12
RAM_DATA_B<31..27> L:S:1907:2356 7 500 (200) 167 MHZ 10 11
I280
(200)
GROUP 4 MEM_DATA<39..32> L:S:1915:2000 7 500
(200)
167 MHZ 9 10
MEM_DQM<4> L:S:1915 MIL:2000 MIL7 500.0000 167.0 MHz::: 9 10

MEM_DQS<4> L:S:1915 MIL:2000 MIL7 500.0000 (200) 167.0 MHz::: 9 10
TOTAL LENGTH CONTROLLED BY
(200) SPREADSHEET ATI_CLK27M_OSC L:S::400 MIL 5 (200) 10 MIL SPACING
RAM_DATA_A<39..32> L:S:1205:1387 7 500 167 MHZ 10 11
19
RAM_DQM_A<4> L:S:1205 MIL:1387 MIL7 500.0000 (200) 167.0 MHz::: 10 11 M10 ATI_CLK27M_OSC_SS L:S::400 MIL 5 (200) 10 MIL SPACING 19
DDR RAM_DQS_A<4> L:S:1205 MIL:1387 MIL7 500.0000 (200) 167.0 MHz::: 10 11
(200)
RAM RAM_DATA_B<39..32> L:S:1404:1686 7 500 (200) 167 MHZ 10 11 & ATI_CLK27M_IN L:S::200 MIL 5 10 MIL SPACING 19 20
RAM_DQM_B<4> L:S:1404 MIL:1686 MIL7 500.0000 (200) 167.0 MHz::: 10 11 (200)

ATI_SSCLK_UF L:S::200 MIL 5 10 MIL SPACING 19
PRIORITY: 2
OSC (200)
(200)
GROUP 5 MEM_DATA<47..40> L:S:1719:1893 7 500
(200)
167 MHZ 9 10
PRIMARY LAYERS: 4,7
ATI_SSCLK_IN L:S::1800 MIL 5 500.0000 10 MIL SPACING 19 20
MEM_DQM<5> L:S:1719 MIL:1893 MIL7 500.0000 167.0 MHz::: 9 10 SECONDARY LAYERS: 2,9
TOTAL LENGTH CONTROLLED BY SPREADSHEET GOAL: MINIMIZE
RAM_DATA_A<47..40> L:S:1607:1898 7 500 (200) 167 MHZ 10 11 EXPOSED ROUTES
RAM_DQM_A<5> L:S:1607 MIL:1898 MIL7 500.0000 (200) 167.0 MHz::: 10 11 MINIMIZE VIAS CRYSTALS CLK18M_INT_XIN L:S:1400 MIL:1500 MIL 10 MIL SPACING 14
RAM_DQS_A<5> L:S:1607 MIL:1898 MIL7 500.0000 (200) 167.0 MHz::: 10 11 CLK18M_INT_XOUT L:S:1250 MIL:1350 MIL 10 MIL SPACING 14
RAM_DATA_B<47..40> L:S:1716:2102 7 500 (200) 167 MHZ 10 11

CLK18M_XTAL_IN
B RAM_DQM_B<5>
RAM_DQS_B<5>
L:S:1716 MIL:2102
L:S:1716 MIL:2102
MIL7
MIL7
500.0000
500.0000
(200)
(200)
167.0 MHz::: 10 11
167.0 MHz::: 10 11 CLK18M_INT_EXT
L:S::300 MIL
L:S::400 MIL
10 MIL SPACING
10 MIL SPACING
14
14
B
(200)
GROUP 6 MEM_DATA<55..48> L:S:2101:2170 7 500
(200)
167 MHZ 9 10

(200) (200)
MEM_DQS<6>
RAM_DATA_A<55..48>
L:S:2101 MIL:2170 MIL7 500.0000
TOTAL LENGTH CONTROLLED BY
(200)
167.0 MHz::: 9 10
SPREADSHEET SOUND INT_I2S0_SND_MCLK 6 500.0000 10 MIL SPACING 14 25 39
L:S:1204:1357 7 500 167 MHZ 10 11

(200)
RAM_DQM_A<6>
RAM_DQS_A<6>
L:S:1204 MIL:1357 MIL7 500.0000
(200)
167.0 MHz::: 10 11 ETHERNET CLKENET_PHY_RX L:S::300 MIL (200) 125.0 MHz::: 26
L:S:1204 MIL:1357 MIL7 500.0000 167.0 MHz::: 10 11 (200)
(200) CLKENET_LINK_RX L:S:8000 MIL:9000 MIL 6 800.0000 10 MIL SPACING 125.0 MHz::: 13 26
RAM_DATA_B<55..48> L:S:1400:1546 7 500 167 MHZ 10 11
CLKENET_PHY_GBE_REF L:S::300 MIL (200) 125.0 MHz::: 26
CLKENET_LINK_GBE_REF L:S:8000 MIL:9000 MIL 6 500.0000 (200) 10 MIL SPACING 125.0 MHz::: 13 26
CLKENET_PHY_TX L:S::300 MIL (200) 25.00 MHz::: 26
(200)
GROUP 7 MEM_DATA<63..56> L:S:1903:2000 7 500
(200)
167 MHZ 9 10
CLKENET_LINK_TX L:S:8000 MIL:9000 MIL 6 500.0000 (200) 10 MIL SPACING 25.00 MHz::: 13 26
CLKENET_LINK_GTX L:S::300 MIL (200) 125.0 MHz::: 13
TOTAL LENGTH CONTROLLED BY SPREADSHEET CLKENET_PHY_GTX L:S:8000 MIL:9000 MIL 6 600.0000 (200) 10 MIL SPACING 125.0 MHz::: 13 26
RAM_DATA_A<63..56> L:S:1611:1696 7 500 (200) 167 MHZ 10 11

CLKFW_PHY_PCLK L:S::300 MIL (200) 49.15 MHz:::
RAM_DQS_A<7> L:S:1611 MIL:1696 MIL7 500.0000 (200) 167.0 MHz::: 10 11 FIREWIRE CLKFW_LINK_PCLK L:S:7500 MIL:8000 MIL 5 500.0000 (200) 10 MIL SPACING 49.15 MHz:::
27
13 27
RAM_DATA_B<63..56> L:S:1809:1887 7 500 (200) 167 MHZ 10 11
CLKFW_PHY_LCLK L:S:7500 MIL:8000 MIL 5 500.0000 (200) 10 MIL SPACING 49.15 MHz::: 13 27
CLKFW_LINK_LCLK L:S::300 MIL (200) 49.15 MHz::: 13
FW_XI L:S::500 MIL (200) 10 MIL SPACING 98.03 MHz::: 27
ADDR MEM_ADDR<12..0> L:S::500 4
(200)
83 MHZ 9
FW_OSC L:S::300 MIL (200) 10 MIL SPACING 98.03 MHz::: 27
RAM_ADDR<12..0> L:S:2000:3000 10 9 11
MEM_BA<1..0> L:S::500 4 9
RAM_BA<1..0> L:S:2000:3300 8 (200) 9 11
MEM_CS_L<3..0> L:S::500 4
CONTROL RAM_CS_L<3..0> L:S:2500:3200 7 (200)
9
9 11
SIGNAL CONSTRAINTS - PAGE 1
A MEM_CKE<3..0> L:S::500 4
(200)
9
PRIORITY: 1 NOTICE OF PROPRIETARY PROPERTY
A
RAM_CKE<3..0> L:S:2500:3200 7 9 11
PRIMARY LAYERS: 4,7
MEM_RAS_L L:S::500 MIL 4 9 SECONDARY LAYERS: 2,9 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
RAM_RAS_L L:S:2000 MIL:4100 MIL7 (200) 9 11
GOAL: MINIMIZE EXPOSURE ON LONG NETS PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MEM_CAS_L L:S::500 MIL 4 9
RAM_CAS_L L:S:2000 MIL:4100 MIL7 (200) 9 11
MEM_WE_L L:S::500 MIL 4 9
RAM_WE_L L:S:2000 MIL:3100 MIL8 (200) 9 11
MEM_MUXSEL_MSB L:S:1700 MIL:3000 MIL8 9 10 APPLE COMPUTER INC.

D 051-6653 C
MEM_MUXSEL_LSB L:S:1700 MIL:3000 MIL7 9 10
SCALE
NONE
SHT
35 44 OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GROUP SIG_NAME PROPAGATION_DELAY MAX_VIAS MAX_EXPOSED_LENGTH STUB_LENGTH NET_SPACING_TYPE NO_TEST PULSE_PARAM
CPU_AACK_L L:S:1500 MIL:2700 MIL7 (250) 5 8
MAXBUS CPU_ADDR<0..31>
CPU_ARTRY_L
L:S:1500:3100
L:S:1500 MIL:2700
7
MIL7
(250)
(250)
TRUE 83 MHZ 5 8
5 8
Temporary Area for TMDS/DVO signal constraints
CPU_BG_L L:S:1500 MIL:2700 MIL7 (250) 5 8
CPU_BR_L L:S:1500 MIL:2700 MIL7 (250) 5 8 ALL TMDS GROUP SIGNALS ROUTE AT LAYER 4 OR 7 AND HAVE SAME WIDTH SPACING RULE AS OTHER TMDS SIGNALES
CPU_CI_L L:S:1500 MIL:2700 MIL7 (250) 5 8 100 OHM SPACING
CPU_DATA<0..31> (250) I231GPU_TMDS_CLKN GPU_CLKTMDS GPUTMDS:G:L:S:0 MIL:50 MIL 500.0000 100 OHM SPACING 5 19 20
L:S:1100:2700 7 TRUE 83 MHZ 6 8 100 OHM SPACING
CPU_DATA<32..63> (250) I233GPU_TMDS_CLKP GPU_CLKTMDS GPUTMDS:G:L:S:0 MIL:50 MIL 500.0000 100 OHM SPACING 5 19 20
L:S:1100:2700 8 83 MHZ 6 8 100 OHM SPACING
CPU_DBG_L (250) I232GPU_TMDS_DN<0> GPU_TMDS_D0 500.0000 100 OHM SPACING 8 19 20
L:S:1500 MIL:2700 MIL7 5 8 PRIORITY: 4 100 OHM SPACING
I234GPU_TMDS_DP<0> GPU_TMDS_D0 500.0000 100 OHM SPACING 8 19 20
DIGITAL SIGNALS
CPU_DTI<0..2> (250) 100 OHM SPACING

D CPU_DRDY_L
L:S:1500:2950
L:S:1500 MIL:3200
7
MIL7 (250)
5 8
5 8
PRIMARY LAYERS: 9
SECONDARY LAYERS: 4,7 I235GPU_TMDS_DN<1>
GPU_TMDS_DP<1>
GPU_TMDS_D1
GPU_TMDS_D1
600.0000
600.0000
100 OHM SPACING
100 OHM SPACING
100 OHM SPACING
8
8
19 20
19 20
D
CPU_GBL_L (250) I236
L:S:1500 MIL:2700 MIL7 5 8 GOAL: MINIMIZE TH VIAS 100 OHM SPACING
CPU_HIT_L (250) I238GPU_TMDS_DN<2> GPU_TMDS_D2 830.0000 100 OHM SPACING 8 19 20
L:S:1500 MIL:2800 MIL7 5 8 100 OHM SPACING
CPU_QACK_L (250) I237GPU_TMDS_DP<2> GPU_TMDS_D2 830.0000 100 OHM SPACING 8 19 20
L:S:1500 MIL:2700 MIL7 5 8
CPU_QREQ_L L:S:1500 MIL:2700 MIL7 (250) 5 8
CPU_TA_L L:S:1500 MIL:2700 MIL7 (250) 5 8 100 OHM SPACING

I240
SI_TMDS_CLKN SI_CLKTMDS SITMDS:G:L:S:0 MIL:50 MIL 100 OHM SPACING 5 19
CPU_TBST_L L:S:1500 MIL:2700 MIL7 (250) 5 8 100 OHM SPACING
(250) I239 SI_TMDS_CLKP SI_CLKTMDS SITMDS:G:L:S:0 MIL:50 MIL 100 OHM SPACING 5 19
CPU_TEA_L L:S:1500 MIL:3000 MIL7 5 8 100 OHM SPACING
I242 SI_TMDS_DN<0> SI_TMDS_D0 100 OHM SPACING 8 19
CPU_TS_L L:S:1500 MIL:2700 MIL7 (250) 5 8 100 OHM SPACING
(250) I241 SI_TMDS_DP<0> SI_TMDS_D0 100 OHM SPACING 8 19
CPU_TSIZ<0..2> L:S:1500:3500 7 5 8 100 OHM SPACING
(250) I243 SI_TMDS_DN<1> SI_TMDS_D1 100 OHM SPACING 8 19
CPU_TT<0..4> L:S:1500:3400 7 100 OHM SPACING
5 8
(250) I245 SI_TMDS_DP<1> SI_TMDS_D1 100 OHM SPACING 8 19
CPU_WT_L L:S:1500 MIL:3100 MIL7 5 8 100 OHM SPACING
I244 SI_TMDS_DN<2> SI_TMDS_D2 100 OHM SPACING 8 19
100 OHM SPACING
I246 SI_TMDS_DP<2> SI_TMDS_D2 100 OHM SPACING 8 19
STUB_LENGTH OF 250 MILS NEEDED WHEN DESIGN SWITCHED TO 14.2
ALL THE DVOD GROUP SIGNALS ROUTE AT LAYER 4 OR 7 AND ROUTE AS STANDARD 50OHM SIGNALS AT 4 MILS
ATI_DVOD<11..0> ATIDVOD:G:L:S:0 MIL:50 MIL 6 610 19 20

I263
I265 ATI_DVOD_DE ATIDVOD:G:L:S:0 MIL:50 MIL 6 610.0000 19 20
ATI_DVO_HSYNC ATIDVOD:G:L:S:0 MIL:50 MIL 6 610.0000 19 20

I264
I267
ATI_DVO_VSYNC ATIDVOD:G:L:S:0 MIL:50 MIL 6 610.0000 19 20
I266 ATI_DVO_CLKP ATIDVOD:G:L:S:0 MIL:50 MIL 6 610.0000 165.0 MHz::: 19 20
C 700
C
I258
GPU_DVOD<11..0> GPUDVOD:G:L:S:0 MIL:50 MIL 6 19
I259 GPU_DVOD_DE GPUDVOD:G:L:S:0 MIL:50 MIL 6 500.0000 19
GPU_DVO_HSYNC GPUDVOD:G:L:S:0 MIL:50 MIL 6 500.0000 19

I260
I261
GPU_DVO_VSYNC GPUDVOD:G:L:S:0 MIL:50 MIL 6 500.0000 19
I262 GPU_DVO_CLKP GPUDVOD:G:L:S:0 MIL:50 MIL 6 500.0000 165.0 MHz::: 19
TMDS_CONN_CLKN
100 OHM SPACING
I268 CLKCONN_TMDS TMDS_CONN:G:L:S:0 MIL:50 MIL 500.0000 100 OHM SPACING 4 22 39
100 OHM SPACING
TMDS_CONN_CLKP
I269 CLKCONN_TMDS TMDS_CONN:G:L:S:0 MIL:50 MIL 500.0000 100 OHM SPACING 4 22 39
100 OHM SPACING
TMDS_CONN_DN<0>
I271 CONN_TMDS_D0 500.0000 100 OHM SPACING 4 22
TMDS_CONN_DP<0>
100 OHM SPACING
100 OHM SPACING
TMDS_CONN_DN<1>
TMDS_CONN_DP<1>
100 OHM SPACING
TMDS_CONN_DN<2>
100 OHM SPACING
100 OHM SPACING
TMDS_CONN_DP<2>
B B

A
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
36 44
OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Digital Signals (cont’d) Differential Signals
GROUP SIG_NAME PROPAGATION_DELAY
MAX_VIASMAX_EXPOSED_LENGTH
STUB_LENGTH NET_SPACING_TYPE NO_TEST PULSE_PARAM GROUP SIG_NAME DIFFERENTIAL_PAIR RELATIVE_PROPAGATION_DELAY
MAX_EXPOSED_LENGTH
NET_SPACING_TYPE
MAX_VIAS
FW_TPI0N FW_TPI0 FW_TPI0:G:L:S:0 MIL:5 MIL 500.0000 110 OHM SPACING 27 28 39
FIREWIRE I241
AGP AGP_AD<15..0> L:S:1050:1450 7 66 MHz 12 19 Zo = 110 I242FW_TPI0P FW_TPI0 FW_TPI0:G:L:S:0 MIL:5 MIL 500.0000 110 OHM SPACING 27 28 39
AGP BYTES 0-1 AGP_CBE<1..0> L:S:1050:1450 7 66 MHz 12 19 I244FW_TPO0N FW_TPO0 FW_TPO0:G:L:S:0 MIL:5 MIL 500.0000 110 OHM SPACING 27 28 39
AGP_AD_STB<0>
AGP_AD_STB_L<0>
L:S:1050 MIL:1450
L:S:1050 MIL:1450
6MIL
6MIL
(250)
(250)
8 MIL SPACING
8 MIL SPACING
133.0 MHz::: 12 19
133.0 MHz::: 12 19
I243FW_TPO0P
FW_TPBI0N
FW_TPO0
FW_TPBI0
FW_TPO0:G:L:S:0 MIL:5 MIL
FW_TPBI0:G:L:S:0 MIL:5 MIL
500.0000
500.0000
110
110
OHM
OHM
SPACING
SPACING
27 28 39
28
LAYERS 4 OR 7
AGP BYTES 2-3 AGP_AD<31..16> L:S:1050:1450 7 66 MHz 12 19 FW_TPBI0P FW_TPBI0 FW_TPBI0:G:L:S:0 MIL:5 MIL 500.0000 110 OHM SPACING 28 Er = 4.3 (DIELECTRIC CONSTANT)
AGP_CBE<3..2> L:S:1050:1450 7
(250)
66 MHz 12 19 FW_TPAO0N FW_TPAO0 FW_TPAO0:G:L:S:0 MIL:5 MIL 500.0000 110 OHM SPACING 28
W = 3MIL (TRACE WIDTH)
AGP_AD_STB<1> L:S:1050 MIL:1450 6MIL 8 MIL SPACING 133.0 MHz::: 12 PRIORITY: 4 FW_TPAO0P FW_TPAO0 FW_TPAO0:G:L:S:0 MIL:5 MIL 500.0000 110 OHM SPACING
AGP_AD_STB_L<1> L:S:1050 MIL:1450 6MIL (250) 8 MIL SPACING
19
133.0 MHz::: 12 PRIMARY LAYERS: 9 FW_TPA1N FW_TPA1 FW_TPA1:G:L:S:0 MIL:4% 500.0000 110 OHM SPACING
28
27 28
S = 11MIL (TRACE SEPERATION)
D AGP SIDEBAND AGP_SBA<7..0> L:S:1050:1450 7 66 MHz
19
12 19
SECONDARY LAYERS: 4,7 FW_TPA1P FW_TPA1 FW_TPA1:G:L:S:0 MIL:4% 500.0000 110 OHM SPACING 27 28
H = 16.8MIL (DIST BETW PLANES)D
AGP_SB_STB L:S:1050 MIL:1450 6MIL (350) 8 MIL SPACING 66.00 MHz::: 12 GOAL: MINIMIZE TH VIAS FW_TPB1N FW_TPB1 FW_TPB1:G:L:S:0 MIL:4% 500.0000 110 OHM SPACING 27 28
T = 0.6MIL (TRACE THICKNESS)
19
AGP_SB_STB_L L:S:1050 MIL:1450 6MIL (350) 8 MIL SPACING 66.00 MHz::: 12 19 FW_TPB1P FW_TPB1 FW_TPB1:G:L:S:0 MIL:4% 500.0000 110 OHM SPACING 27 28
AGP CONTROL AGP_FRAME_L L:S:1250 MIL:1950 6MIL 66.00 MHz::: 12 19 FW_TPI1N FW_TPI1 FW_TPI1:G:L:S:0 MIL:4% 500.0000 110 OHM SPACING 28 39
Zo(diff) = 106.2 OHMS
AGP_IRDY_L L:S:1250 MIL:1950 6MIL 66.00 MHz::: 12 19 FW_TPI1P FW_TPI1 FW_TPI1:G:L:S:0 MIL:4% 500.0000 110 OHM SPACING 28 39
Zo(single) = 55.4 OHMS
AGP_TRDY_L L:S:1250 MIL:1950 6MIL 66.00 MHz::: 12 19 FW_TPO1N FW_TPO1 FW_TPO1:G:L:S:0 MIL:4% 500.0000 110 OHM SPACING 28 39
AGP_DEVSEL_L L:S:1250 MIL:1950 7MIL 66.00 MHz::: 12 19 FW_TPO1P FW_TPO1 FW_TPO1:G:L:S:0 MIL:4% 500.0000 110 OHM SPACING 28 39
Clear adjacent power plane!
AGP_STOP_L L:S:1250 MIL:1950 6MIL 66.00 MHz::: 12 19
MDI_P<0>
ENET 11 MIL SPACING Zo will be lower due to
ETHERNET ENET_MDI0 ENET_MDI0:G:U43.29:J23.1:0 MIL:100 MIL ENET 11 MIL SPACING 26 39
AGP_PAR L:S:1250 MIL:1950 6MIL 66.00 MHz::: 12 19
MDI_M<0>
ENET 11 MIL SPACING asymmetric stackup.
Zo = 100 ENET_MDI0 ENET_MDI0:G:U43.31:J23.2:0 MIL:100 MIL ENET 11 MIL SPACING 26 39
AGP_REQ_L L:S:1250 MIL:1950 6MIL 66.00 MHz::: 12 19 ENET 11 MIL SPACING
MDI_P<1> ENET_MDI1 ENET_MDI1:G:U43.33:J23.3:0 MIL:100 MIL ENET 11 MIL SPACING 26 39
AGP_GNT_L L:S:1250 MIL:1950 6MIL 66.00 MHz::: 12 19 ENET 11 MIL SPACING
MDI_M<1> ENET_MDI1 ENET_MDI1:G:U43.34:J23.4:0 MIL:100 MIL ENET 11 MIL SPACING 26 39
AGP_RBF_L L:S:1250 MIL:1950 6MIL 66.00 MHz::: 19
12 ENET 11 MIL SPACING
MDI_P<2> ENET_MDI2 ENET_MDI2:G:U43.39:J23.7:0 MIL:100 MIL ENET 11 MIL SPACING 26 39
ENET 11 MIL SPACING
MDI_M<2> ENET_MDI2 ENET_MDI2:G:U43.41:J23.8:0 MIL:100 MIL ENET 11 MIL SPACING 26 39
PCI_AD<31..0> L:S:6000:12500 MIN_DAISY_CHAIN 33 MHz 9 12 17 18 24 ENET 11 MIL SPACING
PCI PCI_CBE<3..0> L:S:6000:12500 MIN_DAISY_CHAIN 33 MHz
39
12 17 18 24
MDI_P<3>
MDI_M<3>
ENET_MDI3 ENET_MDI3:G:U43.42:J23.9:0 MIL:100 MIL ENET 11 MIL SPACING
ENET 11 MIL SPACING
26 39
ENET_MDI3 ENET_MDI3:G:U43.43:J23.10:0 MIL:100 MIL ENET 11 MIL SPACING 26 39

PCI_FRAME_L L:S:6000 MIL:12500 MIL MIN_DAISY_CHAIN 33.00 MHz::: 12 17 18 24 PRIORITY: 7
PCI_IRDY_L
39
CLKLVDS_LN
100 OHM SPACING
L:S:6000 MIL:12500 MIL MIN_DAISY_CHAIN 33.00 MHz::: 39
12 17 18 24 PRIMARY
LVDS CLKLVDS_L LVDS:G:L:S:0 MIL:110 MIL 500.0000 100 OHM SPACING 4 20 22 39
LAYERS: 4,7 100 OHM SPACING
PCI_TRDY_L L:S:6000 MIL:12500 MIL MIN_DAISY_CHAIN 33.00 MHz::: 12 17 18 24 39 Zo = 100 CLKLVDS_LP CLKLVDS_L LVDS:G:L:S:0 MIL:110 MIL 500.0000 100 OHM SPACING 4 20 22 39
PCI_DEVSEL_L SECONDARY LVDS_L0N

100 OHM SPACING
L:S:6000 MIL:12500 MIL MIN_DAISY_CHAIN 33.00 MHz::: 12 17 18 24 LAYERS: 2,9 LOWER LVDS_L0 LVDS:G:L:S:0 MIL:110 MIL 500.0000 100 OHM SPACING 20 22 39
39 100 OHM SPACING
PCI_STOP_L L:S:6000 MIL:12500 MIL MIN_DAISY_CHAIN 33.00 MHz::: 12 17 18 24 39 LVDS_L0P LVDS_L0 LVDS:G:L:S:0 MIL:110 MIL 500.0000 100 OHM SPACING 20 22 39
100 OHM SPACING
PCI_PAR L:S:6000 MIL:12500 MIL MIN_DAISY_CHAIN 33.00 MHz::: 12 17 18 24 LVDS_L1N LVDS_L1 LVDS:G:L:S:0 MIL:110 MIL 500.0000 100 OHM SPACING 20 22 39
39
LVDS_L1P
100 OHM SPACING
LVDS_L1 LVDS:G:L:S:0 MIL:110 MIL 500.0000 100 OHM SPACING 20 22 39
ULTRA ATA-100 UIDE_DATA<15..8> L:S::710 (200)
100 MHZ 100 OHM SPACING
100 OHM SPACING
13 24 LVDS_L2N LVDS_L2 LVDS:G:L:S:0 MIL:110 MIL 500.0000 20 22 39
UIDE_DATA<7> U51.V1:RP19.3::600 MIL (200) 100.0 MHz::: 13 24 LVDS_L2P
100 OHM SPACING
LVDS_L2 LVDS:G:L:S:0 MIL:110 MIL 500.0000 100 OHM SPACING 20 22 39
100 OHM SPACING
UIDE_DATA<6..0>
UIDE_ADDR<2..0>
L:S::600
L:S::650 (200)
(200)
NEED TO MATCH
100 MHZ
DELAY TO 250
100 MHZ
13 24
13 24
UPPER
CLKLVDS_UN CLKLVDS_U LVDS:G:L:S:0 MIL:110 MIL 500.0000 100
100
OHM
OHM
SPACING 4
SPACING 4
20 22 LAYERS 4 OR 7
CLKLVDS_UP CLKLVDS_U LVDS:G:L:S:0 MIL:110 MIL 500.0000 100 OHM SPACING 20 22
(200) 100 OHM SPACING
UIDE_RST_L L:S::400 MIL 100.0 MHz::: 13 24 LVDS_U0N Er = 4.3 (DIELECTRIC CONSTANT)C
C UIDE_DIOW_L L:S::400 MIL (200)
(200)
100.0 MHz::: 13 24 LVDS_U0P
LVDS_U0
LVDS_U0
LVDS:G:L:S:0
LVDS:G:L:S:0
MIL:110
MIL:110
MIL
MIL
500.0000
500.0000
100
100
100
100
OHM
OHM
OHM
OHM
SPACING
SPACING
SPACING
SPACING
20 22
20 22
W = 3.1MIL (TRACE WIDTH)
UIDE_DIOR_L L:S::600 MIL 10 MIL SPACING 100.0 MHz::: 13 24 LVDS_U1N LVDS_U1 LVDS:G:L:S:0 MIL:110 MIL 500.0000 100 OHM SPACING
UIDE_DMACK_L L:S::400 MIL (200) 100.0 MHz::: 13 24 LVDS_U1P LVDS_U1 LVDS:G:L:S:0 MIL:110 MIL 500.0000
100
100
OHM
OHM
SPACING
SPACING
20 22
20 22
S = 4.9MIL (TRACE SEPERATION)
UIDE_CS0_L L:S::500 MIL (200)
100.0 MHz::: 13 24 LVDS_U2N LVDS_U2 LVDS:G:L:S:0 MIL:110 MIL 500.0000
100
100
OHM
OHM
SPACING
SPACING 20 22
H = 9.6MIL (DIST BETW PLANES)
(200) 100 OHM SPACING
UIDE_CS1_L L:S::500 MIL
(200)
100.0 MHz::: 13 24
PRIORITY: 6
LVDS_U2P LVDS_U2 LVDS:G:L:S:0 MIL:110 MIL 500.0000 100 OHM SPACING 20 22 T = 0.6MIL (TRACE THICKNESS)
UIDE_DMARQ L:S::400 MIL 100.0 MHz::: 13
UIDE_IOCHRDY L:S::600 MIL 10 MIL SPACING (200)
100.0 MHz::: 13 24 PRIMARY TMDS
UIDE_INTRQ L:S::400 MIL (200) 100.0 MHz::: 13
LAYERS: 4,7 Zo = 100
100 OHM SPACING
Zo(diff) = 94 OHMS
HD_DATA<15..0> L:S:5000:6500 7 (200) 100 MHZ 24
SECONDARY
LAYERS: 2,9
TMDS_CLKN CLKTMDS TMDS:G:L:S:0 MIL:50 MIL 500.0000 100 OHM SPACING 5 19 22 Zo(single) = 50 OHMS
(200) TMDS_CLKP CLKTMDS TMDS:G:L:S:0 MIL:50 MIL 500.0000 100
100 OHM
OHM SPACING
SPACING 5
HD_ADDR<2..0> L:S:5000:6500 7 100 MHZ 24
19 22
100 OHM SPACING
HD_RESET_L L:S:4000 MIL:6000 7MIL (200) TOTAL UIDE+HD SKEW <500MIL
100.0 MHz::: 24 TMDS_DN<0> TMDS_D0 500.0000 100 OHM SPACING 8 19 22 39
100 OHM SPACING
HD_DIOW_L (200) TMDS_DP<0> TMDS_D0 500.0000 100 OHM SPACING 8 19 22 39
L:S:3000 MIL:5200 7MIL 100.0 MHz::: 24 100 OHM SPACING
HD_DIOR_L L:S:6100 MIL:6150 7MIL 10 MIL SPACING (200) 100.0 MHz::: 24 TMDS_DN<1> TMDS_D1 500.0000 100 OHM SPACING 8 19 22 39
TMDS_DP<1>
100
100 OHM
OHM SPACING
SPACING
HD_DMACK_L L:S:4500 MIL:6000 7MIL (200) 100.0 MHz::: 24 TMDS_D1 500.0000 8 19 22 39
(200) TMDS_DN<2> TMDS_D2 500.0000 100

100 OHM SPACING
OHM SPACING 8
HD_CS0_L L:S:3000 MIL:6000 7MIL 100.0 MHz::: 24 100 OHM SPACING
19 22 39
HD_CS1_L L:S:3000 MIL:6000 7MIL (200) 100.0 MHz::: 24 TMDS_DP<2> TMDS_D2 500.0000 100 OHM SPACING 8 19 22 39
100 OHM SPACING
HD_DMARQ L:S:4500 MIL:6000 7MIL (200) 100.0 MHz::: 13 24 I233ATI_TMDS_CLKN ATI_CLKTMDS ATITMDS:G:L:S:0 MIL:50 MIL 200.0000 100 OHM SPACING 5 20
100 OHM SPACING
HD_IOCHRDY L:S:6200 MIL:6300 7MIL 10 MIL SPACING (200)
100.0 MHz::: 24 I234ATI_TMDS_CLKP ATI_CLKTMDS ATITMDS:G:L:S:0 MIL:50 MIL 200.0000 100 OHM SPACING 5 20
100
100 OHM SPACING
OHM SPACING
HD_INTRQ L:S:3000 MIL:5000 7MIL 100.0 MHz::: 13 24 I235ATI_TMDS_DN<0> ATI_TMDS_D0 200.0000 8 20
100 OHM SPACING
I236ATI_TMDS_DP<0> ATI_TMDS_D0 200.0000 100 OHM SPACING 8 20
100 OHM SPACING
EIDE EIDE_DATA<15..0>
EIDE_ADDR<2..0>
L:S::850
L:S::850
33 MHZ
33 MHZ
13 24
I237ATI_TMDS_DN<1> ATI_TMDS_D1 200.0000 100
100
OHM SPACING
OHM SPACING
8 20
I238ATI_TMDS_DP<1>
13 24
ATI_TMDS_D1 200.0000 100 OHM SPACING 8 20
INTREPID EIDE_CS0_L L:S::850 MIL 33.00 MHz::: 13 24 100 OHM SPACING
I240ATI_TMDS_DN<2> ATI_TMDS_D2 500.0000 100 OHM SPACING 8 20
EIDE_CS1_L L:S::850 MIL 33.00 MHz::: 13 24 USB 1.1I239ATI_TMDS_DP<2> ATI_TMDS_D2 500.0000 100 OHM SPACING
100 OHM SPACING 8 20
EIDE_RD_L L:S::500 MIL 33.00 MHz::: 13 24 Zo = 90
EIDE_WR_L L:S::500 MIL 33.00 MHz::: 13 24
USB_DEM USB_DE USB_DE:G:L:S:0 MIL:200 MIL 5.6 MIL SPACING 14
EIDE_IOCHRDY
B EIDE_INT
L:S::500 MIL
L:S::500 MIL
33.00 MHz::: 13 24
33.00 MHz::: 13 24
USB_DEP USB_DE USB_DE:G:L:S:0 MIL:200 MIL 5.6 MIL SPACING 14 LAYERS 4 OR 7 B
EIDE_RST_L L:S::500 MIL 33.00 MHz::: 13 24
USB_DFM USB_DF USB_DF:G:L:S:0 MIL:200 MIL 5.6 MIL SPACING 14
Er = 4.3 (DIELECTRIC CONSTANT)
USB_DFP USB_DF USB_DF:G:L:S:0 MIL:200 MIL 5.6 MIL SPACING
EIDE_DMACK_L L:S::500 MIL 33.00 MHz::: 13 24
BT_USB_DM BT_USB_D BT_USB:G:L:S:0 MIL:200 MIL 5.6 MIL SPACING
14
14 25 39
W = 3.9MIL (TRACE WIDTH)
PRIORITY: 8
EIDE_DMARQ L:S::500 MIL 33.00 MHz::: 13 24
BT_USB_DP BT_USB_D BT_USB:G:L:S:0 MIL:200 MIL 5.6 MIL SPACING 14 25 39
S = 5.6MIL (TRACE SEPERATION)
EIDE_OPTICAL_DATA<15..0>
L:S:4000:6000 33 MHZ PRIMARY
OPTICAL EIDE_OPTICAL_ADDR<2..0>L:S:4000:6000 33 MHZ
24 39
24 39
LAYERS: 4,7 USB 2.0 MODEM_USB_DM MODEM_USB_D MODEM_USB:G:L:S:0 MIL:200 MIL 5.6 MIL SPACING 14 25 39 H = 9.6MIL (DIST BETW PLANES)
Zo = 90
EIDE_OPTICAL_CS0_L L:S:4500 MIL:6500 MIL 33.00 MHz::: 24 39 SECONDARY
LAYERS: 2,9
MODEM_USB_DP MODEM_USB_D MODEM_USB:G:L:S:0 MIL:200 MIL 5.6 MIL SPACING 14 25 39
T = 0.6MIL (TRACE THICKNESS)
EIDE_OPTICAL_CS1_L L:S:4500 MIL:6500 MIL 33.00 MHz::: 24 39 NEC_USB_DAM USB_D1 USB_D1:G:L:S:0 MIL:20 MIL 500.0000 90 OHM SPACING 17 25 39
EIDE_OPTICAL_READ_L L:S:4500 MIL:6500 MIL 33.00 MHz::: 24 39 NEC_USB_DAP USB_D1 USB_D1:G:L:S:0 MIL:20 MIL 500.0000 90 OHM SPACING 17 25 39
Zo(diff) = 89.8 OHMS
EIDE_OPTICAL_WR_L L:S:4500 MIL:6500 MIL 33.00 MHz::: 24 39 NEC_USB_DBM USB_D2 USB_D2:G:L:S:0 MIL:20 MIL 500.0000 90 OHM SPACING 17 25 39 Zo(single) = 46.6 OHMS
EIDE_OPTICAL_IOCHRDY L:S:4500 MIL:6500 MIL 33.00 MHz::: 24 39 NEC_USB_DBP USB_D2 USB_D2:G:L:S:0 MIL:20 MIL 500.0000 90 OHM SPACING 17 25 39
EIDE_OPTICAL_INT L:S:5000 MIL:7000 MIL 33.00 MHz::: 24 39
EIDE_OPTICAL_RST_L L:S:4500 MIL:6500 MIL 33.00 MHz::: 24 39 1772_CSSN 1772_CSS 1772_CSS:G:L:S:0 MIL:100 MIL 30
EIDE_OPTICAL_DMAACK_L L:S:4500 MIL:6500
POWER
MIL 33.00 MHz::: 24 39 1772_CSSP 1772_CSS 1772_CSS:G:L:S:0 MIL:100 MIL
EIDE_OPTICAL_DMA_RQ
SUPPLIES 30
L:S:4500 MIL:6500 MIL 33.00 MHz::: 24 39 1772_CSIN 1772_CSI 1772_CSI:G:L:S:0 MIL:100 MIL 30
1772_CSIP 1772_CSI 1772_CSI:G:L:S:0 MIL:100 MIL 30

ETHERNET MII
3V_SNSM
ENET_LINK_RXD<7..0>
ENET_RX_DV
L:S:8000:9000
L:S:8000 MIL:9000
7
MIL
(400) (400) 13 26
13 26
3V_SNSP
3V_SNS
3V_SNS
3V_SNS:G:L:S:0
3V_SNS:G:L:S:0
MIL:100
MIL:100
MIL
MIL
32
32
LAYERS 2 OR 9
ENET_RX_ER 5V_SNSM 5V_SNS 5V_SNS:G:L:S:0 MIL:100 MIL 32
L:S:8000 MIL:9000 MIL 13 26
ENET_PHY_TXD<7..0> L:S:8000:9000 7 (400) (400) 13 26

5V_SNSP 5V_SNS 5V_SNS:G:L:S:0 MIL:100 MIL 32
ENET_LINK_TXD<7..0> L:S::600 13 THERMOSTAT THERM1_DM THERM1:G:L:S:0 MIL:100 MIL 25

PRIORITY: 5
ENET_PHY_TX_ER L:S:8000 MIL:9000 7MIL 13 26 THERM1_DP THERM1:G:L:S:0 MIL:100 MIL 25
ENET_LINK_TX_ER L:S::400 MIL 13

PRIMARY THERM2_DM THERM2:G:L:S:0 MIL:100 MIL 25
LAYERS: 4,7
ENET_PHY_TX_EN THERM2_DP
ENET_LINK_TX_EN
L:S:8000 MIL:9000 7MIL 13 26
SECONDARY
THERM1_M_DM
THERM2:G:L:S:0 MIL:100 MIL 25
A ENET_MDIO
L:S::400 MIL
L:S:8000 MIL:9000 MIL
13
13 26
LAYERS: 2,9
THERM1_M_DP
THERM1_MAIN
THERM1_MAIN
THERM1_MAIN:G:L:S:0 MIL:100 MIL
THERM1_MAIN:G:L:S:0 MIL:100 MIL
25
25
A
ENET_MDC L:S:8000 MIL:9000 MIL 13 26 THERM2_M_DM THERM2_MAIN THERM2_MAIN:G:L:S:0 MIL:100 MIL 25
ENET_COL L:S:8000 MIL:9000 MIL 13 26 THERM2_M_DP THERM2_MAIN THERM2_MAIN:G:L:S:0 MIL:100 MIL 25 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
ENET_CRS L:S:8000 MIL:9000 MIL 13 26 THERM1_A_DM THERM1_ALT THERM1_ALT:G:L:S:0 MIL:100 MIL 25 AGREES TO THE FOLLOWING
THERM1_A_DP THERM1_ALT THERM1_ALT:G:L:S:0 MIL:100 MIL 25 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
FIREWIRE MII FW_LINK_DATA<7..0> L:S:2700:3500 7 (400) (400) 13 27
(400) (400)
THERM2_A_DM THERM2_ALT THERM2_ALT:G:L:S:0 MIL:100 MIL 25 II NOT TO REPRODUCE OR COPY IT
FW_PHY_DATA<7..0> L:S:4700:5500 7 27
PRIORITY: 5 THERM2_A_DP THERM2_ALT THERM2_ALT:G:L:S:0 MIL:100 MIL 25 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
FW_LINK_CNTL<1..0> L:S:9000:10000 13 27
FW_PHY_CNTL<1..0> L:S::300 27
PRIMARY SIZE DRAWING NUMBER REV.
LAYERS: 4,7 PRIORITY: 3
FW_LINK_LREQ
FW_PHY_LREQ
L:S::300 MIL
L:S:8500 MIL:9500 MIL
13
13 27
SECONDARY
LAYERS: 2,9
PRIMARY LAYERS: 4,7 FOR CONTROLLED IMPEDANCE DIFF PAIRS
SECONDARY LAYERS: 2,9 FOR UNCONTROLLED IMPEDANCE DIFF PAIRS APPLE COMPUTER INC.
D 051-6653 C
FW_PINT L:S:8500 MIL:9500 MIL 13 27 SCALE
NONE
SHT
37 44
OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POWER NET CONSTRAINTS GROUP SIG_NAME
CPU_VCORE_SLEEP
VOLTAGE
VOLTAGE=1.3V
MIN_LINE_WIDTH
MIN_LINE_WIDTH=25
MIN_NECK_WIDTH
MIN_NECK_WIDTH=10
GROUP
LTC1625
SIG_NAME
1625_VIN
VOLTAGE
VOLTAGE=24V
MIN_LINE_WIDTH
MIN_LINE_WIDTH=10
MIN_NECK_WIDTH
31
GROUP SIG_NAME VOLTAGE MIN_LINE_WIDTH MIN_NECK_WIDTH CPU CPU_AVDD VOLTAGE=1.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
5 6 33 39
1625_VSW VOLTAGE=14V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31
5
14V SWITCHER +PBUS_JUMPER
MAXBUS_SLEEP VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 5 6 7 8 15 16 33
VOLTAGE=14V MIN_LINE_WIDTH=10
+24V_PBUS VOLTAGE=24V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 1625_EXTVCC VOLTAGE=5V MIN_LINE_WIDTH=10
MAIN/SLEEP +BATT VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
39
I362 CPU_AVDD_VIN
CPU_AVDD_VOUT
VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 5
1625_INTVCC VOLTAGE=5V MIN_LINE_WIDTH=10
31
31
I363 VOLTAGE=1.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 5
+PBUS VOLTAGE=12.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39 1625_SGND VOLTAGE=0V MIN_LINE_WIDTH=10 31
+5V_MAIN VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39 1V20_REF VOLTAGE=1.2V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 30 31
+5V_SLEEP VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39
+3V_MAIN VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 23 39

DDR RAM DDR_VREF VOLTAGE=1.25V MIN_LINE_WIDTH=10 11
LTC3707 3707_INTVCC
5V_SW
VOLTAGE=5V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 32
5V SWITCHER VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 32

+3V_SLEEP VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6 39
D +3V_PMU VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39

INTREPID
5V_RSNS
+5V_MAIN_JUMPER
VOLTAGE=5V
VOLTAGE=5V
MIN_LINE_WIDTH=25
MIN_LINE_WIDTH=25
MIN_NECK_WIDTH=10
MIN_NECK_WIDTH=10
32
D
+2_5V_MAIN VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39 I333 +2_5V_INTREPID VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 9 10 15 16
+2_5V_SLEEP +3V_INTREPID_USB
3V SWITCHER 3V_SW VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 32
VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 14
3V_RSNS VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 32
+1_8V_MAIN VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6 39
PLLS +1_5V_INTREPID_PLL VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 8 12 14 +3V_MAIN_JUMPER VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_8V_SLEEP VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_5V_INTREPID_PLL1 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 14 3707_SGND VOLTAGE=0V MIN_LINE_WIDTH=10 32
+1_5V_MAIN VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_5V_SLEEP VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_5V_INTREPID_PLL2 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 14 MAX1715 2_5V_LX VOLTAGE=2.5V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 34
+1_5V_LDO
+1_5V_INTREPID_PLL3 VOLTAGE=1.5V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=6 14 2.5V SWITCHER 2_5V_LX_F VOLTAGE=2.5V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10
VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_5V_INTREPID_PLL4 VOLTAGE=1.5V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=6 14 2_5V_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10
+1_5V_SLEEP_VIN VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 34
+1_5V_INTREPID_PLL5 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 12 2_5V_BOOST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 34
+1_5V_INTREPID_PLL6 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 12 2_5V_DH VOLTAGE=2.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 34
+1_5V_INTREPID_PLL7 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 8 2_5V_DL VOLTAGE=2.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
ADAPTER +ADAPTER VOLTAGE=24V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 30 31 39
+1_5V_INTREPID_PLL8 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 14
34
I311 +ADAPTER_SW VOLTAGE=24V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 30 38 1.65V SWITCHER

+ADAPTER_SW VOLTAGE=24V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 1_5V_FB VOLTAGE=1.5V MIN_LINE_WIDTH=8 34
30 38
REFERENCE INT_MEM_VREF VOLTAGE=1.25V MIN_LINE_WIDTH=10 9
+ADAPTER_SENSE VOLTAGE=24V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 1_5V_LX VOLTAGE=1.5V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 34
30 INT_AGP_VREF VOLTAGE=1.25V MIN_LINE_WIDTH=10 12 19
1_5V_LX_F VOLTAGE=1.5V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10
INT_MEM_REF_H VOLTAGE=0V MIN_LINE_WIDTH=10 9
+BATT_POS VOLTAGE=16.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 1_5V_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 34
BATTERY BATT_NEG VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
30 39
30 39
UIDE_REF VOLTAGE=0V MIN_LINE_WIDTH=8 13
1_5V_BOOST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 34
CHARGER 1772_DCIN VOLTAGE=24V MIN_LINE_WIDTH=10 30 AIRPORT +3V_AIRPORT VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39 1_5V_DH
1_5V_DL
1772_LX VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 30

I365 +3V_SLEEP_PCCARD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 18

CONTROL 1_5V_ILIM MIN_LINE_WIDTH=8
+BATT_14V_FUSE VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 34
+BATT_24V_FUSE VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10

30
30
CARDBUS +VCC_CBUS_SW
+VPP_CBUS_SW
2_5V_ILIM MIN_LINE_WIDTH=8 34
+BATT_RSNS VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 30
MAX1715_TON MIN_LINE_WIDTH=8 34
GPU_VCORE VOLTAGE=1.2V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 19 20 39 MAX1715_SKIP MIN_LINE_WIDTH=8
+BATT_VSNS
1772_LDO
ATI M11 +3V_GPU VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 12 19 20 21 MAX1715_REF VOLTAGE=2.0V MIN_LINE_WIDTH=8
34
34
VOLTAGE=5.4V MIN_LINE_WIDTH=10 30
+3V_GPU_FLT VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 21 MAX1715_VCC
1772_DLOV VOLTAGE=5.4V MIN_LINE_WIDTH=10 30
+2_5V_GPU VOLTAGE=2.5V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 MAX1715_GND VOLTAGE=0V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10
C PMU
1772_GND
+ADAPTER_ILIM
VOLTAGE=0V
VOLTAGE=24V
MIN_LINE_WIDTH=10
MIN_LINE_WIDTH=10
30
31
GPU_MEM_IO VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 19 21 VCORE_VCC VOLTAGE=5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
34
33 C
+ADAPTER_OR_BATT VOLTAGE=24V MIN_LINE_WIDTH=10 31
GPU_MEM_IO_FLT
+2_5V_GPU_MEMCORE
MAX1717 VCORE_LX VOLTAGE=1.4V MIN_LINE_WIDTH=200 MIN_NECK_WIDTH=10 33
+4_85V_RAW VOLTAGE=4.85V MIN_LINE_WIDTH=10 29 31
+1_8V_GPU VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 19 20 21 VCORE_DH MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
+4_6V_BU VOLTAGE=4.6V MIN_LINE_WIDTH=10 31 32
33
+1_5V_AGP VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 12 15 16 19 20 21 VCORE_DL MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
+4_85V_ESR VOLTAGE=4.85V MIN_LINE_WIDTH=10 31
33
+2_5V_GPU_PNLIO VOLTAGE=2.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 21 VCORE_BOOST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10
+3V_PMU_ESR VOLTAGE=3.3V MIN_LINE_WIDTH=10 31
33
+1_8V_ATI_PVDD VOLTAGE=1.8V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 20 21 VCORE_BST
+3V_PMU_AVCC VOLTAGE=3.3V MIN_LINE_WIDTH=10 25 29
+1_5V_AGP_GPU VOLTAGE=1.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 21 VCORE_ILIM MIN_LINE_WIDTH=8 33
MISC +5V_HD_SLEEP
+1_5V_GPU_VDD15 VOLTAGE=1.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 20 VCORE_REF MIN_LINE_WIDTH=8 33
HD VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 24 32 +1_8V_GPU_PLL VOLTAGE=1.8V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21 VCORE_TON VOLTAGE=5V MIN_LINE_WIDTH=8 33
+HD_LOGIC_SLEEP VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 24 +1_8V_GPU_VDDDI VOLTAGE=1.8V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21 VCORE_CC MIN_LINE_WIDTH=8 33
+5V_TPAD_SLEEP GPU_VCORE_VDDCI VOLTAGE=1.2V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 19 VCORE_FB

VOLTAGE=5V MIN_LINE_WIDTH=10 23 39 VOLTAGE=1.4V MIN_LINE_WIDTH=8 33 39
TRACKPAD +2_5V_GPU_A2VDD VOLTAGE=2.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21 VCORE_TIME MIN_LINE_WIDTH=8 33
+1_8V_GPU_AVDD VOLTAGE=1.8V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21 VCORE_VGATE MIN_LINE_WIDTH=8 14 33
+3V_HALL_EFFECT VOLTAGE=3.3V MIN_LINE_WIDTH=10 23 39 +1_8V_GPU_PNLPLL VOLTAGE=1.8V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21 VCORE_GND
HALL EFFECT VOLTAGE=0V MIN_LINE_WIDTH=30 33
+1_8V_GPU_PNLIO VOLTAGE=1.8V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21 VCORE_GNDSNS VOLTAGE=0V MIN_LINE_WIDTH=8 33
+2_5V_GPU_MCLK VOLTAGE=2.5V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 21 VCORE_SNS VOLTAGE=1.4V MIN_LINE_WIDTH=8 33
VIDEO +1_8V_GPU_AVDDQ VOLTAGE=1.8V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 21 VCORE_GNDDIV VOLTAGE=0V MIN_LINE_WIDTH=8

+14V_INV VOLTAGE=14V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 22 39
33
+1_8V_GPU_MEMPLL VOLTAGE=1.8V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10
I315 VCORE_GNDA
21
+5V_INV_UF_SW VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 22
VOLTAGE=0V MIN_LINE_WIDTH=10 33
+3V_ATI_OSC_SLEEP VOLTAGE=3.3V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 19
+5V_INV_SW
+5V_DDC_SLEEP
VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 22 39
+3V_ATI_SS VOLTAGE=3.3V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 19
LTC1778 1778_VIN
1778_VCC
VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 22 39 VOLTAGE=5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 20

I346 +GPU_VDD15_UF VOLTAGE=1.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 20
+5V_DDC_SLEEP_UF VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 22 1778_GND VOLTAGE=0V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 20
I347 +2_5V_SLEEP_NECK1 VOLTAGE=2.5V MIN_LINE_WIDTH=10 20
+3V_LCD VOLTAGE=3.3V MIN_LINE_WIDTH=12 MIN_NECK_WIDTH=10 22 39 1778_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 20
I348 +3V_SLEEP_NECK VOLTAGE=3V MIN_LINE_WIDTH=10 34
+3V_LCD_SW VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 22 1778_BST_RC VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 20
I349 +1_5V_AGP_NECK VOLTAGE=1.5V MIN_LINE_WIDTH=10 20
GPU_TV_GND1 VOLTAGE=0V MIN_LINE_WIDTH=25 22 1778_TG MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 20
I350 +1_8V_PVDD_NECK VOLTAGE=1.8V MIN_LINE_WIDTH=10 20
GPU_TV_GND2 VOLTAGE=0V MIN_LINE_WIDTH=25 22 1778_BG MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 20
B TV_GND1 VOLTAGE=0V MIN_LINE_WIDTH=25 22 39

I351
I352
GPU_VCORE_NECK
+GPU_VDD15_NECK
VOLTAGE=1.2V
VOLTAGE=1.5V
MIN_LINE_WIDTH=10
MIN_LINE_WIDTH=10
20
20
GPU_VCORE_SW VOLTAGE=1.2V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 20 B
TV_GND2 VOLTAGE=0V MIN_LINE_WIDTH=25 22 39 GPU_VCORE_SW_F VOLTAGE=1.2V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10
I353 +2_5V_SLEEP_NECK2 VOLTAGE=2.5V MIN_LINE_WIDTH=10 34
1778_ION MIN_LINE_WIDTH=8 20
+5V_MAIN_AUD VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 I354 +1_8V_SLEEP_NECK VOLTAGE=1.8V MIN_LINE_WIDTH=10 34
AUDIO I357 25 32 1778_ITH MIN_LINE_WIDTH=8 20
+3V_MAIN_AUD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 I355 +1_5V_SLEEP_NECK VOLTAGE=1.5V MIN_LINE_WIDTH=10 34
I356 25 32 1778_ITH_RC MIN_LINE_WIDTH=8 20
+1_8V_ATI_TPVDD VOLTAGE=1.8V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
I358 AUD_GND
21
VOLTAGE=0V MIN_LINE_WIDTH=50 25 I360 1778_VFB MIN_LINE_WIDTH=8 20 39
I361 +1_8V_GPU_TP_PLL VOLTAGE=1.8V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21
+FAN_PWR VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 1778_FCB MIN_LINE_WIDTH=8 20
FAN I308 25 39
1778_VRNG
FAN1_GND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 MIN_LINE_WIDTH=8 20
39 +2_5V_MARVELL VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 26
FAN2_GND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39
ETHERNET +2_5V_MARVELL_AVDD
+1_0V_MARVELL
LTC3411 LTC3411_VCC VOLTAGE=3.3V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 34
LTC3411_GND VOLTAGE=0V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 34
88E1111 LTC3405_SW VOLTAGE=1.0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 26
1_8V_SW VOLTAGE=1.8V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 34
I316 +3V_NEC_VDD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 17
1_8V_SW_F
NEC USB2.0 I317 NEC_AVDD VOLTAGE=3.3V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 17
VOLTAGE=1.8V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6 1_8V_VFB MIN_LINE_WIDTH=8 34
IN I332 LM2594_IN VOLTAGE=33V MIN_LINE_WIDTH=40 MIN_NECK_WIDTH=12 27 LTC3411_ITH_RC MIN_LINE_WIDTH=8 34
I312 +FW_PBUS VOLTAGE=12.8V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 28 LTC3411_ITH MIN_LINE_WIDTH=8 34

VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12
IN +FW_SW VOLTAGE=12.8V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 28 LTC3411_SYNC MIN_LINE_WIDTH=8 34
CHGND1 +FW_AMP_SENSE VOLTAGE=12.8V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12
I345
+FW_PWR_OR
LTC1962 LTC3411_SHDN MIN_LINE_WIDTH=8 34
I/O AREA CHGND2

IN
I310 +FW_PWR1
VOLTAGE=33V
VOLTAGE=33V
MIN_LINE_WIDTH=100
MIN_LINE_WIDTH=100
MIN_NECK_WIDTH=12
MIN_NECK_WIDTH=12
27 28
28
INT PLLS LTC1962_INT_VIN MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 14

IN FW +FW_VP0 VOLTAGE=33V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 28 39 CY28512D I364 +3V_MAIN_SSCG VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
INVERTER CHGND3
+FW_VP1 VOLTAGE=33V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 28 39 LMU CONN I366 +3V_MAIN_LMU VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 23
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 +3V_FW VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 +5V_SLEEP_OPT VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
TRACKPAD IN
+3V_FW_UF VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
27 28
27
OPT DRIVER I367 24
CHGND4 +3V_FW_AVDD_PORT2 VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27
LVDS +3V_FW_AVDD_PORT1 VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27 SIGNAL CONSTRAINTS - PAGE 3

A +3V_FW_AVDD_PORT0 VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27
A
+3V_FW_AVDD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27
+1_95V_FW_DVDD VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27

+1_95V_FW_DVDD_RX0 VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27
ENET_CTAP_CHGND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 AGREES TO THE FOLLOWING
+1_95V_FW_DVDD_TX0 VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27
+1_95V_FW_DVDD_PORT1 VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27
+1_95V_FW_PLLVDD VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27
+1_95V_FW_PLL400VDD VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27
+1_95V_FW_PLL500VDD VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27

I314
FW_VGND0
FW_VGND1
VOLTAGE=0V
VOLTAGE=0V
MIN_LINE_WIDTH=100
MIN_LINE_WIDTH=100
MIN_NECK_WIDTH=12
MIN_NECK_WIDTH=12
28

D 051-6653 C
I359 FW_VDD_ON VOLTAGE=12.8V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12
SCALE
NONE
SHT
38 44OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FUNCTIONAL TEST POINTS

PROBES ARE ON BOTTOM SIDE. MINIMUM PAD/HOLE SIZE IS 25 MIL.
FUNC_TEST IS ONLY PROPERTY USED BY THE TOOLS. FUNC_QTY IS FOR REFERENCE AND
LISTS THE NUMBER OF TEST POINTS ON THAT NET AND WITHIN THAT GROUP/CONNECTOR.
FUNC_DIST IS SIMILARLY USED TO DEFINE MAXIMUM DISTANCE FROM A CONNECTOR.
GROUP SIG_NAME FUNC_TEST FUNC_QTY FUNC_DIST GROUP SIG_NAME FUNC_TEST FUNC_QTY FUNC_DIST GROUP SIG_NAME FUNC_TEST FUNC_QTY FUNC_DIST
JTAG_ASIC_TMS TRUE NEC_USB_DAM TRUE FW_TPO1P TRUE 1000

SCAN/TEST I2
I3 JTAG_ASIC_TDI TRUE
13 26
13
USB I94
I96 NEC_USB_DAP TRUE
17 25 37
17 25 37
FIREWIRE I183
I185 FW_TPO1N TRUE 1000
28 37
28 37
I1 JTAG_ASIC_TDO_TP TRUE 26 I95 NEC_USB_DBM TRUE 17 25 37

(CONT.) I184 FW_TPI1P TRUE 1000 28 37
D I4 JTAG_ASIC_TCK
JTAG_ASIC_TRST_L
TRUE
TRUE
13 26
13 26
I97 NEC_USB_DBP
BT_USB_DM
TRUE
TRUE
17 25 37
14 25 37
I186 FW_TPI1N
+FW_VP1
TRUE
TRUE
1000
1000
28 37
28 38
D
I6 I98 I187
CPU_CHKSTP_OUT_L TRUE 5 BT_USB_DP TRUE 14 25 37 FW_VGND TRUE 1000 39
I5 I99 I188
I7 CPU_SRESET_L TRUE 5 I101 MODEM_USB_DM TRUE 14 25 37
3 (100 MIL PROBE PREFERRED)1000
I9 CPU_HRESET_L
JTAG_CPU_TMS
TRUE 5 6 7 I100 MODEM_USB_DP
NEC_RUSB_PPON
TRUE 14 25 37
DC PWR IN I189 +ADAPTER TRUE 30 31 38
TRUE TRUE
I8
I10 JTAG_CPU_TDI TRUE
5 6
5 6
RT. USB I102
I104 NEC_RUSB_OCI_UF TRUE
17 25
17 25
1000 ST7_SLEEP_LED_H TRUE
I12 JTAG_CPU_TDO_TP
JTAG_CPU_TCK
TRUE 5
WIRELESS I103 PCI_AD<0..31>
PCI_FRAME_L
TRUE
1000
9 12 17 18 24 37
LMU/ALS I251
I250 PMU_SLEEP_LED TRUE
23
23
I11 TRUE 5 6 I106 TRUE 12 17 18 24 37
JTAG_CPU_TRST_L PCI_TRDY_L 1000 I253 PMU_LID_CLOSED_L TRUE 23 29

I13 TRUE 5 6 I105 TRUE 12 17 18 24 37
INT_JTAG_TEI PCI_IRDY_L 1000 I252 LMU_DETECT TRUE 23

I18 TRUE 13 I107 TRUE 12 17 18 24 37
INT_TST_MONIN_PD TRUE 13 PCI_DEVSEL_L TRUE 1000 12 17 18 24 37
I20 I109
INT_TST_MONOUT_TP TRUE 13 PCI_STOP_L TRUE 1000 12 17 18 24 37
I19 I108
INT_TST_PLLEN_PD TRUE 13 PCI_PAR TRUE 1000 12 17 18 24 37 6 1000
I21 I111 TRUE
AIRPORT_PCI_REQ_L 1000 IN
INT_I2C_CLK0 TRUE I110 TRUE 12 24
INT I2C I15
I14
INT_I2C_DATA0 TRUE
6 11 13 23
6 11 13 23 I112 AIRPORT_PCI_GNT_L TRUE 1000 12 24

(100 MIL PROBE PREFERRED)
AIRPORT_PCI_INT_L TRUE 1000 SLEEP_LED TRUE
I16 INT_I2C_CLK1
INT_I2C_DATA1
TRUE 13 14 25 I114
I113
MAIN_RESET_L TRUE 1000
14 24
14 17 18 19 24 29
MISC. I192
I195
PMU_KB_RESET_L TRUE
23
29
I17 TRUE 13 14 25
CLK33M_AIRPORT TRUE 1000 12 24 35 SLEEP TRUE 23 25 29 32 34
I116 I196
PWR/GND I215
+PBUS
+24V_PBUS
TRUE 38
I115 PMU_PME_L TRUE 1000 14 17 24 29 I198 PMU_CPU_HRESET_L TRUE 6 29
I216 TRUE 38
1000
I117 ROM_ONBOARD_CS_L TRUE 9 I197 BB_RESET_L TRUE 6
I25 GPU_VCORE TRUE 19 20 38
1000
I119 ROM_OE_L TRUE 9 12 I248 +3V_PMU_RESET TRUE 29 33
1778_VFB TRUE 20 38
I24 ROM_CS_L TRUE 1000 9 12
CPU_VCORE_SLEEP I118
I27 TRUE 5 6 33 38
1000
I121 ROM_RW_L TRUE 9 12
I26 VCORE_FB TRUE 33 38
RF_DISABLE_L TRUE 1000 24
+1_8V_MAIN I229
I217 TRUE 38
1000
I230 AIRPORT_CLKRUN_L TRUE 24
I218 +2_5V_MAIN TRUE 38
4 2000
+3V_AIRPORT TRUE
C I219
I220
+5V_MAIN
+5V_SLEEP
TRUE
TRUE
2
2
38 39
38 39
I120
TRUE 6 1000
38
IN
C
+3V_MAIN TRUE 4 23 38
I221 1000
TRUE EIDE_OPTICAL_DATA<0..15> TRUE 2000
+3V_PMU
IN
OPTICAL I124
I123 EIDE_OPTICAL_DMA_RQ TRUE 2000
24 37
24 37
I222 TRUE 38
EIDE_OPTICAL_READ_L TRUE 2000 24 37
2000 I126
CARDBUS I36 CBUS_DET_1_L
CBUS_DET_2_L
TRUE
2000
18
I125 EIDE_OPTICAL_DMAACK_L TRUE 2000 24 37
I35 TRUE 18
2000
I127 EIDE_OPTICAL_ADDR<0..2> TRUE 24 37
1000
DVI I37 TMDS_DN<0..2>
TMDS_DP<0..2>
TRUE
1000
19 22 37
I128
EIDE_OPTICAL_CS0_L TRUE 2000 24 37
I38 TRUE 19 22 37
2000
1000 I129 EIDE_OPTICAL_CS1_L TRUE 24 37
I40 TMDS_CONN_CLKN TRUE 22 36
2000
I131 EIDE_OPTICAL_RST_L TRUE 24 37
TMDS_CONN_CLKP TRUE 1000 22 36
I39 EIDE_OPTICAL_WR_L 2000
1000 I130 TRUE 24 37
I42 VGA_R TRUE 22
EIDE_OPTICAL_IOCHRDY TRUE 2000 24 37
VGA_G 1000 I132
I41 TRUE 22
2000
1000 I134 EIDE_OPTICAL_INT TRUE 24 37
I44 VGA_B TRUE 22
1000 +5V_TPAD_SLEEP TRUE 3000
I43 VGA_HSYNC
VGA_VSYNC
TRUE
1000
22
TRACKPAD I133
I136 TPAD_F_TXD TRUE 3000
23 38
23
I46 TRUE 22
1000 TPAD_F_RXD TRUE 3000
I45 DVI_DDC_CLK_UF TRUE 22 I135 23
1000 LID_CLOSED_L TRUE 3000

I47 DVI_DDC_DATA_UF TRUE 22 I137 23
1000 +3V_HALL_EFFECT TRUE 3000

I48 DVI_HPD_UF TRUE 22 I138 23 38
2000 SOFT_PWR_ON_L TRUE 3000

I49 +5V_DDC_SLEEP TRUE 22 38 I139 22 23 29 33
4000
TRUE 2 2000
IN MODEM/ I141 COMM_RESET_L TRUE
4000
14 25
CHGND1 TRUE 6 1000

IN SERIAL I140 COMM_SHUTDOWN
COMM_RING_DET_L
TRUE
4000
14 25
1000 I142 TRUE 14 25 29

LVDS I52 LVDS_L0N
LVDS_L0P
TRUE
1000
20 22 37
I144 COMM_TXD_L TRUE 4000 14 25
I51 TRUE 20 22 37
4000
1000 I143 COMM_TRXC TRUE 14 25
I53 LVDS_L1N TRUE 20 22 37
COMM_GPIO_L TRUE 4000 14 25
LVDS_L1P TRUE 1000 20 22 37
I146
I55 COMM_DTR_L 4000
B I54 LVDS_L2N
LVDS_L2P
TRUE
TRUE
1000
1000
20 22 37
20 22 37
I145
I147 COMM_RTS_L
TRUE
TRUE 4000
14 25
14 25
B
I57 COMM_RXD 4000
1000 I149 TRUE 14 25
I56 CLKLVDS_LN TRUE 20 22 37
1000 KBD_ID TRUE 3000
I58 CLKLVDS_LP
LVDS_DDC_CLK
TRUE
1000
20 22 37
KEYBOARD I148
I151 KBD_INTL TRUE 3000
23 29
23
I59 TRUE 20 22
1000 KBD_JIS TRUE 3000
I60 LVDS_DDC_DATA TRUE 20 22 I150 23
2 2000 KBD_CAPSLOCK_LED TRUE 3000

I62 +3V_LCD TRUE 22 38 I152 23
2000 KBD_NUMLOCK_LED TRUE 3000

I223 +3V_SLEEP TRUE 38 39 I154 23
TRUE 2 2000 KBD_FUNCTION_L TRUE 3000 23 29

IN I153
TRUE 6 1000 KBD_COMMAND_L TRUE 3000 23 29
CHGND4 IN I155
+14V_INV TRUE 2000 22 38 KBD_OPTION_L TRUE 3000 23 29
I67 I157
INVERTER I66 +5V_INV_SW TRUE 2000 22 38 I156 KBD_CONTROL_L TRUE 3000 23 29
BRIGHT_PWM TRUE 2000 22 KBD_SHIFT_L TRUE 3000 23 29

I68 I159
INV_GND TRUE 2000 22 KBD_X<0..9> TRUE 3000 23 29
I249 I158
TRUE 1000 IN KBD_Y<0..7> TRUE 3000 23 29
I161
2000
S-VIDEO I70 TV_C
TV_Y
TRUE
2000
22
BATTERY I160 +BATT_POS TRUE (100 MIL PROBE PREFERRED) 1000 30 38
I72 TRUE 22
(100 MIL PROBE PREFERRED) 1000
I162 BATT_NEG TRUE 30 38
TV_COMP TRUE 2000 22
I71
2000 BATT_CLK TRUE 1000
I73 TV_GND1 TRUE 22 38 I164 30
2000 BATT_DATA TRUE 1000

I74 TV_GND2 TRUE 22 38 I163 30
1000 PMU_BATT_DET_L TRUE 1000

LIO I76 INT_I2S0_SND_TO_DAC
INT_I2S0_SND_LRCLK
TRUE
1000
14 25 I166 29 30
I75 TRUE 14 25
1000 +FAN_PWR TRUE 3000
I78 INT_I2S0_SND_MCLK
INT_I2S0_SND_SCLK
TRUE
1000
14 25 35
FANS I167
I168 FAN1_TACH TRUE 3000
25 38
25
I83 TRUE 14 25
1000 FAN2_TACH TRUE 3000
I82
INT_I2S0_SND_FROM_ADC TRUE 14 25 I169 25
1000 FAN1_GND TRUE 3000

I77 SND_HP_MUTE_L TRUE 14 25 I170 38
FAN2_GND 3000
A I79
I84
SND_AMP_MUTE
SND_HW_RESET_L
TRUE
TRUE
1000
1000
25
14 25
I171 TRUE 38

A
1000 MDI_P<0..3> TRUE 1000
I85 SND_HP_SENSE_L
SND_LIN_SENSE_L
TRUE
1000
14 25
ETHERNET I174
MDI_M<0..3> TRUE 1000
26 37
26 37 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I86 TRUE 14 25 I173
INT_I2C_CLK2 TRUE 1000 14 25
I81
1000 FW_TPO0P TRUE 1000
I80 INT_I2C_DATA2
ADAPTER_DET
TRUE
1000
14 25
FIREWIRE I177
I176 FW_TPO0N TRUE 1000
27 28 37
27 28 37
I87 TRUE 25 29
1000 FW_TPO0R TRUE 1000 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I88 CHARGE_LED_L TRUE 25 29 I179 28
1000 FW_TPI0P TRUE 1000

I89 NEC_LUSB_OCI_UF TRUE 17 25 I178 27 28 37
1000 SIZE DRAWING NUMBER REV.
NEC_LUSB_PPON 1000 I180 FW_TPI0N TRUE 27 28 37
TRUE
I90
I224 +5V_MAIN
+5V_SLEEP
TRUE
TRUE
2
2
2000
3000
17 25
38 39
38 39
I182
I181
+FW_VP0
FW_VGND
TRUE
TRUE
1000
1000
28 38
39
APPLE COMPUTER INC.
D 051-6653 C
I225 SCALE SHT OF
I226 +3V_SLEEP TRUE 2000 38 39
NONE 39 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REVISION HISTORY
Proto/EVT Release
10/27/03 - 1. Schematic originated from Q16 MLB
11/10/03 - 1. Replace U56 symbol
2. Connect OVDDSENSE to MAXBUS_SLEEP
3. Modify SRW0, SRW1 and IARTRY0 connection
4. Connect VDD(Page 6) to CPU_VCORE_SLEEP(PAGE 5)
5. Connect SENSEVDD to CPU_VCORE_SLEEP
6. Connect SENSEGND to GND
7. Add 4 pcs 0 ohm resistor for AMD BootRom issue (R1,R194,R236,R271)
8. Connect TEMP_ANODE and TEMP_CATHODE to ADT7460
9. Modify CPU PLL config
10. Add 0 ohm resistor on CG_FSEL Interpid side(R450)
11. Replace U47 symbol
12. Change R743 from 2m ohm to 1m ohm
13. Change C774,C781,C788,C793,C797,C802 from 220uF to 330uF
D 12/01/03 -
14.
1.
Change R748 from 410 ohm to 10 ohm
Modify CPU_VCORE setting. D
12/02/03 - 1. Modify CPU_BTR CPU_VCORE VID setting
12/05/03 - 1. Add CPU AVDD LDO (Page 5)
2. Change Q45 and Q41 to IRF7805 (376S0035)
3. Change Q47 and Q42 to IRF7811W (376S0104)
4. Change R402 and R409 to 4.7ohm resistors
5. Connect INT_TDO from intrepid to Cypress Chip PD* (U31)
12/12/03 - 1. Add R468 and R601 for MAX1715 2.5V adjust
2. Modify CPU_VCORE setting to Motorola new spec
3. Modify LDO power sequence
12/16/03 - 1. Add 10K pull down for INT_TDO on page 13
12/17/03 - 1. Change LDO Vin from +3V_MAIN to +3V_SLEEP
2. Connect INT_TDO from Intrepid to Marvell 88E1111(U43)
3. Add R755,R756,R758,R759 for power rail
DVT Release (Rev. 02)
01/30/04 - 1. Add Soft_Modem(Pin#14) 10K pull-up at J15.7 (Pg 25)
2. Add Bom Table for R97 2.21K ohm VCore Offset (Pg 33)
02/04/04 - 1. C811 change to 4.7uF per MOT A7PM requirement (Pg 5)
2. NO STUFF R236,R1,R271&R194 to remove PCI stub (Pg 9)

02/12/04 - 1. CPU VCore adjustment for V1.1 A7PM CPU (Pg 33)
2. CPU AVDD adjustment for V1.1 A7PM CPU (Pg 5)
3. ATI INT.TMDS termination change to 0 ohm, Qty:8 (Pg 20)
4. AGP I/O VREF voltage divider chagne to both 1K ohm (Pg 12)

02/13/04 - 1. INT. TMDS Termination change to 2* 49.9ohm = 100ohm (Pg 20)
PVT Release (Rev. A)

C 03/11/04 - 1. INT. TMDS Termination change to 2* 75 ohm = 150ohm (except CLK pair) (Pg 20)
2. USB series termination near NEC PHY change to 47 ohm (Pg 17) C
PVT Release (Rev. A - 051-6570)
04/02/04 - 1. USB series termination near NEC PHY change to 43.2 ohm (Pg 17)
Production Release (Rev. A - 051-6653)

04/09/04 - 1. Updated to Apollo 7PM rev 1.1.1 part numbers (Pg 5)
04/09/04 - 2. Updated to production BootROM part number (Pg 9)
Production Release (Rev. B - 051-6653)

04/30/04 - 1. Updated to Fast Intrepid part for 6A ReadMacro Delay value (Pg 8-15)
04/30/04 - 2. Add ATI M11 A16 parts as alternative for A15 parts (Pg 19-21)
04/30/04 - 3. Use new VGA filter to remove ghost image on external VGA display (Pg 22)
Production Release (Rev. C - 051-6653)

05/27/04 - 1. Updated BOM : 113S0006 -> 113S1000
05/27/04 - 2. Updated BOM : 132S0020 -> 132S0100
B B

A
APPLE COMPUTER INC.

D 051-6653 C
SCALE
NONE
SHT
40 44
OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
*** Signal Cross-Reference for the entire design *** 3V_BG 32C4<> AGP_REQ_L 12C2< 12D2<> 19B7<> 37D5> CBUS_INPACK_L 18B2<> 18B4< CPU_DATA<32..63> 36D5> EIDE_OPTICAL_DATA<7> 24A5<> 24B7< GPU_DVOD<6> 19B3< 19C4< JTAG_ASIC_TDO_TP 26A5> 39D6> MEM_DATA<29> 9C8<> 10B5<>
3V_BOOST 32C4<> AGP_SBA<0> 12B2< 19C6> CBUS_INT_L 14B5<> 14D7< 18A7<> CPU_DATA<33> 6C8<> 8C3<> 8D8< EIDE_OPTICAL_DATA<8> 24A6<> 24D7< GPU_DVOD<7> 19B3< 19C4< JTAG_ASIC_TMS 13C5< 13D2< 26A5< 39D6> MEM_DATA<30> 9C8<> 10B5<>
+1_0V_MARVELL 26D2< 38B3> 3V_BOOST_ESR 32D3<> AGP_SBA<7..0> 37D5> CBUS_IORD_L 18B2<> 18C4> CPU_DATA<34> 6C8<> 8C3<> 8D8< EIDE_OPTICAL_DATA<9> 24A6<> 24C7< GPU_DVOD<8> 19B2< 19C4< JTAG_ASIC_TRST_L 13C2< 13C5< 26A5< 39D6> MEM_DATA<31> 9C8<> 10B5<>
+1_5V_AGP 12B5< 12D1< 12D4< 15D6< 16C8< 3V_ITH 32C4<> AGP_SBA<1> 12B2<> 19C6> CBUS_IOWR_L 18B2<> 18C4> CPU_DATA<35> 6C8<> 8C3<> 8D8< EIDE_OPTICAL_DATA<10> 24A6<> 24D7< GPU_DVOD<9> 19B2< 19C4< JTAG_CPU_TCK 5A2< 5B3< 6A3> 39D6> MEM_DATA<32> 9C8<> 10C3<>
19C6< 19D6< 20A8< 20B4<> 20D5<> 3V_ITH_RC 32C3< AGP_SBA<2> 12B2<> 19C6> CBUS_MFUNC1_PD 18A7<> 18A7< CPU_DATA<36> 6B8<> 8C3<> 8D8< EIDE_OPTICAL_DATA<11> 24A6<> 24C7< GPU_DVOD<10> 19B2< 19C4< JTAG_CPU_TDI 5B2< 5C3< 6B2<> 39D6> MEM_DATA<39..32> 35C5>
21B8< 21D6< 38C3> 3V_PMU_VTAP 31B3< AGP_SBA<3> 12B2<> 19C6> CBUS_MFUNC2_PD 18A7<> 18A7< CPU_DATA<37> 6B8<> 8C3<> 8D8< EIDE_OPTICAL_DATA<12> 24A6<> 24C7< GPU_DVOD<11> 19B2< 19C4< JTAG_CPU_TDO_TP 5C3> 39D6> MEM_DATA<33> 9C8<> 10C3<>
+1_5V_AGP_GPU 21C5< 38C3> 3V_RSNS 32D2< 38D1> AGP_SBA<4> 12B2<> 19C6> CBUS_MFUNC3_PD 18A7<> 18A7< CPU_DATA<38> 6B8<> 8C3<> 8D8< EIDE_OPTICAL_DATA<13> 24A6<> 24C7< GPU_DVOD_DE 19B2< 19C4< 36C1> JTAG_CPU_TMS 5B2< 5B3< 6B2<> 39D6> MEM_DATA<34> 9C8<> 10C3<>
+1_5V_AGP_NECK 20B4<> 38B3> 3V_RUNSS 32C4< AGP_SBA<5> 12B2<> 19C6> CBUS_MFUNC4_PD 18A7<> 18A7< CPU_DATA<39> 6B8<> 8B3<> 8D8< EIDE_OPTICAL_DATA<14> 24A6<> 24C7< GPU_DVO_CLKP 19B2< 19C4< 36C1> JTAG_CPU_TRST_L 5A3< 5B3< 6B2<> 39D6> MEM_DATA<35> 9C8<> 10C3<>
+1_5V_GPU_VDD15 20D3< 38C3> 3V_SLEEP_PWREN_L 32B3<> AGP_SBA<6> 12B2<> 19C6> CBUS_MFUNC5_PD 18A7<> 18A7< CPU_DATA<40> 6B8<> 8B3<> 8C8< EIDE_OPTICAL_DATA<15> 24A6<> 24C7< GPU_DVO_HSYNC 19B2< 19C4< 36C1> KBD_CAPSLOCK_LED 23C1<> 39B3> MEM_DATA<36> 9C8<> 10C3<>
+1_5V_INTREPID_PLL 8D6< 12D4< 12D8< 14D6<> 38D3> 3V_SNSM 32C4< 37A2> AGP_SBA<7> 12B2<> 19C6<> CBUS_MFUNC6_PD 18A7<> 18A7< CPU_DATA<41> 6B8<> 8B3<> 8C8< EIDE_OPTICAL_DMAACK_L 24A6<> 24A7< 37A5> 39C3> GPU_DVO_VSYNC 19B2< 19C4< 36C1> KBD_COMMAND_L 23A2< 23C1<> 29C6<> 39B3> MEM_DATA<37> 9C8<> 10C3<>
+1_5V_INTREPID_PLL1 14C3< 38D3> 3V_SNSP 32C4< 37A2> AGP_SB_STB 12B2< 12B2<> 19C6<> 37D5> CBUS_OE_L 18B1<> 18C4> CPU_DATA<42> 6B8<> 8B3<> 8C8< EIDE_OPTICAL_DMA_RQ 24A6<> 24A7< 37A5> 39C3> GPU_G 20D6<> 22C8< KBD_CONTROL_L 23B2< 23C1<> 29A8< 29C6<> 39A3> MEM_DATA<38> 9C8<> 10C3<>
+1_5V_INTREPID_PLL2 14D3< 38D3> 3V_SW 32C4<> 38D1> AGP_SB_STB_L 12A2< 12A2<> 19C6<> 37D5> CBUS_PCI_GNT_L 12D7<> 18A7< CPU_DATA<43> 6B8<> 8B3<> 8C8< EIDE_OPTICAL_INT 24A5<> 24A7< 37A5> 39B3> GPU_G_FILTR 22C8< KBD_FUNCTION_L 23A2< 23C1<> 29B6<> 39B3> MEM_DATA<39> 9B8<> 10C3<>
+1_5V_INTREPID_PLL3 14D3< 38D3> 3V_TG 32D4<> AGP_ST<0> 12A2<> 19C6< CBUS_PCI_IDSEL 18B7< CPU_DATA<44> 6B8<> 8B3<> 8C8< EIDE_OPTICAL_IOCHRDY 24A5<> 24A7< 37A5> 39B3> GPU_HPD 20C5< 22C3<> KBD_ID 23B2< 23C1<> 29B6<> 39B3> MEM_DATA<40> 9B8<> 10C3<>
+1_5V_INTREPID_PLL4 14D3< 38D3> 3V_VOSNS 32C4<> AGP_ST<1> 12A2<> 19C6< CBUS_PCI_REQ_L 12A7< 12D7<> 18A7> CPU_DATA<45> 6B8<> 8B3<> 8C8< EIDE_OPTICAL_READ_L 24A6<> 24A7< 37B5> 39C3> GPU_MEM_IO 19A6<> 19B8< 21A7< 21B4< 21D2< KBD_INTL 23C1<> 39B3> MEM_DATA<47..40> 35B5>
+1_5V_INTREPID_PLL5 12D3< 38D3> 5V_BG 32C5<> AGP_ST<2> 12A2<> 19C6< CBUS_PCI_RESET_L 18A7< CPU_DATA<46> 6B8<> 8B3<> 8B8< EIDE_OPTICAL_RST_L 24A7< 24B5<> 37A5> 39C3> 38C3> KBD_JIS 23C1<> 39B3> MEM_DATA<41> 9B8<> 10C3<>
+1_5V_INTREPID_PLL6 12D6< 38D3> 5V_BOOST 32C5<> AGP_STOP_L 12B2<> 12C2< 19B7<> 37D5> CBUS_READY 18B1<> 18C4< CPU_DATA<47> 6B8<> 8B3<> 8B8< EIDE_OPTICAL_WR_L 24A5<> 24A7< 37B5> 39B3> GPU_MEM_IO_FLT 21C2< 38C3> KBD_LED1_OUT 23B5<> 23D7<> MEM_DATA<42> 9B8<> 10C3<>
+1_5V_INTREPID_PLL7 8D5< 38D3> 5V_BOOST_ESR 32D6<> AGP_STP_L 19C6< CBUS_REG_L 18B2<> 18C4> CPU_DATA<48> 6B8<> 8A8< 8B3<> EIDE_RD_L 13A7> 24A8< 37B5> GPU_R 20D6<> 22B8< KBD_LED2_OUT 23B4<> 23D7<> MEM_DATA<43> 9B8<> 10C3<>
+1_5V_INTREPID_PLL8 14D3< 38C3> 5V_HD_PWREN 32A8<> AGP_SUS_STAT_L_PU 19C6< CBUS_RESET_L 18B2<> 18C4> CPU_DATA<49> 6B8<> 8A8< 8B3<> EIDE_RST_L 13B7> 24A8< 37B5> GPU_R_FILTR 22B8< KBD_NUMLOCK_LED 23C1<> 39B3> MEM_DATA<44> 9B8<> 10C3<>
D
+1_5V_LDO
+1_5V_MAIN
+1_5V_SLEEP
38D6>
38D6>
38D6>
5V_ITH
5V_ITH_RC
5V_RSNS
32C5<>
32C6<
32D7< 38D1>
AGP_TRDY_L
AGP_WBF_L
12B2<> 12C2< 19B7<> 37D5>
12A4<> 12B2< 19B7>
AIRPORT_CLKRUN_L 24C6<> 39C3>
CBUS_SUSPEND_PU
CBUS_VCCD0_L
CBUS_VCCD1_L
18A7< 18D7<
18C4<>
18C4<>
CPU_DATA<50>
CPU_DATA<51>
CPU_DATA<52>
6B8<>
6B8<>
6B8<>
8A8<
8A8<
8A8<
8B3<>
8B3<>
8B3<>
EIDE_WR_L
ENET_COL
ENET_COMA
13A7> 24A8< 37B5>
13C5< 26B7> 37A5>
26B7<>
GPU_THERM_DM
GPU_THERM_DP
GPU_TMDS_CLKN
19A6<> 25A6<
19A6<> 25A6<
19B2< 20B8< 20D7< 36D1>
KBD_OPTION_L
KBD_SHIFT_L
KBD_X<0>
23A2< 23C1<> 29A8< 29B6<> 39B3>
23A2< 23C1<> 29A8< 29C6<> 39A3>
23B2< 23C1<> 29C6<>
MEM_DATA<45>
MEM_DATA<46>
MEM_DATA<47>
9B8<> 10B3<>
9B8<> 10B3<>
9B8<> 10B3<>
D
+1_5V_SLEEP_NECK 34D2<> 38B3> 5V_RUNSS 32C5< AIRPORT_IDSEL 24C5<> CBUS_VPPD0 18C4<> CPU_DATA<53> 6B8<> 8A8< 8B3<> ENET_CRS 13C5< 26B7> 37A5> GPU_TMDS_CLKP 19B2< 20B8< 20D8< 36D1> KBD_X<0..9> 39A3> MEM_DATA<48> 9B8<> 10C1<>
+1_5V_SLEEP_VIN 38D6> 5V_SLEEP_PWREN 32A8<> AIRPORT_PCI_GNT_L 12D7<> 24D5<> 39C3> CBUS_VPPD1 18C5<> CPU_DATA<54> 6B8<> 8A8< 8B3<> ENET_CTAP_CHGND 38A6> GPU_TMDS_CLK_CMF 20D7< KBD_X<1> 23B2< 23C1<> 29C6<> MEM_DATA<55..48> 35B5>
+1_8V_ATI_PVDD 20C5<> 21B6< 21B6< 21D6<> 38C3> 5V_SNSM 32C5< 37A2> AIRPORT_PCI_INT_L 14B5<> 14D7< 24D5<> 39C3> CBUS_VS1 18B2<> 18C4<> CPU_DATA<55> 6B8<> 8A8< 8B3<> ENET_ENERGY_DET 14B5<> 26B7<> GPU_TMDS_D0_CMF 20D7< KBD_X<2> 23B2< 23C1<> 29C6<> MEM_DATA<49> 9B8<> 10C1<>
+1_8V_ATI_TPVDD 21D2<> 38B3> 5V_SNSP 32C5< 37A2> AIRPORT_PCI_REQ_L 12A7< 12D7<> 24D6<> 39C3> CBUS_VS2 18B2<> 18C4<> CPU_DATA<56> 6B8<> 8B3< 8B3<> ENET_HSDACM 26A7<> GPU_TMDS_D1_CMF 20C7< KBD_X<3> 23B2< 23C1<> 29C6<> MEM_DATA<50> 9B8<> 10C1<>
+1_8V_GPU 19A8< 19C2< 20D7< 21A2< 21A6< 5V_SW 32C5<> 38D1> ATI_AGP_FBSKEW<0> 20C2< 20C7<> CBUS_WAIT_L 18B2<> 18B4< CPU_DATA<57> 6B8<> 8B3< 8B3<> ENET_HSDACP 26A7<> GPU_TMDS_D2_CMF 20C7< KBD_X<4> 23B2< 23C1<> 29C6<> MEM_DATA<51> 9B8<> 10C1<>
21B1< 21B6< 21C8< 21D6< 21D8< 38C3> 5V_TG 32C5<> ATI_AGP_FBSKEW<1> 20C2< 20C7<> CBUS_WE_L 18B1<> 18C4> CPU_DATA<58> 6B8<> 8B3< 8B3<> ENET_LINK_RXD<0> 13C5< 26C7> GPU_TMDS_DN<0> 19B2< 20B8< 20D7< 36D1> KBD_X<5> 23B2< 23C1<> 29C6<> MEM_DATA<52> 9B8<> 10C1<>
+1_8V_GPU_AVDD 21D5< 38B3> 5V_VOSNS 32C5<> ATI_BUS_CFG<0> 20B2< 20C7<> CBUS_WP_L 18A1<> 18B4< CPU_DATA<59> 6B8<> 8B3< 8B3<> ENET_LINK_RXD<7..0> 37A5> GPU_TMDS_DN<1> 19B2< 20B8< 20C7< 36D1> KBD_X<6> 23B2< 23D1<> 29C6<> MEM_DATA<53> 9B8<> 10C1<>
+1_8V_GPU_AVDDQ 21D4< 21D7< 38B3> 1625_BG 31C5<> ATI_BUS_CFG<1> 20B2< 20C7<> CG_ADDRSEL 14B7< CPU_DATA<60> 6B8<> 8B3< 8B3<> ENET_LINK_RXD<1> 13C5< 26C7> GPU_TMDS_DN<2> 19A2< 20B8< 20C7< 36D1> KBD_X<7> 23B2< 23D1<> 29C6<> MEM_DATA<54> 9B8<> 10C1<>
+1_8V_GPU_DVO 21B2< 1625_BST 31C5< ATI_BUS_CFG<2> 20B2< 20C7<> CG_CLKOUT 14B6<> CPU_DATA<61> 6B8<> 8B3< 8B3<> ENET_LINK_RXD<2> 13C5< 26C7> GPU_TMDS_DP<0> 19B2< 20B8< 20D8< 36D1> KBD_X<8> 23A2< 23D1<> 29C6<> MEM_DATA<55> 9B8<> 10C1<>
+1_8V_GPU_MEMPLL 21B5< 38B3> 1625_BST_ESR 31C5<> ATI_CLK27M_IN 19A2< 20B7< 35B1> CG_FSEL 14B7< 14C5< CPU_DATA<62> 6A8<> 8B3< 8B3<> ENET_LINK_RXD<3> 13C5< 26B7> GPU_TMDS_DP<1> 19B2< 20B8< 20C8< 36D1> KBD_X<9> 23A2< 23D1<> 29C6<> MEM_DATA<56> 9B8<> 10C1<>
+1_8V_GPU_PLL 21D5< 38C3> 1625_COMP 30D2< 31C6< ATI_CLK27M_OSC 19A2< 35B1> CG_FSEL_INT 14C5<> CPU_DATA<63> 6A8<> 8B3< 8B3<> ENET_LINK_RXD<4> 13C5< 26B7> GPU_TMDS_DP<2> 19A2< 20B8< 20C8< 36D1> KBD_Y<0> 23D1<> 29D6<> MEM_DATA<63..56> 35A5>
+1_8V_GPU_PNLIO 21A5< 38B3> 1625_DIV 31C8< ATI_CLK27M_OSC_SS 19A1< 19A4< 35B1> CG_LOCK 14B7<> CPU_DBG_L 5C3< 8A3<> 8C2< 36D5> ENET_LINK_RXD<5> 13C5< 26B7> GPU_TV_GND1 22B8<> 38B6> KBD_Y<0..7> 39A3> MEM_DATA<57> 9B8<> 10C1<>
+1_8V_GPU_PNLPLL 21B5< 38B3> 1625_ENABLE 31D7<> ATI_DBI_HI_PU 19C6<> CG_RESET_L 14B7< CPU_DRDY_L 5C3> 8A3< 8C2< 36D5> ENET_LINK_RXD<6> 13C5< 26B7> GPU_TV_GND2 22A8<> 38B6> KBD_Y<1> 23D1<> 29D6<> MEM_DATA<58> 9B8<> 10C1<>
+1_8V_GPU_TP_PLL 21B5< 21D1< 38B3> 1625_ENABLE_L 31D6<> ATI_DBI_LO_PU 19C6<> CG_SYSCLK_EN 14B5< 14B7< CPU_DTI<0> 5C3< 8A3<> ENET_LINK_RXD<7> 13C5< 26B7> GPU_VCORE 19D8< 20A3<> 20B5<> 20D4< 38C3> KBD_Y<2> 23D1<> 29D6<> MEM_DATA<59> 9B8<> 10C1<>
+1_8V_GPU_VDDDI 21C7< 21D4< 38C3> 1625_EXTVCC 31D5<> 38D1> ATI_DVOD<0> 19B4< 20D7<> CHARGE_DISABLE 30A7<> CPU_DTI<0..2> 36D5> ENET_LINK_TXD<0> 13B4< 13D5> 39C6> KBD_Y<3> 23D1<> 29D6<> MEM_DATA<60> 9B8<> 10C1<>
+1_8V_MAIN 38D6> 39C6> 1625_FCB 31C6< ATI_DVOD<11..0> 36C1> CHARGE_LED_L 25D8<> 29C6<> 29D7< 39A6> CPU_DTI<1> 5C3< 8A3<> ENET_LINK_TXD<7..0> 37A5> GPU_VCORE_CNTL 20A3<> KBD_Y<4> 23D1<> 29D6<> MEM_DATA<61> 9B8<> 10B1<>
+1_8V_PVDD_NECK 20B5<> 38B3> 1625_INTVCC 31C5<> 38D1> ATI_DVOD<1> 19B4< 20D7<> CLK10M_PMU_XIN 29B6< CPU_DTI<2> 5C3< 8A3<> ENET_LINK_TXD<1> 13B4< 13D5> GPU_VCORE_CNTL_L 20A4< 20B7<> KBD_Y<5> 23D1<> 29C6<> MEM_DATA<62> 9B8<> 10B1<>
+1_8V_SLEEP 38D6> 1625_RUNSS 31C6< ATI_DVOD<2> 19B4< 20D7<> CLK10M_PMU_XOUT 29B6< CPU_EDTI 5A2< 5C3< ENET_LINK_TXD<2> 13B4< 13D5> GPU_VCORE_CNTL_RC 20A3<> KBD_Y<6> 23D1<> 29C6<> MEM_DATA<63> 9B8<> 10B1<>
+1_8V_SLEEP_NECK 34D2<> 38B3> 1625_SGND 31B7<> 38D1> ATI_DVOD<3> 19B4< 20D7<> CLK10M_PMU_XOUT_UF 29B7< CPU_EMODE0_L 5A3< 7A4< ENET_LINK_TXD<3> 13B4< 13D5> GPU_VCORE_NECK 20B5<> 38B3> KBD_Y<7> 23D1<> 29C6<> MEM_DQM<0> 9C6<> 10C7<> 35D5>
+1_95V_FW_DVDD 27C4< 27C7<> 27D5< 38A3> 1625_TG 31C5<> ATI_DVOD<4> 19B4< 20D7<> CLK18M_INT_EXT 14B6<> 35B1> CPU_EMODE1_L 5A3< 5C2< ENET_LINK_TXD<4> 13B4< 13D5> GPU_VCORE_PWR_SEQ 20A8<> LCD_DIGON_L 22B6< MEM_DQM<1> 9C6<> 10B7<> 35D5>
+1_95V_FW_DVDD_PORT1 27D6< 38A3> 1625_VFB 31B5<> ATI_DVOD<5> 19B4< 20D7<> CLK18M_INT_XIN 14A5< 35B1> CPU_GBL_L 5A7<> 8B5<> 36D5> ENET_LINK_TXD<5> 13B4< 13D5> GPU_VCORE_SEQ 20A8< LCD_PWREN_L 22B5<> MEM_DQM<2> 9C6<> 10C5<> 35C5>
+1_95V_FW_DVDD_RX0 27C5< 38A3> 1625_VIN 31C6< 38D1> ATI_DVOD<6> 19B4< 20D7<> CLK18M_INT_XOUT 14A5<> 35B1> CPU_HIT_L 5A7> 8B5< 8D2< 36D5> ENET_LINK_TXD<6> 13A4< 13D5> GPU_VCORE_SEQ_L 20A8< LED_LINK10 26B5<> MEM_DQM<3> 9C6<> 10B5<> 35C5>
+1_95V_FW_DVDD_TX0 27C5< 38A3> 1625_VSW 31C4<> 38D1> ATI_DVOD<7> 19B4< 20D7<> CLK18M_XTAL_IN 14A5< 35B1> CPU_HRESET_INV 7A7<> ENET_LINK_TXD<7> 13A4< 13D5> GPU_VCORE_SW 20A4<> 38B1> LED_LINK100 26B5<> MEM_DQM<4> 9C6<> 10C3<> 35B5>
+1_95V_FW_PLL400VDD 27C4< 38A3> 1772_ACIN 30B5< ATI_DVOD<8> 19B3< 20D7<> CLK25M_ENET_XIN 26A7<> CPU_HRESET_L 5B3< 5C2< 6A1<> 7A5< 7A8< 39D6> ENET_LINK_TX_EN 13D5<> 37A5> GPU_VCORE_SW_F 38B1> LED_RX_SPN 26B5> MEM_DQM<5> 9C6<> 10B3<> 35B5>
+1_95V_FW_PLL500VDD 27D4< 38A3> 1772_ACOK_L 30B5<> 30C4<> ATI_DVOD<9> 19B3< 20D7<> CLK25M_ENET_XOUT 26A7<> CPU_L1TSTCLK 5B2< 5B3< ENET_LINK_TX_ER 13D5<> 37A5> GPU_VCORE_VDDCI 19C8< 19D6< 38B3> LID_CLOSED_L 23B4<> 39B3> MEM_DQM<6> 9C6<> 10C1<> 35B5>
+1_95V_FW_PLLVDD 27D4< 27D6<> 38A3> 1772_BST 30B4<> ATI_DVOD<10> 19B3< 20D7<> CLK25M_XTAL_IN 26A7<> CPU_L2TSTCLK 5B3< 5C2< ENET_MDC 13C5> 26B7< 37A5> GPU_Y 20D6<> 22B8< LM2594_IN 27D8<> 38A3> MEM_DQM<7> 9C6<> 10B1<> 35A5>
+2_5V_CG_MAIN 14C6< 1772_BST_ESR 30C3< ATI_DVOD<11> 19B3< 20D7<> CLK32K_PMU_XIN 29B3<> CPU_LSSD_MODE 5B3< 5C2< ENET_MDIO 13C5<> 26B7<> 37A5> HD_ADDR<0> 24C2<> 24C3< LMU_DETECT 23C7< 23D6<> 39D1> MEM_DQS<0> 9C6<> 10C7<> 35D5>
+2_5V_GPU 38C3> 1772_CCI 30B5<> ATI_DVOD_DE 19B3< 20C7<> 36C1> CLK32K_PMU_XOUT 29B3<> CPU_MCP_L 5B3< 5D2< ENET_PHY_TXD<0> 13B5< 26C7< HD_ADDR<2..0> 37C5> LT1962_INT_ADJ 14D7< MEM_DQS<1> 9C6<> 10B7<> 35D5>
+2_5V_GPU_A2VDD 21D4< 21D7< 38B3> 1772_CCS 30B5< ATI_DVOVMODE 21A3< CLK32K_PMU_XOUT_UF 29B2<> CPU_PLL_CFG<0> 5C3< 7D3< ENET_PHY_TXD<7..0> 37A5> HD_ADDR<1> 24C2<> 24C3< LT1962_INT_BYP 14D7<> MEM_DQS<2> 9C6<> 10C5<> 35C5>
+2_5V_GPU_MCLK 21C7< 21D4< 38B3> 1772_CCV 30B5<> ATI_DVO_CLKP 19B3< 20C7<> 36C1> CLK33M_AIRPORT 12D8< 24D5<> 35C1> 39C3> CPU_PLL_CFG<1> 5C3< 7D3< ENET_PHY_TXD<1> 13B5< 26C7< HD_ADDR<2> 24B3< 24C1<> LTC1625_ITH 30D2<> MEM_DQS<3> 9C6<> 10B5<> 35C5>
+2_5V_GPU_MEMCORE 21C5< 38C3> 1772_CCV_RC 30B5< ATI_DVO_HSYNC 19B3< 20C7<> 36C1> CLK33M_AIRPORT_UF 12C7<> 35C1> CPU_PLL_CFG<2> 5C3< 7D3< ENET_PHY_TXD<2> 13B5< 26C7< HD_CS0_L 24C2<> 24C3< 37B5> LTC1962_INT_VIN 14D8<> 38A1> MEM_DQS<4> 9C6<> 10C3<> 35B5>
+2_5V_GPU_PNLIO 21A5< 38C3> 1772_CELLS 30B4< ATI_DVO_VSYNC 19B3< 20C7<> 36C1> CLK33M_CBUS 12D8< 18A7< 35C1> CPU_PLL_CFG<3> 5C3< 7D3< ENET_PHY_TXD<3> 13B5< 26C7< HD_CS1_L 24B3< 24C1<> 37B5> LTC3405_SW 26D4<> 38A3> MEM_DQS<5> 9C6<> 10B3<> 35B5>
+2_5V_INTREPID 9A7< 10D3< 10D5< 10D6< 10D8< 15D6< 1772_CLS 30A4< ATI_GPIO7_SPN 20C7<> CLK33M_CBUS_UF 12C7<> 35C1> CPU_PLL_CFG<4> 5C3< 7D3<> ENET_PHY_TXD<4> 13B5< 26C7< HD_DATA<0> 24C2<> 24D3< LTC3411_EN_L 34A7< MEM_DQS<6> 9C6<> 10C1<> 35B5>
16B8< 38D3> 1772_CSIN 30B4<> 37A2> ATI_GPIO8_PD 20C7<> CLK33M_NEC 12C8< 17B7< 35C1> CPU_PLL_CFGEXT 7D4<> ENET_PHY_TXD<5> 13B5< 26C7< HD_DATA<15..0> 37C5> LTC3411_GND 34A5<> 38A1> MEM_DQS<7> 9C6<> 10B1<> 35A5>
+2_5V_MAIN 38D6> 39C6> 1772_CSIP 30B4<> 37A2> ATI_GPIO9_SPN 20C7<> CLK33M_NEC_UF 12C7<> 35C1> CPU_PLL_FS00 7C4<> ENET_PHY_TXD<6> 13A5< 26C7< HD_DATA<1> 24C2<> 24D3< LTC3411_ITH 34A5<> 38A1> MEM_MUXSEL_LSB 9B6<> 10B5<> 10B7<> 35A5>
+2_5V_MARVELL 26B8< 26C4<> 38B3> 1772_CSSN 30C5< 37A2> ATI_GPIO10_SPN 20C7<> CLK66M_AGP_1_5V_TP 12C4> CPU_PLL_FS01 7C4< ENET_PHY_TXD<7> 13A5< 26C7< HD_DATA<2> 24D2<> 24D3< LTC3411_ITH_RC 34A5< 38A1> MEM_MUXSEL_LSB_L_TP 9B6<>
+2_5V_MARVELL_AVDD 26C4< 38B3> 1772_CSSP 30C5< 37A2> ATI_GPIO11_SPN 20C7<> CLK66M_GPU_AGP 12C8< 19B7< 35C1> CPU_PLL_FS10 7C4< ENET_PHY_TX_EN 13D6< 26C7< 37A5> HD_DATA<3> 24D2<> 24D3< LTC3411_SHDN 34A6<> 38A1> MEM_MUXSEL_MSB 9B6<> 10B1<> 10B3<> 35A5>
+2_5V_SLEEP 38D6> 1772_DCIN 30B5< 38C6> ATI_GPIO12_SPN 20C7<> CLK66M_GPU_AGP_UF 12C7<> 35C1> CPU_PLL_STOP_BASE 7C7< ENET_PHY_TX_ER 13D6< 26C7< 37A5> HD_DATA<4> 24C3< 24D2<> LTC3411_SYNC 34A6<> 38A1> MEM_MUXSEL_MSB_L_TP 9B6<>
+2_5V_SLEEP_NECK1 20C4<> 38B3> 1772_DHI 30B4<> ATI_GPIO13_SPN 20C7<> CLKENET_LINK_GBE_REF 13C5< 26C8< 35B1> CPU_PLL_STOP_OC 7C4<> 7C8<> 29B6<> ENET_RSET 26A5< HD_DATA<5> 24C3< 24D2<> LTC3411_VCC 34A6< 34A7< 38B1> MEM_RAS_L 9A5< 9C6<> 35A5>
+2_5V_SLEEP_NECK2 34D2<> 38B3> 1772_DLO 30B4<> ATI_HSYNC 20D5<> 22D8< CLKENET_LINK_GTX 13C5<> 35A1> CPU_PMONIN_L 5A3< 5C2< ENET_RST_L 26B7< HD_DATA<6> 24C3< 24D2<> LTC3707_START_RC 32B6< MEM_WE_L 9A5< 9C6<> 35A5>
+3V_AIRPORT 38C3> 39C3> 1772_DLOV 30B4<> 38C6> ATI_HSYNC_BUF 22D8<> CLKENET_LINK_RX 13D5< 26C8< 35B1> CPU_PULLDOWN 5A2< 5A3< 5A3< 5C7<> ENET_RX_DV 13D5< 26B7> 37A5> HD_DATA<7> 24C3< 24D2<> LUX_ALS_GAIN_SW 23B7<> 23D6<> MODEM_USB_DM 14B1< 25C3<> 37B2> 39D3>
C +3V_ATI_OSC_SLEEP 19B2< 38B3>

+3V_ATI_SS 19A3< 38B3>
+3V_CG_PLL_MAIN 14C6<
1772_GND
1772_ICHG
1772_ICTL
30A5<> 38C6>
30B5<>
30B5<>
ATI_MEMTEST
ATI_MEMVMODE0
ATI_MEMVMODE1
19A6<>
19A7<
19A7<
CLKENET_LINK_TX 13D5< 26D8< 35A1>
CLKENET_PHY_GBE_REF 26C7<> 35B1>
CLKENET_PHY_GTX 13C6< 26C7< 35A1>
CPU_PULLUP
CPU_QACK_L
CPU_QREQ_L
5A3< 5C2<
5B3< 8B5<> 36D5>
5B3> 8B5< 8C2< 36D5>
ENET_RX_ER
ENET_VSSC
ESP_EN_L
13C5< 26B7> 37A5>
26A7<>
6C2<> 6C2<
HD_DATA<8>
HD_DATA<9>
HD_DATA<10>
24C3< 24D1<>
24C3< 24D1<>
24C3< 24D1<>
LUX_ALS_OUT
LVDS_DDC_CLK
LVDS_DDC_DATA
23B7<> 23D6<>
20C5<> 22A4< 22B4<> 39B6>
20C5<> 22A4< 22B4<> 39B6>
MODEM_USB_DP
MPIC_CPU_INT_L
NEC_AMC_TP
14C1< 25C3<> 37B2> 39D3>
5B2< 5B3< 14B5>
17A5<
C
+3V_FW 27A3< 27D7<> 28D5< 38A3> 1772_IINP 30B5< ATI_OSC_OE 19A3< CLKENET_PHY_RX 26C7<> 35B1> CPU_SHD0_L 5A7<> 5D2< FAN1_GND 38B6> 39A3> HD_DATA<11> 24D1<> 24D3< LVDS_L0N 20B5> 22B4<> 37C2> 39B6> NEC_AVDD 17D6< 38A3>
+3V_FW_AVDD 27C6< 38A3> 1772_LDO 30C4<> 38C6> ATI_PVDD_BYP 21D6<> CLKENET_PHY_TX 26D7<> 35A1> CPU_SHD1_L 5A7<> 5D2< FAN1_PWM 25A4<> HD_DATA<12> 24B3< 24D1<> LVDS_L0P 20B5> 22B4<> 37C2> 39B6> NEC_AVSS_F 17A5< 17B4<
+3V_FW_AVDD_PORT0 27C6< 38A3> 1772_LX 30B4<> 38C6> ATI_R2SET 20D6<> CLKFW_LINK_LCLK 13C3<> 35A1> CPU_SMI_L 5B3< 5C2< 29C4<> FAN1_PWM_L 25A4<> 25B2<> HD_DATA<13> 24B3< 24D1<> LVDS_L1N 20B5> 22B4<> 37C2> 39B6> NEC_CRUN_L 17A7<>
+3V_FW_AVDD_PORT1 27C6< 38A3> 1772_REF 30B5<> ATI_RSET 20D6<> CLKFW_LINK_PCLK 13C3<> 27C3< 35A1> CPU_SRESET_L 5B2< 5B3< 39D6> FAN1_TACH 25A4< 25B2< 39A3> HD_DATA<14> 24C1<> 24C3< LVDS_L1P 20B5> 22B4<> 37C2> 39B6> NEC_IDSEL 17B7<
+3V_FW_AVDD_PORT2 27D6< 38A3> 1772_VCTL 30B5< ATI_RSTB_MSK 19C6<> CLKFW_PHY_LCLK 13C2< 27B7< 35A1> CPU_SRWX_L 5A3< 5C2< FAN2_GND 38B6> 39A3> HD_DATA<15> 24B3< 24C1<> LVDS_L2N 20B5> 22A4<> 37C2> 39B6> NEC_IO_RESET_L 17A7< 17B7<
+3V_FW_ESD 28B4<> 28D3<> 1778_BG 20A5<> 38B1> ATI_SSCLK_IN 19A2< 20B7<> 35B1> CLKFW_PHY_PCLK 27B4> 27C4< 35A1> CPU_TA_L 5B3< 8A3<> 8D2< 36D5> FAN2_PWM 25A3<> HD_DIOR_L 24A3< 24C2<> 37B5> LVDS_L2P 20B5> 22A4<> 37C2> 39B6> NEC_LEGC 17A7< 17A8<
+3V_FW_ESD_ILIM 28D4< 1778_BST 20A5<> 38B1> ATI_SSCLK_UF 19A2<> 35B1> CLKLVDS_LN 20B5> 22A4<> 37C2> 39B6> CPU_TBEN 5B3< 5D2< 8A5<> FAN2_PWM_L 25A3<> 25B2<> HD_DIOW_L 24A3< 24C1<> 37B5> LVDS_L3N_TP 20B5> NEC_LUSB_OCI 17B3< 17B5<
+3V_FW_UF 27D7<> 38A3> 1778_BST_RC 20A5< 38B1> ATI_TESTEN 20B7< CLKLVDS_LP 20B5> 22A4<> 37C2> 39B6> CPU_TBST_L 5A7> 8B5<> 36D5> FAN2_TACH 25A3< 25B2< 39A3> HD_DMACK_L 24A3< 24C2<> 37B5> LVDS_L3P_TP 20B5> NEC_LUSB_OCI_UF 17B1< 25D8<> 39A6>
+3V_GPU 12D1< 19B8< 19C6< 19C8< 19D6< 1778_FCB 20A6< 38B1> ATI_TMDS_CLKN 20B7> 20B8< 37B2> CLKLVDS_UN 20B5> 22A4<> 37C2> CPU_TEA_L 5B3< 8A3<> 8C2< 36D5> FB_4_85V_BU 31A5< HD_DMARQ 13C6< 24C2<> 37B5> LVDS_U0N 20C5> 22A4<> 37C2> NEC_LUSB_PPON 17B5> 25D8<> 39A6>
20C4< 20C5< 20C7< 20D7< 21A6< 21B1< 1778_GND 20A6< 20A7<> 38B1> ATI_TMDS_CLKP 20B7> 20B8< 37B2> CLKLVDS_UP 20B5> 22A4<> 37C2> CPU_THERM_DM 6A6<> 25A6< FP_PWR_EN 20C6<> 22A5< 22B3<> HD_INTRQ 13C6< 24C1<> 37B5> LVDS_U0P 20C5> 22A4<> 37C2> NEC_MAIN_RESET_L 17A7< 17A7<
38C3> 1778_ION 20A5< 38B1> ATI_TMDS_DN<0> 20B7> 20B7< 37B2> COMM_DTR_L 14C2> 25C1<> 39B3> CPU_THERM_DP 6A6<> 25A6< FP_PWR_EN_L 22B3<> HD_IOCHRDY 24A3< 24C1<> 37B5> LVDS_U1N 20C5> 22A4<> 37C2> NEC_NANDTESTEN_TP 17A4<
+3V_GPU_FLT 21B2< 38C3> 1778_ITH 20A6<> 38B1> ATI_TMDS_DN<1> 20B7> 20B8< 37B2> COMM_GPIO_L 14C2<> 25C2<> 39B3> CPU_TSIZ<0> 5A7> 8B5<> FWB_TPB0 27A3< HD_RESET_L 24A3< 24D2<> 37C5> LVDS_U1P 20C5> 22A4<> 37C2> NEC_NANDTESTOUT_TP 17A4<>
+3V_HALL_EFFECT 23B4<> 38B6> 39B3> 1778_ITH_RC 20A7< 38B1> ATI_TMDS_DN<2> 20B7< 20B7> 37B2> COMM_RESET_L 14C5<> 25C4<> 39B3> CPU_TSIZ<0..2> 36D5> FWB_TPB1 27A3< HIGH_VCORE 20A2<> LVDS_U2N 20B5> 22A4<> 37C2> NEC_NC<1> 17B5<>
+3V_INTREPID_USB 14C3< 38D3> 1778_SHDN_L 20A6<> ATI_TMDS_DP<0> 20B7< 20B7> 37B2> COMM_RING_DET_L 14B5<> 14C7< 25C3<> 29C6<> 39B3> CPU_TSIZ<1> 5A7> 8B5<> FWPLL_BYP 27D8<> HIGH_VCORE_DIVD 20A3< LVDS_U2P 20B5> 22A4<> 37C2> NEC_NC<2> 17B5<>
+3V_LCD 22B4<> 38B6> 39B6> 1778_TG 20A5<> 38B1> ATI_TMDS_DP<1> 20B7> 20B8< 37B2> COMM_RTS_L 14C2> 25C1<> 39B3> CPU_TSIZ<2> 5A7> 8B5<> FW_BIAS0 27A4<> HPD_4V_REF 22C3< LVDS_U3N_TP 20B5> NEC_OCI<3> 17B5<
+3V_LCD_SW 22B4<> 38B6> 1778_VCC 20A5< 38B1> ATI_TMDS_DP<2> 20B7< 20B7> 37B2> COMM_RXD 14C2<> 25C1<> 39B3> CPU_TS_L 5C7<> 8D2< 8D5<> 36D5> FW_BIAS1 27A4<> HPD_PWR_SNS_EN 20C7<> 22C3<> LVDS_U3P_TP 20B5> NEC_OCI<4> 17B5<
+3V_MAIN 23B7<> 38D6> 39C6> 1778_VFB 20A2< 20A5< 38B1> 39C6> ATI_TPVDD_BYP 21D1<> COMM_SHUTDOWN 14C5<> 25C5< 39B3> CPU_TT<0> 5A7<> 8B5<> FW_BMODE 27B6< HPD_PWR_SW 22C2< MAIN_RESET_L 14C7< 17A8< 18A7< 19B8< 19D4< NEC_OCI<5> 17B5<
+3V_MAIN_AUD 25C6<> 32C1<> 38B6> 1778_VIN 20A5< 38B1> ATI_VSYNC 20D5<> 22D8< COMM_SHUTDOWN_PU 25C4<> CPU_TT<0..4> 36D5> FW_CORE_ADJ 27C7< HPD_PWR_SW_BASE 22C2<> 24D6<> 29D4<> 29D7< 39C3> NEC_PCI_GNT_L 12C7<> 17B7<
+3V_MAIN_JUMPER 38D1> 1778_VRNG 20A6< 38B1> ATI_VSYNC_BUF 22D8<> COMM_TRXC 14C2<> 25C2<> 39B3> CPU_TT<1> 5A7<> 8B5<> FW_CORE_BYP 27C7<> HPD_REF_EN_L 22C2<> MAX1715_GND 34B5<> 34C5< 38C1> NEC_PCI_INTA_L 17B7<>
+3V_MAIN_LMU 23D7<> 38A1> 3405_MODE 26D5< ATI_X1CLK_SKEW<0> 20C2< 20C7<> COMM_TXD_L 14C2<> 25C2<> 39B3> CPU_TT<2> 5A7<> 8B5<> FW_CPS 27B6< IAC_FB 30D4< MAX1715_ON_RC 34C7<> NEC_PCI_INTB_L 17B7<>
+3V_MAIN_SSCG 38A1> 3405_VFB 26D4<> ATI_X1CLK_SKEW<1> 20B2< 20C7<> COMP_RC 31C6< CPU_TT<3> 5A7<> 8B5<> FW_GATE_EN 28D6<> IAC_RC_COMP 30D3< MAX1715_REF 34B5<> 38C1> NEC_PCI_INTC_L 17B7<>
+3V_NEC_VDD 17B3< 17D7< 17D7< 38A3> 3707_FCB 32C5< AUD_GND 25C8<> 38B6> CPU_AACK_L 5A7< 8B5<> 8C2< 36D5> CPU_TT<4> 5A7<> 8B5<> FW_GATE_EN_RC 28C6<> ICT_TRST_L 6B2<> 6C2< MAX1715_SKIP 34C4< 38C1> NEC_PCI_INT_L 14B5<> 14D7< 17B8<
+3V_PMU 38D6> 39C6> 3707_FSET 32C5< AUXWIN_PU 20C6<> CPU_ADDR<0> 5C7<> 8D5<> CPU_VCORE_HI_OC 7B8< 29D4<> 33C8< 33D7< FW_INPUT_PD 27A6< INTREPID_ACS_REF 8A5< MAX1715_TON 34C5< 38C1> NEC_PCI_REQ_L 12A7< 12D7<> 17B7>
+3V_PMU_AVCC 25B1< 29B6< 29D5<> 38C6> 3707_INTVCC 32D4<> 38D1> BATTV_HIGH 30B7<> CPU_ADDR<0..31> 36D5> CPU_VCORE_PWR_SEQ 33D8<> FW_LINK_CNTL<0> 13C3<> 27C3< INT_AGPPVT 12D4<> MAX1715_VCC 34D5< 38C1> NEC_PME_L 17A7< 17A7>
+3V_PMU_ESR 31A2< 38C6> 3707_SGND 32B5<> 38D1> BATTV_LOW 30B8<> CPU_ADDR<1> 5C7<> 8D5<> CPU_VCORE_SEQ 33D8< FW_LINK_CNTL<1..0> 37A5> INT_AGP_FB_IN 12C4< 35C1> MAX4172_OUT 30D4<> NEC_PPON3_TP 17B5>
+3V_PMU_RESET 29B7< 33A4<> 39C1> 3707_STBY 32C5<> BATT_14PBUS_EN 30C1<> CPU_ADDR<2> 5C7<> 8D5<> CPU_VCORE_SEQ_L 33D8< FW_LINK_CNTL<1> 13C3<> 27C3< INT_AGP_FB_OUT 12C4<> 35C1> MAXBUS_SLEEP 5A2< 5D2< 5D5< 6B2< 6B4< 7B7< 7D8< NEC_PPON4_TP 17B5>
+3V_SI_AVCC 19D3< A29_CLS_ADJ 30A5<> BATT_14V_GATE 30C1<> CPU_ADDR<3> 5C7<> 8D5<> CPU_VCORE_SLEEP 5D2< 5D8<> 6C6<> 33C1< 33D2< 38D3> FW_LINK_DATA<0> 13D3<> 27B7< INT_AGP_VREF 12B5< 12D4<> 19D6< 38C3> 8B3< 8B8< 8C8< 8D1< 8D8< 15D8< 16D8< NEC_PPON5_TP 17B5>
+3V_SI_PLLVCC 19D3< A29_CURRENT_ADJ 30C4<> BATT_24PBUS_EN 30C2<> CPU_ADDR<4> 5C7<> 8D5<> 39C6> FW_LINK_DATA<7..0> 37A5> INT_CPUFB_IN 8A5< 8B5< 35D1> 33D8< 38D3> NEC_RREF 17B5<>
+3V_SI_VCC 19D3< A29_DETECT 29A2< 30A5<> 30C4<> BATT_24V_GATE 30C1<> CPU_ADDR<5> 5C7<> 8C5<> CPU_VCORE_SNUB 33B3< FW_LINK_DATA<1> 13D3<> 27B7< INT_CPUFB_IN_NORM 8A4< 35D1> MDI0_PD 26B4< NEC_RUSB_OCI 17B3< 17B5<
+3V_SLEEP 38D6> 39A6> 39B6> A29_DET_L 29A3< BATT_CLK 30A4<> 39A3> CPU_ADDR<6> 5C7<> 8C5<> CPU_WT_L 5A7> 8B5<> 36C5> FW_LINK_DATA<2> 13D3<> 27B7< INT_CPUFB_LONG 8A3< 35D1> MDI1_PD 26B4< NEC_RUSB_OCI_UF 17B1< 25D1<> 39D3>
+3V_SLEEP_NECK 34D1<> 38B3> A29_DET_REF 29A4< BATT_DATA 30A4<> 39A3> CPU_ADDR<7> 5C7<> 8C5<> CSLOT_ADDR3_SPN 13B7> FW_LINK_DATA<3> 13D3<> 27B7< INT_CPUFB_OUT 8A5<> 8A5< 35D1> MDI2_PD 26B4< NEC_RUSB_PPON 17B5> 25D1<> 39D3>
+3V_SLEEP_PCCARD 18D7< 38C3> AC_DIV 30C7< BATT_DIV 30A5< CPU_ADDR<8> 5C7<> 8C5<> CSLOT_ADDR4_SPN 13B7> FW_LINK_DATA<4> 13C3<> 27B7< INT_CPUFB_OUT_NORM 8A4< 35D1> MDI3_PD 26B3< NEC_SMI_L_TP 17A7>
+3V_SLP_OK_L 32B4<> AC_ENABLE_GATE 30D6<> BATT_LOW 30A6<> CPU_ADDR<9> 5C7<> 8C5<> CSLOT_ADDR5_SPN 13B7> FW_LINK_DATA<5> 13C3<> 27A7< INT_CPUFB_OUT_SHORT 8A5< 35D1> MDI_M<0> 26B5<> 37D2> NEC_USB_DAM 17D2<> 25D7<> 37B2> 39D3>
+3V_SLP_ON 32A5<> AC_ENABLE_L 30C5<> BATT_LOW_L 30B6<> CPU_ADDR<10> 5B7<> 8C5<> CSLOT_ADDR6_SPN 13B7> FW_LINK_DATA<6> 13C3<> 27A7< INT_DDRCLK2_N_TP 9B6<> MDI_M<0..3> 39A3> NEC_USB_DAP 17D2<> 25D7<> 37B2> 39D3>
+4_6V_BU 31B3<> 32B7< 38C6> AC_GTR_18V 30C3<> BATT_NEG 30A4<> 38C6> 39A3> CPU_ADDR<11> 5B7<> 8C5<> CSLOT_ADDR7_SPN 13B7> FW_LINK_DATA<7> 13C3<> 27A7< INT_DDRCLK2_P_TP 9B6<> MDI_M<1> 26B5<> 37D2> NEC_USB_DBM 17C2<> 25D2<> 37B2> 39D3>
+4_85V_ESR 31A4< 38C6> AC_IN 26B8<> 28C8< 29B3< 30C5<> 30C6<> BBANG_HRESET_L 6A2< 6B3<> CPU_ADDR<12> 5B7<> 8C5<> CSLOT_ADDR8_SPN 13B7> FW_LINK_LREQ 13C3<> 37A5> INT_DDRCLK5_N_TP 9B6<> MDI_M<2> 26B5<> 37C2> NEC_USB_DBP 17C2<> 25D2<> 37A2> 39D3>
+4_85V_RAW 29A5< 31B4<> 38C6> AC_IN_FW_CNTL 28C7<> BBANG_JTAG_TCK 6A4< 6B2<> 6C2< CPU_ADDR<13> 5B7<> 8C5<> CSLOT_ADDR9_SPN 13B7> FW_LKON 13C3<> 27B4<> INT_DDRCLK5_P_TP 9B6<> MDI_M<3> 26B5<> 37C2> NEC_USB_RSDM1 17C5<>
+5V_DDC_SLEEP 22D3<> 22D5<> 38B6> 39B6> AC_IN_L 30C2<> 30C6<> BBANG_TCK_EN 6A4< CPU_ADDR<14> 5B7<> 8C5<> CSLOT_CE1_L_SPN 13C7> FW_OSC 27A4< 35A1> INT_ENET_RST_L 14B5<> 26B8< MDI_P<0> 26B5<> 37D2> NEC_USB_RSDM2 17C5<>
+5V_DDC_SLEEP_UF 22D6< 38B6> AC_IN_L_RC 30C2<> BB_EEPR_ADDR 6C2< 6D3< CPU_ADDR<15> 5B7<> 8C5<> CSLOT_CE2_L_SPN 13C7> FW_OSC_EN 27A3< INT_EXTINT3_PU 14A7< 14B5<> MDI_P<0..3> 39A3> NEC_USB_RSDP1 17C5<>
+5V_HD_SLEEP 24D1<> 32A7<> 38C6> ADAPTER_DET 25D8<> 29A4< 39A6> BB_EEPR_WP_PD 6D2<> CPU_ADDR<16> 5B7<> 8C5<> CSLOT_IORD_L_SPN 13C7> FW_PC_PD 27B6< INT_EXTINT8_PU 14B5<> 14C7< MDI_P<1> 26B5<> 37D2> NEC_USB_RSDP2 17C5<>
+5V_INV_SW 22B2<> 38B6> 39A6> ADAPTER_I_REG 30D3<> BB_MISO 6B3<> 6C2< CPU_ADDR<17> 5B7<> 8C5<> CSLOT_IOWAIT_L_PU 13C7< FW_PC_PU 27B6< INT_EXTINT10_PU 14B5<> 14B7< MDI_P<2> 26B5<> 37C2> NEC_XT1 17D5<
B +5V_INV_UF_SW
+5V_MAIN
+5V_MAIN_AUD
22B2<> 38B6>
38D6> 39A6> 39C6>
25C6<> 32C8<> 38B6>
ADT7460_ADR_ENABLE_L 25B3<>
ADT7460_TACH3_TP 25B3<
ADT7460_THERM_L 25B2<> 25B3<>
BB_MOSI
BB_RESET_L
BB_SCK
6B3<> 6C2<
6C3< 39C1>
6B3<> 6C2<
CPU_ADDR<18>
CPU_ADDR<19>
CPU_ADDR<20>
5B7<> 8C5<>
5B7<> 8C5<>
5B7<> 8C5<>
CSLOT_IOWR_L_SPN 13C7>
CSLOT_OE_L_SPN
CSLOT_WE_L_SPN
13C7>
13C7>
FW_PHY_CNTL<0> 27B4<> 27C4<
FW_PHY_CNTL<1..0> 37A5>
FW_PHY_CNTL<1> 27B4<> 27C4<
INT_EXTINT11_PU 14B5<> 14B7<
MDI_P<3>
MEM_ADDR<0>
MEM_ADDR<12..0>
26B5<> 37C2>
9B5< 9D6<>
35A5>
NEC_XT2
NEC_XT2_R
NUMLOCK_LED
17D5<>
17D4<
23D2<
B
+5V_MAIN_JUMPER 38D1> ADT7460_VCC 25C4< BB_XTAL1_SPN 6C3<> CPU_ADDR<21> 5B7<> 8C5<> CURRENT_THRESHOLD 30C3< FW_PHY_DATA<0> 27B7<> INT_EXTINT14_PU 14B5<> 14C7< MEM_ADDR<1> 9B5< 9D6<> NUMLOCK_LED_L 23D2< 29C7<
+5V_SLEEP 38D6> 39A6> 39C6> ADT7460_VCORE_MON 5C8<> 25B4<> BFR_TDO 6C2< 6C2<> CPU_ADDR<22> 5B7<> 8C5<> CY25811_S0 19A4< FW_PHY_DATA<7..0> 37A5> INT_EXTINT16_PU 14B5<> 14B7< MEM_ADDR<2> 9B5< 9D6<> OVER_18V_ADJ 30C3<>
+5V_SLEEP_OPT 24B5<> 38A1> AGP8X_DET_PU 19C6<> BKFD_PROT_EN_L 30C5<> CPU_ADDR<23> 5B7<> 8C5<> CY25811_S1 19A4< FW_PHY_DATA<1> 27B7<> INT_GPIO1_PU 14A7< 14C5<> 33C8< MEM_ADDR<3> 9B5< 9D6<> PCI1510_VR_EN_L 18C7<
+5V_TPAD_SLEEP 23B5<> 38B6> 39B3> AGP_AD<0> 12D2<> 19C7<> BKFD_PROT_GATE 30D5<> CPU_ADDR<24> 5B7<> 8C5<> DCDC_EN 20A7<> 28C8<> 32B7<> 33C7<> FW_PHY_DATA<2> 27B7<> INT_GPIO9_PU 14A7< 14B5<> MEM_ADDR<4> 9B5< 9D6<> PCI_AD<0> 9C3< 12D6<> 17D7<> 18C7<> 24B5<>
+14V_INV 22B2<> 38B6> 39B6> AGP_AD<15..0> 37D5> BRIGHT_PWM 22A2<> 39A6> CPU_ADDR<25> 5B7<> 8C5<> DCDC_EN_L 32B6< 32B7<> 34C7<> FW_PHY_DATA<3> 27B7<> INT_GPIO12_PU 14B5<> 14B7< MEM_ADDR<5> 9B5< 9D6<> PCI_AD<31..0> 37C5> 39D3>
+24V_PBUS 38D6> 39C6> AGP_AD<1> 12C2<> 19C7<> BRIGHT_PWM_UF 22A2<> CPU_ADDR<26> 5B7<> 8C5<> DDC_CLK_ISO 22D4<> FW_PHY_DATA<4> 27B7<> INT_GPIO15_PU 14B5<> 14B7< MEM_ADDR<6> 9B5< 9D6<> PCI_AD<1> 9C3< 12D6<> 17D7<> 18C7<> 24B6<>
+ADAPTER 30D8<> 31A7< 38C6> 39D1> AGP_AD<2> 12C2<> 19C7<> BT_USB_DM 14C1< 25D8<> 37B2> 39D3> CPU_ADDR<27> 5B7<> 8C5<> DDR_VREF 11D1< 11D3<> 11D5<> 11D6<> 11D8<> FW_PHY_DATA<5> 27A7<> INT_I2C_CLK0 6B3<> 6D2< 11A5<> 11A8<> 13C2< MEM_ADDR<7> 9B5< 9D6<> PCI_AD<2> 9C3< 12D6<> 17D7<> 18C7<> 24C5<>
+ADAPTER_ILIM 31A6<> 38C6> AGP_AD<3> 12C2<> 19C7<> BT_USB_DP 14C1< 25D8<> 37B2> 39D3> CPU_ADDR<28> 5B7<> 8C5<> 38D3> FW_PHY_DATA<6> 27A7<> 13C3<> 23D7<> 39C6> MEM_ADDR<8> 9B5< 9D6<> PCI_AD<3> 9C3< 12D6<> 17C7<> 18C7<> 24C6<>
+ADAPTER_OR_BATT 31A5<> 38C6> AGP_AD<4> 12C2<> 19C7<> CAPSLOCK_LED 23C2< CPU_ADDR<29> 5B7<> 8C5<> DVI_DDC_CLK 22D4<> FW_PHY_DATA<7> 27A7<> INT_I2C_CLK1 13C2< 13C3<> 14B7< 25B4< 39C6> MEM_ADDR<9> 9A5< 9D6<> PCI_AD<4> 9C3< 12D6<> 17C7<> 18C7<> 24C5<>
+ADAPTER_SENSE 30D4<> 38C6> AGP_AD<5> 12C2<> 19C7<> CAPSLOCK_LED_L 23C3< 29C7< CPU_ADDR<30> 5B7<> 8C5<> DVI_DDC_CLK_UF 22C5<> 22D3<> 39B6> FW_PHY_LPS 13C3<> 27B7< INT_I2C_CLK2 14A2<> 25C4<> 25D7<> 39A6> MEM_ADDR<10> 9A5< 9D6<> PCI_AD<5> 9C3< 12D6<> 17C7<> 18C7<> 24C6<>
+ADAPTER_SW 30D5<> 38C6> 38C6> AGP_AD<6> 12C2<> 19C7<> CBUS_ADDR<0> 18B1<> 18B4> CPU_ADDR<31> 5B7<> 8C5<> DVI_DDC_DATA 22C4<> FW_PHY_LREQ 13C2< 27B7< 37A5> INT_I2C_DATA0 6B3<> 6D2<> 11A5<> 11A8<> 13C2< MEM_ADDR<11> 9A5< 9D6<> PCI_AD<6> 9C3< 12C6<> 17C7<> 18C7<> 24C5<>
+BATT 38D6> AGP_AD<7> 12C2<> 19C7<> CBUS_ADDR<1> 18B1<> 18B4> CPU_ARTRY_L 5A7<> 8B5<> 8D2< 36D5> DVI_DDC_DATA_UF 22C5<> 39B6> FW_PHY_PD 14C5<> 27B7< 13C3<> 23D7<> 39C6> MEM_ADDR<12> 9A5< 9D6<> PCI_AD<7> 9C3< 12C6<> 17C7<> 18C7<> 24C6<>
+BATT_14V_FUSE 30D1<> 38C6> AGP_AD<8> 12C2<> 19C7<> CBUS_ADDR<2> 18B1<> 18B4> CPU_AVDD 5C3< 38D3> DVI_HPD 22C4<> FW_PHY_RESET_L 27A7< INT_I2C_DATA1 13B2< 13C3<> 14B7< 25B4<> 39C6> MEM_BA<0> 9A5< 9D6<> PCI_AD<8> 9C3< 12C6<> 17C7<> 18C7<> 24C6<>
+BATT_24V_FUSE 30B1< 30D2<> 38C6> AGP_AD<9> 12C2<> 19C7<> CBUS_ADDR<3> 18B1<> 18B4> CPU_AVDD_ADJ 5C2<> DVI_HPD_DIV 22C3< FW_PINT 13C3<> 27B4> 37A5> INT_I2C_DATA2 14A2<> 25C4<> 25D7<> 39A6> MEM_BA<1..0> 35A5> PCI_AD<9> 9C3< 12C6<> 17C7<> 18C7<> 24C5<>
+BATT_POS 30A4<> 38C6> 39A3> AGP_AD<10> 12C2<> 19C7<> CBUS_ADDR<4> 18B1<> 18B4> CPU_AVDD_SHDN_L 5C3<> DVI_HPD_UF 22C3< 22C5<> 39B6> FW_PLL_ADJ 27C7< INT_I2S0_SND_FROM_ADC 14B2< 25D7<> 39A6> MEM_BA<1> 9A5< 9C6<> PCI_AD<10> 9C3< 12C6<> 17C7<> 18C7<> 24C6<>
+BATT_RSNS 30B2< 38C6> AGP_AD<11> 12C2<> 19C7<> CBUS_ADDR<5> 18B1<> 18B4> CPU_AVDD_VIN 5C3< 38D3> DVI_TURN_ON 22D3<> FW_PORT1_SEL 27B6< INT_I2S0_SND_LRCLK 14B1< 25D8<> 39A6> MEM_CAS_L 9A5< 9C6<> 35A5> PCI_AD<11> 9C3< 12C6<> 17C7<> 18C7<> 24C5<>
+BATT_VSNS 30A4< 38C6> AGP_AD<12> 12C2<> 19C7<> CBUS_ADDR<6> 18B1<> 18B4> CPU_AVDD_VOUT 5C2<> 38D3> DVI_TURN_ON_BASE 22D2<> FW_POWER_UP 28C7<> INT_I2S0_SND_LRCLK_UF 14A3<> MEM_CKE<0> 9B6<> 9C5< PCI_AD<12> 9C3< 12C6<> 17C7<> 18C7<> 24C6<>
+FAN_PWR 25A3< 25A4< 38B6> 39A3> AGP_AD<13> 12C2<> 19C7<> CBUS_ADDR<7> 18B1<> 18B4> CPU_BG_L 5C7< 8C2< 8D5<> 36D5> DVI_TURN_ON_ILIM 22D2< FW_R0 27A4<> INT_I2S0_SND_MCLK 14B1< 25D8<> 35B1> 39A6> MEM_CKE<3..0> 35A5> PCI_AD<13> 9C3< 12C6<> 17C7<> 18C7<> 24C5<>
+FW_AMP_SENSE 38A3> AGP_AD<14> 12C2<> 19C7<> CBUS_ADDR<8> 18B1<> 18B4> CPU_BR_L 5C7> 8D2< 8D5< 36D5> EIDE_ADDR<0> 13B7> 24B8< FW_R1 27A4<> INT_I2S0_SND_MCLK_UF 14A3<> MEM_CKE<1> 9B6<> 9C5< PCI_AD<14> 9C3< 12C6<> 17C7<> 18C7<> 24C6<>
+FW_PBUS 28D7<> 38A3> AGP_AD<15> 12C2<> 19C7<> CBUS_ADDR<9> 18B1<> 18B4> CPU_BUS_VSEL 5C3< 7A6< EIDE_ADDR<2..0> 37B5> FW_TESTM 27A6< INT_I2S0_SND_SCLK 14B1< 25D7<> 39A6> MEM_CKE<2> 9B6<> 9C5< PCI_AD<15> 9C3< 12C6<> 17C7<> 18C7<> 24C5<>
+FW_PWR1 28C5< 38A3> AGP_AD<16> 12C2<> 19C7<> CBUS_ADDR<10> 18B4> 18C1<> CPU_CHKSTP_OUT_L 5B3<> 5C2< 39D6> EIDE_ADDR<1> 13B7> 24B8< FW_TPA1N 27B2<> 28A4<> 37D2> INT_I2S0_SND_SCLK_UF 14A3<> MEM_CKE<3> 9B6<> 9C5< PCI_AD<16> 9C3< 12C6<> 17C7<> 18C7<> 24C5<>
+FW_PWR_OR 27B8< 27D8<> 28D5<> 38A3> AGP_AD<31..16> 37D5> CBUS_ADDR<11> 18B1<> 18B4> CPU_CHKS_L 5A3< 5D2< EIDE_ADDR<2> 13B7> 24B8< FW_TPA1P 27B2<> 28A4<> 37D2> INT_I2S0_SND_TO_DAC 14B1< 25D8<> 39A6> MEM_CS_L<0> 9C5< 9C6<> PCI_AD<17> 9C3< 12C6<> 17C7<> 18C7<> 24C6<>
+FW_SW 28D5<> 38A3> AGP_AD<17> 12C2<> 19C7<> CBUS_ADDR<12> 18B1<> 18B4> CPU_CI_L 5A7> 8B5<> 36D5> EIDE_CS0_L 13B7> 24B8< 37B5> FW_TPAO0N 28C2<> 37D2> INT_I2S0_SND_TO_DAC_UF 14B3<> MEM_CS_L<3..0> 35A5> PCI_AD<18> 9C3< 12C6<> 17C7<> 18B7<> 24C5<>
+FW_VP0 28C1<> 38A3> 39A3> AGP_AD<18> 12C2<> 19C7<> CBUS_ADDR<13> 18B1<> 18B4> CPU_CLKOUT_SPN 5C3> EIDE_CS1_L 13B7> 24A8< 37B5> FW_TPAO0P 28C2<> 37D2> INT_JTAG_TEI 13C2< 13C5< 39D6> MEM_CS_L<1> 9C5< 9C6<> 24D4<
+FW_VP1 28A3<> 38A3> 39D1> AGP_AD<19> 12C2<> 19C7<> CBUS_ADDR<14> 18B1<> 18B4> CPU_CLK_EN 8A5< 29C4<> EIDE_DATA<0> 13C7<> 24C8< FW_TPB1N 27A2<> 28A4<> 37D2> INT_MEM_REF_H 9B6< 38C3> MEM_CS_L<2> 9C5< 9C6<> PCI_AD<19> 9B3< 12C6<> 17C7<> 18B7<> 24C6<>
+GPU_VDD15_NECK 20B5<> 38B3> AGP_AD<20> 12C2<> 19C7<> CBUS_ADDR<15> 18B1<> 18B4> CPU_DATA<0> 6D8<> 8D3<> EIDE_DATA<15..0> 37B5> FW_TPB1P 27B2<> 28A4<> 37D2> INT_MEM_VREF 9A7< 9B6<> 38C3> MEM_CS_L<3> 9C5< 9C6<> PCI_AD<20> 9B3< 12C6<> 17C7<> 18B7<> 24C5<>
+GPU_VDD15_UF 20B5<> 20D4<> 38B3> AGP_AD<21> 12C2<> 19C7<> CBUS_ADDR<16> 18B1<> 18B4< CPU_DATA<0..31> 36D5> EIDE_DATA<1> 13C7<> 24C8< FW_TPB2_PD 27A4<> INT_MOD_BITCLK 14A1< 25C3<> MEM_DATA<0> 9D8<> 10C7<> PCI_AD<21> 12C6<> 17C7<> 18B7<> 24C6<>
+HD_LOGIC_SLEEP 24C2<> 38C6> AGP_AD<22> 12C2<> 19C7<> CBUS_ADDR<17> 18B2<> 18B4> CPU_DATA<1> 6D8<> 8D3<> EIDE_DATA<2> 13C7<> 24C8< FW_TPBI0N 28C2<> 37D2> INT_MOD_BITCLK_UF 14A3<> 14A7< MEM_DATA<7..0> 35D5> PCI_AD<22> 12C6<> 17C7<> 18B7<> 24C5<>
+PBUS 38D6> 39C6> AGP_AD<23> 12C2<> 19C7<> CBUS_ADDR<18> 18B2<> 18B4> CPU_DATA<2> 6D8<> 8D3<> EIDE_DATA<3> 13C7<> 24C8< FW_TPBI0P 28C2<> 37D2> INT_MOD_CLKOUT 14A1< 25C4<> MEM_DATA<1> 9D8<> 10C7<> PCI_AD<23> 12C6<> 17C7<> 18B7<> 24C6<>
+PBUS_JUMPER 38D1> AGP_AD<24> 12C2<> 19C7<> CBUS_ADDR<19> 18B2<> 18B4> CPU_DATA<3> 6D8<> 8D3<> EIDE_DATA<4> 13C7<> 24B8< FW_TPI0N 27B2<> 28C3<> 37D2> 39A3> INT_MOD_CLKOUT_UF 14A3<> 14A7< MEM_DATA<2> 9D8<> 10C7<> PCI_AD<24> 9C1<> 12C6<> 17C7<> 18B7<> 24C5<>
+VCC_CBUS_SW 18B1<> 18B2<> 18D2<> 38C3> AGP_AD<25> 12C2<> 19C7<> CBUS_ADDR<20> 18B2<> 18B4> CPU_DATA<4> 6D8<> 8D3<> EIDE_DATA<5> 13B7<> 24B8< FW_TPI0P 27B2<> 28C3<> 37D2> 39A3> INT_MOD_DTI 14A2< 14A7< 25C3<> MEM_DATA<3> 9D8<> 10C7<> PCI_AD<25> 9C1<> 12C6<> 17C7<> 18B7<> 24C6<>
+VPP_CBUS_SW 18B1<> 18B2<> 18D2<> 38C3> AGP_AD<26> 12C2<> 19D7<> CBUS_ADDR<21> 18B2<> 18B4> CPU_DATA<5> 6D8<> 8D3<> EIDE_DATA<6> 13B7<> 24B8< FW_TPI1N 28A3<> 37D2> 39D1> INT_MOD_DTO 14B1< 25C4<> MEM_DATA<4> 9D8<> 10C7<> PCI_AD<26> 9C1<> 12C6<> 17C7<> 18B7<> 24C5<>
1V20_REF 30C7< 31C8< 38D1> AGP_AD<27> 12B2<> 19D7<> CBUS_ADDR<22> 18A4> 18B2<> CPU_DATA<6> 6D8<> 8D3<> EIDE_DATA<7> 13B7<> 24B8< FW_TPI1P 28A3<> 37D2> 39D1> INT_MOD_DTO_UF 14A3<> 14A7< MEM_DATA<5> 9D8<> 10C7<> PCI_AD<27> 9C1<> 12C6<> 17C8<> 18B7<> 24D6<>
1V65_REF 30A5< AGP_AD<28> 12B2<> 19D7<> CBUS_ADDR<23> 18A4> 18B2<> CPU_DATA<7> 6D8<> 8D3<> EIDE_DATA<8> 13B7<> 24D8< FW_TPO0N 27B2<> 28C3<> 37D2> 39A3> INT_MOD_SYNC 14A1< 25C3<> MEM_DATA<6> 9D8<> 10C7<> PCI_AD<28> 9C1<> 12C6<> 17C7<> 18B7<> 24C5<>
1_5V_BOOST 34C6<> 38C1> AGP_AD<29> 12B2<> 19D7<> CBUS_ADDR<24> 18A4> 18B2<> CPU_DATA<8> 6D8<> 8D3<> EIDE_DATA<9> 13B7<> 24C8< FW_TPO0P 27B2<> 28C3<> 37D2> 39A3> INT_MOD_SYNC_UF 14A3<> 14A7< MEM_DATA<7> 9D8<> 10C7<> PCI_AD<29> 9C1<> 12C6<> 17B7<> 18B7<> 24D6<>
1_5V_BST 34C5<> 38C1> AGP_AD<30> 12B2<> 19D7<> CBUS_ADDR<25> 18A4> 18B2<> CPU_DATA<9> 6C8<> 8D3<> EIDE_DATA<10> 13B7<> 24D8< FW_TPO0R 28C1<> 39A3> INT_PCI_FB_IN 12C7< 35C1> MEM_DATA<8> 9D8<> 10C7<> PCI_AD<30> 9C1<> 12C6<> 17B7<> 18B7<> 24D5<>
1_5V_DH 34C5<> 38C1> AGP_AD<31> 12B2<> 19D7<> CBUS_ADDR_16_UF 18B5<> CPU_DATA<10> 6C8<> 8D3<> EIDE_DATA<11> 13B7<> 24C8< FW_TPO1N 28A3<> 37D2> 39D1> INT_PCI_FB_OUT 12C7<> 35C1> MEM_DATA<15..8> 35D5> PCI_AD<31> 9C1<> 12C6<> 17B7<> 18B7<> 24D6<>
1_5V_DL 34B5<> 38C1> AGP_AD_STB<0> 12A2<> 12B2< 19D6<> 37D5> CBUS_BVD1_L 18A2<> 18C4< CPU_DATA<11> 6C8<> 8D3<> EIDE_DATA<12> 13B7<> 24C8< FW_TPO1P 28A3<> 37D2> 39D1> INT_PEND_PROC_INT 14A5> 29C4<> MEM_DATA<9> 9D8<> 10C7<> PCI_CBE<0> 12C7<> 17B7<> 18B7<> 24C5<>
1_5V_FB 34B5< 34B7< 38C1> AGP_AD_STB<1> 12A2<> 12B2< 19D6<> 37D5> CBUS_BVD2_L 18B2<> 18C4< CPU_DATA<12> 6C8<> 8C3<> EIDE_DATA<13> 13B7<> 24C8< FW_VDD_ON 38A3> INT_PROC_SLEEP_REQ_L 14A5< 29B4<> MEM_DATA<10> 9D8<> 10C7<> PCI_CBE<3..0> 37C5>
1_5V_ILIM 34C5<> 38C1> AGP_AD_STB_L<0> 12A2<> 12B2< 19D6<> 37D5> CBUS_CE1_L 18C1<> 18C4> CPU_DATA<13> 6C8<> 8C3<> EIDE_DATA<14> 13B7<> 24C8< FW_VGND 39A3> 39D1> INT_PU_RESET_L 13D3< 25D5<> 29A2< 29C4<> MEM_DATA<11> 9D8<> 10C7<> PCI_CBE<1> 12C7<> 17B7<> 18B7<> 24C6<>
A 1_5V_LX
1_5V_LX_F
34B5<> 38C1>
38C1>
1_5V_SLEEP_EN_L 34C7<> 34D7<>
AGP_AD_STB_L<1> 12A2< 12A2<> 19D6<> 37D5>
AGP_ATI_INT_L 14B5<> 19B7<>
AGP_ATI_RESET_L 19B7<
CBUS_CE2_L
CBUS_DATA<0>
CBUS_DATA<1>
18B2<> 18B4>
18A1<> 18A4<>
18A1<> 18A4<>
CPU_DATA<14>
CPU_DATA<15>
CPU_DATA<16>
6C8<> 8C3<>
6C8<> 8C3<>
6C8<> 8C3<>
EIDE_DATA<15>
EIDE_DMACK_L
EIDE_DMARQ
13B7<> 24C8<
13A7<> 24A8< 37B5>
13A7< 24A8< 37B5>
FW_VGND0
FW_VGND1
FW_VREG_PD
28C1<> 38A3>
28A3<> 38A3>
27A6<
INT_REF_CLK_IN 14A5< 14B5< 35C1>
INT_REF_CLK_OUT 14A5< 14B7< 35C1>
INT_REF_CLK_OUT_UF 14A5<> 35C1>
MEM_DATA<12>
MEM_DATA<13>
MEM_DATA<14>
9D8<> 10B7<>
9C8<> 10B7<>
9C8<> 10B7<>
PCI_CBE<2>
PCI_CBE<3>
PCI_DEVSEL_L
12C7<> 17B7<> 18B7<> 24C6<>
12C7<> 17B7<> 18B7<> 24C6<>
12B7< 12C7<> 17B7<> 18A7<> 24C5<>
A
1_8V_PVDD_STD 21D6< AGP_ATI_VREF 19B7< CBUS_DATA<2> 18A1<> 18A4<> CPU_DATA<17> 6C8<> 8C3<> EIDE_INT 13A7< 24A8< 37B5> FW_XI 27A4<> 35A1> INT_RESET_L 9B3< 13D3< 29C7< 29D4<> MEM_DATA<15> 9C8<> 10B7<> 37C5> 39C3>
1_8V_SLEEP_PWREN_L 34A3<> AGP_ATI_VREFG 19B7< CBUS_DATA<3> 18A4<> 18C1<> CPU_DATA<18> 6C8<> 8C3<> EIDE_IOCHRDY 13B7< 24A8< 37B5> GPU_AGP_TEST 19C6< INT_ROM_CS_L 12A5< 12C7> MEM_DATA<16> 9C8<> 10C5<> PCI_FRAME_L 12B7< 12C7<> 17B7<> 18B7<> 24C5<>
1_8V_SW 34A5<> 38A1> AGP_BUSY_L 12C4<> 12D2< 19D6> CBUS_DATA<4> 18A4<> 18C1<> CPU_DATA<19> 6C8<> 8C3<> EIDE_OPTICAL_ADDR<0> 24A5<> 24B7< GPU_B 20D6<> 22C8< INT_ROM_OE_L 12A5< 12C7> MEM_DATA<23..16> 35C5> 37C5> 39D3>
1_8V_SW_F 38A1> AGP_CBE<0> 12B2<> 19B7<> CBUS_DATA<5> 18A4<> 18C1<> CPU_DATA<20> 6C8<> 8C3<> EIDE_OPTICAL_ADDR<2..0> 37B5> 39C3> GPU_B_FILTR 22C8< INT_ROM_RW_L 12A5< 12C7> MEM_DATA<17> 9C8<> 10C5<> PCI_IRDY_L 12B7< 12C7<> 17B7<> 18B7<> 24C6<>
1_8V_TPVDD_STD 21D1< AGP_CBE<1..0> 37D5> CBUS_DATA<6> 18A4<> 18C1<> CPU_DATA<21> 6C8<> 8C3<> EIDE_OPTICAL_ADDR<1> 24A5<> 24B7< GPU_C 20D6<> 22A8< INT_SUSPEND_ACK_L 8B5> 29B6<> MEM_DATA<18> 9C8<> 10C5<> 37C5> 39D3>
1_8V_VFB 34A5<> 38A1> AGP_CBE<1> 12B2<> 19B7<> CBUS_DATA<7> 18A4<> 18C1<> CPU_DATA<22> 6C8<> 8C3<> EIDE_OPTICAL_ADDR<2> 24A6<> 24B7< GPU_COMP 20D6<> 22A8< INT_SUSPEND_REQ_L 8B5< 29B6<> 29C7< MEM_DATA<19> 9C8<> 10C5<> PCI_PAR 12C7<> 17B7<> 18B7<> 24C5<> 37C5>
2_5V_BOOST 34C4<> 38D1> AGP_CBE<2> 12B2<> 19B7<> CBUS_DATA<8> 18A2<> 18A4<> CPU_DATA<23> 6C8<> 8C3<> EIDE_OPTICAL_CS0_L 24A5<> 24B7< 37B5> 39C3> GPU_CORE_OK 20A6<> 20D4<> 21D2<> 21D7<> INT_TDO 13C5> 13D2< 14A6< 26A5< MEM_DATA<20> 9C8<> 10C5<> 39C3>
2_5V_BST 34C4<> 38D1> AGP_CBE<3..2> 37D5> CBUS_DATA<9> 18A2<> 18A4<> CPU_DATA<24> 6C8<> 8C3<> EIDE_OPTICAL_CS1_L 24A6<> 24A7< 37B5> 39C3> GPU_DVI_DDC_CLK 20C5<> 22D3<> INT_TST_MONIN_PD 13C2< 13C5< 39C6> MEM_DATA<21> 9C8<> 10C5<> PCI_PERR_L 17B7<> 18B7<> 18D7<
2_5V_DH 34C3<> 38D1> AGP_CBE<3> 12B2<> 19B7<> CBUS_DATA<10> 18A2<> 18A4<> CPU_DATA<25> 6C8<> 8C3<> EIDE_OPTICAL_DATA<0> 24A5<> 24C7< GPU_DVI_DDC_DATA 20C5<> 22C3<> INT_TST_MONOUT_TP 13C5> 39C6> MEM_DATA<22> 9C8<> 10C5<> PCI_SERR_L 17B7> 18B7> 18D7<
2_5V_DL 34B3<> 38C1> AGP_DEVSEL_L 12B2<> 12C2< 19B7<> 37D5> CBUS_DATA<11> 18A4<> 18C2<> CPU_DATA<26> 6C8<> 8C3<> EIDE_OPTICAL_DATA<15..0> 37B5> 39C3> GPU_DVOD<0> 19B3< 19C4< INT_TST_PLLEN_PD 13C5< 13D2< 39C6> MEM_DATA<23> 9C8<> 10C5<> PCI_STOP_L 12A7< 12C7<> 17B7<> 18B7<> 24C5<>
2_5V_FB 34B4< AGP_FRAME_L 12B2<> 12C2< 19B7<> 37D5> CBUS_DATA<12> 18A4<> 18C2<> CPU_DATA<27> 6C8<> 8C3<> EIDE_OPTICAL_DATA<1> 24A5<> 24C7< GPU_DVOD<11..0> 36C1> INT_WATCHDOG_L 14A5> 29C6<> MEM_DATA<24> 9C8<> 10C5<> 37C5> 39C3>
2_5V_ILIM 34C5<> 38C1> AGP_GNT_L 12C2< 12D2<> 19B7< 37D5> CBUS_DATA<13> 18A4<> 18C2<> CPU_DATA<28> 6C8<> 8C3<> EIDE_OPTICAL_DATA<2> 24A5<> 24C7< GPU_DVOD<1> 19B3< 19C4< INV_GND 22A1<> 39A6> MEM_DATA<31..24> 35C5> PCI_TRDY_L 12B7< 12C7<> 17B7<> 18A7<> 24C5<>
2_5V_LX 34B3<> 38D1> AGP_IRDY_L 12B2<> 12C2< 19B7<> 37D5> CBUS_DATA<14> 18A4<> 18C2<> CPU_DATA<29> 6C8<> 8C3<> EIDE_OPTICAL_DATA<3> 24A5<> 24C7< GPU_DVOD<2> 19B3< 19C4< INV_ON_PWM 20C6<> 22A3< MEM_DATA<25> 9C8<> 10C5<> 37C5> 39D3>
2_5V_LX_F 38D1> AGP_PAR 12B2<> 19B7> 37D5> CBUS_DATA<15> 18A4<> 18C2<> CPU_DATA<30> 6C8<> 8C3<> EIDE_OPTICAL_DATA<4> 24A5<> 24B7< GPU_DVOD<3> 19B3< 19C4< IO_RESET_L 17A8< 23D7<> 26B8< 29C6<> 29D7< MEM_DATA<26> 9C8<> 10C5<> PLL_STOP_L 7C4<> 7C8<>
2_5V_SLEEP_PWREN_L 34C2<> AGP_PIPE_L 12A2<> 12B2< CBUS_DET_1_L 18C2<> 18C4< 39C6> CPU_DATA<31> 6C8<> 8C3<> EIDE_OPTICAL_DATA<5> 24A5<> 24B7< GPU_DVOD<4> 19B3< 19C4< JTAG_ASIC_TCK 13C5< 13D2< 26A5< 39D6> MEM_DATA<27> 9C8<> 10C5<> PMU_ACK_L 14C2< 29C4<>
3V_5V_OK 32B4<> 34A8< 34D6< AGP_RBF_L 12A2<> 12C2< 19C6> 37C5> CBUS_DET_2_L 18A2<> 18C4< 39C6> CPU_DATA<32> 6C8<> 8C3<> 8D8< EIDE_OPTICAL_DATA<6> 24A5<> 24B7< GPU_DVOD<5> 19B3< 19C4< JTAG_ASIC_TDI 13C5< 13D2< 39D6> MEM_DATA<28> 9C8<> 10C5<> PMU_AC_DET 29A4< 29B4<>
41
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PMU_AC_IN 29B4<> RAM_DATA_B<25..24> 35C5> THERM2_A_DM 25A7< 25A8< 37A2>
PMU_BATT0_DET_L 29B4<> RAM_DATA_B<25> 10C6<> 11C5<> THERM2_A_DP 25A7< 25A8< 37A2>
PMU_BATT1_DET_L_PU 29B4<> 29D2< RAM_DATA_B<26> 10C6<> 11C5<> 35C5> THERM2_DM 25A5< 25A6< 25B5<> 25B6< 37A2>
PMU_BATT_DET_L 29B3< 29D2< 30A4<> 39A3> RAM_DATA_B<27> 10C6<> 11C5<> THERM2_DP 25A5< 25A6< 25B5<> 25B6< 37A2>
PMU_BYTE 29B6< 29C7< RAM_DATA_B<31..27> 35C5> THERM2_M_DM 25B7< 25B8< 37A2>
PMU_CAPSLOCK_LED_L 29C6<> RAM_DATA_B<28> 10C6<> 11C3<> THERM2_M_DP 25B7< 25B8< 37A2>
PMU_CHARGE_V 29C4<> 30B8<> RAM_DATA_B<29> 10C6<> 11C3<> THERM_INV 25B1<>
PMU_CHRG_BATT_0 29C4<> 30A8<> RAM_DATA_B<30> 10C6<> 11C3<> THERM_L_OC 25B1<> 29B4<>
PMU_CLK 14C2<> 29C4<> RAM_DATA_B<31> 10C6<> 11C3<> TMDS_CLKN 19B1< 19C1< 19D1< 22C8<> 37C2>
PMU_CNVSS 29B6< 29C7< RAM_DATA_B<32> 10D4<> 11B5<> TMDS_CLKP 19B1< 19C1< 19D2< 22C8<> 37C2>
PMU_CPU_HRESET_L 6A2< 6C3<> 29C4<> 39C1> RAM_DATA_B<39..32> 35B5> TMDS_CONN_CLKN 22C7<> 22C7<> 36C1> 39C6>
PMU_EPM 29C4<> 29D2< RAM_DATA_B<33> 10C4<> 11B5<> TMDS_CONN_CLKP 22C7<> 22C7<> 36C1> 39C6>
PMU_FROM_INT 14C2<> 29C4<> RAM_DATA_B<34> 10C4<> 11B5<> TMDS_CONN_DN<0> 22D6<> 36C1>
PMU_I2C_CLK 29B4<> 29C2< RAM_DATA_B<35> 10C4<> 11B5<> TMDS_CONN_DN<1> 22D6<> 36B1>
PMU_I2C_DATA 29B4<> 29C2< RAM_DATA_B<36> 10C4<> 11B3<> TMDS_CONN_DN<2> 22D6<> 36B1>
PMU_INT_L 14B5<> 14B7< 29B6<> RAM_DATA_B<37> 10C4<> 11B3<> TMDS_CONN_DP<0> 22D6<> 36C1>
PMU_INT_NMI 14B5<> 14B7< 29D4<> RAM_DATA_B<38> 10C4<> 11B3<> TMDS_CONN_DP<1> 22D6<> 36B1>
PMU_KB_RESET_IN1 29A7<> RAM_DATA_B<39> 10C4<> 11B3<> TMDS_CONN_DP<2> 22D6<> 36B1>
D
PMU_KB_RESET_IN2 29A7<>
PMU_KB_RESET_L 29A6> 29B7< 39C1>
PMU_LID_CLOSED_L 23B3< 23D6<> 29B2< 29C4<> 39D1>
RAM_DATA_B<40> 10C4<> 11B5<>
RAM_DATA_B<47..40> 35B5>
RAM_DATA_B<41> 10C4<> 11B5<>
TMDS_DN<0>
TMDS_DN<0..2>
TMDS_DN<1>
19B1<
39C6>
19B1<
19C1< 19D1< 22D7<> 37C2>
19B1< 19C1< 22D5<> 37B2>

D
PMU_NMI_BUTTON_L 29C2< 29C4<> RAM_DATA_B<42> 10C4<> 11A5<> TMDS_DN<2> 19A1< 19B1< 19C1< 22D5<> 37B2>
PMU_NMI_L 29C2< 29C4<> RAM_DATA_B<43> 10C4<> 11A5<> TMDS_DP<0> 19B1< 19C1< 19D2< 22D7<> 37B2>
PMU_NUMLOCK_LED_L 29C6<> RAM_DATA_B<44> 10C4<> 11B3<> TMDS_DP<0..2> 39C6>
PMU_OOPS 29B2< 29B4<> RAM_DATA_B<45> 10C4<> 11B3<> TMDS_DP<1> 19B1< 19B1< 19C2< 22C5<> 37B2>
PMU_PME_L 14A5<> 17A8< 24D5<> 29B2< 29C4<> RAM_DATA_B<46> 10C4<> 11A3<> TMDS_DP<2> 19A1< 19B1< 19C2< 22D5<> 37B2>
39C3> RAM_DATA_B<47> 10C4<> 11A3<> TPAD_F_RXD 23B5<> 39B3>
PMU_POWERUP_OK 29B4<> 29D2< RAM_DATA_B<48> 10D2<> 11A5<> TPAD_F_TXD 23B5<> 39B3>
PMU_POWER_UP_L 28C8<> 29C6<> 29D7< 32B8< RAM_DATA_B<55..48> 35B5> TPAD_RXD 23A6< 29C2< 29C4<>
PMU_REQ_L 14B7< 14C2> 29C4<> RAM_DATA_B<49> 10C2<> 11A5<> TPAD_TXD 23B6< 29B2< 29C4<>
PMU_RESET_BUTTON_L 23A7< 29C4<> 29D2< RAM_DATA_B<50> 10C2<> 11A5<> TPS2211_SHTDWN_L 18C5<
PMU_RESET_L 29B6<> RAM_DATA_B<51> 10C2<> 11A5<> TV_C 22A6<> 39A6>
PMU_SLEEP_LED 23C7<> 23D6<> 39D1> RAM_DATA_B<52> 10C2<> 11A3<> TV_COMP 22A6<> 39A6>
PMU_SLEEP_LED_L 23C8<> 29C4<> RAM_DATA_B<53> 10C2<> 11A3<> TV_GND1 22B6<> 38B6> 39A6>
PMU_SMB_CLK 29B4<> 29C2< 30A3< RAM_DATA_B<54> 10C2<> 11A3<> TV_GND2 22A6<> 38B6> 39A6>
PMU_SMB_DATA 29B4<> 29C2< 30A2< RAM_DATA_B<55> 10C2<> 11A3<> TV_Y 22A6<> 39A6>
PMU_TO_INT 14C2<> 29C4<> RAM_DATA_B<56> 10C2<> 11A5<> UIDE_ADDR<0> 13D7<> 24C4<
POWER_UP 28D7<> RAM_DATA_B<63..56> 35A5> UIDE_ADDR<2..0> 37C5>
POWER_VALID 29B2< 29C4<> RAM_DATA_B<57> 10C2<> 11A5<> UIDE_ADDR<1> 13D7<> 24C4<
PWR_BUTTON_L 23A7< 23B4<> RAM_DATA_B<58> 10C2<> 11A5<> UIDE_ADDR<2> 13D7<> 24B4<
RAM_ADDR<0> 9B4< 11B3<> 11B6<> RAM_DATA_B<59> 10C2<> 11A5<> UIDE_CS0_L 13C7<> 24C4< 37C5>
RAM_ADDR<12..0> 35A5> RAM_DATA_B<60> 10C2<> 11A3<> UIDE_CS1_L 13C7<> 24B4< 37C5>
RAM_ADDR<1> 9B4< 11B5<> 11B8<> RAM_DATA_B<61> 10C2<> 11A3<> UIDE_DATA<0> 13D7<> 24D4<
RAM_ADDR<2> 9B4< 11B3<> 11B6<> RAM_DATA_B<62> 10C2<> 11A3<> UIDE_DATA<6..0> 37C5>
RAM_ADDR<3> 9B4< 11B5<> 11B8<> RAM_DATA_B<63> 10C2<> 11A3<> UIDE_DATA<1> 13D7<> 24D4<
RAM_ADDR<4> 9B4< 11B3<> 11B6<> RAM_DQM_A<0> 10B8<> 11D6<> 35D5> UIDE_DATA<2> 13D7<> 24D4<
RAM_ADDR<5> 9B4< 11B5<> 11B8<> RAM_DQM_A<1> 10C7<> 11D6<> 35C5> UIDE_DATA<3> 13D7<> 24D4<
RAM_ADDR<6> 9B4< 11B3<> 11B6<> RAM_DQM_A<2> 10B6<> 11C6<> 35C5> UIDE_DATA<4> 13D7<> 24C4<
RAM_ADDR<7> 9B4< 11B5<> 11B8<> RAM_DQM_A<3> 10C5<> 11C6<> 35C5> UIDE_DATA<5> 13D7<> 24C4<
RAM_ADDR<8> 9B4< 11B3<> 11B6<> RAM_DQM_A<4> 10B4<> 11B6<> 35B5> UIDE_DATA<6> 13D7<> 24C4<
RAM_ADDR<9> 9A4< 11B5<> 11B8<> RAM_DQM_A<5> 10C3<> 11B6<> 35B5> UIDE_DATA<7> 13D7<> 24C4< 37C5>
RAM_ADDR<10> 9A4< 11B5<> 11B8<> RAM_DQM_A<6> 10B2<> 11A6<> 35B5> UIDE_DATA<8> 13D7<> 24C4<
RAM_ADDR<11> 9A4< 11B3<> 11B6<> RAM_DQM_A<7> 10C1<> 11A6<> 35A5> UIDE_DATA<15..8> 37C5>
RAM_ADDR<12> 9A4< 11B5<> 11B8<> RAM_DQM_B<0> 10C8<> 11D3<> 35D5> UIDE_DATA<9> 13D7<> 24C4<
RAM_BA<0> 9A4< 11B5<> 11B8<> RAM_DQM_B<1> 10C8<> 11D3<> 35C5> UIDE_DATA<10> 13D7<> 24C4<
RAM_BA<1..0> 35A5> RAM_DQM_B<2> 10C6<> 11C3<> 35C5> UIDE_DATA<11> 13D7<> 24D4<
RAM_BA<1> 9A4< 11B3<> 11B6<> RAM_DQM_B<3> 10C6<> 11C3<> 35C5> UIDE_DATA<12> 13D7<> 24B4<
RAM_CAS_L 9A4< 11B3<> 11B6<> 35A5> RAM_DQM_B<4> 10C4<> 11B3<> 35B5> UIDE_DATA<13> 13D7<> 24B4<
RAM_CKE<0> 9A4< 9C4< 11C6<> RAM_DQM_B<5> 10C4<> 11B3<> 35B5> UIDE_DATA<14> 13D7<> 24C4<
RAM_CKE<3..0> 35A5> RAM_DQM_B<6> 10C2<> 11A3<> 35B5> UIDE_DATA<15> 13D7<> 24B4<
RAM_CKE<1> 9A4< 9C4< 11C8<> RAM_DQM_B<7> 10C2<> 11A3<> 35A5> UIDE_DIOR_L 13C7<> 24A4< 37C5>
RAM_CKE<2> 9A4< 9C4< 11C3<> RAM_DQS_A<0> 10B8<> 11D8<> 35D5> UIDE_DIOW_L 13C7<> 24A4< 37C5>
C RAM_CKE<3>
RAM_CS_L<0>
RAM_CS_L<3..0>
9A4< 9C4< 11C5<>
9C4< 11B8<>
35A5>
RAM_DQS_A<1>
RAM_DQS_A<2>
RAM_DQS_A<3>
10C7<>
10B6<>
10C5<>
11D8<>
11C8<>
11C8<>
35C5>
35C5>
35C5>
UIDE_DMACK_L
UIDE_DMARQ
UIDE_INTRQ
13C7<> 24A4< 37C5>
13C7<> 37C5>
13C7< 37C5>
C
RAM_CS_L<1> 9C4< 11B6<> RAM_DQS_A<4> 10B4<> 11B8<> 35B5> UIDE_IOCHRDY 13C7< 24A4< 37C5>
RAM_CS_L<2> 9C4< 11B5<> RAM_DQS_A<5> 10C3<> 11B8<> 35B5> UIDE_REF 13C7<> 38C3>
RAM_CS_L<3> 9C4< 11B3<> RAM_DQS_A<6> 10B2<> 11A8<> 35B5> UIDE_RST_L 13C7<> 24A4< 37C5>
RAM_DATA_A<0> 10C8<> 11D8<> RAM_DQS_A<7> 10C1<> 11A8<> 35A5> USB_DAM 14B2<> 14D2<
RAM_DATA_A<7..0> 35D5> RAM_DQS_B<0> 10C8<> 11D5<> 35D5> USB_DAP 14B2<> 14D2<
RAM_DATA_A<1> 10C8<> 11D8<> RAM_DQS_B<1> 10C8<> 11D5<> 35C5> USB_DBM 14B2<> 14D2<
RAM_DATA_A<2> 10C8<> 11D8<> RAM_DQS_B<2> 10C6<> 11C5<> 35C5> USB_DBP 14B2<> 14D2<
RAM_DATA_A<3> 10B8<> 11D8<> RAM_DQS_B<3> 10C6<> 11C5<> 35C5> USB_DCM 14B2<> 14D2<
RAM_DATA_A<4> 10B8<> 11D6<> RAM_DQS_B<4> 10C4<> 11B5<> 35B5> USB_DCP 14B2<> 14D2<
RAM_DATA_A<5> 10B8<> 11D6<> RAM_DQS_B<5> 10C4<> 11B5<> 35B5> USB_DDM 14B2<> 14D2<
RAM_DATA_A<6> 10B8<> 11D6<> RAM_DQS_B<6> 10C2<> 11A5<> 35B5> USB_DDP 14B2<> 14C2<
RAM_DATA_A<7> 10B8<> 11D6<> RAM_DQS_B<7> 10C2<> 11A5<> 35A5> USB_DEM 14B2<> 14C2< 37B2>
RAM_DATA_A<8> 10B8<> 11D8<> RAM_RAS_L 9A4< 11B3<> 11B6<> 35A5> USB_DEP 14B2<> 14C2< 37B2>
RAM_DATA_A<15..8> 35C5> RAM_WE_L 9A4< 11B5<> 11B8<> 35A5> USB_DFM 14B2< 14B2<> 37B2>
RAM_DATA_A<9> 10C7<> 11D8<> RESET_VREF 6C3<> USB_DFP 14B2<> 14C2< 37B2>
RAM_DATA_A<10> 10C7<> 11D8<> RF_DISABLE_L 24D6<> 39C3> USB_OC_AB_L 14B2< 14C7<
RAM_DATA_A<11> 10C7<> 11D8<> ROM_CS_L 9B3< 12A4< 39C3> USB_OC_CD_L 14B2< 14C7<
RAM_DATA_A<12> 10C7<> 11D6<> ROM_CS_TP_L 9C3< 24B6<> USB_OC_EF_L 14B2< 14C7<
RAM_DATA_A<13> 10C7<> 11D6<> ROM_OE_L 9B3< 12A4< 39C3> USB_PWREN_AB_L 14B2<> 14C7<
RAM_DATA_A<14> 10C7<> 11D6<> ROM_OE_TP_L 9B3< 24C5<> USB_PWREN_CD_L 14B2<> 14C7<
RAM_DATA_A<15> 10C7<> 11D6<> ROM_ONBOARD_CS_L 9B3< 39C3> USB_PWREN_EF_L 14B2<> 14C7<
RAM_DATA_A<16> 10C6<> 11D8<> ROM_ONBOARD_CS_TP_L 9B3< 24C6<> VCORE_AB_SEL 33A7<> 33C6<
RAM_DATA_A<23..16> 35C5> ROM_RW_L 9B3< 12A4< 39C3> VCORE_AB_SEL_INV 33A7<>
RAM_DATA_A<17> 10C6<> 11C8<> ROM_RW_TP_L 9B3< 24C6<> VCORE_AB_SEL_OPT 33A6<>
RAM_DATA_A<18> 10C6<> 11C8<> ROM_WP_L 9B3< VCORE_BOOST 33C4<> 38C1>
RAM_DATA_A<19> 10B6<> 11C8<> SI_A2 19C4< VCORE_BST 33C5<> 38C1>
RAM_DATA_A<20> 10B6<> 11D6<> SI_EXT_SWING_SET 19C2<> VCORE_CC 33B6<> 38C1>
RAM_DATA_A<21> 10B6<> 11C6<> SI_HPD 19C4< VCORE_D0 33A3<>
RAM_DATA_A<22> 10B6<> 11C6<> SI_I2C_CLK 19D4< 20C5<> VCORE_D1 33A3<>
RAM_DATA_A<23> 10B6<> 11C6<> SI_I2S_DATA 19C4< 20C5<> VCORE_D2 33A3<>
RAM_DATA_A<24> 10B6<> 11C8<> SI_MSEN 19D2<> VCORE_D3 33A3<>
RAM_DATA_A<31..24> 35C5> SI_PD_L 19C4< VCORE_D4 33A3<>
RAM_DATA_A<25> 10C5<> 11C8<> SI_RST_L 19C4< VCORE_DH 33B5<> 38C1>
RAM_DATA_A<26> 10C5<> 11C8<> SI_TMDS_CLKN 19C2< 19C2<> 36D1> VCORE_DL 33B5<> 38C1>
RAM_DATA_A<27> 10C5<> 11C8<> SI_TMDS_CLKP 19C2<> 19C2< 36D1> VCORE_FAST<1> 33D4< 33D5<
RAM_DATA_A<28> 10C5<> 11C6<> SI_TMDS_CLK_STM 19D1< VCORE_FAST<2> 33D4< 33D5<
RAM_DATA_A<29> 10C5<> 11C6<> SI_TMDS_D0_STM 19D1< VCORE_FAST<3> 33D4< 33D5<
RAM_DATA_A<30> 10C5<> 11C6<> SI_TMDS_D1_STM 19D1< VCORE_FAST<4> 33D4< 33D5<
RAM_DATA_A<31> 10C5<> 11C6<> SI_TMDS_D2_STM 19C1< VCORE_FB 33B5< 38B1> 39C6>
RAM_DATA_A<32> 10C4<> 11B8<> SI_TMDS_DN<0> 19C2< 19C2<> 36D1> VCORE_GND 33B5<> 38B1>
RAM_DATA_A<39..32> 35B5> SI_TMDS_DN<1> 19B2< 19C2<> 36D1> VCORE_GNDA 33B6<> 38B1>
B RAM_DATA_A<33>
RAM_DATA_A<34>
RAM_DATA_A<35>
10C4<> 11B8<>
10C4<> 11B8<>
10C4<> 11B8<>
SI_TMDS_DN<2>
SI_TMDS_DP<0>
SI_TMDS_DP<1>
19B2< 19C2<> 36C1>
19C2< 19C2<> 36D1>
19B2< 19C2<> 36C1>
VCORE_GNDDIV 33A5< 33A5< 38B1>
VCORE_GNDDIV_TEST 33A4<>
VCORE_GNDSNS 33A1<> 33A5< 38B1>
B
RAM_DATA_A<36> 10B4<> 11B6<> SI_TMDS_DP<2> 19B2< 19C2<> 36C1> VCORE_GNDSNS_TEST 33A4<>
RAM_DATA_A<37> 10B4<> 11B6<> SI_VREF_IDCK_N 19C2< 19C4< VCORE_ILIM 33C6<> 38C1>
RAM_DATA_A<38> 10B4<> 11B6<> SLEEP 23D7<> 25D7<> 29B6<> 29D7< 32A4< VCORE_LX 33B5<> 38C1>
RAM_DATA_A<39> 10B4<> 11B6<> 32A6< 32B3< 32B8<> 34B3< 34C2< 39C1> VCORE_MUX_EN 33D5<>
RAM_DATA_A<40> 10B4<> 11B8<> VCORE_MUX_SEL 33D5<>
RAM_DATA_A<47..40> 35B5> SLEEP_LED 23C3<> 39C1> VCORE_OFFSET_DIV 33B6<>
RAM_DATA_A<41> 10D3<> 11B8<> SLEEP_LED_DGND 23C3<> VCORE_REF 33B6<> 38C1>
RAM_DATA_A<42> 10C3<> 11A8<> SLEEP_LED_I 23D3< VCORE_SHDN_L 5B3< 33C6<>
RAM_DATA_A<43> 10C3<> 11A8<> SLEEP_LED_L 23D4< VCORE_SHDN_L_3V 5B3<>
RAM_DATA_A<44> 10C3<> 11B6<> SLEEP_LED_SW_L 23D4<> VCORE_SLOW<1> 33D6<
RAM_DATA_A<45> 10C3<> 11B6<> SLEEP_LED_UF 23D3< VCORE_SLOW<2> 33D6<
RAM_DATA_A<46> 10C3<> 11A6<> SLEEP_LS5 32A4<> 32A8< VCORE_SLOW<3> 33D6<
RAM_DATA_A<47> 10C3<> 11A6<> SLEEP_LS5_EN_L 32A5<> VCORE_SLOW<4> 33D6<
RAM_DATA_A<48> 10C2<> 11A8<> SLEEP_L_LS5 18D5< 20A7<> 26A8<> 32A5<> 33C7<> VCORE_SNS 33A1<> 38B1>
RAM_DATA_A<55..48> 35B5> 34C8< VCORE_TIME 33B4<> 38B1>
RAM_DATA_A<49> 10C2<> 11A8<> SLEEP_L_LS5_EN_L 32A6<> VCORE_TON 33B6< 38C1>
RAM_DATA_A<50> 10C2<> 11A8<> SLEEP_L_LS5_INV 34A3< 34C2< 34C8<> VCORE_VCC 33C6< 38C1>
RAM_DATA_A<51> 10C2<> 11A8<> SLEEP_L_LS5_NET 32B3<> 34C8<> VCORE_VGATE 14B5< 14B7< 33B4> 38B1>
RAM_DATA_A<52> 10B2<> 11A6<> SLEEP_NET 32A3<> VCORE_VID<0> 33B7<
RAM_DATA_A<53> 10B2<> 11A6<> SLEEP_NET_INV 32A3<> VCORE_VID<1> 33B7< 33D3< 33D4>
RAM_DATA_A<54> 10B2<> 11A6<> SND_AMP_MUTE 25C7<> 25D6<> 39A6> VCORE_VID<2> 33B7< 33D3< 33D4>
RAM_DATA_A<55> 10B2<> 11A6<> SND_AMP_MUTE_CTRL 25B5<> 25D6<> VCORE_VID<3> 33B7< 33D3< 33D4>
RAM_DATA_A<56> 10B2<> 11A8<> SND_AMP_MUTE_L 14B5<> 25D5<> VCORE_VID<4> 33B7< 33D3< 33D4>
RAM_DATA_A<63..56> 35A5> SND_HP_MUTE 25C5<> VCORE_VSENSE 33C2<>
RAM_DATA_A<57> 10D1<> 11A8<> SND_HP_MUTE_L 14C5<> 25C5<> 39A6> VGA_B 22C6<> 22C7< 39B6>
RAM_DATA_A<58> 10C1<> 11A8<> SND_HP_MUTE_LO 25C6<> 25C7<> VGA_G 22C5<> 22C7< 39B6>
RAM_DATA_A<59> 10C1<> 11A8<> SND_HP_SENSE_L 14B5<> 25C8<> 39A6> VGA_HSYNC 22C6<> 22D7< 39B6>
RAM_DATA_A<60> 10C1<> 11A6<> SND_HW_RESET_L 14A7< 14B5<> 25D7<> 39A6> VGA_R 22B7< 22C5<> 39B6>
RAM_DATA_A<61> 10C1<> 11A6<> SND_LIN_SENSE_L 14B5<> 25C8<> 39A6> VGA_VSYNC 22C5<> 22D7< 39B6>
RAM_DATA_A<62> 10C1<> 11A6<> SOFT_PWR_ON_L 22D1<> 23A3< 29A8< 29C6<> 29D7< ZT10_SPN 4C2<>
RAM_DATA_A<63> 10C1<> 11A6<> 33A4<> 39B3> ZT301_SPN 4C2<>
RAM_DATA_B<0> 10C8<> 11D5<> ST7_SLEEP_LED_H 23C5<> 23C6<> 23D6<> 39D1> ZT302_SPN 4C2<>
RAM_DATA_B<7..0> 35D5> STOP_AGP_L 12D2< 12D4<> ZV_LCDDATA20_PU 20C7<>
RAM_DATA_B<1> 10C8<> 11D5<> SYSCLK_CPU 5C3< 8A6< 35D1>
RAM_DATA_B<2> 10C8<> 11D5<> SYSCLK_CPU_UF 8A5<> 35D1>
RAM_DATA_B<3> 10C8<> 11D5<> SYSCLK_DDRCLK_A0 9D4< 11D8<> 35D1>
RAM_DATA_B<4> 10C8<> 11D3<> SYSCLK_DDRCLK_A0_L 9D4< 11D8<> 35C1>
RAM_DATA_B<5> 10C8<> 11D3<> SYSCLK_DDRCLK_A0_L_UF 9B6<> 9D5< 35D1>
RAM_DATA_B<6> 10C8<> 11D3<> SYSCLK_DDRCLK_A0_UF 9B6<> 9D5< 35D1>
RAM_DATA_B<7> 10C8<> 11D3<> SYSCLK_DDRCLK_A1 9D4< 11A6<> 35C1>
A RAM_DATA_B<8> 10C8<> 11D5<>

RAM_DATA_B<15..8> 35C5>
RAM_DATA_B<9> 10C8<> 11D5<>
SYSCLK_DDRCLK_A1_L 9D4< 11A6<> 35C1>
SYSCLK_DDRCLK_A1_L_UF 9B6<> 9D5< 35D1>
SYSCLK_DDRCLK_A1_UF 9B6<> 9D5< 35D1>
A
RAM_DATA_B<10> 10C8<> 11D5<> SYSCLK_DDRCLK_B0 9D4< 11D5<> 35C1>
RAM_DATA_B<11> 10C8<> 11D5<> SYSCLK_DDRCLK_B0_L 9C4< 11D5<> 35C1>
RAM_DATA_B<12> 10C8<> 11D3<> SYSCLK_DDRCLK_B0_L_UF 9B6<> 9C5< 35D1> THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
RAM_DATA_B<13> 10C8<> 11D3<> SYSCLK_DDRCLK_B0_UF 9B6<> 9D5< 35D1> PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
RAM_DATA_B<14> 10C8<> 11D3<> SYSCLK_DDRCLK_B1 9D4< 11A3<> 35C1>
RAM_DATA_B<15> 10C8<> 11D3<> SYSCLK_DDRCLK_B1_L 9D4< 11A3<> 35C1> I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
RAM_DATA_B<16> 10C6<> 11D5<> SYSCLK_DDRCLK_B1_L_UF 9B6<> 9D5< 35D1>
RAM_DATA_B<23..16> 35C5> SYSCLK_DDRCLK_B1_UF 9B6<> 9D5< 35D1> II NOT TO REPRODUCE OR COPY IT
RAM_DATA_B<17> 10C6<> 11C5<> SYSCLK_LA_TP 8A5<>
RAM_DATA_B<18> 10C6<> 11C5<> SYSTEM_CLK_EN 14A5< 14B6< 29C4<> III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
RAM_DATA_B<19> 10C6<> 11C5<> THERM1_A_DM 25A7< 25A8< 37A2>
RAM_DATA_B<20> 10C6<> 11D3<> THERM1_A_DP 25A7< 25A8< 37A2> SIZE DRAWING NUMBER REV.
RAM_DATA_B<21> 10C6<> 11C3<> THERM1_DM 25A5< 25A6< 25B5<> 25B6< 37A2>
RAM_DATA_B<22>
RAM_DATA_B<23>
10C6<> 11C3<>
10C6<> 11C3<>
THERM1_DP
THERM1_M_DM
25A5< 25A6< 25B5<> 25B6< 37A2>
25B7< 25B8< 37A2>
APPLE COMPUTER INC.
D 051-6653 C
RAM_DATA_B<24> 10C6<> 11C5<> THERM1_M_DP 25B7< 25B8< 37A2>
SCALE SHT OF
NONE 42
42 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
*** Part Cross-Reference for the entire design *** C167 CAP 16 C335 CAP 16 C503 CAP 22 C673 CAP 27 C850 CAP 25 L62 IND 32 R72 RES 33 R240 RES 14
C168 CAP 16 C336 CAP 31 C504 CAP 21 C674 CAP 26 C851 CAP 26 L63 IND 34 R73 RES 30 R241 RES 14
C1 CAP 5 C169 CAP 11 C337 CAP 14 C505 CAP 20 C675 CAP 26 C852 CAP 26 L64 IND_3P 20 R74 RES 30 R242 RES 24
C2 CAP 5 C170 CAP 16 C338 CAP 34 C506 CAP 21 C676 CAP 27 C853 CAP 30 L65 IND 34 R75 RES 30 R243 RES 14
C11 CAP 30 C179 CAP 16 C347 CAP 16 C515 CAP 20 C685 CAP_P 32 C862 CAP 19 L74 IND 22 R84 RES 7 R252 RES 12
C13 CAP 33 C181 CAP 16 C349 CAP 16 C517 CAP 21 C687 CAP 32 C864 CAP 19 L76 FILTER_4P 28 R86 RES 33 R254 RES 12
C14 CAP 33 C182 CAP 16 C350 CAP 16 C518 CAP 21 C688 CAP 32 C865 CAP 19 L77 FILTER_4P 28 R87 RES 30 R255 RES 12
D
C17
C18
C19
CAP
CAP
CAP
5
5
22
C185
C186
C187
CAP
CAP
CAP
16
16
8
C353
C354
C355
CAP
CAP
CAP
32
16
34
C521
C522
C523
CAP
CAP
CAP
21
20
21
C691
C692
C693
CAP
CAP
CAP
34
25
34
C868
C869
C871
CAP
CAP
CAP
25
25
19
L80
L81
Q1
IND
IND
19
21
TRA_2N7002DW 30
R90
R91
R92
RES
RES
RES
33
33
7
R258
R259
R260
RES
RES
RES
14
13
9
D
C20 CAP 5 C188 CAP 23 C356 CAP 11 C524 CAP 20 C694 CAP 32 C872 CAP 19 Q2 TRA_2N7002DW 30 R93 RES 33 R261 RES 29
C23 CAP 30 C191 CAP 16 C359 CAP 16 C527 CAP 21 C697 CAP 34 C875 CAP 19 Q5 TRA_2N3904 33 R96 RES 30 R264 RES 12
C24 CAP 30 C192 CAP 16 C360 CAP 16 C528 CAP 20 C698 CAP 25 C876 CAP 19 Q6 TRA_SI4435DY 30 R97 RES 33 R265 RES 9
C25 CAP 5 C193 CAP 34 C361 CAP 16 C529 CAP 20 C699 CAP 32 C877 CAP 19 Q7 TRA_SUD45P03 30 R98 RES 33 R266 RES 24
C29 CAP 5 C197 CAP 17 C365 CAP 16 C533 CAP 20 C703 CAP_P 32 C881 CAP 21 Q11 TRA_2N7002DW 34 R102 RES 30 R270 RES 13
C30 CAP 5 C198 CAP 23 C366 CAP 16 C534 CAP 21 C704 CAP 20 D1 DIODE_SCHOT 31 Q12 TRA_2N3904 7 R103 RES 6 R271 RES 9
C31 CAP 5 C199 CAP 23 C367 CAP 16 C535 CAP 21 C705 CAP_P 20 D2 DIODE_SCHOT 31 Q13 TRA_2N7002 7 R104 RES 6 R272 RES 12
C32 CAP 5 C200 CAP 16 C368 CAP 16 C536 CAP 20 C706 CAP 20 D3 DIODE 31 Q14 TRA_2N7002DW 7 R105 RES 6 R273 RES 12
C33 CAP 5 C201 CAP 16 C369 CAP 16 C537 CAP 21 C707 CAP_P 20 D4 DIODE 30 Q15 TRA_FDG6324L 31 R106 RES 33 R274 RES 15
C34 CAP 5 C202 CAP 16 C370 CAP 29 C538 CAP 21 C708 CAP 20 D5 DIODE_SCHOT 33 Q16 TRA_IRF7811W 31 R107 RES 31 R275 RES 21
C35 CAP 30 C203 CAP 16 C371 CAP 16 C539 CAP 21 C709 CAP_P 32 D6 DIODE 30 Q17 TRA_IRF7805 31 R108 RES 31 R276 RES 15
C36 CAP 30 C204 CAP 16 C372 CAP 12 C540 CAP 21 C710 CAP_P 32 D7 DIODE_SCHOT 31 Q18 TRA_2N7002DW 23 R109 RES 31 R277 RES 12
C37 CAP 18 C205 CAP 16 C373 CAP 16 C541 CAP 21 C711 CAP_P 20 D8 DIODE 31 Q19 TRA_2N3906 23 R110 RES 7 R278 RES 12
C38 CAP 5 C206 CAP 16 C374 CAP 16 C542 CAP 21 C712 CAP 20 D9 ZENER_MMBZ15VDLT1 23 Q20 TRA_2N7002DW 32 R111 RES 33 R279 RES 14
C39 CAP 5 C207 CAP 16 C375 CAP 16 C543 CAP 21 C713 CAP_P 32 D10 DIODE_SCHOT 31 Q21 TRA_SI3443DV 32 R112 RES 9 R280 RES 14
C41 CAP 30 C209 CAP 34 C377 CAP 16 C545 CAP 21 C715 CAP 34 D12 DIODE 20 Q23 TRA_SI3446DV 20 R114 RES 34 R282 RES 12
C42 CAP 30 C210 CAP 23 C378 CAP 16 C546 CAP 21 C716 CAP 34 D13 DIODE_SCHOT 32 Q24 TRA_2N7002DW 32 R115 RES 34 R283 RES 5
C44 CAP 5 C212 CAP 16 C380 CAP 16 C548 CAP 22 C718 CAP 34 D15 DIODE 26 Q26 TRA_SI3443DV 32 R117 RES 34 R285 RES 19
C45 CAP 5 C213 CAP 16 C381 CAP 16 C549 CAP 22 C719 CAP 34 D16 DIODE_SCHOT 27 Q27 TRA_SI3443DV 32 R118 RES 31 R286 RES 14
C47 CAP 5 C215 CAP 16 C383 CAP 11 C551 CAP 21 C721 CAP 14 D18 DIODE_DUAL_6P 28 Q29 TRA_SI3443DV 22 R120 RES 31 R288 RES 14
C49 CAP 5 C217 CAP 16 C385 CAP 16 C553 CAP 21 C723 CAP 14 D20 DIODE_DUAL_6P 28 Q31 TRA_2N7002 34 R122 RES 31 R290 RES 19
C50 CAP 5 C218 CAP 16 C386 CAP 14 C554 CAP 32 C724 CAP 29 D21 ZENER 28 Q32 TRA_2N7002DW 26 R123 RES 33 R291 RES 32
C51 CAP_P 33 C219 CAP 16 C387 CAP 14 C555 CAP 32 C725 CAP 34 D22 DIODE_DUAL_6P 28 Q33 TRA_2N7002DW 28 R124 RES 17 R292 RES 14
C52 CAP_P 33 C220 CAP 23 C388 CAP 14 C556 CAP 32 C726 CAP 10 D23 DIODE_DUAL_6P 28 Q34 TRA_NDS9407 28 R125 RES 33 R293 RES 14
C53 CAP 5 C221 CAP 16 C389 CAP 14 C557 CAP 32 C727 CAP 10 D24 DIODE_SCHOT 28 Q35 TRA_DUAL_MMDT3904 22 R126 RES 33 R294 RES 32
C54 CAP 5 C222 CAP 16 C390 CAP 19 C558 CAP 32 C728 CAP 29 D25 DIODE_SCHOT_3P2 27 Q38 TRA_TP0610 22 R127 RES 31 R295 RES 14
C56 CAP 5 C224 CAP 16 C392 CAP 14 C560 CAP 32 C730 CAP 10 D27 DIODE 32 Q40 TRA_2N7002DW 22 R129 RES 33 R297 RES 19
C57 CAP 33 C225 CAP 16 C393 CAP_P 34 C561 CAP 32 C731 CAP 29 D28 DIODE_SCHOT 32 Q41 TRA_IRF7805 32 R130 RES 31 R298 RES 19
C58 CAP 5 C226 CAP 16 C394 CAP 14 C562 CAP 32 C732 CAP 10 D29 DIODE_SCHOT 20 Q42 TRA_IRF7811W 32 R131 RES 7 R299 RES 11
C60 CAP 18 C228 CAP 16 C396 CAP_P 34 C564 CAP 32 C734 CAP 10 D31 DIODE_SCHOT 34 Q44 TRA_2N7002DW 32 R133 RES 7 R301 RES 32
C C61
C62
C63
CAP
CAP
CAP
5
5
33
C229
C230
C231
CAP
CAP
CAP
16
16
16
C397
C398
C399
CAP
CAP
CAP
11
32
14
C565
C566
C567
CAP
CAP
CAP
32
32
32
C735
C736
C737
CAP
CAP
CAP
16
16
31
D32
D33
D36
DIODE_SCHOT 31
DIODE 33
DIODE_SCHOT 30
Q45
Q46
Q47
TRA_IRF7805 32
TRA_2N3904 25
TRA_IRF7811W 32
R134
R135
R136
RES
RES
RES
14
33
8
R302
R303
R304
RES
RES
RES
5
11
19
C
C64 CAP 33 C232 CAP 34 C400 CAP 14 C568 CAP 32 C738 CAP 34 DP1 DPAK3P 30 Q48 TRA_SI7860DP 20 R137 RES 33 R305 RES 19
C65 CAP 33 C233 CAP 23 C401 CAP 19 C569 CAP 32 C739 CAP 16 DP2 DPAK3P 33 Q49 TRA_IRF7832 20 R138 RES 23 R306 RES 32
C66 CAP 33 C234 CAP 16 C402 CAP 14 C570 CAP 32 C740 CAP 31 DP3 DPAK3P 34 Q50 TRA_2N7002DW 32 R139 RES 33 R307 RES 32
C67 CAP 30 C235 CAP 14 C403 CAP 11 C571 CAP 32 C741 CAP 10 DP4 DPAK3P 34 Q51 TRA_2N3904 20 R140 RES 8 R308 RES 12
C68 CAP 5 C236 CAP 16 C404 CAP 11 C572 CAP 32 C742 CAP 10 DP5 DPAK3P 20 Q52 TRA_2N3904 20 R141 RES 8 R309 RES 19
C69 CAP 5 C237 CAP 16 C405 CAP_P 34 C573 CAP 32 C743 CAP 17 DP6 DPAK3P 28 Q53 TRA_SI3446DV 34 R142 RES 14 R310 RES 32
C70 CAP 33 C238 CAP 16 C406 CAP 29 C574 CAP 32 C744 CAP 17 DP7 DPAK3P 20 Q54 TRA_IRF7811W 34 R143 RES 14 R311 RES 32
C71 CAP 30 C239 CAP 16 C407 CAP 20 C575 CAP 32 C745 CAP 10 F1 FUSE 28 Q55 TRA_IRF7805 34 R144 RES 14 R312 RES 21
C72 CAP 5 C240 CAP 16 C408 CAP 19 C576 CAP 32 C746 CAP 17 F2 FUSE 22 Q56 TRA_IRF7805 34 R145 RES 13 R313 RES 19
C73 CAP 5 C241 CAP 16 C409 CAP 19 C577 CAP 32 C747 CAP 17 F3 FUSE 28 Q57 TRA_IRF7811W 34 R146 RES 8 R314 RES 12
C74 CAP 33 C242 CAP 16 C410 CAP 32 C578 CAP 32 C748 CAP 17 F4 FUSE 30 Q58 TRA_2N3906 23 R147 RES 8 R315 RES 19
C75 CAP 5 C243 CAP 16 C411 CAP 20 C579 CAP 32 C749 CAP 17 F5 FUSE 30 Q59 TRA_2N3904 25 R148 RES 14 R316 RES 12
C76 CAP 33 C244 CAP 31 C412 CAP 19 C580 CAP 32 C750 CAP 17 G1 OSC 19 Q60 TRA_IRF7832 33 R149 RES 13 R317 RES 12
C77 CAP_P 33 C245 CAP 16 C413 CAP 21 C581 CAP 32 C751 CAP 17 G2 OSC 27 Q61 TRA_2N3904 25 R150 RES 8 R318 RES 12
C78 CAP_P 33 C246 CAP 14 C414 CAP 21 C582 CAP 32 C752 CAP 17 J1 CON_M4RT_S2MT_SM 25 Q62 TRA_SI7860DP 33 R151 RES 8 R319 RES 21
C79 CAP 33 C247 CAP 16 C415 CAP 32 C583 CAP 27 C753 CAP 31 J2 CON_4RT_WRIB 23 Q63 TRA_IRF7832 33 R152 RES 8 R320 RES 19
C80 CAP 33 C248 CAP 16 C416 CAP 32 C584 CAP 27 C754 CAP 31 J3 CON_M40ST_D4MT_SM 25 Q64 TRA_IRF7811W 30 R153 RES 14 R321 RES 32
C81 CAP 5 C249 CAP 9 C417 CAP 21 C585 CAP 27 C755 CAP 31 J4 CON_4RT_WRIB 22 Q65 TRA_SI7860DP 33 R154 RES 23 R322 RES 32
C82 CAP 5 C250 CAP 16 C418 CAP 21 C586 CAP 27 C756 CAP 17 J5 CON_M80ST_D4MT_SM 18 Q66 TRA_IRF7832 33 R155 RES 8 R323 RES 19
C83 CAP 33 C251 CAP 16 C419 CAP 21 C587 CAP 27 C757 CAP 10 J6 CON_F80ST_D4MT_SM 24 Q67 TRA_2N3904 25 R156 RES 14 R324 RES 19
C84 CAP 33 C252 CAP 16 C420 CAP 21 C588 CAP 27 C758 CAP 10 J7 CON_12 33 Q68 TRA_SI4435DY 30 R157 RES 14 R325 RES 19
C85 CAP 5 C253 CAP 16 C421 CAP 21 C589 CAP 27 C759 CAP 17 J8 CON_2RTSM_125 23 Q69 TRA_SI4435DY 30 R158 RES 14 R326 RES 20
C86 CAP 5 C254 CAP 16 C422 CAP 21 C590 CAP 27 C760 CAP 17 J9 CON_F1ST_S2MT_SM 14 Q70 TRA_IRF7805 30 R159 RES 8 R327 RES 20
C87 CAP 5 C255 CAP 29 C423 CAP 21 C591 CAP 27 C761 CAP 17 J10 CON_10STSM_5087 23 Q71 TRA_2N7002DW 30 R160 RES 13 R328 RES 20
C88 CAP 5 C256 CAP 14 C424 CAP 21 C592 CAP 26 C762 CAP 6 J11 CON_F30RT_S2MT_SM1 23 Q72 TRA_2N7002DW 30 R161 RES 8 R329 RES 20
C89 CAP 5 C257 CAP 16 C425 CAP 21 C593 CAP 27 C763 CAP 25 J12 CON_M50SM_5MM 24 Q74 TRA_2N7002DW 30 R162 RES 9 R330 RES 20
C90 CAP 33 C258 CAP 16 C426 CAP 21 C594 CAP 26 C764 CAP 10 J13 CON_M50SM_5MM 24 Q76 TRA_FDG6324L 22 R163 RES 23 R331 RES 20
C91 CAP_P 33 C259 CAP 16 C427 CAP 21 C595 CAP 26 C765 CAP 17 J14 CON_F30RT_S2MT_SM 22 Q77 TRA_2N7002DW 25 R164 RES 14 R332 RES 20
C92 CAP_P 33 C260 CAP 16 C428 CAP 32 C596 CAP 27 C766 CAP 23 J15 CON_M16ST_D_SMA 25 Q78 TRA_2N7002DW 25 R165 RES 14 R333 RES 20
C93 CAP 33 C261 CAP 16 C429 CAP 32 C597 CAP 26 C767 CAP 31 J16 CON_3RTSM_125 31 Q79 TRA_2N7002DW 25 R166 RES 14 R334 RES 12
C94 CAP 33 C262 CAP 16 C430 CAP 21 C598 CAP 26 C768 CAP 17 J17 CON_M16ST_D_SMA 25 Q82 TRA_2N7002DW 33 R167 RES 12 R335 RES 19
C95 CAP 30 C263 CAP 16 C431 CAP 20 C599 CAP 26 C769 CAP 17 J18 CON_M4RT_S2MT_SM 25 Q83 TRA_2N7002DW 25 R168 RES 8 R336 RES 19
C96 CAP 30 C264 CAP 16 C432 CAP 32 C600 CAP 26 C770 CAP 16 J19 CON_F20ST_D_SM 23 R1 RES 9 R169 RES 8 R337 RES 19
C97 CAP 30 C265 CAP 16 C433 CAP 32 C601 CAP 26 C771 CAP 31 J20 CON_F9RT_1394B_S6MT_SMA 28 R2 RES 5 R170 RES 34 R338 RES 19
C98 CAP 30 C266 CAP 16 C434 CAP 20 C602 CAP 26 C772 CAP 31 J21 CON_F5RT_MINIDIN_TH 22 R3 RES 5 R171 RES 34 R339 RES 20
C99 CAP 30 C267 CAP_P 34 C435 CAP 20 C603 CAP 26 C773 CAP 9 J22 CON_F30RT_T6MT_TH1 22 R4 RES 5 R172 RES 17 R340 RES 20
C100 CAP 33 C268 CAP 16 C436 CAP 21 C604 CAP 26 C774 CAP_P 33 J23 CON_RJ45_10RT_S4MT_TH1 26 R5 RES 7 R173 RES 23 R341 RES 20
C101 CAP 33 C269 CAP 16 C437 CAP 21 C605 CAP 27 C775 CAP 18 J24 CON_F6RT_S4MT_TH1 28 R6 RES 5 R174 RES 14 R342 RES 20
C102 CAP 5 C270 CAP 12 C438 CAP 21 C606 CAP 27 C776 CAP 18 J25 CON_F400RT_DDRDIMM_SM3 11 R7 RES 5 R175 RES 14 R343 RES 20
C103 CAP 5 C271 CAP 16 C439 CAP 21 C607 CAP 27 C777 CAP 30 J26 CON_M8RT_S_SM 30 R8 RES 5 R176 RES 9 R344 RES 20
C104 CAP 5 C272 CAP 16 C440 CAP 20 C608 CAP 26 C778 CAP 18 J27 CON_M4RT_S_SM 30 R9 RES 5 R177 RES 34 R345 RES 29
B C105
C106
C107
CAP
CAP
CAP
33
33
5
C273
C274
C275
CAP
CAP
CAP
16
16
16
C441
C442
C443
CAP
CAP
CAP
20
19
20
C609
C610
C611
CAP
CAP
CAP
27
27
26
C779
C780
C781
CAP_P
CAP
CAP_P
30
30
33
J28
L1
L2
CON_10STSM_5087 25
IND
IND
22
30
R10
R11
R12
RES
RES
RES
5
5
7
R178
R179
R180
RES
RES
RES
14
14
14
R346
R347
R348
RES
RES
RES
20
22
29
B
C108 CAP 5 C276 CAP 31 C444 CAP 21 C612 CAP 26 C782 CAP 18 L3 IND 30 R13 RES 5 R181 RES 14 R349 RES 29
C111 CAP_P 33 C279 CAP 16 C447 CAP 21 C615 CAP 26 C785 CAP 30 L6 IND 30 R16 RES 30 R184 RES 34 R352 RES 20
C114 CAP 32 C282 CAP 16 C450 CAP 21 C618 CAP 26 C788 CAP_P 33 L9 IND 23 R19 RES 5 R187 RES 14 R355 RES 20
C139 CAP 16 C307 CAP_P 34 C475 CAP 21 C645 CAP 26 C813 CAP 22 L34 IND 27 R44 RES 7 R212 RES 34 R380 RES 20
C142 CAP 16 C310 CAP 16 C478 CAP 21 C648 CAP 26 C816 CAP 22 L37 FILTER_4P 22 R47 RES 30 R215 RES 24 R383 RES 20
A C148
C149
C150
CAP
CAP
CAP
16
16
11
C316
C317
C318
CAP
CAP
CAP
16
16
16
C484
C485
C486
CAP
CAP
CAP
20
20
20
C654
C655
C656
CAP
CAP
CAP
22
22
22
C829
C830
C831
CAP
CAP
CAP
25
21
21
L43
L44
L45
IND
IND
FILTER_4P
22
22
22
R53
R54
R55
RES
RES
RES
30
30
30
R221
R222
R223
RES
RES
RES
34
34
23
R389
R390
R391
RES
RES
RES
20
20
20
A
C164 CAP 16 C332 CAP 16 C500 CAP 21 C670 CAP_P 27 C847 CAP 13 L59 IND 27 R69 RES 33 R237 RES 24 R405 RES 32
43
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R408 RES 32 R576 RES 29 R744 RES 30 U36 TSB81BA3A 27
R409 RES 32 R577 RES 23 R745 RES 30 U37 VREG_LM2594 27
R410 RES 32 R578 RES 24 R746 RES 14 U38 VREG_LT1962 27
R411 RES 32 R579 RES 24 R747 RES 24 U39 741G32 22
R412 RES 27 R580 RES 29 R748 RES 5 U40 741G32 22
R413 RES 27 R581 RES 29 R749 RES 25 U42 COMPARATOR_LMC7211 22
R414 RES 27 R582 RES 29 R750 RES 22 U43 TRANSCEIVER_88E1111 26
R415 RES 27 R583 RES 29 R751 RES 25 U44 LTC1761 27
R418 RES 27 R586 RES 29 R754 RES 23 U47 RAGE_MBLTY_M11_CSP64_667 19 20 21
R419 RES 27 R587 RES 29 R755 RES 5 U48 TRA_SI6467BDQ 34
R420 RES 27 R588 RES 29 R756 RES 18 U49 VREG_LT1962 14
R421 RES 26 R589 RES 29 R757 RES 33 U50 TRA_SI3447DV 34
R422 RES 26 R590 RES 29 R758 RES 23 U51 INTREPID 8 9 12 13 14 15
R423 RES 26 R591 RES 29 R759 RES 24 U52 EEPROM_32KX8_M24256B 6
R424 RES 26 R592 RES 29 R760 RES 20 U53 ADT7460 25
R425 RES 26 R593 RES 29 R761 RES 20 U54 AT90S1200 6
D
R426
R427
R428
RES
RES
RES
27
26
26
R594
R595
R596
RES
RES
RES
29
29
29
R762
R763
R764
RES
RES
RES
20
20
20
U55
U56
U57
OPAMP_LMC7111 30
APOLLO_MPC7447A_360 5 6
COMPARATOR_LMC7211 30
D
R429 RES 26 R597 RES 29 R765 RES 20 U58 SIL1162 19
R430 RES 26 R598 RES 29 R766 RES 20 U60 VREG_MM1571J 21
R431 RES 26 R599 RES 29 R767 RES 20 XW1 SHORT 30
R456 RES 22 R624 RES 8 R806 RES 25 Y1 CRYSTAL 17
R458 RES 22 R626 RES 8 R808 RES 25 Y3 CRYSTAL_4PIN 29
R460 RES 22 R628 RES 8 R818 RES 19 Y5 CRYSTAL_4PIN 26
R461 RES 28 R629 RES 8 R819 RES 19 ZT1 HOLE_VIA 4
C R470
R471
R472
RES
RES
RES
22
28
22
R638
R639
R640
RES
RES
RES
8
8
8
R832
R833
R835
RES
RES
RES
19
19
19
ZT10
ZT11
ZT12
HOLE_VIA
HOLE_VIA
HOLE_VIA
4
4
4
C
R481 RES 22 R649 RES 8 RP1 RPAK10P2C 18 ZT21 HOLE_VIA 4
R482 RES 22 R650 RES 8 RP2 RPAK4P 8 ZT22 HOLE_VIA 4
B R514
R515
R516
RES
RES
RES
27
27
27
R682
R683
R684
RES
RES
RES
8
8
8
RP34
RP35
RP36
RPAK4P
RPAK4P
RPAK4P
12
13
12
ZT54
ZT55
ZT56
HOLE_VIA
HOLE_VIA
HOLE_VIA
4
4
4
B
R540 RES 24 R708 RES 33 SH1 SHLD_3P_EMI 4 ZT80 HOLE_VIA 4
R541 RES 24 R709 RES 6 U1 COMPARATOR_LMC7211 30 ZT81 HOLE_VIA 4
R542 RES 24 R710 RES 30 U2 NC7S32 22 ZT82 HOLE_VIA 4
R543 RES 22 R711 RES 30 U3 AMP_MAX4172 30 ZT83 HOLE_VIA 4
R544 RES 22 R712 RES 6 U4 PWR_CNTRL_TPS2211 18 ZT84 HOLE_VIA 4
R545 RES 24 R713 RES 30 U5 FAN2558 5 ZT85 HOLE_VIA 4
R546 RES 24 R714 RES 18 U6 MAX1772 30 ZT86 HOLE_VIA 4
R547 RES 25 R715 RES 30 U7 MAX1717 33
R548 RES 32 R716 RES 30 U8 PCI1510GGU 18
R549 RES 20 R717 RES 30 U9 SN74AUC1G08 6
R551 RES 32 R719 RES 18 U11 FEPR_1MX8 9
R553 RES 12 R721 RES 18 U13 LTC1625 31
R554 RES 34 R722 RES 18 U14 COMPARATOR_LMC7211 31
R555 RES 20 R723 RES 18 U15 PI3B3257 33
R556 RES 20 R724 RES 18 U16 CBTV4020 10
A R557
R558
R559
RES
RES
RES
34
20
20
R725
R726
R727
RES
RES
RES
30
18
30
U17
U18
U19
UPD720101_FBGA 17
CBTV4020 10
MAX1715 34
A
R560 RES 29 R728 RES 30 U20 NC7S32 29
R561 RES 29 R729 RES 30 U21 741125 23
R562 RES 29 R730 RES 30 U22 VREG_LP2951 31
R563 RES 29 R731 RES 30 U23 VREG_LP2951 31
R564 RES 29 R732 RES 30 U24 NC7S32 29
R565 RES 14 R733 RES 30 U25 NC7S32 29
R566 RES 34 R734 RES 30 U26 MAX6804 29
R567 RES 14 R735 RES 30 U27 CBTV4020 10
R568 RES 14 R736 RES 30 U28 CBTV4020 10
R569 RES 23 R737 RES 24 U29 M16C62 29
R570 RES 24 R738 RES 30 U30 CLK_GEN_CY25811 19
R571 RES 34 R739 RES 24 U31 CLK_GEN_CY28512 14
R572 RES 32 R740 RES 30 U32 LTC1778 20
R573 RES 24 R741 RES 30 U33 COMPARATOR_LMC7211 29
R574 RES 14 R742 RES 30 U34 VREG_MM1571J 21
R575 RES 29 R743 RES 33 U35 LTC3707 32
44
8 7 6 5 4 3 2 1

Schem, MLB, Pb15: Bom Options (In Common Parts)

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8 7 6 5 4 3 2 1

C 329994 PRODUCTION RELEASED 05/27/04?

D PAGE CONTENTS PAGE CONTENTS D

4 PCB NOTES AND HOLES 25 FAN CONTROLLER, USB MODEM/SOFT MODEM,

5 MPC7447A MAXBUS INTERFACE 26 GIGABIT ETHERNET INTERFACE

9 INTREPID MEMORY INTERFACE / BOOT ROM 30 BATTERY CHARGER AND CONNECTOR

11 400PIN STACKED DDR SODIMM CONNECTOR 32 3.3V / 5V SYSTEM POWER SUPPLY

15 INTREPID POWER RAILS/1.5V LDO 36 SIGNAL CONSTRAINTS (2 OF 4) - CPU

B 16 INTREPID DECOUPLING 37 SIGNAL CONSTRAINTS (3 OF 4) - DIGITAL/DIFF B

17 USB 2.0 INTERFACE (uPD720101) 38 SIGNAL CONSTRAINTS (4 OF 4) - POWER NETS

18 CARDBUS INTERFACE (PCI1510) 39 FUNCTIONAL TESTPOINTS

19 M11 AGP INTERFACE & SPREAD SPECTRUM SUPPORT

20 M11 LVDS/TMDS/GPIO & GPU VCORE 41 SIGNAL LOCATIONS

21 M11 POWER 42 COMPONENT LOCATIONS (1 OF 2)

METRIC Apple Computer Inc.

SO-DIMM Connector I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

P.11 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

POWER SYSTEM ARCHITECTURE

NO INRUSH PROTECTION +1_5V_SLEEP

PG 30 (D3COLD) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

1/2 OZ CU THICKNESS: 0.7 MILS ZT58

1.0 OZ CU THICKNESS: 1.4 MILS MECH. HOLES

IMPEDANCE : 50 OHMS +/- 10% ZT36

SIGNAL TRACE WIDTH: 4 MILS NO_TEST=TRUE

C PREPREG THICKNESS: 2-3 MILS C

SEE PCB CAD FILES FOR MORE SPECIFIC INFO.

ZT72 ZT52 ZT54 ZT20 ZT24

ZT69 ZT53 ZT55 ZT43 ZT67

6 CORE (5 MIL) ZT38 ZT22 ZT15 ZT75

ZT39 ZT17 ZT44 ZT73

ZT40 ZT35 ZT4 ZT63

ZT78 ZT83 ZT3 ZT65

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

20% 20% 20% 20% 20% 5% +1_8V_SLEEP

PLL_CFG3 D7 CPU_PLL_CFG<3> 7 0 CPU_BST R33 1/16W

CPU_ADDR<5> G2 A9 DTI3 N1 CPU_DTI<2>

36 8 CPU_ADDR<7> L3 A11 2.2uF R2 1%

CPU_ADDR<12> J4 A16 TRST* A5 JTAG_CPU_TRST_L

36 8 CPU_ADDR<18> N4 A22 BGA TEA* L1 CPU_TEA_L 8 36 VCORE_SHDN_L_3V 1/16W

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

36 8 CPU_ADDR<28> B12 A32 114S1005 1 RES,MF,1/16W,100k ohm,1%,0402,SMD R449 (R1) CPU_BTR

CPU_TT<0> E5 PMON_IN* D9 CPU_PMONIN_L 5 5%

GND III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

CPU_DATA<24> R10 D24 NC L17 N/C_33 6 ICT_TRST_L 3

36 8 CPU_DATA<25> N9 D25 NC J18

36 8 CPU_DATA<29> W10 D29 NC K19 N/C_38 1% SSOP 6 BB_EEPR_ADDR 9

36 8 CPU_DATA<35> D35 B19 10K RESET_VREF 13 PB1 PD1 3 BFR_TDO 6

36 8 CPU_DATA<38> P7 D38 E16 39 23 13 11 6 INT_I2C_DATA0 16 PB4 PD4 8 JTAG_CPU_TMS 5 39

36 8 CPU_DATA<39> V6 D39 F12 6 BB_MOSI 17 PB5 PD5 9 JTAG_CPU_TDI 5 39

36 8 CPU_DATA<40> P17 D40 F17 6 BB_MISO 18 PB6 PD6 11 JTAG_CPU_TRST_L 5 39

36 8 CPU_DATA<41> R19 D41 F19 6 BB_SCK 19 PB7

36 8 CPU_DATA<49> W17 D49 M18 009-6240 FW GT4 BBANGER TABLE_5_ITEM

341S1135 1 MCU,PROGRAMMED W/ BBANGER U54 BBANG

CPU_DATA<58> U7 D58 A19

NC DP0 F16 3 6 B BBANG

N19 TEMP_CATHODE II NOT TO REPRODUCE OR COPY IT