COMPUTER ORGANIZATION

INTERRUPTS
.There are many situations where other taskS can be performed while waiting for an 1/0 device to
become ready.
A hardware signal called an Interrupt will alert the processor when an 1/0 device becomes ready.
Interrupt-signal is sent on the interrupt-request line.
The processor can be performing its own task without the need to continuously check the 1/0-device.
.The routine executed in response to an interrupt-request is called ISR.
The processor must inform the device that its request has been recognized by sending INTA signal.
(INTRInterrupt Request, INTA Interrupt Acknowledge, ISR Interrupt Service Routine)
.For example, consider COMPUTE and PRINT routines (Figure 3.6).

Program I1 Program 2

COMPUTE routine DISPLAY routine

Interrupt
Occurs

here

Figure 3.6 Transferofcontrolthrough the use of intenmupts.

.The processor first completes the execution of instruction
of the ISR.
.Then, processor loads the PC with the address of the first instruction i+1.
has to come back to instruction
After the execution of ISR, the processor
Therefore, when an interrupt occurs, the current content of PC is put in temporary storage location.
A return at the end of ISR reloads the PC from
that temporary storage location.
instruction i+1.
This causes the execution to resume at
When processor is handling interrupts, it must inform device that its request has been recognized.
.This may be accomplished by INTA signal. the processor.
.The task of saving and restoring the information can
be done automatically by
The processor sa ves only the contents of PC & Status register.
Saving registers also increases the Interrupt Latency.
Interrupt Latency is a delay between
time an interrupt-request is received and
start of the execution of the ISR.
Generally, the long interrupt latency in unacceptable.

Difference between Subroutine &ISR

ISR
Subroutine ISR may not have anything in common with
A subroutine performs a function required by the
program being executed at time INTR is
received
progran from which it is called. mechanism for coordinating V0
Subroutine is just a linkage of 2 or more function Interrupt is a
related to each other. transfers.

2-33
 1
Computer Organigation CBCS Model Question Paper
Module2
pointer register
A. a. Whot is interrupt hardware ?explain enabling
and disabling iaterrupt?(10 Mark
the instruction are first automatically
Ans.
A n 1/0 device requests an interrupt by activating a bus-line called interrunt.
tive address of the operand.
request(IR).
ointer register A single IR line can be used toserve ,n"
devices
plement an important data structure called All devices are connected to IR line via swiiches to ground.
To request an interrupt, a device closes its associated switch. Thus, if all IR sionalc
,RÍ are inactivei.e. if all switches are open), the voltage on the IR line will be equai to
#NUMI,R2 Initialization Vdd.
RO When a device requests an interrupt by closing its switch, the voltage on the line
R2+RO
to 0, causing the INTR received by the processor to goto I.
drops
The value of INTR is the logical OR of the requests from individual devices
OP
RO,SUM INTR=INTRI+INTR2+.....+1NTRn
A special gates known as open-collector or open-drain are used to drive the INTR line
Statement YqA+B) *(C+D) using three Resistor R is calleda pul-up resistor because it pulls the line voltage up to the high-
ddress iustruction. (04 Marks) voltage state when the switches are open.

AALL Ompul uneamAsty Processor

o e olla b knaA INTR

aNTR-
NTRI NTR2** INTRn
OCuNu To prevent the system from entering into an infinite-loop because of interrupt, there
are 3 possibilities:
1) The first possibility is to have the processor-hardware ignore the interrupt-request
TTR oly. D line until the execution of the first instruction of the ISR has been
completed.
2) The second option is to have the processor automatically disable interrupts before
starting the execution ofthe ISR.
3) la the third option, the processor has a special interrupt-request line for which the
interrupt-handling circuit responds only to the leading edge of the signal. Such a
line is said to be edge-triggered.
Sequence of events involved in handling an interrupt-request from a single device is
as follows:
1) The device raises an interrupt-request.
2) The program currently being executed is interrupted.
3) All interupts are disabled(by changing the control bits in the PS).
4) The device is informed that its request has been recognized, and in response, the
device deactivates the
The action
interrupt-request signal.
5) requested by the interrupt is performed by the ISR.
6) Interrupts are enabled again and execution of the interrupted program is resune
Sunstar Eram Scann wter Eran Seannur 11
 M

b.Write a note on ihandBing multipie devices? (08 Marks)

Ans. Polling
Information needed to determine whether a device is requesting an interrupt is
available in its status-register.
to I in its status-register.
When a device raises an interrupt-request, it sets IRQ bit &
KIRQ and DIRQ are the interrupt-request bits for keyboard dispiay.
ISR po!l all 1/O devices
Simplest way to identify interrupting device is to. have
connected to bus.

The first device encountcred with its IRQ bit set is the device that skould be serviced.
After servicing this device, next requests nmay be serviced.
Main advantage: Simple & easy to implement.
Main disadvantage: More time spent polling IRQ bits of ali devices (that may not be
requesting any service)
DATAIN

DATAOUT

STATUS DIRQ KIRQsoUT SIN

cONTROL DEN KEN

7 6 4 3 21 0

Move #LINE,R0 initialize memory pointer.

WAITK Test Bit
#0,STATUJS Test SIN.
Branch 0 WAITK Wait for character to be entered.
Move DATAIN,RRI Read character.
WAITD Test Bit #1,STATUS Test SOUT.

Sunstar Exam Sander 27

iIt Se(CSt / ISE) Computer OrguAigatiÓ
Branch0 WAITD Wait for display to become ready.
Move RI.DATAOUT Send character to display.
Move RI,(RO)+ Store character and advance pointer.

Compare #SOD,RI Check if Carriage Return.

Branch # 0 WAITK If not, get another character.
Move #SCA,DATAOUT Otherwise, send Line Feed.
Call PROCESS Call a subroutine to process the input line.
Vectored Interrupts
Adevice requesting an interrupt identifies itselfby sending a special-code to processor
Over bus. (This enables processor to ider:tfy individual devices even if they share a
singie interrupt-request lire).
The code represents starting-address of SR for that device.
ISR for a given device must always start at same location.
T h e address stored at the location pointed to by interrupting-device is called the
interrupt-vector.
Proccssor
loads interrupt-vector into PC &
executes appropriate ISR
interrupting-device must wait to put data on bus only when processor is ready to
receive it.
When processoris ready to receive interrupt-vector code, it activates INTA line.
IO device responds by sending its interrupt-vector code & turning off the INTR
signal.
CONTROLLING DEVICE REQUESTS
There are 2 independent mechanis1ns for controlling interrupt requests.
A t device-end, an interrupt-enable bit in a control register determines vhether device
is allowed to generate an interrupt request.
A t processor-end, either an interrupt-enable bit in the PS register or a priority structure
determines whether a given interrupt-request will be accepted.
c. Explain Comparision between memory nmapped I0 and I0 mapped VO.
(04 Marks)
Ans. 1. memory mapped IO uses tlie same address space for both memory and 10 devices. IO
device.
mapped 10 uses two separate address spaces for memory and IO
2. the menory mapped IO uses one address s3ace for both IO and memory, the available
addresses for memory are minimum due to the additional addresses for !O. In 1O mapped

I0, all the addresses can be used by the memory.

3.while inemory mapped I0 uses the same instructions
for both 1O and memory
for read and write operations in 1O
operalions, IO mapped 1O uses separate instructions
10 mapped 1O is more efiicient.
and memory 4.memory mapped IO is less efficient while
 COMPUTER ORGANIZA TION
EXCEPTITONS
An interrupt is an event that causees
execution of one program to be
execution of another program tosuspended
&
begin.
.Exception refers to any event that causes an interruption. For ex:
1. Recovery from Errors 1/0 interrupts.
.These are techniques to
ensure
.For ex: Many computers includethat
all hardware components are
operating propery.
an ECC in
memory which allows detection of errors in store-tata
(ECC Error Checking Code, ESR Exception Service
If an error occurs, control-hardware Routine).
detects the errors &
-

informs processor by raising an

-

.When exception processing is initiated interrupt.

(as a result of errors), processor.
SUspends program being executed &
-

starts an ESR. This routine takes

2. Debugging appropriate action to recover from the error.
Debugger
-
is used to find errors in a
program and
-
uses exceptions to provide 2 important facilities: i) Trace & ii) Breakpoints
i) Trace
.When a processor is
operating in trace-mode, an exception occurs after execution
(using debugging-program as ESR). of every instuction
Debugging-program enables user to examine contents of registers, memory-locations and
.On return from so on.
next
debugging-program,
instruction in program being debugged is
then debugging-program is activated
executed,
.The trace exception is disabled again.
during the execution of the debugging-program.
ii) Breakpoints
Here, the program being debugged is interrupted only at
An instruction called Trap (or Software specific points selected by user
.When program is executed & reaches
interrupt) is usually providedfor this purpose.
breakpoint, the user can examine memory & register
3. Privilege Exception contents.
.To protect OS from being
while processor is in
corrupted by user-programs, Privileged Instructions are executed oniy
supervisor-mode.
.For e.9
When processor runs in user-mode, it will not
execute instruction that change priority of
An attempt processor.
to execute privileged-instruction will produce a Privilege Exception.
As a result, processor switches to
supervisor-mode & begins to execute an appropriatein routine OS.
COMPUTER ORGANIZATION
DIRECT MEMORY ACCESS (DMA)
. The transfer of a block of data directly b/w an external device & main-memory w/o continuous
involvement by processor is called DMA.
DMA controller
i s a control circuit that performs DMA transfers (Figure 8. 13)
i s a part of the 1/O device interface.
performs the functions that would normally be carried out by processor.
While a DMA transfer is taking place, the processor can be used to execute another program.

Processor

Bridge Main
memory
PCI bus

Disk/DMA DMA
controller controller

DhdDt Ethernet
interface
Figure 8.13 Use of DMA controlers in a computer system.
.DMA interface has three registers (Figure 8.12):
1) First register is used for storing starting-address.
2) Second register is used for storing word-count.
3) Third register contains status- & control-flags

Status and control

IRQ Donc
IE R/W
Starting address

Word count

Flgure 8.12 ypical registers in a DMA controlle.

.The R/W bit determines direction
If
of transfer.
R/W=1, controller performs a read-operation (i.e. it transfers
Otherwise, controller performs a write-operation (i.e. it transfersdata from memory to 1/O)
data from I/0 to memory).
I f Done=1, the controller
-has completed transferring a block
-is ready to receive another command. of data and
I f IE=1, controller raises an (IE > Interrupt Enable).
interrupt after it has completed transferring a block
I f IRQ=1, controller
requests an interrupt. of data.
Requests by DMA devices for using the bus are always given
There are 2 ways in which the
DMA operation can be carried out:
higher priority than processor requests.
1) Processor originates most
DMA Controller is said to memory-access cycles.
"steal" memory cycles from
Hence, this technique is usually called processor.
2) DMA Controller is given Cycle Stealing.
exclusive access to main-memory to transfer a block of data without
any interruption. This is known as
Block Mode (or burst mode).

2-33
 TYIOat
3. a. Define bus arbitration? Explain detail
any one approach of the bus arbiteration.
Ans. Bus (08 Marks)
arbiteration is the process by which the next device become the bus
master is
selected and bus mastership is transferred to it. The selection of the
bus aster must
take into account the needs of various devices
by establishing a priority systen for
gaining access to the bus.
There are two approaches to bus arbitration
1. Centralized 2. Distributed

Centralized bus arlbitration

The bus arbiter may be the processor, or a separate unit connected to the bus.
the processor is normally the bus master unless it grart bus master ship to DMA
controller. A DMA controller indicates that it needs to become the bus master by
a activating the Bus request line BR. The is an open drain line for the same resons
that the interrupt request line in figure. The signal on the bus request line is the
logical OR of the bus requests from all the devices connected to it. When bus request
the DMA
is activated, the processor activates the bus grant BG and indicating to
DMA controller
controller that they may use the bus when it becomes free. This if
to other devices.
isrequesting the bus, it blocks the propagation of the grant signal
BG2. The current bus master
Otlherwise it passes the grant doconstream by asserting
another open controler
indicates to all devices that it is using the bus by activating
collector line called bus busy BBSV.
 BPSY

BR

Preccssor

DMA DMA
coniraller controlter
BGI BG2 2

Figwre 4.20 A simpla arrangement for bus arbitrarion using o dai:y

chain

Time

BGI

BG2

BBSY

Bus
muster
Processor DMAComroller 2 Processor

Distributed Arbitration:
Distributed Arbitration means that all devices waiting to use the bus have cqual
responsibility in carrying out the arbitration process, without using a central arbiter.
A simple method for distributed arbitration is shown below. Each device on the bus
in assigned a 4-bit identification number. When one or more devices request the
bus, they assert the start-arbitration signal and place their 4-bit ID numbers on four
open-collector lines, ARBO through ARB3. A winner is selected as a result of thke
interactioi among the siginals transmitted over these lines by all contenders. The net
outcome is that the code on the four lines represents the request that has the highest
D number.

ARB3
ARB2
ARB1
ARBO
Sart-Arbitratiena

O.C.

Interface circuit
for device A
4. a. Vith a block diagram, explain how the printer interfaced to processor.
(08 Marks)
Ans. Printer operates under control of the handshake
signals valid and idle in a manner
similar to the handshake used on thens with master ready and slave ready
Data
-

signais.

Data Out Data

Address
Processor R/W s SOUT Valid Pointer
Master ready
Output
interface
Slave ready Idle

Fig: Printer toprocessor conneetion

Sudstar Exam Scanner

 D,- D Q
Pointer
data
D,
D D
SOUT
Handshake idlc
Slave
Control valid
rcady
Read status
load data

R/W
Master
ready o-

A
Adder
decoder
A
A
Fig: Outputinterface
The interface contair.s & data register DATAOUT and status flag SOUG flag is set
to I when the printer is ready to accept another character and it is closed to 0 when
a new character is loaded into DATAOT by the processor the interface circuit
can

then place a new character on the data line and activate the valid signal; in response.
the new charater and negates the idle signal, which in
turn
the printerstats pointing
causes the interface to deactivate the valid signal.
. cl . T with raenect to IISB..
COMPUTER ORGANIZATION
PRINTER INTERFACED TO PROCESsOR

Output interface
Data
Data
Address DISP DATTA

R/W Ready
Processor Display
DISP STATUS
Master-ready
New-data
Slave-ready
Figure 7.13 Display to processor connection.
Keyboard is connected to a processor using a parallel-port.
Processor usess
memory-mapped I/0 and
asynchronous bus protocol.
.On the processor-side of the interface, we have:
- Data-lines
Address-lines
Control or R/W line
Master-Ready signal and
Slave-Ready signal.
On the keyboard-side of the interface, we have:
- Encoder-circuit which generates a code for the key pressed.
- Debouncing-circuit which eliminates the effect of a key.
for the key.
Data-fines which contain the code is pressed. This causes the code to be loaded
Valid iine changes from 0 to 1 when the key
into DATAIN and SIN to be set to 1.
 GENERAL 8 BIT PARALLEL PROCESSING

P7

DATAIN

DO

DATAOUT

Data
Directio

Myaddes
RS2

E
RS1 C1
RSO Register
sclect
RW
Ready
Accept

NTR
Figure 4.34: General 8 bit parallel interface

Data-lines P, through Po can be used for either input or output purposes (Figure 4.34)
For increased flexibility,
- some lines can be used as inputs and
some lines can be used as outputs.
The DATAOUT register is connected to data-lines via 3-state drivers that are controlled by a DDR.
The processor can write any 8-bit pattern into DDR. (DDR Data Direction Register).
.If DDR=1,
Then, data-line acts as an output-line
Otherwise, data-line acts as an input-line.
Two lines, C, and C, are used to control the interaction between interface-circuit and 1/0 device.
Two lines, C, and C, are also programmable.
Line C is bidirectional to provide different modes of signaling, including the handshake.
The Ready and Accept lines are the handshake control lines on the processor-bus side.
Hence, the Ready and Accept lines can be connected to Master-ready and Slave-ready.
The input signal My-address should be connected to the output of an address-decoder.
The address-decoder recognizes the address assigned to the interface.
There are 3 register select lines: RS,-RS.
Three register select lines allows up to eight registers in the interface.
An
interrupt-request INTR is also provided.
INTR should be connected to the interrupt-request line on the computer-bus.

2-33
 COMPUTER ORGANIZATION
PHASES IN SCSI BUS
.The phases in SCSI bus operation are:
1) Arbitration
2) Selection
3) Information transfer
4) Reselection

1) Arbitration
.When the -BSY signal is in inactive state,
t h e bus will be free &
any controller can request the use of bus.
SCSI uses distributed arbitration scheme because
each controller may generate requests at the same time.
Each controller on the bus is assigned a fixed priority.
.When -BSY becomes active, all controllers that are requesting the bus
examines the data-lines &
determine whether highest priority device is requesting bus at the same time.
The controller using the highest numbered line realizes that it has won the arbitration-process.
At that time, all other controllers disconnect from the bus & wait for -BSY to become inactive again.
Tgets examine ID

DB2

DBS

DB6

BSY

SEL

Free Arbitration Selecion

gure 442 Arbirasion ond selection on the SCSI bua. Device 6 wins arbiration
and selecs device 2.
2) Information Transfer
The information transferred between two controllers may consist of
commands from the initiator to the target
status responses from the target to the initiator or
data-transferred to/from the 1/0 device.
Handshake signaling is used to control information transfers, with the target controllertaking the role
of the bus-master.
3) Selection
.Here, Device
wins arbitration and
asserts -BSY and -DB6 signals
.The Select Target Controller responds by asserting -BSY.
.This informs that the connection that it requested is established.
4) Reselection
The connection between the two controllers has been reestablished, with the target in control of the
bus as required for data transfer to proceed.
 OR
4. a. Explain PCI
bus. (05 Marks)
Ans. The PCI bus is a system bus that grace out of the need for standardization.
1. Devices: Connected to the PCI bus appear to processor as if they werecoanected
directly to the processor bus.
Early PCs used the 8 bit XT bus, whose signal closely mimicked those those of
intel's 80 x 86 processor. 16 bit bus used on the PC AT computer known as ISA bus,
it extended 32 bit is known as EISA bus.
2. The PCI was developed as a low cost bus that iss truly processor independent.
3. the PCI pioneered is a plug and play capability for connecting 1/0 devices.
4. Data transfer It a burst of data.
5. Bus support 3 independent address space, memory, I/0 and configuration.
Configuration space is intended to give the PCI its PLUG and PLAY capablities.
Host

PCI bridge Main memory

DCI bus

Disk Printer Ethernet

Interface

Sunstar Exam Scanne

BCS Vec2016/Janv 2017
PC I bridge : It privides a separate physical connection for the main
Data transfer memory.
signals on the PCI bus
Name Function
CLK A 33 MHz or 66 -

MHz clock
FRAME# Sent by the intiater to indicate the duiration of îransacticn.
AD 32 addres/ data lines, which may be
optionally increased to 64.
C/BE# 4 command/byte enabled Iines
IRDX# Initiator - ready 2nd target ready signals
DEVSEL# A resporse from the device indicating that it has recogniscd its
address and is ready for a transfer transaction.
IDSEL# Initialization device select
The initiater uses the FRAME # signal to indicate. The duration of the burst. Since
it reads four words the intiator égates FRAME # during clock cycle 5, the eycle
in which it receives the third word. The fourth words in clock cycle 6, the target
disconnects its drivers and negates DEVSEL # at the begning of clock cycle 7.
I t CCST h1uc sianol with their functionalities. (05 Marks)
USB PROTOCOLS
All information transferred over the USB is organized in packets.
A packet consists of one or more bytes of information.
There are many types of packets that perform a variety of control functions.
The information transferred on USB is divided into 2 broad categories: 1) Control and 2) Data.
.Control packets perform tasks such as
addressing a device to initiate data transfer.
acknowledging that data have been received correctly or
indicating an error.
Data-packets carry information that is delivered to a device.
A packet consists of one or more fields containing different kinds of information.
The first field of any packet is called the Packet Identifier (PID) which identifies type of tha
packet.
They are transmitted twicce.
1) The first time they are sent with their true values and
2) The second time with each bit complemented.
The four PID bits identify one of 16 different packet types.
Some control packets, such as ACK (Acknowledge), consist only of the PID byte.
Control packets used for controlling data transfer operations are called Token Packets.

)Pctideredd
Bits

PID ADDR ENDP aRCI6

) Ton dNor oUT
0to8192 16

PID DATA CRCI6

(c) D pclet
Fgure 445 USB podet fornc
 D VO INTERFACES

Host computer

Root
hub

Hub Hub

1/0 /O /O /O
device device device device
Hub

/O
levice device

tree structure.
Figure 4.43 Universal Serial Bus
A Serial port is used to connect the
processor to l/O devices that require transmission
Aata one bit at a time. The key feature of an of
interface circuit for a serial is that
capable of communicating in a bit-serial fashion on the port it is
device side and in a bit-paraliel
fashion on the bus side. The transformation between the
parallel and serial
is achieved with shift
registers that have parallel access capability. A block formats
of a typical serial interface is shown in
Figure
diagram
4.37. It includes the familiar DATAIN
and DATAOUT registers. The
input shift register accepts bit-serial input from the I/O
device. When all 8 bits of data have been
loaded in parallel into the DATAIN
received, the contents of this shift register are
register. Similarly, output data in the DATAOUT
register are loaded into the output shift register, from which the bits are shifted out and
sent to the /O device.
The part of the interface that deals with the bus is the
same as in the parallel interface
described earlier. The status flags SIN and SOUT serve similar functions. The SIN lag
1S set to I
when new data are loaded in DATAIN; it is cleared to 0 when the
reads the contents of DATAIN. As soon as the data processor
are transferred from the
input shift
Tegister into the DATAIN register, the shift
register can start accepting the next 8-bit
Cnaracter from the I/O device. The SOUT flag indicates whether the output buffer is
1 D l e . lt is cleared to ) when the
processor writes new data into the DATAOUT
 INPUT/OTP
CHAPTER
258
Input shift register
Seul
joput

DATAIN

D7

DO

DATAOUT

My-address
RSI
RSO Chip and
Serial
register Output shift register
R/W select output
Ready
Accept

Receiving clock
Status
INTR and
Contro!
Transmission clock

Figure 4.37 A serial interface.

register and set to 1 when data are transferred from DATAOUT into the output S
register.
T h e double buffering used in the input and output paths is importantA Simpc
nterface could be
and
implemented by turning DATAIN and DATAOUT into shift registers
eliminating the shift registers in Figure 4.37. However, this would ward

restrictions on the
operation of the 1/O deviceafter receiving one character imposeathe
Serial iine, the device cannot
start receiving the next
d reads

the contents of eharacter until the

procers
DATAIN. Thus, a pause would be needed between two
allow the
processor to read the input data. With the cais
Second character can double buffer, the transi
begin as soon as the first
character is loaded from the
into the DATAIN
register.
Thus, provided the processor reads the contents si TAIN
before the serial transfer
of the second character is completed, the oan rece c e i v e

intertaac
 4.7 STANDARD VO INTERFACES

aantinuous stream of serial data. An

a cor analogous situation occurs in the output nath of
the interface.

Recause it requires fewer wires, serial transmission is convenient for

connecting
devices that are physically far away from the computer. The speed of transmission, often
oiven as a bit rate, depends on the nature of the devices connected. To accommodate
a range of devices, a serial intertace must be able to use a range of clock speeds. The
circuit in Figure 4.37 allows separate clock signals to be used for input and output
operations for increased flexibility.
Because serial interfaces play a vital role in connecting 1/O devices, several widely
features of our
used standards have been developed. A standard circuit that includes the
example in Figure 4.37 is known as a Universal Asynchronous Receiver Transmitter
devices. Data transmission is
(UART). It is intended for use with low-speed serial
start-stop format, which we discuss in Chapter 10.
performed using the asynchronous
standard known as RS-232-C
lo facilitate connection to communication links, a popular

Was developed. It is also described in Chapter

10.
 Module-3
5. a Explain the organization of 1kx 1 memory chip. 08 Marks)
Ans. Organization of a IK x 1 memory chip.
IK (1024) menory cels. This circuit can be organized as a 128x 8 memory, requiring
a total of 19 external connections. Alternatively, the same number of cells can be
organized into a 1K x 1 format. in this case, a 10-bit address is needed, but there is
only one data line, resulting in 15 externai connections.The required 10-bit address
is divided into two groups of 5 bits each to form the row and column addresses for
the cell array. A row address selects a row of 32 cells, all of which are accessed in
parallel. But, only one of these cells is connected to the external data line, based on
the column address.
CBCS Deo 2019Jan 2020
5-bi row
aderess Wo
W 32x 32
S-bit memory cel
decoder array
Sense/Write
circuitry

10-bit
address 32-t0-1 R/W
output muliplexer
md
CSS
nput demuhiplexer

S-bit colunin
address
Data
input/output

cache in mapping functions,

b. With a neat figure explain the direct mapped (08 Marks)
is
nnche locations in which to store menory
blocks
 b. With a neat diagram explain the internal organization of memory chip (2M*8
and dynamic memory chip). (08 Marks)
Ans. Static RAMs are fast but high cost:
Dynamic RAM cell stores data in the form of charge on a capacitor and this charge
can be maintained for only tens of milliseconds. Since the cell is required to store
information for much longer time. Its contents must be periodically refreshed by
restoring the capacitor charge to its full values.
Bit line Word line

The transfer continues to conduct a tiny amount of current, measured in picoampers

after it turned off to maintain capacitor charge.
2MX 8 DRAM chip:

Row address Row 40964096 x (512 x 8)

latch decoder Cell array

Azo Azo
Sense/Write circuis]-R/W
. .

Column
address latch Column decoder

D D

12 Sunetar Fvan Saaar

CBCS Dec 2015/Jan 2017
The cells are
organised
in the form of a 4k x 4k array. 4096 cells in each row ure
divided into 512 groups of 8. So that a row can store 512
bytes of data. Therefore 12
address bits are needed to select a row. Another 9 bits are needed to
specify a group
of 8 bits in the selected row. This a 21 bit address is ended to access a byte in this
memory.
The high order 12 bits and the low order 9 bits of the address econstitute the rOw
and column address of a byte. To reduce the umber of pins needed for external
connections, the row and coBumn address are multiplexed on 12 pins.
Working
I. During read/ write operation the row address is applied first. It is loaded into row
address latch in response to a signal pulse on the row address stobe input of the chip.
2. Row address is loaded the column address latch under control CAS signal.
3. It read signaiis initiated, the output values of selected circuits are transferred to
the dat& line D,.e* the D, lines is transferred to selected
4. For a write operation the information on

circuits.
OR
6. a. Explain thefollowing: (08 Marks)
ii) Virtual memory organization.
i) lit Rate and Miss penalty data in 7 cache is cailed a hit. The number of hits