Internship Vvce Final

VISVESVARAYA TECHNOLOGICAL
UNIVERSITY JNANA SANGAMA,

BELAGAVI – 590018
An Internship Report On
Standard Cell Library Design
Submitted in partial fulfilment of the requirement for the award of the degree
of
Bachelor of Engineering
In
Electronics and Communication Engineering
By
Prashanth Ananth Hegde 4VV17EC065

Kavya M S 4VV17EC036
Shivasagar K 4VV17EC082
Prajwal Gowda E 4VV17EC060
Internship Carried Out At

Vivarthan Technologies LLP
Under the Guidance of

Prof. Kiran Kumar Humse
Assistant Professor
Dept. of ECE
VVCE, Mysuru
Department of Electronics and Communication Engineering

Vidyavardhaka College of Engineering,
Mysuru – 570002
2020-2021
VIDYAVARDHAKA COLLEGE OF ENGINEERING
Ш STAGE, GOKULAM, MYSURU-570002
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
CERTIFICATE
Certified that the INTERNSHIP work entitled “Standard Cell Library Design” carried out by
Mr. Prashanth Ananth Hegde, USN 4VV17EC065, a bonafide student of Vidyavardhaka
College of Engineering in partial fulfilment for the award of Bachelor of Engineering in
Electronics and Communication of the Visveswaraiah Technological University, Belgaum
during the year 2020-2021. It is certified that all corrections/suggestions indicated for Internal
Assessment have been incorporated in the Report deposited in the departmental library. The
internship report has been approved as it satisfies the academic requirements in respect of
internship work prescribed for the said Degree.
NAME & SIGNATURE NAME & SIGNATURE SIGNATURE OF THE

OF THE GUIDE OF THE HOD PRINCIPAL
EXTERNAL VIVA
NAME OF THE EXAMINERS SIGNATURE WITH DATE
1.
2.
CERTIFICATE
Ms. Kavya M S, USN 4VV17EC036, a bonafide student of Vidyavardhaka College of
Engineering in partial fulfilment for the award of Bachelor of Engineering in Electronics and
Communication of the Visveswaraiah Technological University, Belgaum during the year 2020-
2021. It is certified that all corrections/suggestions indicated for Internal Assessment have been
incorporated in the Report deposited in the departmental library. The internship report has been
approved as it satisfies the academic requirements in respect of internship work prescribed for
the said Degree.
NAME & NAME & SIGNATURE OF THE

SIGNATURE OF THE SIGNATURE OF THE PRINCIPAL
GUIDE HOD
EXTERNAL VIVA
1.
2.
CERTIFICATE
Mr. Shivasagar K, USN 4VV17EC082, a bonafide student of Vidyavardhaka College of
the said Degree.

EXTERNAL VIVA
1.
2.
CERTIFICATE
Mr. Prajwal Gowda E, USN 4VV17EC060, a bonafide student of Vidyavardhaka College of
the said Degree.

EXTERNAL VIVA
1.
2.
VIVARTHAN TECHNOLOGIES LLP
MC LAYOUT, VIJAYANAGAR, BENGLURU - 560 040
CERTIFICATE
Certified that the internship work entitled “Standard Cell Library Design” carried out by Mr.
Prashanth Ananth Hegde, a bonafide student of Vidyavardhaka College of Engineering in partial
fulfilment for the award of Bachelor of Engineering in Electronics and Communication of the
Visvesvaraya Technological University, Belgaum during the year 2020-2021. It is certified that,
he has completed the work satisfactorily.
Name & Signature of the Guide Name & Signature of the Head of
organization
MC LAYOUT, VIJAYANAGAR, BENGLURU - 560
CERTIFICATE
Certified that the internship work entitled “Standard Cell Library Design” carried out by Ms.
Kavya M S, USN 4VV17EC036, a bonafide student of Vidyavardhaka College of Engineering
in partial fulfilment for the award of Bachelor of Engineering in Electronics and Communication
of the Visvesvaraya Technological University, Belgaum during the year 2020-2021. It is
certified that, he has completed the work satisfactorily.
organization
CERTIFICATE
Shivasagar K, USN 4VV17EC082, a bonafide student of Vidyavardhaka College of Engineering
in partial fulfilment for the award of Bachelor of Engineering in Electronics and Communication
of the Visvesvaraya Technological University, Belgaum during the year 2020-2021. It is
certified that, he has completed the work satisfactorily.
organization
CERTIFICATE
Prajwal Gowda E, USN 4VV17EC060, a bonafide student of Vidyavardhaka College of
Engineering in partial fulfilment for the award of Bachelor of Engineering / Bachelor of
Technology in Electronics and Communication of the Visvesvaraya Technological University,
Belgaum during the year 2020-2021. It is certified that, he has completed the work satisfactorily.
organization
I. DECLARATION
We, Prashanth Ananth Hegde, Kavya M S, Shivasagar K, Prajwal Gowda E, studying in 8th
semester of Bachelor of Engineering in Electronics and Communication Engineering at
Vidyavardhaka College of Engineering, Mysuru, hereby declare that the presented report of
internship carried out at “Vivarthan Technologies LLP” which is being submitted by us in the
partial fulfilment for the award of the degree of Bachelor of Engineering in Electronics and
Communication Engineering, from Visvesvaraya Technological University, Belagavi is a record
of us carrying out the internship during the academic year 2020-2021, under the guidance of
Prof. Kiran Kumar Humse, Department of Electronics and Communication Engineering,
Vidyavardhaka College of Engineering, Mysuru. We further undertake that the matter embodied
in the dissertation has not been submitted previously for the award of any degree or diploma by
us to any other university or institution.
Place: Mysuru.
Date:
i
II. ACKNOWLEDGEMENT
It is our proud privilege to acknowledge the kind of help and guidance received from several
people in preparation of this report. It would not have been possible to prepare this report in this
form without their valuable help, cooperation and guidance.
First and foremost, we wish to place on record our sincere gratitude to Management of this
college and to our beloved Principal, Dr. B. Sadashive Gowda, Vidyavardhaka College of
Engineering, Mysuru, for his constant support and encouragement in preparation of this report
and for making available library and laboratory facilities needed to prepare this report.
Our sincere thanks to Dr. Chandrashekar M Patil, Professor and Head, Department of
Electronics and Communication Engineering, VVCE, for his valuable suggestions and guidance
throughout the period of this seminar report.
We express our sincere gratitude to our guide, Prof. Kiran Kumar Humse , Department of
Electronics and Communication Engineering, VVCE, Mysuru for guiding us through Internship.
Our numerous discussions with him were extremely helpful.
Our sincere thanks to Prof. Rohith K, Internship Coordinator, Department of Electronics and
Communication Engineering, VVCE, Mysuru for having supported the work related to this
Internship. His contributions and technical support in preparing this report are greatly
acknowledged.
Place: Mysuru.
i
III. ABSTRACT
Internship provides a nice learning curve for students with a little experience of the professional
world. It also allows us to harness the skill, knowledge, and theoretical practice that we learnt in
the university.
A standard cell library is a collection of low-level electronic logic functions such as AND, OR,
INVERT, flip-flops, latches, and buffers. These cells are realized as fixed-height, variable-width
full-custom cells. The key success factor for the rapid growth of the integrated system is use of
ASIC library for various system functions. It consists of pre-verified logic blocks that help
designers to shorten the product development time and manage complexity of a chip having
millions of logic gates or more.
This report shows the experience gathered during the course of one month internship at
Vivarthan technologies LLP. We procured both practical and theoretical knowledge about
standard cell library design. We were able to design the schematic and layout of various
combinational and few sequential circuits.
i
CONTENTS Page
number
Abstract iii
List of Figures v
Chapter -1 Company details 15
1.1 Company Profile 15
1.2 About the Company 15
1.3 General introduction 16
1.5 History 16
1.5 Vision and Mission 17
1.5.1 Vision 17
1.5.2 Mission 17
1.6 Facilities and Services 17
1.6.1 Digital Design 17
1.6.2 Analog and Mixed Signal 17
1.6.3 Foundation IPs 17
1.6.4 Design Automation 17
1.7 Collaboration 19
Chapter -2 Role as an Intern 20
Chapter -3 Design of Standard Cell 21
3.1 Schematic View 23
3.2 Test Bench Generation 24
3.3 Transient Analysis 25
3.4 DC And Power Analysis 26
3.5 Layout 26
Chapter -4 Learning Outcomes of Internship 29
4.1 Schematic 29
4.2 Layout 29
Chapter -5 Conclusion and Future work 30
References 31
i
LIST OF FIGURES
Figure Description Page

No. No.
Fig.1.6 Vivartan collaborated institutions 19
Fig.3 Standard Cell Library 22
Fig.3.1 Schematic of Inverter 23
Fig.3.2 Test Bench of Inverter Schematic 24
Fig.3.3 Transient analysis of Inverter 25
Fig.3.5 Layout of Inverter 27
v
Vivartan Technologies
1. COMPANY DETAILS
1.1 Company Profile

Company Name: Vivartan Technologies LLP.
Address : No. 732, 9thCross, 5thMain, MC Layout, Vijayanagar, Bengaluru - 560 040
Telephone Number: +91 988 671 6583
Email address : vivartan.edu@gmail.com
Website: www.vivartan.com
Type of Company: Private
Founder: Mr. Sunil Kumar H V
Founded: September - 2009
Business Registration Number: AAG - 1708 (LLPIN)
Registered Capital: Rs. 50,000
Services: Digital Design, Analog and Mixed Signal, Foundation IPs, Digital Automation
Number of Employees: 30
1.2 About the Company

We are a group of industry professionals committed to transform learning space in
engineering education that creates quality, employable and industry ready engineering
professionals.
Ideation without Execution is mere Delusion – We started executing our idea of bridging the
gap between Industry and Academia in 2009. We see education powerfully confederated with
training and development as a tool; to enable people in fulfilling the market demand
consistently.
Every member of our team is an active working professional from different companies;
Passionate in contributing to the student community and to define a profound way of holistic
learning resulting in competent talent pool.
Our Team comprises of experts from various domains of IC design who are currently
Dept. of ECE, VVCE, Mysuru (2020- Page

working on high end processor designs and cutting edge technology nodes including the
latest 7 nm FINFET process node. This enables us in creating and fine tuning our training
programs in sync with frequently changing industry needs.
1.3 General Introduction

Vivartan offers a full time training program in Custom Physical Design or Custom Layout for
people who have completed engineering. They aim to start more programs in the future.
Vivartan believes in long term training programs rather than short term programs as they
don’t want to compromise on the quality of training and delivery Vivartan stitches the whole
program from model to model.
The software used by the company is Cadence. Cadence Design Systems, Inc. is an American
multinational electronic design automation (EDA) software and engineering services
company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company
produces software, hardware and silicon structures for designing integrated circuits, systems
on chips (SoCs) and printed circuit boards.
1.4 History
It was established in 2009, by a few industry professionals with the passion to contribute the
education sector and bridging the gap between industry and academia is Vivartan. Project-
based approach is followed by Vivartan which equips the students with industry ready skills.
The students are taught to be self-sufficient.
Vivartan aims to tie up with engineering colleges and institutes and then deliver courses to
bridge the gap between industry and the academia. Vivartan’s university program is where
they will tie up with colleges to run a certificate program for under graduate students for a
span of 2 years. They are looking forward to tie up with at least 20-25 colleges in the next 5
years. They might enter into digital design and verification in the next year.
Our Team comprises of experts from various domains of IC design who are currently
working on high end processor designs and cutting edge technology nodes including the
latest 7 nm FINFET process node.

1.5 Vision and Mission

The company’s vision and mission which are driving the company towards its success are
given below
1.5.1 Vision
Being a preferred sourcing partner; for hi-tech and niche technology companies.
1.5.2 Mission
• Design and deliver programs creating best quality, employable, industry ready
professionals.
• Create a robust model bridging Industry and Academia for a conscious engineering
community.
• Build scale model to enable the growing need for employable engineers.
1.6 Facilities and Services
Vivartan Technologies provides solutions to building System on Chips(SoC) which involves

both Digital and Analog designs. They focus on end to end services for IoT, Mobile and
NextGen Automobiles.
They have experience in all major technology nodes and fabs including latest FinFETs upto
7nm. Teams have expertise in all the industry standard EDA tools.
1.6.1 Digital Design

• Architecture Design at IP and SoC level for FPGA/ASIC flows
• RTL Design at IP and SoC level using Verilog/VHDL/System Verilog
• Low power design at IP and SoC level
• Methodology based verification using System Verilog.
• SoC level verification using C language
• Gate Level Simulation
• Synthesis using Synopsys/Cadence flow
• DFT architecture design and Implementation
• Physical Design and Verification
• Static Timing Analysis at IP/Sub-system/SoC level

1.6.2 Analog and Mixed Signal

• Analog Mixed Signal Design and Verification
– Our team has expertise in PMIC, Data Converters, and Clocked
– Circuits, from SPEC to GDS for various Technology nodes
– We have a dedicated team of engineers who are focussing on Analog mixed signal
modelling and verification.
• Analog Layout
– Our team has immense experience in PMIC, Data Converters, and Clocked Circuits, IO
layout design for various Technology nodes from Bulk CMOS toFinFet. Team’s core
competency is both in block level design to full chip integration and verification.
1.6.3 Foundation IPs

• Memory Design and Layout
– Compiler design development
– Compiler regression
– Characterization
– Leaf cell circuit design and Layout design for SRAM, Register files,
TCAM/B- CAM
• Standard Cell Library Development
– Design from scratch
– Migration (Technology migration or Channel length modifications) Layout design and
Physical verifications
– Characterization and View generations
1.6.4 Design Automation

Design Automation: We offer design automation services in industry accepted languages like
SKILL, Perl, Shell, Python

1.7 Collaboration
Today’s learning is becoming increasingly competitive for students, institutions and as well
for corporations. We believe that every individual must develop abilities in accelerated
learning, and self-learning along with specialized domain skills required for their career.
The outcome of our program offerings is to produce high quality, skilled and industry ready
professionals for niche and hi-tech industries.
Our program offerings are designed keeping the above articulated idea in mind. It has always
been at back of our mind - what makes learning more enjoyable. All our programs are
designed with competence of both technical skills and soft skills. Engineering Colleges play
vital and dual role in our model. They are our primary and strategic partners and as well
customers in achieving our mission.
We deliver programs at our partner college facilities under the respective college banner in
association with Vivartan Technologies.
Our Partner Institutions:
• ATME College of Engineering, Mysuru
• Vidyavardhaka College of Engineering, Mysuru
• CHRIST (Deemed to be University), Bengaluru
(a) ATME College of Engineering (b) Vidyavardhaka College (c) CHRIST University
Fig.1.6 Vivartan Collaborated Institutions

2. ROLE AS AN INTERN
Our internship sessions started with a detailed introduction to standard cell library and
various steps carried out in designing standard cells, followed by an exposure to the design
tool, Virtuoso which we used in later stages to complete our tasks.
The Virtuoso platform is the industry’s most silicon-proven, comprehensive, custom IC
design platform, trusted in taping out thousands of designs each year for more than 25 years.
Key Benefits:
 Supports custom analog, digital, and mixed-signal designs at the device, cell, block,
and chip levels.
 Accelerated performance and productivity from advanced full custom polygon editing
through more flexible schematic and constraint-driven assisted full custom layout, to
full custom layout automation
 Enables creation of differentiated custom silicon that is both fast and silicon accurate
As interns, we carried out following tasks
 Coming up with the schematic and layout designs of different combinational circuits
using CMOS technology.
 We were encouraged to explore the tool, learn different aspects of it so that we get a
hands-on experience.
 We designed a standard cell library, which included basic gates, inverters, buffers,
etc. with different drive strengths like X1, X2, X4, X8, X16 and X32.
 The design steps included schematic and symbol generation, test bench circuit, layout
and verification of our design.
 DRC and LVS are the two different verifications performed on our design.
By the end of our internship we were able to successfully complete all the tasks assigned to
us. And we also gained knowledge about standard cells.

3. DESIGN OF STANDARD CELL
A standard cell library is a collection of low-level electronic logic functions such as

AND, OR, INVERT, flip-flops, latches, and buffers. These cells are realized as fixed-
height, variable-width full-custom cells. The key aspect with these libraries is that they
are of a fixed height, which enables them to be placed in rows, easing the process of
automated digital layout. The cells are typically optimized full-custom layouts, which
minimize delays and area.
Usually, the initial design of a standard cell is developed at the transistor level, in the
form of a transistor netlist or schematic view. The netlist is a nodal description of
transistors of their connections to each other, and of their terminals (ports) to the external
environment.
A schematic view may be generated with a number of different Computer Aided Design
(CAD) or Electronic Design Automation (EDA) programs that provide a Graphical User
Interface (GUI) for this netlist generation process. Designers use additional CAD
programs such as SPICE or Spectre to simulate the electronic behavior of the netlist, by
declaring input stimulus (voltage or current waveforms) and then calculating the circuit's
time domain (analogue) response. The simulations verify whether the netlist implements
the desired function and predict other pertinent parameters, such as power consumption
or signal propagation delay.
Since the logical and netlist views are only useful for abstract (algebraic) simulation, and
not device fabrication, the physical representation of the standard cell mustbe designed
too. Also called the layout view, this is the lowest level of design abstraction in common
design practice. From a manufacturing perspective, the standard cell's VLSI layout is the
most important view, as it is closest to an actual "manufacturing blueprint" of the
standard cell. The layout is organized into base layers, which correspond to the different
structures of the transistor devices, and interconnect wiring layers and via layers, which
join together the terminals of the transistor formations. The interconnect wiring layers
are usually numbered and have specific via layers representing specific connections
between each sequential layer.
Non-manufacturing layers may be also be present in a layout for purposes of Design
Automation, but many layers used explicitly for Place and route (PNR) CAD programs
are often included in a separate but similar abstract view. The abstract view often

contains much less information than the layout and may be recognizable as a Layout
Extraction Format
(LEF) file or an equivalent. After a layout is created, additional CAD tools are often used to
perform a number of common validations. A Design Rule Check (DRC) is done to verify that
the design meets foundry and other layout requirements as shown in the Figure 3. A Parasitic
Extraction (PEX) then is performed to generate a PEX-netlist with parasitic properties from
the layout. The nodal connections of that netlist are then compared to those of the schematic
netlist with a Layout Vs Schematic (LVS) procedure to verify that the connectivity models
are equivalent.
Fig.3: Standard Cell Library

3.1 Schematic View
A schematic diagram is a representation of the elements of a system using graphic symbols

rather than realistic pictures. A schematic usually omits all details that are not relevant and
includes oversimplified elements. This is done interactively with the help of a schematic
capture tool also known as schematic editor shown in the Fig.3.1. The circuit design is the
very first step of actual design of an electronic circuit. Typically sketches are drawn on paper,
and then entered into a computer using a schematic editor. Therefore schematic entry is said
to be a front-end operation of several others in the design flow.
Fig.3.1: Schematic of Inverter
The Layout Versus Schematic (LVS) is the class of electronic design automation (EDA)
verification software that determines whether a particular integrated circuit layout
corresponds circuit layout corresponds to the original schematic or circuit diagram of the
design.

3.2 Test Bench Generation
A test bench or testing workbench is an environment used to verify the correctness or

soundness of a design or model. Test bench is an isolated, controlled environment, very
similar to the production environment but hidden/ not visible to the general public,
customers, etc. Instead symbols of the cells are created in order to instantiate them in the
higher level schematics and make them more readable.
Fig.3.2: Test Bench of Inverter Schematic
While editing the symbol, you can use only Save, which does not check anything. At this
point, checking a symbol means comparing the symbol view with the corresponding
schematic view, by matching all of the pin names. This occurs only when you click on Check
and save.

3.3 Transient Analysis
Transient analysis is the analysis of the circuits during the time it changes from one steady
state condition to another steady state condition. Transient analysis will reveal how the
currents and voltages are changing during the transient period.
Transient analysis gives time domain waveform which is a plot of voltage or current versus
time. Transient analysis calculates a circuit’s response over a period of time defined by the
user.
Fig.3.3: Transient analysis of Inverter
If the variable involved in defining the state of a system does not vary with respect to time,
then the system is said to be in steady state. If not, it is in unsteady state. Transient simulation
is the calculation of a network's response on arbitrary excitations. The results are network
quantities (branch currents and node voltages) as a function of time as shown in the Fig.3.3.

Substantial for the transient analysis is the consideration of energy storing components, i.e.,
inductors and capacitors. For every time step, the node voltages and currents are calculated
and compared to the previous time step DC solution. Only when the difference between two
DC solutions falls within a specified tolerance (accuracy) will the analysis move on to the
next internal time step.
3.4 DC AND POWER ANALYSIS

DC analysis is a straightforward process of applying ohm's law, then a little algebraic
manipulation and plug in numbers to solve for some constant value. This usually only
involves resistors and no complex impedance. AC analysis is the same process, until you get
to plugging in the values. In VLSI design implementation simulation software operating at
various levels of design abstraction. In general simulation at a lower-level design abstraction
offers better accuracy at the expense of increased computer resource. The increasing
complexity of VLSI digital systems has dramatically supported system-level representations
in modelling and design activities. This evolution makes often necessary a compliant
rearrangement of the modalities followed in validation and analysis tasks, as in the case of
power performances estimation. Nowadays, transaction-level paradigms are having a wider
and wider consideration in the research on electronic system level design techniques as
shown in the With regard to the available modelling resources, the most relevant framework
is probably the transaction-level extension of the System C language (System C/TLM), which
therefore represents the best platform for defining transaction-level design techniques. The
present discussion illustrates the implementation modalities of the proposed approach,
verifying its effectiveness through a comparison with RTL estimation techniques.
3.5 LAYOUT
Layout design is a schematic of the Integrated Circuit (IC) which describes the exact
placement of the components for fabrication. Layout design rules describe how small features
can be closely packed in a manufacturing process. The main layers used in the layout are
oxide (diffusion), n-implant, p-implant, poly-silicon and different metal layers such as metal1,
metal2 ...... metal8. The interconnection of these layers and their usage.
When using a standard process where the interaction of the many chemical, thermal, and
photographic variables is known and carefully controlled the behaviour of the final
integrated
circuit depends largely on the positions and interconnections of the geometric shapes as
shown in the Fig.3.5. Using a computer-aided layout tool, the layout engineer or layout
technician places and connects all of the components that make up the chip such that they
meet certain criteria typically: performance, size, density, and manufacturability. This layout
which is shown in the Fig 3.5 consists of different layers used for the fabrication. The green
colored layer is the poly-silicon layer, blue colored layer is metal1, red colored layer is oxide
(diffusion) layer and cross boxes are the input and output pins.
Fig.3.5: Layout of Inverter
This design process is carried out for the following cell listed below:
 Inverter 1X, 2X, 4X, 8X, 16X, 32X
 Buffer 1X, 2X, 4X, 8X, 16X, 32X
 OR Gate 4X
 NOR Gate 4X
 NAND Gate 4X, 8X

 AOI21 1X
 OAI21 2X
 AO21 1X
 IAOI22 4X
 IOAI22 8X
 ADDH , ADDF 1X 2X
 MUX 2:1

4. LEARNING OUTCOMES OF INTERNSHIP
Applied the knowledge and concepts acquired related to VLSI in practice. Learned the basics
of Cadence tool used in the industry. Enhance classroom education with better understanding
of concepts in VLSI. We were able to develop skilled competencies that are specific to VLSI
domain and also gained knowledge about the job opportunities available in VLSI. Developed
observation, recording and interpretation skills. Commercially available Electronic Design
Automation (EDA) tools use the technology libraries to automate synthesis, placement, and
routing of a digital ASIC.
4.1 Schematic
A schematic, or schematic diagram, is a representation of the elements of a system using
abstract, graphic symbols rather than realistic pictures. A schematic usually omits all details
that are not relevant to the key information the schematic is intended to convey, and may
include oversimplified elements in order to make this essential meaning easier to grasp.
4.2 Layout
Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the
representation of an integrated circuit in terms of planar geometric shapes which correspond
to the patterns of metal, oxide, or semiconductor layers that make up the components of the
integrated circuit.

5. CONCLUSION AND FUTURE WORK
In this ever growing world of technology, we expect the size of the systems to be reduced
and have optimized performance. For this to be possible the Integrated Chips used inside the
system have to be minimized in area and low power. Standard library cells with minimum
area improve designer’s productivity through reduced design time and debugging. Using such
cells from High Density Standard Cell Library, the total area of the Integrated Chip is
minimized and Low Density Standard cell library has low power.
In future more investigations have to be done on the behavior of transistors in series.

To improve the efficiency of the library for building complex design, mega cells such as: 1
bit register file slice, a 1 bit ALU, decoder, UART, PIO/PIA microcontroller core, fixed point
DSP core, FIFO, SRAM should be included in the existing library. To achieve higher speed
and lesser area transistors can be scaled and single and double height cells can be
implemented. Few analog cells and filler cells can be inc luded. We can take up a project to
design a complete Customized Standard Cell Library for an ASIC Processor.

REFERENCES
 www.vivartan.com
 Ni Haiyan and Hu Jianping. “Near-threshold sequential circuits using Improved

Clocked Adiabatic Logic in 45nm CMOS processes”. In Proceedings of IEEE
54th International Midwest Symposium on Circuits and Systems (MWSCAS), p.
1–4 (2011).
 Poornima H S, Chetana K S, “Standard Cell Library Design and Characterization

using 45nm technology,” IOSR Journal of VLSI and Signal Processing
(IOSRJVSP), Volume 4, Issue 1, Jan 2014.
 Srujan R, Suraj M, Vinay S, Vishal M S, “Design, Implementation and

characterization of 45nm Standard Cell Library for industrial synthesis flow”.
 Kuhn, Kelin J. “Reducing variation in advanced logic technologies: Approaches

to process and design for manufacturability of nanoscale CMOS.” In 2007 IEEE
International Electron Devices Meeting, pp. 471-474. IEEE, 2007.
 D. Z. Pan, B. Yu, and J.-R. Gao, "Design for manufacturing with emerging
nanolithography," IEEE Transactions on CAD, vol. 32, no. 10, pp. 1453--1472,
2013.
 J.-0. Plouchart et al, “Application of an SO1 0.12um CMOS Technology to SoCs

with Low-Power and High-Frequency Circuits”. IBM J. Res. Devel., p. 611- 629,
Vol. 47, No. 516 (2003)
 IEEE.
 www.frenustech.com
 www.vlsifacts.com

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VISVESVARAYA TECHNOLOGICAL

UNIVERSITY JNANA SANGAMA,

Prashanth Ananth Hegde 4VV17EC065

Internship Carried Out At

Under the Guidance of

Department of Electronics and Communication Engineering

Ш STAGE, GOKULAM, MYSURU-570002

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NAME & SIGNATURE NAME & SIGNATURE SIGNATURE OF THE

NAME OF THE EXAMINERS SIGNATURE WITH DATE

Ш STAGE, GOKULAM, MYSURU-570002

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NAME & NAME & SIGNATURE OF THE

NAME OF THE EXAMINERS SIGNATURE WITH DATE

Ш STAGE, GOKULAM, MYSURU-570002

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NAME & SIGNATURE NAME & SIGNATURE SIGNATURE OF THE

NAME OF THE EXAMINERS SIGNATURE WITH DATE

Ш STAGE, GOKULAM, MYSURU-570002

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NAME & SIGNATURE NAME & SIGNATURE SIGNATURE OF THE

NAME OF THE EXAMINERS SIGNATURE WITH DATE

Figure Description Page

Fig.3 Standard Cell Library 22

Fig.3.1 Schematic of Inverter 23

Fig.3.2 Test Bench of Inverter Schematic 24

Fig.3.3 Transient analysis of Inverter 25

Fig.3.5 Layout of Inverter 27

1.1 Company Profile

1.2 About the Company

Dept. of ECE, VVCE, Mysuru (2020- Page

1.3 General Introduction

Dept. of ECE, VVCE, Mysuru (2020- Page

1.5 Vision and Mission

1.6 Facilities and Services

Vivartan Technologies provides solutions to building System on Chips(SoC) which involves

1.6.1 Digital Design

Dept. of ECE, VVCE, Mysuru (2020- Page

1.6.2 Analog and Mixed Signal

1.6.3 Foundation IPs

1.6.4 Design Automation

Dept. of ECE, VVCE, Mysuru (2020- Page

Fig.1.6 Vivartan Collaborated Institutions

Dept. of ECE, VVCE, Mysuru (2020- Page

Dept. of ECE, VVCE, Mysuru (2020- Page

3. DESIGN OF STANDARD CELL

A standard cell library is a collection of low-level electronic logic functions such as

Dept. of ECE, VVCE, Mysuru (2020- Page

Fig.3: Standard Cell Library

Dept. of ECE, VVCE, Mysuru (2020- Page

3.1 Schematic View

A schematic diagram is a representation of the elements of a system using graphic symbols

Fig.3.1: Schematic of Inverter

Dept. of ECE, VVCE, Mysuru (2020- Page

3.2 Test Bench Generation

A test bench or testing workbench is an environment used to verify the correctness or

Fig.3.2: Test Bench of Inverter Schematic

Dept. of ECE, VVCE, Mysuru (2020- Page

3.3 Transient Analysis

Fig.3.3: Transient analysis of Inverter

Dept. of ECE, VVCE, Mysuru (2020- Page

3.4 DC AND POWER ANALYSIS

Fig.3.5: Layout of Inverter