Chapter-4 Updated

Electrical and Electronic Equipment for
Industrial Machinery
Chapter 4
Digital System
Chapter 4. Digital System >>1. Numeration Systems
Analog signal Digital signal
HCM City Univ. of Technology, Faculty of Mechanical Engineering 2 Duong Van Tu

An analog signal is a time-varying A digital signal is a time separated signal.

continuous signal.
The analog signal is denoted by sine The digital signal is denoted by square
waves. waves.

The values of the analog signal varies in The values of the digital signal is only one
the range. of two values: LOW or HIGH.
The analog signal doesn’t offer any fixed The digital signal has a finite number, 0 and
range. 1.

TTL Signal Levels
Acceptable TTL Gate Input Acceptable TTL Gate

Signal Levels Output Signal Levels

CMOS Signal Levels
Acceptable CMOS Gate Acceptable CMOS Gate

Input Signal Levels Output Signal Levels

Digital Number System
System Base Symbol Example

Binary 2 0, 1 0b11001111 (110011112)
Octal 8 0, 1, …, 7 0O52 (528)
Decimal 10 0, 1, …, 9 255 (25510)
Hexadecimal 16 0, 1, …, 9, A, B, C, D, E, F 0x1F (1F16)
Decimal Number
255 = 2 × 10 + 5 × 10 + 5 × 10

Decimal Number
Weights
102 101 100 . 10-1 10-2 10-3
2 5 5 . 1 2 3
Most Significant Decimal point Least Significant

Digit (MSD) Digit (LSD)
255.123 = 2 × 10 + 5 × 10 + 5 × 10 + 1 × 10 + 2 × 10 + 3 × 10

Binary Number
Prefix 27 26 25 24 23 22 21 20 bit
0 b 1 1 0 0 1 1 1 1
MSB 8 bit = 1 byte LSB
Binary Number to Decimal Number
0b11001111 = 1 × 2 + 1 × 2 + 0 × 2 + 0 ×
2 + 1 × 2 + 1 × 2 + 1 × 2 + 1 × 2 = 207
25010 = 0b_________

Binary Number
27 26 25 24 23 22 21 20 . 2-1 2-2 2-3
1 1 0 0 1 1 1 1 . 1 0 1
Binary Number to Decimal Number Binary point
11001111.1012= 1 × 2 + 1 × 2 + 0 × 2 + 0 × 2 + 1 × 2 + 1 × 2 + 1 × 2 + 1 × 2 +
1 × 0.5 + 0 × 0.25 + 1 × 0.125 = 207.625
13.687510 = _________2

Octal Number Octal Number to Decimal Number
Prefix 81 80 bit 0O52= 5 × 8 + 2 × 8 = 42
0 O 5 2 25010= 0O____
Octal Number to Binary Number

0 O 5 2
0 b 1 0 1 0 1 0
22 21 20 22 21 20
Octal Number
Prefix
0 O 5 2 . 1 7
52.1728= 5 × 8 + 2 × 8 + 1 × 8 +7×8 +2×8 = 40 + 2 + 1 ×

0.125 + 7 × 0.015625 = 42.234375

Hexadecimal Number Hexadecimal to Binary Number
Prefix 1 0 bit 0x1F= 1 × 16 + 15 × 16 = 31
0 X 1 F 25010= 0x________
Hexadecimal Number to Binary Number

0 X 1 F
0b10101100 = 0x____
0 b 0 0 0 1 1 1 1 1

Hexadecimal Number
0 X 1 F . 1 2
Hexadecimal point
1F.1216= 1 × 16 + 15 × 16 + 1 × 16 + 2 × 16 = 31.0703125
B2F16= ____________2

Binary Coded Decimal (BCD) Number 0 0000
1 0001
1 0 0 1 1 0 0 0 BCD 2 0010
3 0011
4 0100
5 0101
9810
6 0110
7 0111
8510 = 1000 0101 (BCD) 8 1000
57210 = 0101 0111 0010 (BCD) 9 1001
857910 = 1000 0101 0111 1001 (BCD)
1010, 1011, 1100, 1110, 1111 are not used

Binary Coded Decimal (BCD) Number 0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001

Chapter 4. Digital System >>2. Binary Arithmetic
Binary Addition
There is little to memorize in the way of rules for the addition of binary bits
0+0=0
1+0=1
0+1=1
1 + 1 = 10
1 + 1 + 1 = 11

Negative Binary Numbers
1012 = 510 (positive number)
Extra bit, representing sign (0 = positive, 1 = negative)
01012 = 510 (positive number)
11012 = -510 (negative number) However it can also be thirteen (13)
Complementation
We assign the leftmost bit to serve a special purpose.
The leftmost bit possesses a negative place-weight value.
10112 = -510
1 × −2 + 0 × 2 + 1 × 2 + 1 × 2 = −8 + 3 = −5

Two’s Complementation
To obtain the two’s complement of five (1012):
Step 1: Invert all the bits to obtain 0102 (the “one’s complement”).
Step 2: Add one to obtain 0112, or -510 in three-bit. (The two’s complement form)
Step 3: Combine two’s complement form and the negative-weight bit. (10112)
In eight bits form: The negative-weight bit is expressed as 100000002
We’d have to determine the two’s complement based on all seven of the other bits.
510 -> 00001012 , invert all bit -> 11110102, then add one 11110112, and combine
negative-weight bit 111110112

Binary Subtraction 1111 <--- Carry bits
Subtraction: 710 - 510 0111
+ 1011
Extra bit ------
Addition equivalent: 710 + (-510)
10010
positive seven = 01112 Discard extra bit
Answer = 00102
negative five = 10112
Example: -2510 + 1810 = ?

+2510 = 0110012 (showing all six bits). One's complement of 110012 is 001102
One's complement + 1 is 001112, then two's complement is 1001112
-2510 = 1001112

Binary Subtraction
Example: -2510 + 1810 = ?
1810= 0100102
11 <--- Carry bits
100111 -2510
+010010 1810
--------
111001
Since there is no extra bit, we don’t need to discard any bit.
(1 x -3210) + (1 x 1610) + (1 x 810) + (1 x 110) = -710

Binary Multiplication
Example: Multiplication of 111012 and 10012
1 Denotes a carry over bit
Rule of Multiplication: 1 1 1 0 1
0x0=0 x 1 0 0 1
0x1=0 1
1x0=0 1 1 1 0 1
Add all the 1
1x1=0 0 0 0 0 0
partial products 1
1 0 0 0 0 0
Rule of Binary Addition:
+ 1 1 1 0 1
0+0=0
0+1=1 Final product 1 0 0 0 0 0 1 0 1
1+0=1
1 + 1 = 0 carry 1
1 + 1 + 1 = 1 carry 1
Binary Division
Example: Consider two binary numbers, B = 0110102
Rule for Binary Division: and C = 01012 where we want to divide B by C.
1
0:1=0 1 1 0 1 0 1 0 1
1:1=1 -
1 0 1 1 0 1
Division by zero is 1 1
-
meaningless 0 0
1
Rule of Binary Subtraction: - 1 1 0
0 – 1 = 1 borrow 1 1 0 1 Quotient: 1012

1 Remainder: 1
0–0=0
1–1=0 1 Denotes a bit borrowed from the
1–0=0 next more significant bit.

Chapter 4. Digital System >>3. Logic Gates
Truth Table
Describes the dependence of the logic circuit output on the logic level of inputs
A A
Q B Q
B ? ?
C A B C Q
Logic gate
0 0 0
Logic gate/circuit
0 0 1
A B Q 0 1 0
0 0 0 0 1 1
0 1 1 1 0 0
1 0 1 1 0 1
1 1 1 1 1 0
1 1 1

OR operation/ OR Gate
The output Q of a “Logic OR Gate” only returns “LOW” when ALL of its inputs are LOW.
A A
Q B Q
B C
A B C Q
Q=A+B Q=A+B+C 0 0 0 0
0 0 1 1
A B Q
0 1 0 1
0 0 0
0 1 1 1
0 1 1
1 0 0 1
1 0 1
1 0 1 1
1 1 1
1 1 0 1
“If either A or B is true, then Q is true” 1 1 1 1

OR operation/ OR Gate
B
OUT
A B Q
X=A+B
0 0 0
0 1 1
1 0 1
1 1 1

AND operation/ AND Gate
The output state of a logic AND gate returns “LOW” when ANY of its inputs are LOW.
A A
Q B Q
B
C
Q = A.B Q = A.B.C A B C Q
0 0 0 0
A B Q 0 0 1 0
0 0 0 0 1 0 0
0 1 0 0 1 1 0
1 0 0 1 0 0 0
1 1 1 1 0 1 0
1 1 0 0
“If both A and B are true, then Q is true” 1 1 1 1

AND operation/ AND Gate
B
A B Q OUT
0 0 0 X = A.B
0 1 0
1 0 0
1 1 1

NOT operation/ NOT Gate
The output from a NOT gate returns “HIGH” when its input is LOW.
A Q
A Q
0 1 Q=A
1 0
“If A is NOT true, then X is true”

A Q
0 1
1 0
OUT
Q=A
A

NOR (Not – OR) Gate
The output of a logic NOR gate only goes to logic level “0” when ANY of its inputs are at
logic level “1”.
A A
Q B Q
B C
A B Q
Q = A+B 0 0 1 Q = A+B+C
0 1 0
Logic NOR Gate Equivalent 1 0 0
1 1 0
A A+B Q = A+B
B
“If both A and B are NOT true, then Q is true”

NOR (Not – OR) Gate
A B Q
0 0 1
0 1 0
1 0 0
OUT
1 1 0
Q = A+B
A

NAND (Not – AND) Gate
The output of a logical NAND gate goes LOW when ALL of its inputs are HIGH.
A A
Q B Q
B C
A B C Q
A B Q 0 0 0 1
0 0 1 0 0 1 1
0 1 1 0 1 0 1
Q = A. B Q = A. B. C
1 0 1 0 1 1 1
1 1 0 1 0 0 1
1 0 1 1
1 1 0 1
“If both A and B are true, then Q is NOT true” 1 1 1 0

NAND (Not – AND) Gate
A B Q
0 0 1
0 1 1
1 0 1
1 1 0 OUT
Q = A. B
A

Exclusive OR (EX-OR)
A A
Q B Q
B C
A B Q A B C Q
0 0 0 Q=A⊕B Q=A⊕B⊕C 0 0 0 0
0 1 1 0 0 1 1
Equivalent equation
1 0 1 0 1 0 1
1 1 0 Q = AB + AB Q = ABC + ABC + ABC + ABC 0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Exclusive NOR (EX-NOR)
A A
Q B Q
B C
A B Q A B C Q
0 0 1 Q=A⊕B Q=A⊕B⊕C 0 0 0 1
0 1 0 0 0 1 0
Equivalent equation
1 0 0 0 1 0 0
1 1 1 Q= + B Q = ̅BC + C+ C + ABC 0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

Buffer Gate
The output from a BUFFER gate returns “HIGH” when its input is HIGH.
A Q
A Q
0 0 Q=A
1 1

Chapter 4. Digital System >>4. Boolean Algebra
Boolean Algebraic Identities
Adding Zero
Adding One

Adding a Quantity to Itself
Add a Quantity to Its Complement

Multiplying by 0 or 1
Multiplying a Quantity by Itself

Multiplying a Quantity by Its Complement

Double Complement

Boolean Algebraic Properties
The Commutative Property

The Associative Property

The Distributive Property

Boolean Rules for Simplification



Circuit Simplification Examples
1 3
2 4

Circuit Simplification Examples

Circuit Simplification Examples 1

DeMorgan’s Theorems

2
Example:

Example:

Example:

Example:

Example:

Combination Logic Circuits
Find
Give
• Combinational Logic Circuits are made up from basic logic AND, OR or NOT gates.
• The outputs of Combinational Logic Circuits are determined by the logical function
of their current input state.

Sum of Product (SOP)
The Sum of Product expression consisting purely of Minterms (minimize input) is
equivalent to the logical OR function which sums two or more products (AND function)
to produce an output. i.e. Q = A. B + A. B + . B
A B Q Minterm
0 0 0 AB
0 1 1 AB
1 0 1 AB
1 1 1 AB
To get the desired canonical SOP expression we will add the Minterms (product terms)
for which the output is 1
Let denote the following notation
AB = (00)2 = m0 A B Q Minterm
0 0 0 AB
AB = (01)2 = m1
0 1 1 AB
AB= (10)2 = m2 1 0 1 AB
AB= (11)2 = m3 1 1 1 AB
The Minterms are expressed as shorthand notation given below

Q = ∑m 1, 2, 3
Q =m +m +m
Q = AB + AB + AB
The following steps to find a combination logic circuit from a given logical equation:
Step 1. Convert this logical equation into an equivalent SOP term.
Step 2. Use a truth table to show all the possible combinations of input conditions that
will produces an output.
Step 3. Draw a logic gate diagram for the SOP expression.

Example: A logical equation is given by Sum of Product Truth Table Form
Q = A(BC + BC + BC) + ABC Inputs Output Product
Step 1. Convert this logical equation into C B A Q

0 0 0 0
an equivalent SOP term.
0 0 1 0
Q = A. B. C + A. B. C + A. B. C + A. B. C 0 1 0 1 A. B. C
= ∑m(2, 4, 6, 7) 0 1 1 0
1 0 0 1 A. B. C
Step 2. Use a truth table to show all the 1 0 1 0
possible combinations of input conditions 1 1 0 1 A. B. C
that will produces an output. 1 1 1 1 A. B. C

Example: A logical equation is given by: Sum of Product Truth Table Form
Q = A(BC + BC + BC) + ABC Inputs Output Product
Step 3. Logic Gate SOP Diagram C B A Q

0 0 0 0
0 0 1 0
0 1 0 1 A. B. C
0 1 1 0
1 0 0 1 A. B. C
1 0 1 0
1 1 0 1 A. B. C
1 1 1 1 A. B. C

Product of Sum (POS)
The Product of Sum expression consisting purely of Maxterms (sum terms) is
equivalent to the logical AND function which products two or more sums (OR function)
to produce an output. i.e. Q = (A + B)(A + B)
A B Q Maxterm
0 0 0 A + B
0 1 1 A + B
1 0 1 A+ B
1 1 0 A + B
To get the desired canonical POS expression we will multiply the maxterms (sum terms)
for which the output is 0.
Let denote the following notation
A + B = (00)2 = M0 A B Q Maxterm
A + B = (01)2 = M1 0 0 0 A + B
A + B = (10)2 = M2 0 1 1 A + B
1 0 1 A+ B
A + B = (11)2 = M3
1 1 0 A + B
The Maxterms are expressed as shorthand notation given below

Q = M0 . M3
= ∏M(0, 3)

The following steps to find a combination logic circuit from a given logical equation:
Step 1. Convert this logical equation into an equivalent POS term.
Step 2. Use a truth table to show all the possible combinations of input conditions that
will produces a “0” output.
Step 3. Draw a logic gate diagram for the POS expression.

Example: A logical equation is given by Q = A + B + C A + B + C (A + B +
C) A + B + C Inputs Output Product
C B A Q
0 0 0 0 A + B + C
0 0 1 1
0 1 0 0 A + B + C
0 1 1 1
1 0 0 1
1 0 1 0 A + B + C
1 1 0 0 A + B + C
1 1 1 1

Chapter 4. Digital System >>5. Karnaugh Mapping
Introduction
The Karnaugh map is a simplification tool applicable to digital logic.
The Karnaugh Map will simplify logic faster and more easily in most cases.
Recommended logic simplification vs number of inputs

computer
Variables Boolean algebra Karnaugh map
automated
1 -2 X ?
3 X X ?
4 ? X ?
5-6 X X
7-8 ? X
>8 X

Venn Diagrams and Sets: The Venn diagram bridges the Boolean algebra to the
Karnaugh Map.
If everything inside the circle is A, then anything outside of the circle is not A. It is a
similar manner for set B and set not B.
set A = {1,2,3,4} set A = {1,2} set A = {1,2,3,4} set A = {1,2,3,4}

set B = {5,6,7,8} set B = {1,2,3,4,5,6,7,8} set B = {1,2,3,4} set B = {3,4,5,6}

Venn Diagrams and Sets:

Sum of two sets Not of one set
Product of two sets Not of product

Karnaugh Map ̅ ≡ 0, ≡1
≡ 0, ≡1
Two variables
The boolean equation =1

is expressed in Karnaugh map.

Karnaugh Map ̅ ≡ 0, ≡1
≡ 0, ≡1
Three variables ̅ ≡ 0, ≡1

Steps to solve expression using the Karnaugh map
1. Select Karnaugh map size according to the number of variables.
2. Identify Minterms or Maxterms as given in the problem.
3. For SOP, put 1’s in cell of Karnaugh map respective to the Minterms.
4. For POS, put 0’s in cell of Karnaugh map respective to the Maxterms.
5. Make rectangular groups containing total cells in terms of 2 (except 1).
6. Find the product terms and sum them up for SOP form.

Rules for grouping adjacent cells (Step 5)
1. No zeros allowed.
2. No diagonals.
3. Only power of 2 number of cells in each group.
4. Groups should be as large as possible.
5. Everyone must be in at least one group.
6. Overlapping allowed.
7. Wrap around is allowed.
8. Get the fewest number of groups possible.

Rules for grouping adjacent cells (Step 5)

Logic Simplification With Karnaugh Maps


Chapter 4. Digital System

Chapter 4. Digital System


Don’t Care Cells in the Karnaugh Map
Don’t cares in a Karnaugh map, or truth table, may be either 1’s or 0’s.
We plot these cells with an asterisk, *, among the normal 1’s and 0’s.
Treat the don’t care cell as either a 1 or a 0, or ignore the don’t cares.

Chapter 4. Digital System >>6. Multivibrators
Flip-Flops
Flip-flops is formed by the basic building blocks called Latches.
S-R Latches
Reset ->
Output
Set ->
Invalid of illegal state

Flip-Flops
S-R Latches
Timing diagram

Flip-Flops
S-R Flip-Flops Present Inputs Present Next

State State
S-R Latches
S R Q(t) Q(t+1)
R
0 0 0 0
Q(t) 0 0 1 1
0 1 0 0
CLK 0 1 1 0
1 0 0 1
Q(t) 1 0 1 1
1 1 0 x
S
1 1 1 x

Flip-Flops
S-R Flip-Flops Present Inputs Present Next

State State
RQ(t) S R Q(t) Q(t+1)
S 00 01 10 11
0 0 0 0
0 1
0 0 1 1
1 1 1 x x S 0 1 0 0
0 1 1 0
RQ
1 0 0 1
The simplified expression for next state is 1 0 1 1
1 1 0 x
Q t + 1 = S + RQ(t)
1 1 1 x

Flip-Flops
D Flip-Flops
D Q(t+1)
S-R Latches
0 0
1 1
Q(t)
Q(t+1) = D
CLK
Q(t)
D
Flip-Flops
D Flip-Flops
D Q(t+1)
0 0
Timing diagram
1 1
Q(t+1) = D

Flip-Flops
JK Flip-Flops
Present Inputs Present Next
State State
S-R Latches
J K Q(t) Q(t+1)
K 0 0 0 0
Q(t)
0 0 1 1
0 1 0 0
0 1 1 0
CLK
1 0 0 1
1 0 1 1
Q(t)
J 1 1 0 1
1 1 1 0

Flip-Flops
JK Flip-Flops
State State
J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Flip-Flops
JK Flip-Flops
State State
KQ(t)
J 00 01 10 11 J K Q(t) Q(t+1)
0 0 0 0
0 1
0 0 1 1
1 1 1 1 JQ(t) 0 1 0 0
0 1 1 0
KQ(t)
1 0 0 1
1 0 1 1
Q(t + 1) = JQ(t) + KQ(t) 1 1 0 1
1 1 1 0

Flip-Flops
T Flip-Flop
S-R Latches
Inputs Present Next
State State
Q(t)
T Q(t) Q(t+1)
0 0 0
CLK 0 1 1
1 0 1
Q(t) 1 1 0
T

Flip-Flops
T Flip-Flop
Clock Inputs Present Next

State State
T Q(t) Q(t+1)
T
0 0 0
0 1 1
Q
1 0 1
1 1 0
Q(t + 1) = TQ(t) + TQ(t)
⇒ Q t + 1 = T⨁Q(t)
Chapter 4. Digital System >>7. Sequential Circuits
Binary Count Sequence
J-K flip-flops are ideally suited for this task, because they have the ability to “toggle”
their output state at the command of a clock pulse when both J and K inputs are made
“high”.

Binary Count Sequence
J-K flip-flops are ideally suited for this task, because they have the ability to “toggle”
their output state at the command of a clock pulse when both J and K inputs are made
“high”.

Asynchronous Counters
Four-bit “Up” Counter

Simultaneous “Up” and “Down” Counter

Simultaneous “Up” and “Down” Counter

Synchronous Counters



Counter with encoder
Chapter 4. Digital System >>8. Exercises
Exercise 1: Simplification of the logic expression by Boolean Algebra and K-map.
, , = (3, 6, 7)
Truth Table
Input Output
Decimal equivalent Product
A B C Y
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
= + ̅ + ABC
= + ̅+ + ABC Applying + =
= + ̅ + + ̅ Applying + ̅=1
= +
Karnaugh map – 3 variables
AB
00 01 11 10
C
, , = (1,2,3,6)
Truth Table
Input Output
Decimal equivalent Product
A B C Y
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
Boolean Algebra
= ̅BC + ABC + ABC + ABC
Applying + = = ̅BC + ABC + ABC + ABC + ABC + ABC
Applying + ̅=1 = ̅C B + B + AB C + C + BC(A + A)
= ̅C + AB + BC
Is this expression simplified?

AB
00 01 11 10
C
Simplified expression:
=
Exercise 3: Simplification of the logic expression by K-map

Y=A'B'C' D'+A' B' CD'+A' BCD'+A' BCD+AB' C' D'+ABCD'+ABCD
CD
00 01 11 10
AB
00
01
11
10
=
Exercise 4: Simplification of the logic expression by K-map
Y = (A’+B’)(A’+B)(A+B)
B
0 1
A
Simplified expression: 1
=
Input Decimal Output
Exercise 5: Simplification of the logic equivalent
Sum
A B C D Y
expression by K-map. 0 0 0 0 0
0 0 0 1 1
F(A,B,C,D)=∏ (3,5,7,8,10,11,12,13) 0 0 1 0 2
0 0 1 1 3
AB 0 1 0 0 4
00 01 11 10
0 1 0 1 5
CD
0 1 1 0 6
00 0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
01
1 0 1 0 10
1 0 1 1 11
11 1 1 0 0 12
1 1 0 1 13
10 1 1 1 0 14
1 1 1 1 15
Exercise 5: Simplification of the logic expression by K-map.
F(A,B,C,D)=∏ (3,5,7,8,10,11,12,13)
Karnaugh map – 4 variables AB

00 01 11 10
CD
00 1 1 0 0
01 1 0 0 1
11 0 0 1 0
10 1 1 1 0
=
Exercise 6: Design a digital system whose output is defined as logically low if the 4-bit
input binary number is a multiple of 3; otherwise, the output will be logically high. The
output is defined if and only if the input binary number is greater than 2.
Exercise 6 Truth Table Input Decimal
Product
Output
A B C D equivalent Y
Minterm: 0 0 0 0 0
0 0 0 1 1
= ( ) 0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
+ ( ) 0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
Maxterm:
1 0 0 0 8
= ( ) 1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
+ ( ) 1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
Exercise 6 Truth Table Input Decimal
Product
Output
A B C D equivalent Y
0 0 0 0 0 x
Karnaugh map – 4 variables 0 0 0 1 1 x
0 0 1 0 2 x
0 0 1 1 3 0
CD 0 1 0 0 4 1
00 01 11 10
0 1 0 1 5 1
AB
0 1 1 0 6 0
00 0 1 1 1 7 1
1 0 0 0 8 1
1 0 0 1 9 0
01
1 0 1 0 10 1
1 0 1 1 11 1
11 1 1 0 0 12 0
1 1 0 1 13 1
10 1 1 1 0 14 1
1 1 1 1 15 0
Exercise 6 Grouping
CD CD
00 01 11 10 00 01 11 10
AB AB
00 X X 0 X 00 X X 0 X
01 1 1 1 0 01 1 1 1 0
11 0 1 0 1 11 0 1 0 1
10 1 0 1 1 10 1 0 1 1
SOP POS
Exercise 6 Grouping
CD CD
00 01 11 10 00 01 11 10
AB AB
00 X X 0 X 00 X X 0 X
01 1 1 1 0 01 1 1 1 0
11 0 1 0 1 11 0 1 0 1
10 1 0 1 1 10 1 0 1 1
SOP POS
Exercise 6
Exercise 6

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Electrical and Electronic Equipment for

Analog signal Digital signal

HCM City Univ. of Technology, Faculty of Mechanical Engineering 2 Duong Van Tu

Analog signal Digital signal

An analog signal is a time-varying A digital signal is a time separated signal.

HCM City Univ. of Technology, Faculty of Mechanical Engineering 3 Duong Van Tu

Analog signal Digital signal

HCM City Univ. of Technology, Faculty of Mechanical Engineering 4 Duong Van Tu

Acceptable TTL Gate Input Acceptable TTL Gate

HCM City Univ. of Technology, Faculty of Mechanical Engineering 5 Duong Van Tu

Acceptable CMOS Gate Acceptable CMOS Gate

HCM City Univ. of Technology, Faculty of Mechanical Engineering 6 Duong Van Tu

System Base Symbol Example

HCM City Univ. of Technology, Faculty of Mechanical Engineering 7 Duong Van Tu

102 101 100 . 10-1 10-2 10-3

Most Significant Decimal point Least Significant

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MSB 8 bit = 1 byte LSB

Binary Number to Decimal Number

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27 26 25 24 23 22 21 20 . 2-1 2-2 2-3

Binary Number to Decimal Number Binary point

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Octal Number to Binary Number

52.1728= 5 × 8 + 2 × 8 + 1 × 8 +7×8 +2×8 = 40 + 2 + 1 ×

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Hexadecimal Number to Binary Number

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01012 = 510 (positive number)

11012 = -510 (negative number) However it can also be thirteen (13)

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In eight bits form: The negative-weight bit is expressed as 100000002

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Example: -2510 + 1810 = ?

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0 – 1 = 1 borrow 1 1 0 1 Quotient: 1012

1–0=0 next more significant bit.

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“If A is NOT true, then X is true”

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“If both A and B are NOT true, then Q is true”

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Add a Quantity to Its Complement

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Multiplying a Quantity by Itself

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