CD4071BMS, CD4072BMS

CD4075BMS
December 1992 CMOS OR Gate

Features Pinout
• High-Voltage Types (20V Rating) CD4071BMS
TOP VIEW
• CD4071BMS Quad 2-Input OR Gate
• CD4072BMS Dual 4-Input OR Gate
A 1 14 VDD
• CD4075BMS Triple 3-Input OR Gate
B 2 13 H
• Medium Speed Operation:
J=A+B 3 12 G
- tPHL, tPLH = 60ns (typ) at 10V
K=C+C 4 11 M = G + H
• 100% Tested for Quiescent Current at 20V
C 5 10 L = E + F
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC D 6 9 F

VSS 7 8 E
• Standardized Symmetrical Output Characteristics
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V CD4072BMS
- 2V at VDD = 10V TOP VIEW
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings J=A+B+C+D 1 14 VDD

• Meets All Requirements of JEDEC Tentative Standard A 2 13 K = E +F + G + H

No. 13B, “Standard Specifications for Description of B 3 12 H
‘B’ Series CMOS Devices”
C 4 11 G

Description D 5 10 F

NC 6 9 E
CD4071BMS, CD4072BMS and CD4075BMS OR gates pro-
vide the system designer with direct implementation of the VSS 7 8 NC
positive-logic OR function and supplement the existing fam-
ily of CMOS gates. NC = NO CONNECTION

The CD4071BMS, CD4072BMS and CD4075BMS are supplied CD4075BMS

in these 14 lead outline packages: TOP VIEW
Braze Seal DIP *H4H †H4Q
Frit Seal DIP H1B
A 1 14 VDD
Ceramic Flatpack H3W B 2 13 G
*CD4071, CD4072 †CD4075 Only D 3 12 H

E 4 11 I

F 5 10 L = G + H + I

K=D+E+F 6 9 J=A+B+C

VSS 7 8 C

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3323
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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 CD4071BMS, CD4072BMS, CD4075BMS

Functional Diagram

VDD
14

1 3
B
2 J
A
5 4
D
6 K
C
8 10
F
9 L
E
12 11
H
13 M
G

7
VSS

CD4071BMS

VDD
14

2
A
3
B 1
4 J
C
5
D
9
E
10
F 13
11 K
G
12
H

7
VSS

CD4072BMS

VDD
14
1
C
2 9
B J
8
A
3
F
4 6
E K
5
D
11
I
12 10
H L
13
G
7
VSS

CD4075BMS

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 Specifications CD4071BMS, CD4072BMS, CD4075BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125 C o

Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A LIMITS
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 0.5 µA
2 +125oC - 50 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 0.5 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25o C -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD = 20V, VIN = VDD or GND 7 +25oC VDD/2 VDD/2

VDD = 18V, VIN = VDD or GND 8A +125oC

VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs.

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 Specifications CD4071BMS, CD4072BMS, CD4075BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTES 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL VDD = 5V, VIN = VDD or GND 9 +25oC - 250 ns
TPLH
10, 11 +125oC, -55oC - 338 ns
Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTLH
10, 11 +125oC, -55oC - 270 ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.25 µA
+125 C o
- 7.5 µA
VDD = 10V, VIN = VDD or GND 1, 2 o
-55 C, +25 C o
- 0.5 µA
+125oC - 15 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.5 µA
+125 oC - 30 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 4.95 - V
-55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 9.95 - V
-55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -2.6 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - 3 V
-55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, 7 - V
-55oC
Propagation Delay TPHL VDD = 10V 1, 2, 3 +25oC - 120 ns
TPLH
VDD = 15V 1, 2, 3 +25oC - 90 ns

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 Specifications CD4071BMS, CD4072BMS, CD4075BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Transition Time TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns
TTLH o
VDD = 15V 1, 2, 3 +25 C - 80 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 o
+25 C - 2.5 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - SSI IDD ±0.1µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11

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 Specifications CD4071BMS, CD4072BMS, CD4075BMS

TABLE 6. APPLICABLE SUBGROUPS (Continued)

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
PART NUMBER CD4071BMS
Static Burn-In 1 3, 4, 10, 11 1, 2, 5 - 9, 12 - 13 14
Note 1
Static Burn-In 2 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9,
Note 1 12 - 14
Dynamic Burn- - 7 14 3, 4, 10, 11 1, 2, 5, 6, 8, 9, 12,
In Note 1 13
Irradiation 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9,
Note 2 12 - 14
PART NUMBER CD4072BMS
Static Burn-In 1 1, 6, 8, 13 2 - 5, 7, 9 - 12 14
Note 1
Static Burn-In 2 1, 6, 8, 13 7 2 - 5, 9 - 12, 14
Note 1
Dynamic Burn- 6, 8 7 14 1, 13 2 - 5, 9 - 12
In Note 1
Irradiation 1, 6, 8, 13 7 2 - 5, 9 - 12, 14
Note 2
PART NUMBER CD4075BMS
Static Burn-In 1 6, 9, 10 1 - 5, 7, 8, 11 - 13 14
Note 1
Static Burn-In 2 6, 9, 10 7 1 - 5, 8, 11 - 14
Note 1
Dynamic Burn- - 7 14 6, 9, 10 1 - 5, 8, 11 - 13
In Note 1
Irradiation 6, 9, 10 7 1 - 5, 8, 11 - 14
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

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 CD4071BMS, CD4072BMS, CD4075BMS
VDD
14

p p p p
* p

1 (6, 8, 13) 3 (4, 10, 11) VDD

n n n n

p n
* VSS

2 (5,9, 12) n * ALL INPUTS PROTECTED BY

CMOS PROTECTION NETWORK
7
VSS

FIGURE 1. SCHEMATIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES)

B
1 (6, 8, 13)
J

A 3 (4, 10, 11)

2 (5, 9, 12)

FIGURE 2. LOGIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES)

VDD VDD

INV.1** p
p p
VDD VDD
n
p p
* p
2 (12) 1 (13)
n
n n n
n

VSS VSS VSS

VDD VSS
p
p
*
3 (11) INV 2**
VDD
n
*
5 (9) INV 3**
n
*
4 (10) INV 4** VSS

VSS * ALL INPUTS PROTECTED BY

** INVERTERS 2, 3 AND 4 ARE IDENTICAL TO INVERTER 1. CMOS PROTECTION NETWORK

FIGURE 3. SCHEMATIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)

A
2 (12)

B
3 (11) J

D
1 (13)
5 (9)

C
4 (10)

FIGURE 4. LOGIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)

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 CD4071BMS, CD4072BMS, CD4075BMS

VDD
14

p p p
n p p
p
9 (6, 10)
* n n n
8 (5, 13)
n
p n
*
2 (4, 12)
n VDD
p
n
*
1 (3, 11)
n

VSS

* ALL INPUTS PROTECTED BY

CMOS PROTECTION NETWORK
7
VSS

FIGURE 5. SCHEMATIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)

A
1 (3, 11)

B J
2 (4, 12)
9 (6, 10)
C
8 (5, 13)

FIGURE 6. LOGIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)

Typical Performance Characteristics

20 200
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

SUPPLY VOLTAGE (VDD) = 15V

OUTPUT VOLTAGE (VO) (V)

150
15
SUPPLY VOLTAGE (VDD) = 5V

10V
10 100

5V
5 50 10V
15V

0 5 10 15 20 0 20 40 60 80
INPUT VOLTAGE (VIN) (V) LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERIS- FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
TICS FUNCTION OF LOAD CAPACITANCE

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 CD4071BMS, CD4072BMS, CD4075BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 9. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 10. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15 -10 -5 0 -15 -10 -5 0
0 0
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10 -5

-15

-10V -10V
-20 -10

-25

-15V -15V
-30 -15

FIGURE 11. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 12. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS

105 AMBIENT TEMPERATURE (TA) = +25oC

8
POWER DISSIPATION PER GATE (PD) (µW)

o
AMBIENT TEMPERATURE (TA) = +25 C 6
4
TRANSITION TIME (tTHL, tTLH) (ns)

2 SUPPLY VOLTAGE (VDD) = 15V

104 10V
8 10V
200 6
4 5V
2
SUPPLY VOLTAGE (VDD) = 5V 103
150
8
6
4
100 2
10V 102
8
15V 6
50 4 CL = 50pF
2 CL = 15pF
10
0 2 4 68 2 4 6 8 2 4 6 8 2 4 6 8
0 20 40 60 80 100
1 10 102 103 104
LOAD CAPACITANCE (CL) (pF)
INPUT FREQUENCY (fI) (kHz)
FIGURE 13. TYPICAL TRANSITION TIME AS A FUNCTION OF FIGURE 14. TYPICAL DYNAMIC POWER DISSIPATIONAS A
LOAD CAPACITANCE FUNCTION OF FREQUENCY

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 CD4071BMS, CD4072BMS, CD4075BMS

Chip Dimensions and Pad Layouts

CD4071BMS CD4072BMS

CD4075BMS
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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