1._____________________ gives relationship between input and output.
[ ]
a)assignment operator b)architecture c)Entity d)none
2.______________________gives list of signals used in design. [ ]
a)assignment operator b)architecture c)Entity d)none
3.Logic High levels for CMOS_____________________ [ ]
a)0-1.5V b)0-5V c)3.5V-5V d)0-3.5V
4.Logic Low levels for CMOS___________________________ [ ]
a)0-1.5V b)0-5V c)3.5V-5V d)0-3.5V
5.The power consumption of CMOS circuit at Steady condition is known as________[ ]
a) Static power dissipation b) Dynamic power dissipation
c)Leakage d)Output power
6. The power consumption of CMOS circuit during transition is known as_______ [ ]
a) Static power dissipation b) Dynamic power dissipation
c) Leakage d)Output power
7.The propagation delay is less in_____________ [ ]
a)TTL b)CMOS c)ECL d)DTL
8.The power dissipation per gate less in_________ [ ]
a)TTL b)CMOS c)ECL d)DTL
9.High level nose margin in CMOS is defined as _________ [ ]
a)VOH-VIH b)VIL-VOL c)VOH-VOL d)VIH-VIL
10.Low level nose margin in CMOS is defined as _________ [ ]
a)VOH-VIH b)VIL-VOL c)VOH-VOL d)VIH-VIL
I. Fill in the blanks.
11.Abbrivate VHDL__________________________________
12. Abbrivate CMOS_________________________
13. CMOS is a combination of _____________________and
___________________Transistors.
14.CMOS is a _____________________controlled device(Current/Voltage).
15. ECL is also called as_____________________________.
16. TTL is a Voltage controlled device(TRUE/FALSE)
17. The power consumption during transition is given by PT=__________________.
18. The TTL has high Fan Out driving scapability (TRUE/FALSE)
19. A VHDL architecture that uses components is called as____________________model
20.A VHDL architecture that uses Process Statement is called
as__________________model.
1. The power consumption of CMOS circuit during transition is known as_______[ ]
a) Static power dissipation b) Dynamic power dissipation
c) Leakage d)Output power
2.The propagation delay is less in_____________ [ ]
a)TTL b)CMOS c)ECL d)DTL
3.The power dissipation per gate less in_________ [ ]
a)TTL b)CMOS c)ECL d)DTL
4.High level nose margin in CMOS is defined as _________ [ ]
a)VOH-VIH b)VIL-VOL c)VOH-VOL d)VIH-VIL
5.Low level nose margin in CMOS is defined as _________ [ ]
a)VOH-VIH b)VIL-VOL c)VOH-VOL d)VIH-VIL
6._____________________ gives relationship between input and output. [ ]
a)Assignment operator b)architecture c)Entity d)none
7.______________________gives list of signals used in design. [ ]
a)assignment operator b)architecture c)Entity d)none
8.Logic High levels for CMOS_____________________ [ ]
a)0-1.5V b)0-5V c)3.5V-5V d)0-3.5V
9.Logic Low levels for CMOS___________________________ [ ]
a)0-1.5V b)0-5V c)3.5V-5V d)0-3.5V
10.The power consumption of CMOS circuit at Steady State condition is known as[ ]
a) Static power dissipation b) Dynamic power dissipation
c)Leakage d)Output power
I. Fill in the blanks.
11. Static power dissipation is also called as_______________
12. The power consumption during transition is given by PT=__________________
13. The total Dynamic power of a CMOS PD=_____________________
14. A VHDL architecture that uses components is called as___________________model
15. TTL is a Voltage controlled device(TRUE/FALSE).
16.Expand VHDL__________________________________
17. Expand CMOS___________________________
18. CMOS is a combination of _____________________and
___________________Transistors.
19.CMOS is a _____________________controlled device.
20. ECL is also called as_____________________________
