Execution of a Complete Instruction

• Add (R3), R1
• Fetch the instruction
• Fetch the first operand (the contents of the
memory location pointed to by R3)
• Perform the addition
• Load the result into R1

16
 Architectur e R
iin I nternal processor
bus
R
i

R
iout
Y in

Constant 4

Select
M
U
X
A B
ALU

Z
in

Eigure 7.². Input and output gating £or the registers in Eigure 7.1.
Z 17
out
 Execution of a Complete Instruction
Internal processor
bus

Add (R3), R1 Control signals

PC
Step Action Instructio
Address n decoder
lines
and
1 PCout , MAR in , Read, Select4,Add, Zin M
control
Memory
2 Zout , PCin , Yin , WMF C bus

3 MDR out , IRin Data

lines M
4 R3out , MAR in , Read I

5 R1out , Yin , WMF C Y

Constant 4 R0
6 MDR out , SelectY, Add, Zin
7 Zout , R1in , End Select MUX

Add
A B
ALU Sub R n - 1
control ALU
lines

Figure 7.6. Control sequencefor execution of the instruction Add (R3),RXO1R. Carry-in
TEMP

Z
Add R2, R1 ?

18
Figure 7.1. Single-bus organization of the datapath inside a proc