Stanford University

EE 218: Introduction to Nanotechnology and

Nanoelectronics

H.-S. Philip Wong

Professor of Electrical Engineering
Stanford University, Stanford, California, U.S.A.
hspwong@stanford.edu
http://www.stanford.edu/~hspwong

Center for Integrated Systems EE 218 Department of Electrical Engineering

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What is Nanotechnology?

Source: Apple Computer, Inc.

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The Beginning of Nano Source: IBM

Source: IBM

Invention of the
Scanning Tunneling Gerd Binnig, Heinrich Rohrer
Microscope (STM)
Nobel Prize, 1986
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Source: IBM

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Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.

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 The Scale of Things -- Nanometers and More
Source: NSF website
Things Natural Things Manmade

Nanotechnology Progress Generating New Excitement

10-2 m 1 cm Source: J. Sphorer (IBM)
10 mm

Head of a pin 21st Century

1-2 mm Challenge
1,000,000 nanometers =
Ant 10-3 m 1 millimeter (mm)
~ 5 mm
MicroElectroMechanical Devices
Dust mite 10 -100 µm wide
200 µm 10-4 m
0.1 mm
100 µm

The Microworld
Fly ash
Human hair ~ 10-20 µm
~ 10-50 µm wide
0.01 mm
O
P

10-5 m
O O

10 µm O O O O

O O O O O O O O

Red blood cells

O O O O O O O O

with white cell

S S S S S S S S

~ 2-5 µm 1,000 nanometers =

10-6 m 1 micrometer (µm) Red blood cells
Pollen grain
spectrum
Visible

Combine nanoscale
10-7 m 0.1 µm building blocks to make
100 nm functional devices, e.g.,
The Nanoworld

a photosynthetic
reaction center with
integral semiconductor
storage
10-8 m 0.01 µm
Nanotube electrode Nanotube transistor
10 nm
~10 nm diameter
ATP synthase

10-9 m 1 nanometer (nm)

DNA 6
~2-1/2 nm diameter 10-10 m 0.1 nm Quantum corral of 48 iron atoms on copper surface Carbon nanotube
Atoms of silicon positioned one at a time with an STM tip ~2 nm diameter
spacing ~tenths of nm
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US Nanotechnology Funding

Source: M. Roco, NNI (10/29/2003).

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NNI Funding by Agency

Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.

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Global Nanotechnology Investment

Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.

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Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.

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Source: M. Roco, NNI (10/29/2003).

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Source: M. Roco (NNI), National Research Council, Washington, D.C., March 23, 2005

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Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.
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http://www.research.ibm.com/pics/nanotech/

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Questions?

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An 8 nm Transistor Gate

Gate

Source Drain

Lgate=8 nm
Source: IBM

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Atoms are starting to look big

Source: IBM

ƒWhen one atom high “bumps” look significant in a

photo of your transistors, both their manufacture and
behavior are “exciting”

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Integrated Circuit Complexity

Source: G. Moore, Intel (2003)

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Source: K. David (Intel)

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Source: K. David (Intel)

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State-of-the-Art Technology

90 nm technology

65 nm technology

Source: M. Bohr,
Intel (2004)

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A view from Intel

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Time Horizon Blue Sky

2004 2007 2010 2013 2016 2020

Physical Gate 37 nm 25 nm 18 nm 13 nm 9 nm 6 nm

Ultrathin SOI High k gate dielectric Double-Gate CMOS FinFET

Strained Si, Ge, SiGe
doped channel
raised source/drain Strained Si, Ge, SiGe top-gate
channel
Gate

halo
buried oxide
depletion layer
buried oxide channel
back-gate
isolation isolation isolation
Silicon Substrate Silicon Substrate buried oxide
Source Drain

Evolutionary Revolutionary

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Poly-silicon

Future Si Devices Tox=16A

Gate Tsi=7 nm
Source
H. Shang et al.,
IEDM 2002
Gate

Drain
Source
NiSi Gate
NiSi

Drain B. Doris et al., IEDM 2002

Si Tox = 1.6nm
J. Kedzierski et al., IEDM Fin
2001 , IEDM 2002
Tsi = 25nm
K. Rim et al., IEDM 2003
Si

BOX

W CoSi2 on
RSD Strained
silicon
HfO2 60nm
SiO2
SiGe
Si Buried
oxide
M. Yang et al., IEDM 2003 B. Lee et al., IEDM 2002
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Innovation Overtakes Scaling in Driving Performance

ƒ Innovation (invention) will increasingly dominate performance gains
– Scheduled "invention" is now the majority component in all plans
• Risk has increased significantly
IBM Transistor Perform ance Im prov em ent
Gain by Traditional S caling Gain by Innovation
100

80
Relative % Improvement

60

40
500 nm

90 nm
130 nm
180 nm
250 nm

65 nm
350 nm

20

0
CMOS5X

CMOS6X

CMOS7S-SOI

CMOS8S2

CMOS9S

CMOS10S

CMOS11S
Source: IBM

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Straight Line Projections Can Be Wrong…

Source:
G. Moore, Intel (2003)

Therefore, we need to focus on the fundamentals

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To Learn More About Si Technology…

ƒ EE 212 – Fabrication technology (J. Plummer)

ƒ EE 316 – Si CMOS device (H.-S. P. Wong)
ƒ EE 311 – Device technology (K. Saraswat)
ƒ EE 309 – Semiconductor memory (H.-S. P. Wong)
ƒ EE 410 – Fabrication lab (K. Saraswat)

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Questions?

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Several distinct technologies have been used to

implement complex logic We are here !
$1000 buys...
1.E+12
Pentium 4 PC
Vacuum tube
Additions per second

1.E+09 Discrete transistor

Integrated circuit IBM PC

1.E+06
DEC PDP-8

1.E+03
ENIAC

1.E+00

1.E-03
1940 1950 1960 1970 1980 1990 2000 2010 2020
Data from R. Kurzweil, 1999,
The Age of Spiritual Machines Year Source: IBM

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Gestation for Technologies

Solid State Diode
Example: Solid State Rectifier T1 26 (1874-1900)
5 T2 7 (1900-1907)
Market production (Established T3 6 (1907-1913)
Learning Period 13 years
Development Level

Technology)
4
Commercialization:
Vacuum Tube
3 1907 (Entrant)
T1 20 (1884-1904)
Prototype built 1900 T2 9 (1904-1913)
2 (Braun) ‘Research Curve’ T3 6 (1913-1919)
Background/Infrastructure: T2 T3 Learning Period 15 years
1874 (Braun)
1
Transistor
T1~ 20years T1 25 (1923-1948)
0 T2 6 (1948-1954)
T3 5 (1954-1959)
1870 1880 1890 1900 1910 1920 1930 Learning period 11years
~10years
Integrated Circuit
T1 17 (1942-1959)
• To be ready for 2016 - start now narrowing T2 3 (1959-1961)
T3 5(1961-1966)
down options Learning Period 8 years
After Ralph Cavin, SRC

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International Technology Roadmap for Semiconductors

ƒ The International Technology Roadmap for Semiconductors (ITRS)

is an assessment of the semiconductor technology requirements.
The objective of the ITRS is to ensure advancements in the
performance of integrated circuits. This assessment, called
roadmapping, is a cooperative effort of the global industry
manufacturers and suppliers, government organizations, consortia,
and universities.
ƒ The ITRS identifies the technological challenges and needs facing
the semiconductor industry over the next 15 years. It is sponsored
by the European Semiconductor Industry Association (ESIA), the
Japan Electronics and Information Technology Industries
Association (JEITA), the Korean Semiconductor Industry
Association (KSIA), the Semiconductor Industry Association (SIA),
and Taiwan Semiconductor Industry Association (TSIA).
International SEMATECH is the global communication center for
this activity. The ITRS team at International SEMATECH also
coordinates the USA region events.

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Source: ITRS, J. Hutchby

Emerging Research Logic Devices
2003 ITRS PIDS/ERD Chapter

Device Resonant
1D Spin
FET RSFQ Tunneling SET Molecular QCA
structures transistor
Devices
Not
Cell Size 100 nm 0.3 µm 100 nm 100 nm 40 nm 60 nm 100 nm
known
Density
3E9 1E6 3E9 3E9 6E10 1E12 3E10 3E9
(cm-2)
Switch 700 GH Not Not
1.2 THz 1 THz 1 GHz 30 MHz 700 GHz
Speed z known known
Circuit 250–
30 GHz 30 GHz 30 GHz 1 GHz <1 MHz 1 MHz 30 GHz
Speed 800 GHz
Switching
2×10–18 >1.4×10–17 2×10–18 >2×10–18 >1.5×10–17 1.3×10–16 >1×10–18 2×10–18
Energy, J
Binary
Throughput, 86 0.4 86 86 10 N/A 0.06 86
2
GBit/ns/cm

http://public.itrs.net
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Source: ITRS, J. Hutchby

Emerging Research Memory Devices
2003 ITRS PIDS/ERD Chapter

Nano- Single/Few Insulator

Phase Floating
Present Day Baseline floating Electron Resistance Molecular
Change Body
Technologies Gate Memories* Change Memories**
Memory* DRAM
Memory** * Memory**
Storage
Mechanism

Engineered Bi-stable
Device NOR 1TDRAM tunnel MIM switch
DRAM OUM SET
Types Flash eDRAM barrier or oxides Molecular
nanocrystal NEMS

Availability 2004 2004 ~2006 ~2006 ~2006 >2007 ~2010 >2010

Cell
1T1C 1T 1T1R 1T 1T 1T 1T1R 1T1R
Elements

http://public.itrs.net
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Source: M. Roco (NNI), Nanotechnology Research Directions II, September 8, 2004.

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Nano Cosmetics

36 H.-S. Philip Wong EE 218 Department of Electrical Engineering

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Nano Skin Care Products

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Questions?

38 H.-S. Philip Wong EE 218 Department of Electrical Engineering