Description

APZ 212 25
Contents
1 Introduction..............................................................................................................................................
1.1 Three of the new features of high calibre...........................................................................................................
2 Overall system description.......................................................................................................................
3 APZ 212 25 Hardware structure...............................................................................................................
4 The central processor APZ 212 25...........................................................................................................
5 Technical data...........................................................................................................................................
6 Abbreviations...........................................................................................................................................

UAB/O-96:723 Rev C 97-05-28 © Ericsson. Commercial in confidence

Description 2 (8)

This page is intentionally left blank

© Ericsson. Commercial in confidence Rev C 97-05-28 UAB/O-96:723

 Description 3 (8)

1 Introduction
The APZ 212 25 is a small, very powerful central processor for the AXE system. It is a further
development of the APZ 212 20 and has most of its characteristics in common with that one.
Both processors are part of the fourth generation central processors in the AXE system.

While requiring only half a subrack in the new equipment practice BYB 501, it has a relative
capacity of 1.5 to 1.7 times or more compared to its much bigger predecessor, the APZ 212 11.
Yet it uses only one tenth of the power consumed in a 212 11. This is made possible through the
introduction of 3.3 volt technology.

With the reduced size follows a substantial reduction in the number of board types, so that the
APZ 212 25 today only contains five boards of different type.

Built for BYB 501 and intended for the serial regional processor bus - RPB-S, the APZ 212 25
is fully compatible with the parallel bus used in earlier versions of AXE switching equipment.

APZ 212 20 in two BYB 202 cabinets APZ 212 25 in a

BYB 501 cabinet
CP-A CP-B
CP-A & CP-B

1 5 10 15 20 25 30 1 5 1 5 10 15 20 25 30

1 5 10 1 5 10 1 5 10 1 5 10 1 5 10 1 5 10 1 5 10 1 5 10
BM 6 12 18 BM 6 12 18

Fig 1. An APZ 212 20 housed in two BYB 202 cabinets measuring 1200 x

400 x 2200 mm each. To the right a single cabinet BYB 501 with an APZ 212 25 occupying half a
subrack. The cabinet measures 600 x 400 x 1800 mm.

UAB/O-96:723 Rev C 97-05-28 © Ericsson. Commercial in confidence

Description 4 (8)

1.1 Three of the new features of high calibre

 Chargeable microprogram.
 This makes handling and maintenance much easier and faster compared to previous methods.
 HW identification with uniquely numbered boards.
 Facilitates remote identification of a single board. This feature is prepared in HW, but SW
will be implemented in a later release.
 Indication for HW maintenance is introduced.
 A light emitting diode - LED - indicates a faulty board. This feature is prepared in HW, but
SW will be implemented in a later release.

2 Overall system description

The central processor is duplicated, with both sides operating in parallel synchronous mode.
Hardware faults can be detected immediately by comparing both sides. If a fault occurs, the
maintenance unit automatically isolates the faulty side and hands over traffic handling
responsibility to the other side. This process is very fast. In the vast majority of cases, hardware
recovery does not effect overall operation in any way.

Each processor side has two processing parts : a signal processing unit, which handles program
inter work and job control, and an instruction processing unit, entirely dedicated to program
execution. Information in the reference store is used for addressing programs and data. The
instruction processing unit has separate access ways to the program and data stores - each bus is
32 bits wide.

Just like all previous central processors the APZ 212 25 is a double sided processor running A-
and B-sides in parallel. It is designed for operation with the newly developed serial regional
processor bus - RPB - S. The processor can in a BSC setting drive 128 RPs from in one
subrack.. Extensions to 256 or even 512 RPs are well within reach for this processor’s capacity.

Switching equipment

RP RP RP RP RP

CP IO

Fig. 2 Schematic view of the APZ’s position in the AXE system

© Ericsson. Commercial in confidence Rev C 97-05-28 UAB/O-96:723

 Description 5 (8)

3 APZ 212 25 Hardware structure

STUD STUD
M CC M CC

IPU MAU IPU

ACC ACC
CPC CPC

UM C UM C

M CC M CC

SPU SPU
SPC SPC

RPH-S RPH-S

Fig 3. The APZ 212 25 shown with the identical A - and B - sides connected by the maintenance board,
the MAU.

UAB/O-96:723 Rev C 97-05-28 © Ericsson. Commercial in confidence

Description 6 (8)

4 The central processor APZ 212 25

RPH-S

RPH-S
STUD
STUD

not used

MAU
SPU

SPU
IPU
MIA
IPU
MI A M IA M IA MIA MI A M IA MIA
MI A

OFF OFF O FF EX OFF OFF

L TE ST EX L TE ST

WO M ANOFF
MAN OFF PHCI WO MANOFF PHCI

UP
PHCI UP PHCI
HA
FEX HA FE X
SE
SE
P EB

MIT
M IT
RP B-S MI T DEBUG MI T RPB-S
3 3

RP B-S FAN RPB-S

2 2

RP B-S RPB-S
POU P OU P OU
1 1
OFF OFF OFF

RPB-S -48V CDU PTB CDU -48V RP B-S

0 0

CP - A CP - B

Fig.4 The central processor APZ 212 25 showing side A and B. Note that the fifth board from the left is
a non active board. Apart from the MAU, which is a common board the two sides are identical. The LED
for “manual intervention allowed” - MIA - is a new feature on all boards.

The introduction of the serial RP bus made it possible to reduce volume by a ratio of 1 : 50
compared to the parallel bus.

The reduction of physical volume in it self facilitates significant reduction in the number of
necessary drivers and associated cabling.

New ASIC technology - 3.3 volt instead of 5 volt - allows much higher density packing
compared to earlier technology.

Initially the APZ 212 25 will only come in one version with a fully extended memory.

To fulfill EMC class B standard is necessary to stay competitive.

© Ericsson. Commercial in confidence Rev C 97-05-28 UAB/O-96:723

 Description 7 (8)

Compatibility
APZ 212 25 is fully compatible with all applications (APT)

Operator interfaces
 CP HW fault management
 Function change
 CP load measurement

Common subsystems
RPS - B, -1, -2, -M, DBS, OCS

SPS, FMS, DCS, MCS

Common reference packages

APZ 212 20/2, IOG 11B/B5, IOG 11C/C5, IOG 20

5 Technical data
 APZ 212 25 is a single processor with two identical sides running in parallel at all times, one
in operation and one as a back up.
 Built for BYB 501 ; requires ½ subrack for the whole processor.
 Fulfils all EMC class B standards
 Clock frequency 20MHz
 3.3 volt design with electrical connectors only
 Number of board types : 5
 Power consumption : 75 W
 Capacity : 1.5 to 1.7 times the APZ 212 11
 Program storage : 64 MW
 Data storage : 256 MW
 Physical data : height 300mm, depth 220mm, width 210mm, weight 8 kg.

6 Abbreviations
ACC Address calculation circuit

BSC Base Station Controller

CP Central processor

CPC Central processor circuit

DBS Data base manager

DCS Data communication subsystem EMC = Electromagnetic compatibility

UAB/O-96:723 Rev C 97-05-28 © Ericsson. Commercial in confidence

Description 8 (8)

FMS File manager subsystem

IPU Instruction processor unit

LED Light emitting diode

MAU Maintenance unit

MCC Memory control circuit

MCS Man-machine communication

MIA Manual intervention allowed

OCS Open communication subsystem

PLD Programmable logic device

PROM Programmable read-only memory

STUD Store unit, Data store

RP Regional processor

RPH-S Regional processor handler - serial

SPS Support processor subsystem

SPC Signal processor circuit

SPU Signal processor unit

UMC Updating & match circuit

© Ericsson. Commercial in confidence Rev C 97-05-28 UAB/O-96:723