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PROJECT COMPLETION REPORT for the project titled DESIGN AND

DEVELOPMENT OF POWER PACKS WITH SUPERCAPACITORS & FRACTIONAL
ORDER MODELLING
Technical Report · March 2020
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PROJECT COMPLETION REPORT
for the project titled
DESIGN AND DEVELOPMENT OF POWER PACKS

WITH SUPERCAPACITORS & FRACTIONAL ORDER
MODELLING
Sponsored by
DEPARTMENT OF ATOMIC ENERGY (DAE)
GOVT. OF INDIA
Under
BOARD OF RESEARCH IN NUCLEAR SCIENCES
(BRNS)
Sanction No: 36(3)/14/50C/2014-BRNS/10186, dt. 06.05.2015
Submitted by
Prof. Vivek Agarwal
(Principal Investigator)
Geethi Krishnan
(PhD Student)
Department of Electrical Engineering

Indian Institute of Technology, Bombay
Powai, Mumbai-400076
and
Shri Shantanu Das
(Principal Collaborator)
Bhaba Atomic Research Centre (BARC), Mumbai

Brief description of the works/summary of the accomplishments
This project on the “Design and Development of Power Packs with Supercapacitors &
Fractional Order Modeling” tried to address the following challenges associated with the design
of supercapacitor systems:
1. Devising a proper model for representing the complete dynamics of a supercapacitor.
2. Standardizing the characterization methods defined for identifying the value of capacitance,
ESR, leakage current, charge-discharge efficiency etc.
3. Designing higher voltage Packs by stacking the capacitors in series with suitable charge
balancing and protection circuits.
4. Designing a proper power electronic interface for matching the characteristics (Voltage, current)
of SC pack with the application demands.
List of Objectives (as mentioned in the project proposal).
PRODUCT A: Series Connection of two super capacitors-charge balancing scheme

PRODUCT B: Series parallel connected super capacitors “Power-Pack of 5V”
PRODUCT C: Series parallel connected super capacitors “Power-Pack of more than 5V”
PRODUCT D: Configurations for higher voltage system- Boosted DC-DC converter circuit
PRODUCT E: Modelling and characterization of supercapacitors using fractional order calculus
a) Modeling of Super Capacitor System analytical approach from circuit theory and fractional
calculus.
b) Method-1 by solving half order differential equation by numerical method
c) By approximating the half order constant phase element the pore impedance by lumped circuit
d) Modeling of Super Capacitor System by state variable approach and fractional calculus.
Major outcomes/accomplishments of the project
Problems targeted Solutions developed/ Accomplishments

o Devising a proper model for
representing the complete 1. Verified the suitability of fractional order model
dynamics of a supercapacitor. (FOM) for characterizing SC dynamics based on
(PRODUCT E) experiments conducted with commercial SCs and
Indigenous SCs manufactured by CMET.
Additionally the characteristics of different FOMs
defined for SCs are compared.
2. Devised a model for representing charge
redistribution characteristics using Mittag Leffler
Function
3. Derived power, energy and charge-discharge
efficiency of supercapacitors in terms of FOM
4. Analyzed and identified some patterns in the
variation of FOM parameters with varying operating
conditions (voltage, frequency, current, charging
cycle, charging pattern).
5. Developed a new algorithm for online identification
of the FOM parameters using least square algorithm
(Fractional derivative is computed numerically using
GL definition). Implemented the algorithm in DSP
(TMSF28335) and verified the effectiveness.
o Standardizing characterization 1. Devised a method for differentiating charge

methods of supercapacitors redistribution from the leakage.
(PRODUCT E)
2. A method for identifying the parameters of SC
models (integer order models) by including initial
conditioning through multiple charge-discharge tests
is developed.
3. Defined a new term ‘Utilizable capacity (UCTY)’
for sizing the supercapacitors instead of the nominal
capacitance value. An empirical method for evaluating
the UCTY of a fresh SC is developed
4. The impedance characteristics of different make
SCs (Commercial as well as CMET manufactured)
were compared. Identified a pronounced faradaic
component of capacitance on the CMET based SCs.
5. The characterization of CMET SCs (Capacitance
and ESR measurements based on IEC 62391 CC
charge-discharge tests and EIS tests, leakage current
measurement with new method, charge-discharge
efficiency/ charge-retention measurement,
repeatability of capacitance value over cycles,
variation of charge redistribution with respect to the
voltage level and charge-discharge history, FO
behavior)
o Designing voltage balancing and 1. Designed, developed and analyzed resistive voltage
protection circuits for high voltage balancing circuit, LP2996 IC based voltage-balancing
series connected SC packs. circuit and transistor based switched resistor over
o Develop higher voltage Packs with voltage protection circuit.
the voltage balancing circuits
2. A compact modular PCB is designed for transistor
(PRODUCT A,B,C)
circuit and verified the performance.
2. Developed a 36 V, 27 F SC power pack with
transistor based protection circuit. (14 Nos of 400F,
2.7 V, Powerstore/Eaton SC in series).
3. Developed a 5V, 38F SC pack with LP2996 IC
based protection circuit. (3 No’s of 25F, 2.7V,
Panasonic SC in series. Two such modules in parallel).
4. Developed a 22V, 2F SC pack with resistive
voltage balancing. (9 No’s of 25F, 2.5 V
Powerstore/Eaton SC in series).
5. Developed a 42 V, 24 F SC pack with resistive
voltage balancing. (14No’ of 350V, 3V Tecate group
SC).
6. Developed a 54V, 2 F SC pack with resistive
voltage balancing. (18 No’s of 50F, 3V AVX SC in
series).
8. Developed a 140F, 10V SC with resistive voltage
balancing (12 No’s of 35F CMET SC is used, 4 No’s
in series, 4 such modules in parallel).
o Designing a proper power 1. Designed, developed and analyzed a bidirectional
electronic interface for SC pack buck-boost converter rated for 200W power for
(PRODUCT D) regulating the voltage of an SC pack. The interface
converter is equipped with input and output voltage
and current sensors and hence can be tested with
various energy management schemes.
2. The performance of the SC pack interfaced with the
designed converter with an existing DC microgrid
(developed at IIT Bombay) is analyzed.
3. Closed loop controller for constant current charging
of the SC pack is implemented.
List of publications in referred journal
1. G. Krishnan, S. Das and V. Agarwal, "An Online Identification Algorithm to Determine the
Parameters of the Fractional-Order Model of a Supercapacitor," in IEEE Transactions on Industry
Applications, vol. 56, no. 1, pp. 763-770, Jan.-Feb. 2020.
List of papers presented in National/Int’l conference

1. G. Krishnan, S. Das and V. Agarwal, "A Simple Adaptive Fractional Order Model of
Supercapacitor for Pulse Power Applications," 2018 IEEE Industry Applications Society Annual
Meeting (IAS), Portland, OR, 2018, pp. 1-7.
2. G. Krishnan, S. Das and V. Agarwal, "State of Charge Estimation of Supercapacitors with

Fractional Order Modelling," 2018 IEEE International Conference on Power Electronics, Drives
and Energy Systems (PEDES), Chennai, India, 2018, pp. 1-5.
3. G. Krishnan, S. Das, V.Agarwal, “Analysis of Variable Fractional Order Behavior of

Supercapacitors based on Constant Current Discharge Tests”, presented at International
Conference on Advanced Rechargeable batteries and allied materials (ICARBM), Pune, March
2017.
4. G. Krishnan, V. Gupta, S. Das, V. Agarwal, “Development of a transistor based dissipative

shunt equalization circuit for supercapacitor packs”, International conference on supercapacitors
and energy storage applications 2019, Thrissur, Kerala.
Chapter 1
Introduction
The Supercapacitors (SC) are high-energy electro chemical capacitors, with much higher
capacitance than a conventional capacitance of the same size. This emerging technology is known
by different names such as ultra-capacitors, electric double layer capacitor (EDLC), gold
capacitors etc. [1]. They are useful alternatives to conventional battery storage systems as they
offer a much higher power density. Compared to battery, where the storage of energy involves
electro chemical reactions, the SCs store energy in electrostatic fields by ion polarization1. One of
the major challenges faced by supercapacitors is that their energy density is considerably low as
compared to batteries. A Ragone plot comparing the typical range of the power density and energy
density of the state of art batteries, supercapacitors and other capacitors is shown in Fig.1 (a). As
per the figure, the energy density of the batteries is around 100-150 Wh/kg whereas the
supercapacitor energy density is only 8-10 Wh/kg.
1000 CURRENT COLLECTOR
Batteries
Specific Energy (Wh/kg)
100 POSITIVE ELECTRODE
- - - - - - - - - - - - - -
10 SuperCapacitors
SEPERATOR
SEPERATOR
1
+ + + + + + + + + + + + + +
0.1
Capacitors NEGATIVE ELECTRODE
0.01
10 100 1000 10,000 100,000 CURRENT COLLECTOR
Specific Power(W/kg)
(a) (b)
Fig.1. (a) Ragone Plot-Power density verses energy density of conventional capacitors, batteries and super
capacitors (b) Basic Construction of an SC
Several researches are taking place worldwide for increasing the energy density of the
supercapacitors while maintaining the power density. Most of them are focused on finding new
1
The basic structure of an SC includes two electrodes separated by a porous membrane, called as the separator. The electrodes are
normally made of any porous materials, like activated carbon or aerogel or carbon nanotubes. The separator is made of a material
that is transparent to ions, however prevents direct contact between the porous electrodes. The typical specific surface area of the
electrode is about 2000m2/g [1]. The electrodes and the separator are immersed in a solvent electrolyte. A simple schematic
representation of an SC is shown in Fig.1 (b).
electrode materials, which can have higher surface area, uniform porosity and lesser cost. Studies
on pseudo capacitors, which utilizes fast surface redox reactions, are also gaining momentum.
Many improvements are also taking place in the commercially available supercapacitors. Despite
the wide variety of choices available for different materials and device architecture, electric double
layer capacitors having activated carbon or aerogel based electrodes is the most widely used
technology for transient power applications. Additionally, printed supercapacitors based on
graphene and carbon nanotube based electrode materials are popular for low power applications
As they store charge in a reversible way, the number of charging discharging cycles of a
super-capacitor will be much higher than that of batteries. Currently super-capacitors having
capacitance of thousands of Farads with voltage limited to 3 V, are available in markets. They
offer low serial resistance and hence are best suited for applications, which demands high levels
of instantaneous power. Other advantages of electro chemical capacitors include long shelf life,
high efficiency and the ability to fully charge and discharge without affecting the performance as
well as lifetime. In addition, they can work at very low temperatures. Owing to these advantages,
supercapacitors are widely employed for substituting/assisting batteries for various applications
like electric vehicles, traction, micro grids, aeronautical systems, energy-harvesting systems in
wireless nodes and so on.
While appreciating all advantages of supercapacitors, the design of a supercapacitor based
system faces several challenges. Most of those challenges originate because of the porous structure
of the supercapacitor electrodes, diffusion effects of the ions and charge storage on the electrode-
electrolyte double layer interface. Some of the main challenges are as follows:
(1) Devising a proper model for representing the complete dynamics of a supercapacitor.
The working of electrochemical capacitors are governed by the same principles as that of
the conventional parallel plate capacitors. However, they incorporate porous electrode materials
having higher surface area (such as activated carbons, aerogel, graphene some metal oxides) and
have thinner dielectric layer (Thickness in the range of angstrom). This results in an increase in
capacitance and thereby the energy. However, it is quite difficult to fabricate a uniform porous
structure having pores of same size and shape. Practical supercapacitors have a complex porous
structure with different sizes (eg: 1 nm- 50 nm) and shapes (Cylindrical open, funnel shaped etc.)
of pores. The accessibility of each of these pores and in turn their charge storing capacity varies
differently depending on the operating conditions [1]. As a result, the capacitance value shows a
nonlinear dependence on the voltage magnitude, frequency, temperature, magnitude of
charge/discharge currents etc. Furthermore, pseudo capacitors2 or faradaic supercapacitors exhibit
much more distinct features than conventional capacitors, which are more similar to characteristic
behavior of certain batteries. It is not possible to represent such dynamics accurately using a simple
RC model, but requires a higher order complex model.
(2) Standardizing the characterization methods defined for identifying the value of capacitance,
ESR, leakage current, charge-discharge efficiency etc.
The characterization of the state of art commercial supercapacitors are performed mostly
based on the tests specified by IEC standard 62391. The specified tests include constant current
charge/discharge, constant resistance charge/discharge, ac impedance analysis etc. The
experimental results of this model is analyzed after assuming that SC can be represented using a
simple RC model. The parameter variation of this simple RC model due to the variation in the
operation conditions like voltage, charging/discharging current, frequency etc. have been
considered by specifying separate testing conditions (for example separate constant current) for
different applications. Nevertheless, this method specified by IEC also may not result inaccurate
characterization of supercapacitor dynamics. This anomaly originates mainly because of the
approximation of the supercapacitor dynamics using a simple RC model. As mentioned before,
the porous nature of the electrodes results in certain dynamics resulting in completely nonlinear
response characteristics. Porous structure causes charge redistribution, resulting in voltage rise or
voltage drop after every discharging and charging cycles respectively. The pattern and the amount
of this voltage rise or drop depends on the charge/discharge history. This charge redistribution is
not to be confused with leakage as in this case there is no loss of charge. However, it results in
retention of some of charges inside the pores. These charges may not be available for immediate
discharge as compared to the charges on the surface and hence affects the charge-discharge
efficiency. Consequently, the approximation with the RC model results in considerably erroneous
results, which cannot be ignored for many high power applications (pulse power and transient
power applications). Moreover, nowadays many of the applications require the real time estimation
2
Depending upon the mode of storage and construction, ECs can be broadly classified under three categories: (i) Electric double
layer capacitors (EDLC) (ii) Redox capacitor (Pseudo capacitor) and (iii) Hybrid capacitor systems. EDLC stores charge
electrostatically in the two oppositely charged layers (electric double layer) formed at the electrode electrolyte interface, non-
faradically (No chemical reactions involved). In contrast with EDLC, pseudo capacitors employ fast and reversible redox reactions
at the surface for storing the charges (Faradaic systems). Hybrid systems incorporate a combination of pseudo capacitors as well
as double layer capacitors.
of the state of health (SOH) of the supercapacitor systems, which demands online characterization.
The applicability of the IEC standard based tests is not well studied in this regard. Therefore, there
is a need for devising and standardizing tests based on some improved model of supercapacitor.
(3) Designing higher voltage Packs by stacking the capacitors in series with suitable charge
Connecting super capacitors in series and/or parallel, forming a power pack, poses several
challenges. As opposed to the higher capacitance the voltage rating of the device is considerably
low (2.5 to 2.7 V). However, most of applications require a much higher voltage rating, which
demands stacking the capacitors in series. If the value of series connected capacitances are
different because of the manufacturing tolerance, voltage mismatch results across the stack. The
voltage unbalance also occurs due to factors such as variable temperature gradient, ageing, variable
ESR and leakage current. Voltage imbalance within a supercapacitor string is undesirable as few
supercapacitors might be overcharged or negatively charged resulting in premature ageing, shelf
life degradation or permanent damage to the supercapacitors. As a result, we have to stop charging
the stack when one of the series connected capacitor reaches the rated voltage. This results in
inefficient use of the energy storage system.
(4) Designing a proper power electronic interface for matching the characteristics (Voltage,
current) of SC pack with the application demands.
The design considerations of the power electronic converter for interfacing the
supercapacitor pack include the ability to cope up with wide input voltage variation while ensuring
sufficient efficiency, high power operation (for transient power applications), follow the
EMI/EMC constraints and higher power density of the converter.
This project on the “Design and Development of Power Packs with Supercapacitors &
Fractional Order Modeling” tried to address the above-mentioned issues and suggested some
possible solutions for the same. The major objectives mentioned in the project proposal, brief
description of the tasks/experiments conducted along with the accomplished results are described
in the following section.
Objectives and Deliverables as mentioned in the project proposal
Product A: Series Connection of two super capacitors-charge balancing scheme
Product B: Series parallel connected super capacitors “Power-Pack of 5V”
Product C: Series parallel connected super capacitors “Power-Pack of more than 5V”
Product D: Configurations for higher voltage system- Boosted DC-DC converter circuit
Product E: Modelling and characterization of supercapacitors using fractional order calculus
e) Modeling of Super Capacitor System analytical approach from circuit theory and fractional
calculus.
f) Method-1 by solving half order differential equation by numerical method
g) By approximating the half order constant phase element the pore impedance by lumped circuit
h) Modeling of Super Capacitor System by state variable approach and fractional calculus.
Brief description of the works conducted
A brief description of the works conducted at IIT Bombay to address each of the challenges
mentioned in the previous section is explained below:
 Standardizing the characterization methods defined for identifying the value of capacitance,
ESR, leakage current, charge-discharge efficiency
Several experiments were conducted on various commercially available supercapacitors
(SCs) and some indigenous SCs. Initially the characteristics of commercial capacitors from
different manufacturers like Maxwell, Eaton, Tecate group, AVX, Nesscap, Elna, Panasonic, and
NEC Tokin were tested and analyzed. The methodology of the experiments conducted were
devised based on the standard tests specified by IEC standard 62391-1, application notes of several
leading manufacturers of SCs and the research literature. During these studies, several
shortcomings and non-standardized practices followed in the characterization of the SCs were
identified. Based on these observations, several improvements in the test and analysis procedure
of the SCs were suggested. Later, several samples of indigenous SCs based on carbon aerogel,
manufactured by CMET and delivered to IIT Bombay were tested and their characteristics were
compared with the commercial SCs. Several inferences regarding the applicability of these
supercapacitors for various applications were drawn and reported in the subsequent chapter.
 Devising a proper model for representing the complete dynamics of a supercapacitor.
Several literature had already reported that the dynamics of the supercapacitors are quite
different from the traditional capacitor and hence cannot be represented using a simple series RC
model. Instead, various models based on RC networks are reported in the literature. However,
these models characterize the dynamics of SC accurately at the cost of higher order model and
higher computational complexity. Hence, the applicability of these models for most of the practical
applications are limited. Alternatively, many authors have reported the suitability of a fractional
order model (FOM) for supercapacitor. The suitability of such models for characterizing
electrochemical systems has been known for a while, although a detail analysis of FOMs for SCs
is missing. In this regard, several time domain and frequency domain experiments were conducted
to evaluate the dependence of the FOM on the operating conditions (voltage, current, frequency)
and thereafter devised a capacitance variation function of SCs based on the FOM parameters. The
FO behavior of various commercial SCs and CMET capacitors are compared. Further, new
methodologies for evaluating the charge-discharge efficiency, utilizable capacity, rest time
behavior and leakage current of the SCs based on FOM were developed.
 Designing higher voltage Packs by stacking the capacitors in series with suitable charge
The decision of the type of the voltage balancing circuit adopted for an SC pack is a trade-
off between the complexity and the efficiency requirement. Such decisions are hence mostly relied
on the requirement of the applications. In this regard, studies were conducted to analyze the
suitability of some voltage balancing circuits (both active and passive) for various applications.
Design, implementation and analysis of three voltage balancing circuit viz. Resistive balancing,
LP2996-IC based balancing and Transistor based switched resistor circuit balancing were
conducted. Various power packs (Maximum voltage rating: 5V, 8V, 36V, 48V) using the above
mentioned balancing circuits were implemented and their frequency response and rest time
characteristics were analyzed.
 Designing a proper power electronic interface for matching the characteristics (Voltage,
current) of SC pack with the application demands.
A bidirectional buck-boost converter designed and implemented for interfacing an SC pack
with an existing DC microgrid (developed at APEL, IIT Bombay). The designed system can
support 100 W for 4 seconds continuously. During this period, supercapacitor voltage is allowed
to vary from 25V-35V. The interfacing converter is designed to step up the voltage of the SC pack
to 48V irrespective of the input voltage variations and is rated at 200W. The interface converter is
equipped with input and output voltage and current sensors and hence can be tested with various
energy management schemes.
Chapter 2
Fractional Order Modelling of Supercapacitors
Brief review of the literature on the modelling and characterization of
Supercapacitors
All the design aspects of supercapacitor systems require accurate modelling of the system
dynamics. As described in the previous chapter, modelling the dynamics of the supercapacitor
accurately is a challenge as the charge-discharge characteristics of the SCs are highly nonlinear. It
has been observed that the conventional model of capacitors comprising of a simple RC network
cannot represent such dynamics accurately. Several other higher order models of supercapacitors
have been reported in the literature. Some of the models are physical models while others are
electrical circuit models. The physical models represent the electrochemical charge storage
characteristics, like diffusion, polarization effects and shape and size of the pores of the SC. The
earliest physical model of a supercapacitor is the conceptual model of double layer, proposed by
Von Helmholtz. According to his model, the two oppositely charged layers formed at each
electrode- electrolyte interface behave as a parallel plate capacitor. Gouy Chapman model and
Stern models are improvements of Helmholtz model, which have included the voltage dependence
of the capacitance in the model. However, the analysis of such models mostly employ complex
partial differential equations, which make the models computationally intensive.
On the other hand, electrical circuit models are approximate electrical network representations
of the characteristics of supercapacitors. The parameters of these circuit models do not bear direct
relationship with the physical system. Most of these models are derived from De Levi’s porous
impedance model wherein the supercapacitor is approximated by an RC cascaded network. Among
the RC cascaded network models, Zubeita’s three-branch model is the most popular. Zubeita
addresses the question of number of branches required to represent the supercapacitor accurately.
He suggested that with three RC branches and a nonlinear capacitance, satisfactory accuracy
required for most of the applications in the low frequency range could be obtained. However, this
model does not represent the rest-time dynamics and leakage current of the SC. Several papers
have reported work that attempt to eliminate these shortcomings and improve the model. Some of
them included the charge redistribution/leakage effects by adding controlled sources in the model,
while some others included thermal and ageing effects in the model parameters. However, most of
these improvements involve complex higher order models, which are computationally intensive
and hence not suitable for real-time estimation of the SOC and the State of Health (SOH) of the
supercapacitors. Similarly, some other well-known models of supercapacitors like Buller’s
dynamic model, Musolino’s full-frequency range model and German’s multi penetrability model
cannot be used where real time computations are required.
Alternatively, many authors have reported the suitability of a fractional order model for
supercapacitor. The supercapacitor shows resemblance to a fractal system owing to the dependence
of its behavior on the past charging/discharging history. Such systems exhibit a fractional slope
relation in their frequency response and their voltage-time characteristics can be better represented
using fractional order derivatives and integrals. Fractional order model generalizes the concept of
differentiability by including non-local memory effects thereby also helps in accounting the charge
redistribution effects.
The fractional order modelling (FOM) was discussed extensively for analyzing the suitability of
various electrode materials and electrolytes for supercapacitors. However, the reported work from
an application perspective is limited. Among these few reported work, most of them deals with the
characterization, analysis and validation of the simplest fractional order model comprising a
resistor and a constant phase element (CPE) around a particular operating point, although this
assumption of a constant operating point does not always hold, for example transient/pulse power
applications. In this regard, there is a need for further studies on the characterization and analysis
of SC systems using fractional order modelling.
Introduction to Fractional Order Modelling (FOM)
The simplest FOM of a supercapacitor comprises a resistor and a Constant Phase Element
(CPE) in series as shown in Fig. 2.1(a). CPE represents the fractional integration of (1/Cn), where
‘n’ is the order of integration (such that 0<n<1) and ‘Cn’ is the fractional capacity. ‘Cn’ is not the
same as the nominal/utilizable capacitance and hence its unit is not ‘F’ but ‘F/ (sec)(1-α). The
expression of CPE is as follows:
1
CPE  α
s C
R CPE
Fig.2.1. Simplest fractional order model of an SC
It has been observed that this simple fractional order model can give a better representation
of the dynamics of the supercapacitor as compared to the other existing integer order models
(IOM). A typical IOM of an SC is same as the series RC network model of a conventional
capacitor. FOMs are in fact the generalization of the IOMs (when α=1) and are generally used for
representing the characteristics of those systems, whose present behavior depends on the past
history. SCs exhibit such a behavior owing to the porous nature of its electrodes. This behavior of
supercapacitors can be recognized from their frequency domain and time domain characteristics.
For instance, consider the Nyquist diagram shown in Fig. 2.2(a) where the frequency response
characteristic of a 1.5 F supercapacitor is plotted. It is observed that the real part of the SC
impedance varies with frequency. This kind of phenomenon is typically not seen in a conventional
capacitor, which follows IOM model. This is clear from the Nyquist plot of a 1000 μF electrolytic
capacitor shown in Fig. 2.2 (b). Therefore, an IOM cannot represent the characteristic of Fig.
2.2(a). On the other hand, an FOM can characterize the SC accurately, which is validated in the
subsequent sections.
1500
4
Z IMAG
ZIMAG
2
(b)
0 (a) 0
6 -500 500
12 ZREAL
ZREAL
Fig. 2.2 (a) Nyquist plot of a 1.5F supercapacitor; (b) Nyquist plot of 1000 μF electrolytic capacitor.
The parameters of IOMs can be directly derived through standard IEC tests like constant
current charge-discharge, constant resistance charge-discharge etc. using simple algebraic
calculations. For example, the slope of the constant current charge/discharge curve gives the
capacitance value for a simple RC network model. However, such direct analysis is not possible
for FOM because of its non-linear nature. Hence, identification of the parameters of the FOM, viz.
‘Cα’, ‘R’ and ‘α’ is mostly done by fitting the experimental data into the model. In order to explore
the suitability of IOM and FOM for characterizing the SC dynamics, constant current (CC)
charging tests on 4 sample SCs were conducted in the laboratory to identify the FOM and IOM
parameters. The parameters were determined by fitting the obtained experimental SC voltage
response data into the FOM and IOM using least square optimization. The identified parameters
of the two models for the 4 samples are listed in Table 2.1. The experimental voltage response of
the 1.5F, 5.5V, SC sample (charged with a constant current, Icc = 0.2A) is plotted in Fig. 2.3
alongside the voltage response predicted by the FOM and IOM. While the IOM is clearly
inadequate for predicting the actual voltage response, FOM shows a near perfect fit.
TABLE 2.1
FOM AND IOM PARAMETERS OF SAMPLE SUPERCAPACITORS
FOM
FOM Parameters IOM Parameters
Voltage (V)
Sample R(Ω) Cα((F/s(1- α)) α R (Ω) C (F)

Expt. plot
1.5 F, 5.5 V 0.80 0.25 0.60 0.99 0.78
10F, 2.7V 0.07 6.70 0.80 0.05 9.06 (a) IOM
25F, 2.5V 0.02 20.10 0.83 0.06 36.59 Time (s)

50F, 3V 0.02 25.54 0.81 0.07 61.72 Fig.2.3. Simulated IOM and
FOM with experimental plots
Fractional order calculus-An introduction
Fractional order differential calculus is the generalized form of integer order integral and
differential calculus. The order of a fractional derivative or integral ‘α’ can be any real or complex
number. There exist three main definitions of the fractional order integrals and derivatives:
Riemann-Liouville, Grünwald-Letnikov and Caputo derivative. These definitions are applied for
both fractional order integration and differentiation depending on whether the ‘α’ is negative or
positive, hence commonly called as ‘differ integration’.
According to Riemman_Liouville (R-L) definition, the fractional derivative is given by:
𝑑𝑛 1 𝑡 𝑓(𝜏)
𝑎𝐷𝑡𝛼 𝑓(𝑡) = 𝑑𝑡 𝑛 [ ℾ(𝑛−𝛼) ∫𝑎 (𝑡−𝜏)𝛼+1−𝑛 𝑑𝜏
By Grunwald_Letnikov definition (G-L)

𝑥−𝑎
1 ℾ(𝛼+1) 𝑓(𝑥−𝑚ℎ)
𝑎𝐷𝑡𝛼 𝑓(𝑡) = lim ℎ𝛼 ∑𝑚=0
ℎ
(−1)𝑚
ℎ→0 𝑚!ℾ(𝛼−𝑚+1)
Caputo definition is given by the following equation

1 𝑡 𝑓(𝜏)
𝑎𝐷𝑡𝛼 𝑓(𝑡) = ∫ 𝑑𝜏
ℾ(𝑛−𝛼) 𝑎 (𝑡−𝜏)𝛼+1−𝑛
Special functions
1. Gamma Function
Gamma function is the generalization of the factorial. The basic integral representation of the
Gamma function is as follows:

(z)   et t z 1dt
0
Gamma function has simple poles at -1,-2,-3 etc.., making the function discontinuous. A typical
definition of gamma function is given in Fig. 2.4
Fig.2.4. Gamma Function

2. Mittag-Leffler Function
Mittag-Leffler function commonly abbreviated as MLF is the generalization of the exponential
function. The basic one parameter approximation of MLF is as follows:
 zk
E ( z )  
k  0 ( k  1)
The expansion of the function as an infinite series is as follows:

z z2
E ( z ) 1    ...
(  1) (2  1)
This definition is again generalized as a two parameter MLF function, where
 zk
E ,  ( z )  
k  0 ( k   )
(a) (b)
Fig.2.5. One parameter MLF (a) α < 1 (b) α > 1
Identification of FOM parameters
The major step in defining and applying a fractional order model is associated with
identifying the parameters of such models. The parameters of integer order models can be derived
directly from some standard IEC tests like constant current charge-discharge, constant resistance
charge-discharge etc., with some simple algebraic calculations. For example, the slope of the
constant current charge/discharge curve gives the capacitance value for a simple RC circuit. Such
direct analysis is not possible for a fractional order model as it is not possible to represent the
solution of the fractional differential equation in terms of common analytical functions like
exponential function.
Alternatively, identification of the parameters of the model is mostly done using a curve
fitting routine by comparing the experimental results with the simulated model response.
Simulating or emulating the FOM in any controller requires understanding of the definitions of the
fractional differentiation/integration and familiarity with the special functions, which are explained
in the previous section. Typical experiments for identification of FOM parameters include constant
current (CC) charge/discharge test, constant resistance (CR) charge/discharge test and
electrochemical impedance spectroscopy (EIS) test.
A. Constant resistance charge-discharge test
A schematic representation of this test is given in Fig. 2.6. The supercapacitor is
represented using a simple fractional order model. Rch and Rdisch represents the external resistances
connected during charging and discharging respectively.
S1 Rch S2
Rs
V Rdisch
1
Sn Cn
Supercapacitor
Fig. 2.6. Schematic representation of Constant resistance charge/discharge test

During charging,
1
if Z1  Rch  Rs and Z 2 
Cn S n
 1   1 
 Z2   Cn S n   CR 
V0 ( s )    in
V ( s )    Vin ( s )   n
 Vin ( s ), where R  Rch  Rs
 Z 2  Z1   1 R R   Sn  1 
 C Sn ch s   Cn R 
 n  
 k  1
V0 ( s )   n  Vin ( s ), where k 
 S k  Cn R
VR
Vin (t )  VRu (t )  Vin ( s ) 
s
 V k   V k 
V0 ( s)   R
  V (t )  L1
 R

 S Sn  k   0
 S S n  k  
   
From the tables of Mittag- Leffler function we have,
k !s  

L t  k   1
E ,   at    


s  a
For k  0,   n,   n  1, we have
s 1
 t n En ,n 1  at n 
s  a
n
Using the above,

 V k   tn 
n , n 1   RC n,n1   RC 
VR n
V0 (t )  L1  R
  V k t n
E  k t n
 t E
 S Sn  k   R
 n 
  n
Representing the expression of the charging voltage across an SC using one parameter MLF
VR k VR k VR k  k k2 k3 
V0 ( s )    n 1 
1   2 n  3n  ... 
s  s  k  s n 1 1  k 
n n
s  s s s 
 
 s 
n
 k k2 k3 
 VR  n 1  2 n 1  3n 1  ... 
s s s 
 1 
n
t
Using Laplace definition, L1  n 1  
 s    n  1
 kt n k 2t n k 3t n 
V0 (t )  VR     ... 
   n  1   2n  1   3n  1 
To the above series, add and subtract 1 to get,
  kt n k 2t n k 3t n 
V0 (t )  VR 1  1     ...  
    n  1   2n  1   3n  1
 

  kt n  
m
   t n 
 VR 1  
   VR 1  En    (I)
 m 0   mn  1    RCn 
 

xm
En ( x)   is one parameter MLF
m  0   mn  1
 
t

n  1, En ( x)  e  V0 (t )  VR 1  e
x RC1

 
 
Charging current
VR
s  VR VR s n 1
I ( s)  
Z ( s)  1   1 
s  R  n  R  sn  
 s Cn   RCn 
s n 1
From L  En  at n    n ,
s  a
VR  t n 
I (t )   En  
R  RCn 
During discharging,
Similar analysis can be performed for deriving the voltage equation of SC while discharging.
Suppose the initial voltage is Vc (0)
Vc (0)
I (s)  s
1
Rs  Rdisch  n
s Cn
 
Vc (0) V (0)  Rdisch  s n 1 
 V0 ( s )  I ( s )  Rdisch   Rdisch  c 
 1 
s  Rs  Rdisch  n 
 Rs  Rdisch   s n  1 
 Cn  Rs  Rdisch  
 s Cn  
Vc (0)  Rdisch  t n 
V0 (t )   En   (II)
 Rs  Rdisch   Cn  Rs  Rdisch  
These voltage equations (I and II) are curve fitted with the experimentally obtained
capacitor voltage-time graphs during charging/discharging for identifying the fractional order
model parameters [Rs, Cn, n].
B. Constant current charge-discharge test

The capacitor is charged through a constant current (CC) source during charging and
discharged through a controlled constant current load. The schematic representation is given in
Fig. 2.7. The fractional order parameters can be identified from CC charge/discharge test results
using the following equations.
During charging,
The voltage appearing across the supercapacitor terminals while undergoing constant current (CC)
charging can be represented as follows: (Assume initial voltage as Vinit)
S1 S2
Rs Idisch
Ich
1
SnCn
Supercapacitor
Fig. 2.7. Schematic representation of Constant current charge/discharge test
Vinit I ch Rs I ch  1 
V0 ( s )  Vinit ( s ) VR ( s ) Vc ( s )     
s s s  s ncn 
where Vinit is the initial capacitor voltage and Vc is the charging voltage across the capacitor and VR
is the voltage drop.Expressing the capacitor voltage in time domain, we get,
1 Ich  I ch 1 1  I ch  tn 

Vc (t )  L   L  n 1    
 s n 1cn  cn s  cn   (1 n) 
  n

  I ch  Rs    I ch  
t
V0 (t )  Vinit 
  Cn    n   
During discharging,
Similar analysis can be performed for deriving the voltage equation of SC while discharging.
Vinit I ch Rs I ch  1 
V0 ( s )  Vinit ( s ) VR ( s ) Vc ( s )     
s s s  s ncn 
  n

  I disch  Rs    I disch   
t
V0 (t )  Vinit 
  Cn    n   
C. Impedance spectroscopy
The fractional order model parameters can also be identified from impedance spectroscopy
analysis. Impedance spectroscopy (IS) is method of characterizing the electrical properties of
electrical interfaces with electronically conducting electrodes. The commonly employed procedure
for conducted EIS is to apply a single frequency voltage or current to the device under test (SC)
and measure the phase shift or magnitude or real and imaginary parts of the resulting current or
voltage using any method. Most of the impedance analyzers available in market have a frequency
range varying from few μHz to MHz. The excitation signal consists of a constant dc potential or
current superimposed with an ac signal. The output response will be in the form of bode or Nyquist
plots. The FOM parameters can identified by comparing these frequency analysis plots with the
following equations:
1 1  1     1   
Z  Rs   Rs    Rs   cos      j   sin    

   c  2    c  2 
s c  (cos   j sin  )c 
2 2
2 2
 1     1   
Magnitude   Rs   cos        sin    
  c  2     c  2 
 1   
   sin    
 c  2 
Phase  tan 1  tan 1 
Z imag
Z real  1   
 Rs   cos    
  c  2 
Experimental analysis of the Fractional order behavior of the commercial SCs

In order to evaluate the suitability of an FOM for characterizing SC dynamics, the above-
described tests were conducted on several commercial SCs and indigenous SCs (manufactured by
CMET). Commercial SCs of different make (different electrodes, electrolytes, varying effect of
faradaic reactions), different capacitance values (1.5 F to 400F) and different voltage ratings (2.3V,
2.5V, 2.7V, 3, 5V, 5.5V) were chosen for the tests. The detailed list of the commercial SCs along
with their significant attributes as mentioned in their datasheet is provided in Table.2.2.
TABLE.2.2: DETAILS OF THE COMMERCIAL SCS TESTED FOR FRACTIONAL ORDER BEHAVIOR
No Capacitance (F) Voltage (V) Manufacturer Other datasheet information

1 1.5 F 5.5 V Panasonic Cap tolerance (%)=-20% to +80% @+20 °C
ESR @ 1kHz < 30Ω
I leakage: 1 mA or less
2 1.5 F 5.5 V PowerStor Cap tolerance (%)=-20% to +80% @+20 °C
ESR @ 1kHz < 30Ω
3 1.5 F 5.5 V Elna Cap tolerance (%)= ±30% @+20 °C
ESR @ 1kHz < 30Ω
4 4F 3V Taiyo Yuden Cap tolerance (%)= ±20% @+20 °C
ESR @ 1kHz < 300mΩ
I disch: 0.5 A or less
5 4.7 F 2.5 V Panasonic Cap tolerance (%)= ±30% @+20 °C
ESR @ 1kHz ≤ 0.3Ω
I disch: 300mA or less
6 5F 5V AVX Cap tolerance (%)=-0% to +100% @+65 °C
ESR @ 1kHz ≤ 100mΩ
I disch (Peak): 7.14 A or less
7 10 F 2.5 V PowerStor Cap tolerance (%)=-10% to +30% @+20 °C
ESR @ 1kHz < 0.06Ω
I disch (continuous): 2.5 A or less
8 10 F 2.7 V Nichicon Cap tolerance (%)=-20% to +20% @+20 °C
ESR @ 1kHz < 0.2 Ω
I leakage: 5 mA or less
ESR @ 1kHz < 0.027 Ω
ESR @ 1kHz < 0.040 Ω
11 25 F 2.7 V Illinois Cap tolerance (%)=-10% to +30% @+20 °C
ESR @ 1kHz < 0.030 Ω
12 25 F 2.7 V Vishay Cap tolerance (%)=-20% to +50% @+20 °C
ESR @ 1kHz < 0.015 Ω
I disch (peak): 25 A or less
13 25 F 3V Maxwell Cap(F): 22.5 F to 30 F
ESR @ 1kHz < 0.017 Ω
14 50 F 3V AVX Cap tolerance (%)=-10% to +30% @+20 °C
ESR @ 1kHz < 0.018 Ω
I disch (peak): 37.5 A
15 50 F 2.3 V Panasonic Cap tolerance (%)=-20% to +40% @+20 °C
ESR @ 1kHz < 0.100 Ω
16 100 F 2.7 V AVX Cap tolerance (%)=-10% to +30% @+20 °C
ESR @ 1kHz < 0.015 Ω
I disch (peak): 48.2 A or less
17 100 F 2.7 V Tecate group ESR @ 1kHz < 0.010 Ω
I disch (rated): 54 A or less
I leakage: 0.26 mA or less
18 100 F 2.7 V Nesscap Cap tolerance (%)=-0% to +20% @+20 °C
DC ESR < 8 mΩ
I disch (max): 17 A or less
DC ESR < 4.5 mΩ
I disch (continuous): 20 A or less
20 350 F 3V Tecate group DC ESR < 4 mΩ
21 350 F 2.7 V Maxwell DC ESR < 3.2 mΩ
DC ESR < 3.2mΩ
I disch (continuous): 26 A or less
The parameters of the FOM for each of the SCs of Table 2.2 is identified under appropriate
operating conditions based on the tests described in the previous section. The identified parameters
along with the testing conditions are listed in Table 2.3. The value of ‘α’ for all the SCs are falling
within the range of 0.6-0.8, indicating a fractional order behavior. It is to be noted, the FOM is
valid irrespective of the make (electrode material and manufacturer) and the range (1F to 400F) of
supercapacitors.
TABLE.2.3: IDENTIFIED FOM PARAMETERS OF THE COMMERCIAL SCS
No R Cα α Testing details
1 0.99 0.1 0.76 CC Charging @ 0.8mA
2 0.99 0.17 0.84 CC Charging @ 0.8mA
3 0.001 0.21 0.82 CC Charging @ 0.8mA
4 0.52 1.65 0.77 CC Charging @ 0.5 A
5 0.23 2.96 0.82 CC Charging @ 0.5 A
6 0.001 2.84 0.81 CC Charging @ 0.5 A
7 0.115 6.67 0.801 CC Charging @ 2.5 A
8 0.245 6.3 0.785 CC Charging @ 2.5 A
9 0.203 16.75 0.843 CC Charging @ 3.4 A
10 0.046 13.54 0.78 CC Charging @ 2.6 A
11 0.001 23.86 0.66 CC Charging @ 2.6 A
12 0.044 16.10 0.84 CC Charging @ 2.6 A
13 0.025 16.67 0.85 CC Charging @ 2.6 A
14 0.001 22.8 0.73 CC Charging @ 4 A
15 0.035 30.64 0.85 CC Charging @ 4 A
16 0.015 77.59 0.89 CC Charging @ 7 A
17 0.02 56.39 0.81 CC Charging @ 7 A
18 0.01 58.97 0.81 CC Charging @ 7 A
19 0.006 139.75 0.79 CC Charging @ 10 A
20 0.006 161.31 0.78 CC Charging @ 10 A
21 0.002 155.46 0.79 CC Charging @ 10 A
22 0.004 158.88 0.77 CC Charging @ 10 A
FO behavior observed in the experimental results of various commercial SCs
Case 1: FO behavior observed in the voltage-time graph from constant current charging test
Because of the porous nature of the electrodes, for an EDLC the value of
capacitance increases with voltage. Consequently, the slope of the voltage-time curve for a
constant current (CC) charge/discharge decreases as voltage increases (as shown in Fig. 2.8) as
opposed to a constant slope for other capacitors. It has been observed that, the resulting nonlinear
characteristics can be accurately represented using the simple fractional order model. The
parameters of this model are identified by curve fitting the experimental results of the CC charging
using nonlinear least square routine in Matlab. The identified parameters are given in Table 2.4
and the simulation of the resultant model along with the experimental results is presented in
Fig.2.8.
Voltage(V)
θ1 θ2
Time(s)
Fig.2.8. Experimental results (GREEN) of Constant current charge test of a 25F, 2.5V, PowerStor
supercapacitor with simulated fractional order model characteristics (BLACK)
TABLE 2.4: IDENTIFIED PARAMETERS OF THE FRACTIONAL ORDER MODEL OF 25F, 2.5V SC
Sample Current Rs ( Ω) Cα ( F /s(1-α)) α
25F, 2.5V PowerStor 10 A 0.049 16.604 0.77
Case 2: FO behavior observed in the voltage-time graph from constant resistance charging test
Fig.2.9. gives the constant resistance test result of a 1.5 F, 5.5V Panasonic supercapacitor.
This 1.5F SC is charged from a constant voltage source of 5V through a series resistance of 10 Ω.
The parameters of the fractional order model is then identified by comparing with the experimental
results. It is clearly visible that the experimental characteristics and the simulated characteristics
from the identified model parameters are matching perfectly.
Fig.2.9. Experimental results (RED) of Constant resistance charge test of a 1.5F, 5.5V, Panasonic
supercapacitor with simulated fractional order model characterististics (BLUE)
TABLE 2.5: IDENTIFIED PARAMETERS OF THE FRACTIONAL ORDER MODEL OF 1.5F, 5.5V SC
Sample Voltage Cα ( F /s(1-α)) α
1.5F, 5.5V Panasonic 5V 0.7728 0.3
Case 3: FO behavior observed during electrochemical impedance spectroscopy test

Electrochemical Impedance Spectroscopy (EIS) test is commonly used for performing the
frequency response analysis of the electrochemical systems. Fig.2.10 shows the results of the EIS
test result of 25F, 2.5V, PowerStor supercapacitor superimposed with the simulated fractional
order model. The experiment is conducted in Autolab 302N potentiostat/galvanostat. The
parameters of the FOM are obtained by comparing the experimental results and is given in Table.
2.6. The plot is fairly matching with the experimental results especially in the medium frequencies.
Fig.2.10. Experimental results (Black) of Constant resistance charge test of a 25F, 2.5V, PowerStore
supercapacitor with simulated fractional order model characterististics (Blue)
TABLE 2.6: IDENTIFIED PARAMETERS OF THE FRACTIONAL ORDER MODEL OF 25F, 2.5V, POWER
STORE SC
Sample Rs ( Ω) Cα ( F /s(1-α)) α
25F, 2.5V PowerStor 28.1 m Ω 15.2 0.523
Representing the charge redistribution characteristics of a supercapacitor

using FOM
Owing to the porous nature of the electrodes, the available capacitance of supercapacitors
varies over charging, discharging and rest time periods. If the capacitor is subjected to very fast
charging, the pore depths remains inaccessible while charging. As a result, charges accumulate
only on the surface of the pores, resulting in a rise of terminal voltage to the rated value, without
utilizing the complete storage capacity. However, with time, the charges on the surface redistribute
occupying the inner areas of the pores. For the same charge, as more capacitance becomes
available, the voltage drops. Similarly, following a sudden discharge the voltage rises back.
Consequently, direct calculation of SOC from the capacitor voltage without considering the charge
redistribution effects gives erroneous results. Several studies try to model this characteristic with
some variable leakage resistance and dependent charge/discharge current sources [15-18].
However, the identification of the parameters and the analysis is quite complicated.
It has been observed that the variation of capacitance with respect to time and the resulting
change in the terminal voltage during rest period can be predicted more accurately by the simple
fractional order model. The variation in the terminal voltage after a sudden charge can be modelled
by the following equation.
 
 t 
V0 (t )  Vc (0)   E ,1   
   
Where ‘Vc(0)’ represents the terminal voltage of the supercapacitor just after the charging
period and ‘τ’ represents the time constant of charge redistribution. This time constant depends on
the charging history. i.e., the time constant for fast charging is less as compared to slow charging.
Similarly, the voltage rise also follows the MLF, which can be represented using the equation:
 
 t 
V0 (t )  Vc ()  1  E ,1   
   
However, Vc (∞) is not known or rather it depends on the charging history. As the
magnitude of the discharging current increases, Vc (∞) increases correspondingly. In order to
verify these observations, the charge redistribution of a 25F, 2.7V Cooper Bussman capacitor
following a constant current charge and discharge (10A) is analyzed. The terminal voltage drop
following a 10A constant current charging and voltage rise after a 10A constant current discharge
is compared with the simulated response of the above equations respectively. The results are shown
in Fig.2.11 and Table.2.7. It has been observed that, the redistribution characteristics also shows a
fractional behavior and can be predicted using MLF.
Experiment
Simulation
Experiment
Simulation
(a) (b)
Fig. 2.11. Charge redistribution of 25F cooper busman SC represented using MLF (a) After discharging
(b) After charging
TABLE 2.7: EXTRACTED MODEL PARAMETERS FROM CHARGE REDISTRIBUTION DATA
Sample Condition before α τ

25F, 2.7V Cooper Bussman Discharging 0.239 35198 s
25F, 2.7V Cooper Bussman Charging 0.554152 1092 s
Power and energy equation and charge-discharge efficiency of supercapacitor

based on a FOM
Most of the supercapacitor applications rely on the conventional power and energy
equations based on the simple RC model (The value of capacitance is assumed constant) for the
design of SC systems. However, as illustrated in the previous section, the available capacitance is
very much dependent on the charge redistribution, which in turn depends on the charging history.
Ignoring this variability of the available capacitance for power and energy calculation can
undoubtedly give erroneous results. It was observed that, a more suitable expression of the power,
energy and charge-discharge efficiency of a supercapacitor could be derived from a FOM. This
section details these derivations and subsequent inferences.
The instantaneous power from an SC can be expressed as follows:
p (t )  v (t )  i (t )
d v t 
n
d n v (t )
i (t )  C n  p (t )  v (t )  C n
dt n dt n
The energy stored in the SC from time t = 0 to t = t1 can be given as
t1 
d v (t )
e(t )  C  v (t ) 
dt
0 dt
As opposed to an integer order differential equation, deriving a simple solution for these
fractional order differential equations is not so easy. Moreover, a generalized solution may not
give much insight to a practicing engineer. Rather, in order to analyze the variation in the charge-
discharge efficiency because of the fractional behavior, a typical case of constant current
charging/discharging is taken and interpreted. The detailed derivation is as follows:
Case 1: Constant current charging/discharging
The voltage appearing across the supercapacitor terminals while undergoing constant current (CC)
charging can be represented as follows: (Assume initial voltage as Vinit)
  n

  I ch  Rs    I ch  
t
V0 (t )  Vinit 
  Cn    n   
   
tn
p (t )  v (t )  i (t )   Vinit  I ch Rs  I ch      I ch
  
   Cn  n    
  2  
  tn
t t
e(t )   p (t ) dt   Vinit I ch  I ch Rs  I ch 
 2
   dt (III)
0  
0   C
 n  n    
2 2  t
n 1

e (t )  Vinit I ch t  I ch Rs t  I ch  
 Cn  ( n  1)    n  
For a special case, when n=1
2 I ch 2t 2
e (t )  Vinit I ch t  I ch Rs t 
2Cn
dv V I C
n  1, I ch  Cn dt  Cn t V  ch t n
(IV)
2 2
1 2 I t
 CnV  ch
2 2Cn
From the above equations, it is clear that conventional power and energy expression of an SC given
in (III) is a special case of the (IV). The energy equation corresponds to the total input energy from
the source.
The energy transferred to the capacitor for the time ‘t’ is given by
2  t
n 1

e (t )  I ch
c  
 Cn  ( n  1)    n  
Now consider the case of a constant current discharge where the initial voltage is Vfinal,
  n

  I disch  Rs    I disch   
t
V0 (t )  V final 
  n C    n  
   
tn
p (t )  v (t )  i (t )   V final  I disch Rs  I disch      I disch
   Cn  n    
   
t   
  tn
t
e (t )   p (t ) dt    V final I disch  I disch 2 Rs  I disch 2     dt
0   Cn  n    
0    
2 2  t
n 1

e (t )  V final I disch t  I disch Rs t  I disch  
 Cn  ( n  1)    n  
The energy transferred to the load from the capacitor for the time‘t’ is given by
2  t
n 1

e (t )  I disch
c  
 Cn  ( n  1)    n  
Consider a case with same charging and discharging current, ‘I’ and initial voltage before charging
as zero. It is assumed that the FOM parameters remains same during charging as well as
discharging.
 I disch  Rs    I ch arg e  Rs    I  Rs 
V V final   I  Rs 
If the time taken for charging the SC to ΔV is t1 and time taken to discharge ΔV is t2 (Note that the
time is different because of the charge redistribution characteristics), charge discharge efficiency
is function of the ratio of charging and discharging time.
edisch arg e (t )  t2 n 1   t2  n 1
   n 1    
ech arg e (t )
 t1   t1 
For a different case where charging and discharging currents are not equal. The time taken for
charging the SC (From zero initial voltage to rated voltage) and discharging after keeping the SC
in open circuit condition for certain period is same (Assumptions: (1) Because of charge
redistribution, the voltage drops from the rated value and almost settles at some voltage (2) The
voltage drop across ESR can be neglected)). Here charge discharge efficiency is a function of the
ratio of the discharging and charging currents.
2  t
n 1

ech arg e (t )  I ch  
 Cn  ( n  1)    n  
2  t
n 1

edisch arg e (t )  I disch  
 Cn  ( n  1)    n  
2
I
edisch arg e (t ) 
   disch 
ech arg e (t )  I ch 
Dependence of FOM Parameters on the SC Operating Point

The operating point of an SC is determined by the value of its charging/discharging current,
voltage appearing across it and the frequency. The suitability of FOM in reproducing the
experimental plot for a given operating point was demonstrated in Section II. At the same time,
the limitation of the identified parameter set (R, Cα, α) in predicting the voltage response of the
SC at a different operating point was also illustrated. The fact is that practical supercapacitors are
subjected to continuously varying operating conditions in most of their applications and hence
there is a need for adaptive (online) identification of the parameters of an FOM. The following
study, based on the experiments conducted on Auto lab PGSTAT302N Potentiostat-Galvanostat
with FRA module, further strengthen this point.
Case 1: Dependence of FOM parameters on voltage levels.
The value of capacitance varies with respect to the magnitude of charging voltage. This is
because of the nonlinear variation of the capacity with the effective electric field. Consequently, the
voltage-time characteristics of the supercapacitor during charging and discharging shows
considerable deviation from the predicted characteristics of the conventional models. Several
integer order models with a nonlinear voltage dependent capacitor branch are employed to reflect
this behavior. However, it has been observed that these model parameters depend on the test
conditions substantially. i.e, the identified value from a constant discharge test at a specific charging
current I1 is found to be different from the value obtained at a different charging current I2.
A 25F, 2.5V SC is charged to different voltage (SOC) levels (0V, 0.5V, 0.1V, 2V) and
frequency response analysis (FRA) test is conducted at each level. The Bode magnitude plots and
the Nyquist plots obtained from the FRA tests are shown in Fig. 2.12. Further, FOM parameters
are identified by fitting the Bode magnitude plot with the following equation.

2 2 
1     1    
Z Mag   R   cos        sin     
  C  2     C  2   
It is observed that, the variation in voltage results in nonlinear variation of the capacity. This
variation in the capacity is reflected in the value of ‘Cα’ as seen from Table 2.8.
0.1 0.1
ZIMAG (Ω)
V= 2 V
Z IMAG (Ω)
V=2 V
V=1 V V=1 V
V=0.5V
V= 0 V V=0.5V V= 0 V
0.1
4
10 -0.05
Frequency (Hz) 0
Z Real(Ω) 0.1
Fig. 2.12. Bode magnitude plots and Nyquist Plots of a 25F, 2.5V supercapacitor at different voltage
levels.
Case 2: Dependence of FOM parameters on frequency

Frequency response analysis of a 25F, 2.5V SC is conducted over a range of frequency
(0.01Hz to 1 kHz) and the resultant plot is shown in Fig. 2.13. The whole frequency range is
divided into 3 zones and a zone-wise curve fitting is employed for identifying the FOM parameters
in each zone separately using (2). It is clear from Table 2.8. that the identified values of ‘Cα’ and
‘α’ in the different zones are not the same.
ZONE 1
R=51.5 mΩ
α =0.957
Zimag(Ω) Cα=17.7
ZONE 2
R=29.8 mΩ
α =0.48
Cα=15
ZONE 3
F(Hz) R=26.8 mΩ Zreal(Ω)
α =0.338
Cα=22.9
Fig. 2.13. Nyquist plot of a 25F, 2.5V supercapacitor with frequency zone wise identified FOM
parameters.
Case 3: Dependence of FOM parameters on current

Several constant current charging tests are performed on a 25F, 2.5V SC. The current magnitudes
are taken as 0.1A, 1A, 5A and 10A respectively. Subsequently the experimental data is fitted into
the following expression for the voltage derived from the FOM.
  

V0 (t )  Vinit   I ch  Rs    I ch  
t

  C       
The identified FOM parameters are given in Table 2.8. The FOM parameter variation with the
charging/discharging current magnitude is reflected in the values of ‘α’ and ‘Cα’. However, for
small variations in the current, the deviations observed in these parameters are negligible. As the
range of the variation in the operating current increases, the values of ‘α’ and ‘Cα’change
correspondingly.
10 A
5A 1A
0.1 A
5A
1A
10 A
0.1 A
(a) (b)
Fig.2.14. Constant current (CC) charge discharge characteristics of 25F, 2.5V Power store supercapacitor
(a) CC Charging (b) CC Discharging
TABLE.2.8: DEPENDENCE OF THE FOM PARAMETERS OF 25F, 2.5V SC ON VOLTAGE, FREQUENCY
AND MAGNITUDE OF CURRENT
CASE 1 CASE 2 CASE 3
NO Voltage Frequency Zones Current
0 V 0.5V 1 V 2V 0.01- 1-100 100- 0.1 A 1 A 5 A 10 A
1Hz Hz 1000 Hz
R (mΩ) 35.2 41.3 29.7 64.5 51.5 29.8 26.8 29.5 29.4 30.1 29.6
(1- α)
Cα (F/s ) 19.4 20.4 22 25 17.7 15 22.9 21.7 20.7 20.4 18.6
α 0.86 0.86 0.8 0.8 0.95 0.481 0.338 0.98 0.98 0.98 0.87
Online parameter identification of FOM

Considering the limitations of the offline identification of FOM parameters, this section presents
a method for identifying the parameters of FOM in real time (online) using the least square
algorithm with high accuracy. The various steps involved in the implementation of the online
estimation are as follows:
Step 1: Developing the state space representation of the fractional order model of the
supercapacitor.
The impedance of a supercapacitor in terms of fractional order model is defined as:
1 V (s) 1
Z  R    R 
s C I (s) s C
1 
V ( s )  RI ( s )  s I (s)
C
1 
V (t )  RI (t )  D I (t )
C
where D-α represents fractional differentiation/integration. There are several definitions for
implementing fractional differentiation and integration. Among them, Grunwald-Letnikov (G-L)
definition is considered more suitable for numerical evaluation, and hence it is used in this work.
By G-L definition:
 1 L m  (  1)
D f ( x )  lim 
 ( ) f ( x  mh)
T 0 T m0 m !  (  m  1)
where Г(x) represents the gamma function, which is the generalization of factorial function.
Using GL definition for discretization, the voltage for the kth sampling instant is written as:
1  
V ( k ) RI ( k ) D I (k ) 
C 

 D V ( k ) RD I ( k ) I ( k ) 
  1
C 
For multiple sample instants, the above equation can be rewritten in a matrix form as follows:
 DV (1)   D I (1) I (1) 
    
 D V (2)   D I (2) I (2) 
   R 

    

 
   1/ C 
 
  
 DV ( n )   D I ( n ) I ( n) 
  
 Y  AX 
T 
Y   DV (1) DV (2)   DV ( n )  
T 
X   R 1/ C  
Step 2: Implementation of G-L definition in DSP
It is to be noted that the fractional differentiation of a function f(x) at a particular sample instant
depends on all past samples of the function. In contrast, the integer order differentiation depends
only on the previous sample. In other words, IO differentiation is a local operation, whereas the
FO differentiation has a global nature. This feature of FO differentiation contributes to the memory
effect, which helps in modelling the dynamics of supercapacitor electrodes accurately. However,
including the complete past history for computing the FO differentiation at each sample instance
imposes heavy computational burden and large memory requirements on DSP. Hence, the number
of samples are limited to ‘L’ following the short memory principle [25]. The choice of appropriate
value of ‘L’ decides the accuracy of the characterization.
Each iteration for FO derivative using GL derivative requires the computation of gamma
function. Several analytical definitions of gamma function are available in the literature. Weir
strass theorem is one among them, which is used in this work. According to this theorem, the
gamma function can be expressed as follows:
z  
 x 1 
 ( x ) e x  1  e n 


n 1 n 

  0.577216, Euler-Mascheroni constant 
The limit of the power series in (2.9) cannot be infinity and hence needs to be chosen properly
to ensure the required accuracy. Similarly, (2.9) provides good accuracy only for x<1. The value
of gamma function for x>1, is hence calculated from the following property of gamma function:
 ( z  1)  z  ( z ) 

x  1, let y  trun ( x ) 
 ( x)  1  2       y  ( x  y ) 

Similar to the choice of the suitable value of ‘L’, the initial conditions also need to be
properly selected during the implementation. The G-L definition as expressed above is valid only
when the initial condition of the operating function is zero. Nevertheless, the following modified
definition based on the Jumarie type derivative can be employed for non-zero initial conditions:
1 L   
D f ( x ) lim   ( )m    f ( xmh) f (0) 
T 0 T m0 j 


   ( 1) 
   and f (0)Initialcondition 
 
j m! ( m1) 

The sampling time also determines the correctness of the computation. It is indeed logical
to assume that smaller the sampling time, better the results. However, it is to be noted that if the
limit, ‘L’ is kept constant, the minimum required sampling time for a preset accuracy varies as a
function of the operating conditions. In order to illustrate this, the variation of the values of ‘Cα’and
‘R’ of a supercapacitor during different sampling times (T) and ‘L’ is tabulated in Table 2.9.
Step 3: Implementation of least square algorithm
Least square approximation is commonly employed for identifying the parameters when the
number of equations for each iteration is much greater than the number of unknowns. This is the
case with the identification of the FOM of the supercapacitor. The basic structure of least square
implementation is given by the following equation:
Y  AX  X   AT A A Y
1 T
If the measurement error is large, so that the above equation does not have a solution, then the
minimization algorithm follows the following equation,
 
x   AT A
1 T
A Y X xe
where ‘e’ is the predefined error limit:
TABLE 2.9: DEPENDENCE OF IDENTIFIED FOM PARAMETERS ON ‘T’ AND ‘L’

Identified Values Actual Values
Cα(F/s(1- Cα((F/s(1-
L T R (Ω) α) R(Ω) α)
)
200 0.005 0.198 7.82 0.2 10
200 0.05 0.193 9.974 0.2 10
200 0.1 0.187 9.96 0.2 10
50 0.05 0.19 9.538 0.2 10
50 0.1 0.187 9.9 0.2 10
Step 4: Identification of ‘α’ value
It may be noted that the value of ‘α’ is assumed constant for each iteration of the above
steps, while computing ‘Cα’ and ‘R’ values. However, the value of ‘α’ is not constant but varies
between 0 and 1 and this variation, in turn, reflects in the value of ‘Cα’. Consequently, a wrong
choice of ‘α’ results in erroneous results. In order to tackle this situation, an outer loop is added in
the estimation algorithm, wherein the values of ‘Cα’and ‘R’ for all possible values of ‘α’ are
calculated. Further, the error between the experimental data and the FOM with all the identified
parameters are calculated. The value of ‘α’ which provides minimum mean square error (MSE) is
subsequently chosen and then ‘Cα’ and ‘R’ values are computed. The flow of the algorithm is
depicted in Fig. 2.15.
2
 Vx  Vmeas   
1 n
MSE 
n i 1
Computation of FO derivative Computation of α

Measure ‘n’ samples of V and I
G-L definition
 1 L m  (  1) i=1,α =0
D f ( x )  lim n  ( ) f ( x  mh)
h0 h m0 m !  (  m  1)
α (i)=α +0.1
YES Computation of Cα and R

Gamma function (z > 1) α (i) >1
 ( z  1)  z   ( z )
Find ‘α’ corresponding to
x  1, let y  trun( x ) NO min (MSE)→ α_id
 ( x)  1  2       y  ( x  y ) Compute Dα(i) V(1)…. Dα(i) V(n)
Compute Dα(i) I(1)…. Dα(i) I(n) Compute Dα_id V(1)…….. Dα_id V(n)
Gamma function (z <1)
z 
Compute Dα_id I(1)…….. Dα_id I(n)
 x 1 
 ( x )  e  1  e n
 x  Least square Fitting
 
 1 T
n 1  n X  AT A A Y
  0.577216, Euler  Mascheroni cons tan t Least square Fitting
 
1 T
1 N
2 X  AT A A Y
MSE   Vx  Vmeas   
N i 1
Fig. 2.15. Online identification of FOM parameters using GL derivative and least square fitting algorithm
Experimental Validation
In order to validate the proposed online estimation algorithm, several experiments were
conducted on various SCs using Autolab PGSTAT302N Potentiostat-Galvanostat and the
frequency response module FRA32M (Fig. 2.16). Firstly, the FOM parameters of each of the SCs
were identified through offline constant current charge-discharge tests. The experimental voltage
response data was fitted into the FOM based voltage equation using a curve fitting routine. The
value of the constant current was chosen arbitrarily, but the limit imposed by the manufacturer on
the maximum constant current was considered. The details of the supercapacitors and the identified
FOM parameters are given in Table. 2.10. Subsequently, the correctness of the FOM with the
offline-identified parameters in replicating the experimental results during some typical dynamical
load profiles were analyzed.
Autolab PGSTAT 302N SUPERCAPACITORS
DSP(TMS320f28379D)
Fig. 2.16. Experimental set up used for online identification of FOM
TABLE 2.10: FOM PARAMETERS IDENTIFIED FROM OFFLINE TESTS

Sample
Details I(A) Rs Cα α
No
1 1F,5.5V 0.1 A 1 0.147 0.42
2 25F,2.7V 0.5 A 0.02 20.1 0.83
3 50F,3V 0.5 A 0.02 25.54 0.81
4 300F,2.7V 1A 0.01 120.04 0.82
Fig. 2.17 depicts the voltage-characteristics from offline and online identified FO models
of the sample SCs with the experimental results. The need for online identification of the FOM
parameters is clearly visible from Fig.2.17. The discrepancy associated with the offline identified
FOM under varying operating conditions is already explained. The variation of the online-
identified FOM parameters with time is depicted in the bar graph given in Fig. 2.18. It may be
noted that for the sake of clarity in the representation, instead of showing the variation of ‘C α’
directly, the variation of its normalized value (which is defined as ‘Cα/ Cnominal’) is plotted in Fig.
2.18 (b). Cnominal is plotted along the horizontal axis. Similarly, the variation of R/ 100 is provided
in the bar graph as the value of ‘R’ for 1F supercapacitor is much higher than the other sample
SCs. It can be observed that, the variation of ‘R’ among the indicated zones of each supercapacitor
is almost negligible as compared to the variation in ‘Cα’ and ‘α’. For example, consider the case
of the 300F supercapacitor for which the value of ‘α’ varies from (0.4-0.8) and ‘Cα’ varies from
(140-266) F/s (1- α).
These results indicate considerable deviation in the effective/utilizable capacitance under
different operating regions. This variation in the capacitance value in turn affect the state of charge
(SOC) and state of health (SOH) measurements. The capacitance value also varies with
temperature and ageing and online estimation of the parameters is expected to take care of these
effects inherently thereby ensuring accurate characterization of supercapacitors.
Voltage(V)
Exp. Result Online FOM (c)
Voltage(V)
v
v
Exp. Result
Offline FOM
v
(a) Offline FOM
Online FOM
Voltage(V)
(d)
Voltage(V)
Offline FOM
Online FOM
Online FOMExp. Result
(b) Exp. Result Online FOM
Offline FOM
Time(s)
Time(s)
Fig. 2.17. Comparison of the voltage response of the super capacitor from the experiment with the
predicted response with online-adaptive and non-adaptive FOM (a) 1 F (b) 25 F (c) 50 F (d) 300 F
Zone1 Zone2 Zone3 Zone4

1 ‘α’
0.8
0.6
0.4 (a)
0.2
0
1F 25F 50F 300F
1 Cα/Cnominal
0.8
0.6
(b)
0.4
0.2
0
1F 25F 50F 300F
0.04
R
0.03
(c)
0.02
0.01 R ∕100
0
25F 50F 300F 1F
Fig. 2.18. Variation of FOM parameters of different supercapacitors: (a) Variation of α; (a) Variation of
Cα; (c) (a) Variation of R.
To validate the above statements and to evaluate the graveness in the error in the estimated
SOC from offline FOM, extensive studies were carried out.
Method 1: Coulomb counting
As a first step of this study, the SOC of several SCs was calculated from coulomb counting
method using the following equation
t final 

 Idt  SOCinitial 

t
SOC (%) init 
SOCno min al 

SOCno min al  Cno min al Vrated 
Method 2: FOM based SOC estimation

Subsequent to the Coulomb counting method, the SOC values of the same set of SCs were
estimated from FOM based method. The following equations were employed for the FOM based
SOC estimation.
 
C  DV ( k ) D I ( k )R  I ( k ) 


SOC ( k )  I ( k )T  SOC ( k 1) 


 
C  DV ( k ) D I ( k )R T  SOC ( k 1) 


SOC (%) SOC ( k ) 
SOCno min al 

The test results shown in Fig.2.19 prove that the online model predicts the SOC more accurately
than the offline FOM.
Online FOM
SOC(%)
Coloumb counting
Offline FOM
Time(s)
Fig. 2.19. SOC estimation of 25F, 2.7V supercapacitor (sample 2, Table.2.10) from online and offline
FOMs and Coulomb counting method.
Chapter 3
Standardizing the characterization methods of
supercapacitors
Most of the characterization methods defined by IEC standards are based on the assumption
that a constant series RC model can represent the characteristics of a supercapacitor. The
inaccuracy of such a model owing to the porous nature of the SC electrodes and its resulting effect
in the design of SC systems are already detailed in the previous chapter. This chapter presents
some of the modifications in the characterization of the supercapacitors considering the inferences
obtained from the analysis based on a FOM.
Differentiating the characteristics of charge redistribution from the leakage of

supercapacitors
Porous structure causes charge redistribution, resulting in voltage rise or voltage drop after
every discharging and charging cycles respectively. The pattern and the amount of this voltage rise
or drop depends on the charge/discharge history. This charge redistribution is not to be confused
with leakage as in this case there is no loss of charge. However, it results in retention of some of
charges inside the pores. These charges may not be available for immediate discharge as compared
to the charges on the surface and hence affects the charge-discharge efficiency. The study of these
characteristics can therefore help in proper designing of the system by optimizing the sizing,
charging pattern and estimating the actual state of the available charge from the system.
As mentioned before, because of the charge redistribution, it is not possible to extract the
complete stored charge from a supercapacitor in one discharging cycle. However, with multiple
discharge-redistribution cycles, it is possible to extract the complete charges from the
supercapacitor. Fig. 3.1 shows the experimental results of a multiple charge redistribution
experiment conducted on a 25 F, 2.5V, PowerStor supercapacitor.
First discharge-Redis Cycle
Fig.3.1. Experimental results of Multiple Charge Redistribution Test Conducted on 25F,2.5V, PowerStor
Supercapacitors
It has been observed that the initial variation in the voltage during the rest period is fast as
compared to the drop in the voltage after significant period. . It is assumed that the typical variation
of this characteristics follows Mittag-Leffler behavior during this phase. At a particular time, the
leakage starts dominating the voltage drop as compared to the charge redistribution. If this
variation due to the leakage is approximated by a linear curve, the leakage current can be calculated
as follows:
𝑑𝑉
𝐼𝑙𝑒𝑎𝑘𝑎𝑔𝑒 = 𝐶𝑒𝑞𝑢𝑖𝑣𝑎𝑙𝑒𝑛𝑡 𝑑𝑡
𝑑𝑉
= 𝑠𝑙𝑜𝑝𝑒 of the linear portion
𝑑𝑡
𝐼𝑙𝑒𝑎𝑘𝑎𝑔𝑒 = 𝐶𝑒𝑞𝑢𝑖𝑣𝑎𝑙𝑒𝑛𝑡 × 𝑠𝑙𝑜𝑝𝑒

𝐼𝑐ℎ𝑎𝑟𝑔𝑒 ×(𝑡2 −𝑡1 )
𝐶𝑒𝑞𝑢𝑖𝑣𝑎𝑙𝑒𝑛𝑡 = , where t2 and t1 are the time instants corresponding to the capacitor
(𝑉2 −𝑉1 )
voltages V1 and V2 respectively.
Modified parameter identification method after initial conditioning of the

supercapacitors
The parameters of most of the RC models (simple RC, three branch model, transmission line
network etc.) of supercapacitors are identified from the characterization plots obtained from various tests
as defined by IEC standards. These IEC tests mandates short-circuiting the supercapacitors for more than
48 hours before conducting the tests so that the complete residual charges trapped in the porous electrodes
are extracted. However, during our studies it was observed that this methodology could give wrong
indication of the utilizable capacitance. If the supercapacitor is completely discharged, (short-circuited for
sufficiently long, to ensure no residual charges), the initial charging cycle will be longer as compared to the
consecutive cycles. In other words, the charge required to reach a specific voltage will be higher during the
first cycle. In order to verify this, a repeated constant current charging-discharging test is conducted on a
25F, 2.7V, supercapacitor (Fig.3.2 (a)). The results of the tests are tabulated in Table. 3.1.
It can be observed that, the Qcharge (Ist cycle) = 85 C, however after 10 cycles, the Qcharge settle down
to 63 C. The charge extracted during the consecutive cycle remains the same. Based on this analysis, it is
clear that the residual charge (Q_IstCycle – Q_Steady state) is not available for immediate discharge. Hence,
accounting the residual charge for identifying the parameters of SC models may not be helpful in the design
of any applications. In this regard, it is better to define the model parameters based on the steady state
charge. Considering this observation into account, a slight modification in the testing procedure for
identifying the parameters of any SC model is advisable. Accordingly, instead of conducting the tests
directly on a fresh supercapacitor (or completely discharged SC), the SC is subjected to multiple CC charge-
discharge pulses such that a steady state charge state is reached (Fig.3.2 (b)). The intended tests are
performed on the SC following this initial conditioning. After conducting experiments on several
commercial SCs, the typical number of initial conditioning charge-discharge cycles is taken to be 7-10.
Table. 3.1. Impact of cycle number on the Residual charge (Vinit=0V)
Voltage Q extracted CC Mode (cycle) Voltage Q extracted CC Mode (cycle)

2.7V 85.5C 3A Charging (1) 2.7V 63.3 C 3A Charging(11)
2.7V 60.9 C 3A Discharging (1) 2.7V 61.2 C 3A Discharging(11)
2.7V 70.5 C 3A Charging(2) 2.7V 63.6 C 3A Charging(12)
2.7V 61.5 C 3A Discharging(2) 2.7V 61.2 C 3A Discharging(12)
2.7V 64.2 C 3A Charging (7) 2.7V 63.0 C 3A Charging(17)
2.7V 61.5 C 3A Discharging (7) 2.7V 61.2 C 3A Discharging(17)
Voltage (volts)
Time (Seconds)
Fig.3.2. (a) Repeated constant current charge-discharge tests, Vinit= 0V, (b) Modified Parameter identification using
pulse conditioning
Utilizable capacity (UCTY)
Practical supercapacitors have a complex porous structure with different sizes (e.g. 1 nm -
50 nm) and shapes (cylindrical, funnel shaped etc.) of pores. The accessibility of each of these
pores and in turn their charge storing capacity vary differently depending upon the operating
conditions. For example, if the capacitor is subjected to fast charging, the pore depths remain
inaccessible while charging. As a result, charges accumulate only on the surface of the pores,
resulting in a rise of terminal voltage to the rated value, without utilizing the complete storage
capacity. However, with time, the charges on the surface redistribute occupying the inner areas of
the pores. For the same charge, as more capacitance becomes available, the voltage drops.
Similarly, following a sudden discharge, the voltage rises back after rest period.
The amount of drop/rise of the voltage following a charging/discharging cycle is dependent
on the charging history like the magnitude of charging current [Fig 3.3(a) and Fig 3.3(b)], level of
voltage, duration of charging and so on. This charge redistribution is not to be confused with
leakage as in this case there is no loss of charge. However, it results in retention of some of the
charges inside the pores. These charges are not available for immediate discharge as compared to
the charges on the surface and hence affect the charge-discharge efficiency or in other words
determine the utilizable SOC.
10 A 2A
10 A 2A
Fig.3.3. Experimental results of Charge Redistribution Test s(a) Voltage Drop) following CC charging (b)
Voltage Rise following CC discharging
Utilizable Capacity (UCTY) is defined as the charge, which can be extracted from a
supercapacitor resting at a particular voltage after redistribution. Resting condition implies that the
capacitor is open circuited and is not connected to any voltage source or load. It is to be noted that
this is not the same as the total charge stored inside the capacitor (actual SOC). In other words,
depending on the charging history there will be some residual charge stored inside the pores of the
supercapacitor, which is not extracted in one discharging cycle. Nevertheless, with multiple
discharge-redistribution cycles, it might be possible to extract the most of the stored charges from
the supercapacitor. The information of the utilizable charge during a single discharge cycle is
however desirable for the design of the power sharing algorithms.
In order to understand the concept of utilizable capacity, several tests are conducted on
different commercially available supercapacitors. Fig. 3.4 shows the result of one of such tests
conducted on a 25F, 2.7V supercapacitor. Before conducting the test, the supercapacitor is short-
circuited for sufficiently long time (100 hours) to ensure that it is completely discharged. The
procedure of the test is explained in Table 3.2. The details of charge stored, redistributed and
extracted in each cycle is provided in Table 3.3.
Table 3.2: Procedure of the test conducted on a 25F, 2.5V supercapacitor
STEP1:0.5 A CC Charge till V=2.49 V
STEP2: REST for 300 s
TEST STEP3: 2 A CC Discharge till V=0.007V
PROCEDURE STEP4: REST for 2000 s
STEP5: 2 A CC Discharge till V=0.009V
STEP6: REST for 1000 s
REST REST
Fig.3.4 Experimental results of multiple charge discharge test of a 25F, 2.7V supercapacitor
Table 3.3: Results of the test conducted as per Table.3
STEP1 Qchg = 64.69 C, Vfinal = 2.49 V

STEP2 Voltage drops, Vfinal = 2.24 V
STEP3 Q dishg = 47.31 C, Vfinal = 0.007 V
STEP4 Voltage rises, Vfinal = 0.3612 V
STEP5 Q dishg = 3.75 C, Vfinal = 0.009V
STEP6 Voltage rises, Vfinal = 0.2159 V
It is to be noted from Table 3.3 that the charge available inside the supercapacitor after 0.5
A constant current charging (step 1) is 64.9C. However, the charge extracted during Step 3 is only
47.31 C. In order to check whether the extra charges are still present inside the porous electrodes,
the supercapacitor is allowed to rest so that the charges inside the depth of the pores can resurface.
During this rest time (Step 4) voltage rises, indicating the presence of the charge inside the pores.
During step 5, supercapacitor is subjected again to a 2A discharge and 3.75C is extracted. By
continuing the same procedure, most of the charge can be extracted. It is observed that even though
the total available charge (actual SOC) is 64.9C, the extracted charge in the consecutive cycle is
considerably less (47.31 C). This extractable charge (Utilizable SOC) is what must be known for
the proper design of an SC system for any application.
Estimation of UCTY
After conducting various tests on several commercially available supercapacitors, it is
observed that the UCTY follows some empirical relations with the operating current and the
resting voltage (Fig.3.5). The major observations are as follows:
1. UCTY is independent of the charging history, but depends only on the voltage at rest and the
discharging current magnitude.
Consider two 25F supercapacitors, charged with 60C and 50C respectively. After keeping them at
rest for sufficient time (say t1 and t2 respectively), let the voltage across both the supercapacitors
reach the same value (say 1V). These two capacitors are now subjected to a constant current
discharge (say 1 A CC discharge). The extracted charge from both the supercapacitors remains the
same
2. A linear relation (Fig.3.5) can represent the variation of UCTY with the discharging current
magnitude.
Consider a supercapacitor resting at voltage ‘V1’. The UCTY follows an approximate linear
relation with the discharging current. As the current increases, the UCTY decreases. An example
of the variation of UCTY with current magnitude is given in Table 3.4. The results were from the
tests conducted with a 25F, 2.5 V supercapacitors
3. The variation of UCTY with the voltage magnitude also follows a linear relation (Fig.3.5).
As voltage increases the UCTY increases linearly. Table 3.5 provides the variation of UCTY with
voltage of a 25F, 2.5 V supercapacitors
Table 3.4: UCTY with current Table 3.5: UCTY with voltage
Current UCTY
Voltage UCTY
1A 20.36C
1V 20.88C
2A 20.19C
1.5 V 34.47C
3A 19.79C 49.74C
2V
The test results of 25F, 2.5V depicting the variation of the capacitance with voltage and current is
given in Fig. 3.5.
Capacitance (F)
0.1 A 1A
Voltage(V)
Capacitance (F)
1V 1.5 V 2V
Current (A)
Capacitance (F)
Fig.3.5. (a) Capacitance versus voltage (b) Capacitance versus current

(c) 3D plot of Capacitance_Voltage_Current
Empirical estimation of UCTY

Based on the above inferences, if the range of load current is known, the UCTY of any
supercapacitor can be calculated with the help of some simple offline tests.
Step 1: Conduct two constant current charge tests on the fresh capacitor (fully discharged
capacitor) at Imax and Imin, where Imax and Imin corresponds to the maximum and minimum current
expected for the particular application. Charge till the capacitors reach the rated voltage.
Step 2: Calculate the total charge stored at different voltages either by using Ampere counting
method or by using the charge equation specified in the previous section.
Step 3: Calculate the utilizable capacitance corresponding to each voltage and current as follows:
1
UCTY  Qchg Vc  c  (1   )t
Step 4: Make a look up table or devise Ceq_Vc and Ceq_I relation based on this data. Use this online
for calculating the UCTY.
Experimental validation of the empirical relation.
In order to validate the procedure described in the previous section, constant current charging
tests (at 0.1A,1A,2A,3A) of completely discharged (Short circuited for 48 hours) 25F, 2.5 V,
PowerStor/Eaton supercapacitors were conducted. From the tests, UCTY corresponding to
different voltages and currents are calculated and tabulated as given in Table.4. Further CC charge
and discharge tests of some capacitors resting at different voltage and having different charge
history are conducted. The measured value of UCTY is found to be matching perfectly with the
UCTY predicted based on Table.3.6. The validation test details are given in Table.3.7.
Table.3.6. UCTY of 25F, PowerStor from CC Tests
Voltage 1V 1.5V 2V
Current
0.1 A 20.88F 22.98F 24.87F
1A 20.36F 22.08F 23.53F
2A 20.19F 22.12F 23.58F
3A 19.79 21.98 23.83
Table.3.7. Experimental results comparing UCTYMeasured and UCTYPredicted

Sample Test UCTYMeasured UCTYPredicted
25F,2.5V Discharged from 0.73V at 0.1A CC 14.7 C 14.785 C
PowerStor/ Discharged from 0.99V at 0.1A CC 20.5 C 20.687 C
Eaton Discharged from 2.5 V at 10A CC 42 C 42.08 C
Charged to 2.4V at 5A CC 48.5 C 49 C
Characterization of CMET supercapacitors

As part of this project several bundles of CMET SCs were delivered to IIT Bombay.
Several characterization tests were conducted on these SCs and based on those tests performance
analysis reports were made and conveyed to CMET. This section summarizes the details of the
tests conducted on CMET capacitors and provides the major inferences and results drawn from
these tests. The different tests include:
(a) Capacitance and ESR measurement test from constant current charge discharge tests based on
IEC 62391 standard
(b) Capacitance, ESR and ESL measurement from EIS (frequency response analysis using Autolab
PGSTAT302N potentiostat-galvanostat instrument)
(c) Repeatability of the capacitance value over different cycles
(d)Variation of charge redistribution pattern over various charging history
(e) Fractional order behavior.
(f) Charge-discharge efficiency/ charge retention measurement
(g) Leakage current measurement
Test 1: Constant current charge-discharge test for measurement of the capacitance and ESR
Procedure:
Step 1: Short-circuit the capacitors for more than 48 hours.
Step 2: Perform constant current charging experiment on the capacitors.
Step 3: Maintain few seconds of rest period.
Step 4: Perform constant current discharging experiment on the capacitors. The value of the set
constant current is chosen as per the IEC 62391 standard as illustrated in Table 3.8.
TABLE 3.8: DISCHARGE CONDITIONS AS SPECIFIED BY IEC 62391 STANDARDS

Classification Class 1 Class 2 Class 3 Class 4
Application Memory Backup Energy Storage Power Instantaneous
Power
Charge time 30 min 30 min 30 min 30 min
I(mA) 1× C 0.4 × CUR 4 × CUR 40 × CUR
U1 80% of charging voltage (0.8 × UR)
U2 40% of charging voltage (0.8 × UR)
NOTE: C is the rated capacitance and UR is the rated voltage
Step 5: Calculate the capacitance from the slope of the curve and the ESR value from the initial
value of the drop in the voltage as follows
V1 t
V2
Current (A)
I t
1A C
(V3  V2 )
0A V1
V3 ESR 
I
-1A
Fig.3.6. Constant Current charge-discharge tests

Test 2: Capacitance, ESR and ESL measurement from EIS (frequency response analysis
using Autolab PGSTAT302N potentiostat-galvanostat instrument)
From the project equipment fund, Autolab N-series potentiostat-galvanostat with a frequency
response analysis (FRA) module (manufactured by Metrohm) was procured. The details of the
equipment relevant for the tests conducted for this project are tabulated in Table 3.9.
TABLE 3.9: KEY FEATURES OF PGSTAT 302N WITH BOOSTER10A AND FRA32M
MODULES
Key features Details
Potential range +/- 10 V
Maximum current +/- 2 A (20 A with BOOSTER10A)
Minimum current 10 nA
Potential resolution 0.3 µV
Current resolution 0.0003 % (of current range)
Input impedance > 1 TΩ
Potentiostat bandwidth 1 MHz
Frequency range 10 µHz - 1 MHz
Frequency resolution 0.003 %
AC amplitude 0.2 mV to 0.35 V
Autolab provides the results of the frequency response analysis in the form of Nyquist and
Bode plot in a graphical interface ‘NOVA’. The obtained results can be analyzed using different
circuit models in this software. These analyses can give information regarding the capacitance,
ESR, ESL and the different cut off frequencies/ time constants of the SCs. The basic FRA
characteristics of most of the CMET capacitors appears similar to Fig.2. The total characteristics
can be broadly divided into three zones for better analysis. Zone 1 corresponds to the low
frequency region, Zone 2 is the semi-circle region and Zone 3 is the inductive region. The real part
of the impedance at the starting of the Zone 1 is assumed as Rdc and the real part of the impedance
at the starting of the Zone 2, i.e. starting of the semi-circle is a taken as Rac. Zone 3 corresponds to
the region where the ESL dominates. The capacitance is calculated from the impedance
corresponding to the starting frequency of Zone 1.
ZONE 1
1
C (From thestarting of Zone1) 
Rac 2    f  Z ''
Rdc  Z '(@ thestarting of Zone1)
Rdc Rac  Z '(@ thestarting of Zone 2)
ZONE 2 ESL (From Zone 3)  2    f  Z ''
cut off frequency1  f Zone1 Zone 2
cut off frequency 2  f Zone 2  Zone3
Nyquist plot obtained from the FRA analysis
of a CMET capacitor
Fig.3.7. FRA analysis of a CMET capacitor
Test 3: Repeatability of the capacitance value over different cycles

Inorder to test the whether the capacitance value obtained from Test 1 is consistent over
various cycles; repeated charge-discharge test is conducted on the SCs. The capacitance is
continuously monitored over the cycles. The value of the charge-discharge current is chosen
similar to Test 1.
Test 4: Variation of charge redistribution pattern over various charging history
The rest time behavior of the CMET capacitors are studied for different charging history.
The brief procedure of the tests is as follows:
Step 1: Short-circuit the capacitors for more than 48 hours.
Step 2: Perform constant current charging experiment on the capacitors.
Step 3: Keep the SC in the open circuit condition continuously for 6-12 hours and record the
variation in the open circuit voltage appearing across the SCs during the rest time
Step 4: Perform the constant current discharging experiment and continue step 3
Step 5: Repeat Step 1-4 for different value of currents.
Test 5: Fractional order behavior of the CMET capacitors

The CMET capacitors exhibit clear fractional order behavior throughout the frequency
range. Zone1 (Low frequency) behavior could be approximated by a series R-CPE model and Zone
2 (Semi circle region) by a randles circuit model (Fig.3.8). In order to identify the parameters of
the FOM in the respective frequency range, FRA tests were conducted and the resultant response
plots were cure fitted with the corresponding models. The fractional order behavior of the
capacitors were reflected in the time domain response also, which is validated by comparing the
voltage responses from constant resistance and constant current tests with FOMs.
CPE 2
R CPE Rs
R CPE 1
(a) (b)
Fig.3.8. (a) Series R-CPE model (Low frequency zone) (b) Randles circuit model (Semicircle region)
Test 6: Charge-discharge efficiency/ charge retention measurement

Because of the charge-redistribution associated with the porous electrodes, the amount of charge
available for immediate discharge from a charged SC varies with the charging history. The residual charge
in an SC can be calculated from an FOM as explained in the previous section. The following tests were
conducted to study the utilizable capacity (UCTY) of a supercapacitor under different charging profiles.
(1) Charge the SC with a constant current (CC) followed by constant voltage (CV). Subsequently, discharge
the SC immediately with the same magnitude of charging current (CC) without any rest time. Record the
total stored charge during CC-CV charging and the extracted charge during the CC discharge. Repeat the
experiment with a different value of current and the retention time of CV charging. Calculate and tabulate
the charge-discharge efficiency from each case.
(2) Charge the SC with a constant current (CC) followed by a rest time. Subsequently, discharge the SC
immediately with the same magnitude of charging current (CC). Record the total stored charge during CC
charging and the extracted charge during the CC discharge. Repeat the experiment with a different value of
resting times. Repeat the test with different magnitude of current.
(3) Charge the SC with different constant current (CC) values until they reach the rated voltage, say ‘V2
and then allow them to rest. The time of rest should be taken such that the final value of the voltage for
each case is same, say ‘V1’. Discharge the SC immediately with a same magnitude of current (CC). Later
repeat the procedure with different magnitude of discharging current.
Test 7: Leakage current measurement

It has been observed that the initial variation in the voltage during the rest period is fast as
compared to the drop in the voltage after significant period. At a particular time, the leakage starts
dominating the voltage drop as compared to the charge redistribution. If this variation due to the
leakage is approximated by a linear curve, the leakage current can be calculated as follows:
dV dt
I leakage  Cequivalent  , where Cequivalent  I charge 
dt dV
dV
 slope of the linear portion
dt
Fig. 3.9. Leakage current measurement from the linear part of the rest time characteristics
Summary of the major results of the tests conducted on CMET Supercapacitors

(1) Constant current charge-discharge test for measurement of the capacitance and ESR
ASC category-25F
Tested at IIT Bombay Tested at C-MET
Sample I=0.5 A I =2A
Cap(F) ESR(Ω) Cap(F) ESR(Ω) Cap(F) ESR(Ω)

TB729 46.42 0.84 18.4 0.896 25±10% 240 mΩ
TB730 44.12 0.267 25.159 0.312 25±10% 145 mΩ
TB714 39.39 0.299 15.46 0.345 25±10% 110 mΩ
TB751 27.94 0.25 18.02 0.29 25±10% 175 mΩ
TB679 38.67 0.818 6.566 0.9145 25±10% 187 mΩ
TB683 37.64 0.28 16.79 0.333 25±10% 100 mΩ
TB725 33.95 0.412 24.16 0.405 25±10% 240 mΩ
TB756 27.99 0.356 19.24 0.355 25±10% 200 mΩ
TB734 41.69 0.228 22.106 0.24 25±10% 100 mΩ
TB755 29.62 0.28 19.89 0.285 25±10% 175 mΩ
TB752 27.27 0.437 19.37 0.367 25±10% 200 mΩ
TB749 32.01 0.134 25.98 0.184 25±10% 100 mΩ
TB723 40.02 0.552 14.601 0.667 25±10% 160 mΩ
TB750 28.38 0.098 20.29 0.146 25±10% 100 mΩ
TB728 35.39 0.2608 26.02 0.193 25±10% 120 mΩ
TB718 54.58 0.546 19.28 0.633 25±10% 165 mΩ
TB682 43.97 0.3044 19.12 0.3815 25±10% 100 mΩ
TB719 45.52 0.2836 26.66 0.3385 25±10% 150 mΩ
TB726 33.65 0.207 24.19 0.2495 25±10% 155 mΩ
TB678 34.49 0.48 13.85 0.579 25±10% 137 mΩ
TB747 29.83 0.166 21.14 0.256 25±10% 160 mΩ
TB757 31.63 0.138 24.57 0.1635 25±10% 100 mΩ
TB687 26.41 0.244 17.82 0.268 25±10% 146 mΩ
TB753 27.90 0.258 20.0527 0.212 25±10% 125 mΩ
TB732 56.60 0.207 25.54 0.2165 25±10% 125 mΩ
TB704 37.02 0.4 15.00 0.4768 25±10% 130 mΩ
TB746 30.08 0.298 20.13 0.291 25±10% 190 mΩ
TB721 54.25 0.576 15.44 0.7257 25±10% 200 mΩ
TB731 45.60 0.342 19.45 0.3968 25±10% 125 mΩ
TB724 32.53 0.1412 23.08 0.145 25±10% 100 mΩ
TB693 30.20 0.915 4.58 0.993 25±10% 175 mΩ
TB748 31.95 0.1006 22.83 0.146 25±10% 100 mΩ
TB676 35.03 0.2903 22.64 0.292 25±10% 100 mΩ
TB735 28.18 0.306 20.26 0.298 25±10% 190 mΩ
TB686 50.10 0.405 17.485 0.437 25±10% 100 mΩ
TB717 37.06 0.292 23.67 0.29 25±10% 175 mΩ
ASC Category-15F
Tested at CMET Tested at IITB
SN ASC ID Cap(F) ESR (mΩ) Cap(F) ESR (Ω)
1 TB-610 15 F ± 10 % 230 mΩ 15 F ± 30 % 1.11 Ω
2 TB-611 15 F ± 10 % 240 mΩ 15 F ± 30 % 1.3 Ω
3 TB-613 15 F ± 10 % 250 mΩ 15 F ± 20 % 1.32 Ω
4 TB-620 15 F ± 10 % 250 mΩ 15 F ± 20 % 0.816 Ω
5 TB-621 15 F ± 10 % 220 mΩ 15 F ± 20 % 0.474 Ω
6 TB-622 15 F ± 10 % 200 mΩ 15 F ± 30 % 1.07 Ω
7 TB-623 15 F ± 10 % 225 mΩ 15 F ± 20 % 0.625 Ω
8 TB-624 15 F ± 10 % 230 mΩ 15 F ± 20 % 0.602Ω
9 TB-627 15 F ± 10 % 225 mΩ 15 F ± 35 % 1.35 Ω
10 TB-630 15 F ± 10 % 215 mΩ 15 F ± 35 % 0.742 Ω
ASC Category-25F
SN ASC ID Cap(F) ESR (mΩ) Cap(F) ESR (mΩ)
1 TB-580 25 F ± 10 % 230 mΩ 25 F ± 20 % 773 mΩ
2 TB-581 25 F ± 10 % 190 mΩ 25 F ± 20 % 550 mΩ
3 TB-583 25 F ± 10 % 190mΩ 25 F ± 20 % 406 mΩ
4 TB-584 25 F ± 10 % 185 mΩ 25 F ± 20 % 620 mΩ
5 TB-585 25 F ± 10 % 175 mΩ 25 F ± 20 % 370 mΩ
6 TB-588 25 F ± 10 % 170 mΩ 25 F ± 20 % 337 mΩ
7 TB-589 25 F ± 10 % 190 mΩ 25 F ± 20 % 502 mΩ
8 TB-590 25 F ± 10 % 175 mΩ 25 F ± 20 % 835 mΩ
9 TB-591 25 F ± 10 % 190 mΩ 25 F ± 20 % 571 mΩ
10 TB-592 25 F ± 10 % 185 mΩ 25 F ± 20 % 576 mΩ
ASC Category-35F
SN ASC ID Cap(F) ESR (mΩ) Cap(F) ESR (mΩ)
1 TB-552 35 F ± 10 % 140 mΩ 35 F ± 20 % 471 mΩ
2 TB-553 35 F ± 10 % 150 mΩ 35 F ± 20 % 407 mΩ
3 TB-554 35 F ± 10 % 170mΩ 35 F ± 20 % 430 mΩ
4 TB-555 35 F ± 10 % 227 mΩ 35 F ± 35 % 713 mΩ
5 TB-560 35 F ± 10 % 165 mΩ 35 F ± 20 % 320 mΩ
6 TB-561 35 F ± 10 % 180 mΩ 35 F ± 30 % 506 mΩ
7 TB-562 35 F ± 10 % 190 mΩ 35 F ± 30 % 351 mΩ
8 TB-563 35 F ± 10 % 205 mΩ 35 F ± 30 % 610 mΩ
9 TB-595 35 F ± 10 % 240 mΩ 35 F ± 20 % 128 mΩ
10 TB-597 35 F ± 10 % 240 mΩ 35 F ± 35 % 809 mΩ
First samples (5F – 42 mA and 10F – 92 mA)
Sample 268- 269- 270- 271- 272- 274- 276- 277-5F 278- 279-
number 10F 10F 10F 10F 10F 5F 5F 5F 5F
ESR(Ω) 3.283 5.124 5.054 4.25 5.254 5.595 6.76 9.7619 5.4285 9.9047
C(F) 8.8 7.7 7.9 8.2 6.8 4.2 5.1 4.4 5.2 4.2
First samples (5F – 4.6 mA and 10F – 9.2 mA)
Sample 268- 269- 270- 271- 272- 274- 276- 277- 278- 279-
number 10F 10F 10F 10F 10F 5F 5F 5F 5F 5F
ESR(Ω) 11.75 4.68 5.729 3.33 5.833 5.76 6.875 9.761 12 20
C(F) 6.5 14.6 15.6 14.2 12.5 6.8 7.0 4.4 7.1 7.3
Latest samples
Capacitor S. No. ESRCharge ESRdischarge Ccharge Cdischarge
TB35F capacitors
TB839 0.538 0.504 47.31 23.27
TB837 0.519 0.4814 52.78 27.38
TB842 0.5534 0.420 58.36 43.9
TB798 0.4468 0.3906 60.95 38.79
TB821 0.4915 0.438 61.53 30.79
TB810 0.578 0.4785 60.155 46.18
TB815 0.816 0.916 30.5 11.25
TB828 0.654 0.6578 49.936 27.05
TB844 0.985 0.802 67.9 27.55
TB826 0.519 0.473 71.12 37.97
TB819 0.504 0.471 48.54 36.93
TB813 0.317 0.3162 62.52 39.54
TB809 0.4186 0.386 59.261 33.184
TB25F Capacitors
TB857 1.02 1.0 22.53 15.7
TB889 1.55 1.29 26.48 20.7
TB866 1.325 1.28 26.107 17.53
TB858 0.68 0.65 24.2 19.07
TB861 0.7435 0.7755 25.2 20.8
TB855 1.675 1.670 23.26 14.73
TB856 1.12 1.085 23.787 16.72
TB879 0.81 0.74 26.38 21.84
TB881 1.365 0.97 28.62 21.75
TB850 1.475 1.37 24.26 17.17
Sample Results (As per IEC standard)

TB734
C=30.66F, R=0.415Ω
TB757
C=37.88F, R=0.315Ω
TB726
C=34.74F, R=0.257Ω
(2) Capacitance, ESR and ESL measurement from frequency response analysis
ASC- 15RL (TB610 to TB630)

Frequency response analysis results-Bode Magnitude plot (Left) and Bode Phase plot (Right)
Frequency response analysis results-Nyquist plots of ASC- 15RL (TB610 to TB630) (Left), ASC
Category: ASC- 25RL (TB580 to TB592) (Middle) ASC Category: ASC- 35RL (TB552 to TB597)
(Right)
SN ASC ID C(F) Rdc (Ω) Rac (Ω) ESL fZone1-2 fZone2-3
1 TB-693 25 F ± 10 % 1.54 Ω 0.32 Ω - 1.04 Hz >10000
2 TB-729 25 F ± 10 % 1.76 Ω 0.09 Ω - 0.32 Hz >10000
3 TB-748 25 F ± 10 % 0.10 Ω 0.04 Ω 0.6 nH 17.57 Hz 7906
4 TB-750 25 F ± 10 % 0.093 Ω 0.04 Ω 0.39 nH 22.23 Hz 7906
(3) Repeatability of the capacitance value over different cycles

Sample Cycle Ccharge Cdischarge
TB560 1 34.29352 25.71479
2 29.02894 28.85007
3 28.62651 28.82837
4 28.45574 28.90461
5 28.34351 28.8394
TB555 1 25.01461 13.98185
2 18.88723 19.1075
3 18.39945 19.22481
4 18.24044 19.43215
5 18.19518 19.62877
TB554 1 37.89152 25.98981
2 30.46376 30.11231
3 29.99126 30.15126
4 29.83771 30.33685
5 29.78327 30.33516
TB553 1 36.87667 24.41832
2 30.06188 28.46709
3 29.08147 28.52281
4 28.77064 29.6559
5 28.60712 28.72029
TB552 1 36.36538 25.98981
2 28.49796 30.11231
3 27.94849 30.15126
4 27.75761 30.33685
5 27.65632 30.33516
(4) Variation of charge redistribution pattern over various charging history

The amount of drop/rise of the voltage during the rest time following a
charging/discharging cycle is dependent on the magnitude of charging/ discharging current. When
the current magnitude is high, smaller pores and the depth of the other pores won’t be accessible
during charging/discharging. Whereas the surface of the pores will be filled rising the voltage to
the rated value. During the rest time, charge redistribute and occupy the rest of the surface.
Similarly, only the surface charges can be extracted with a higher magnitude of current during
discharge. When allowed to rest, the charged redistribute resulting in a rise of the voltage. The
time constant of the charge redistribution is quite high as compared to the charging/ discharging
time constant.
CC Charging At 0.2 A
Rest (Open circuit)

CC Discharging At 0.2 A
Rest (Open circuit)
(5) Fractional order behavior of the CMET capacitors
From time domain response (constant current tests)

Sample 268- 269- 270- 271- 272- 274- 276- 277- 278- 279-
number 10F 10F 10F 10F 10F 5F 5F 5F 5F 5F
Rs 0.0958 3.8227 4.1124 2.8980 4.44 3.30 4.868 6.091 3.810 7.976
Cn 3.6087 1.3540 2.4575 2.8061 2.06 1.36 1.744 1.272 1.851 0.995
α 0.8006 0.5978 0.7342 0.7659 0.69 0.73 0.761 0.712 0.774 0.666
Sample 268- 269- 270- 271- 272- 274- 276- 278- 279-
number 10F 10F 10F 10F 10F 5F 5F 5F 5F
Rs 6.806 4.48 2.139 2.780 4.05 4.87 5.94 5.327 5.10
Cn 3.303 7.55 4.16 4.38 4.16 1.28 2.03 2.17 4.21
α 0.92 0.91 0.82 0.81 0.80 0.78 0.83 0.83 0.92
From frequency domain analysis
Sample Zone R Cα α
TB704 0.01 Hz- 0.1Hz 472 mΩ 6.35 F/s(1-α) 0.734
TB748 150mΩ 11.3 F/s(1-α) 0.817
(7) Leakage current measurement
Samples Results
TB657 Cequivalent = 70 F Ileakage = 579 µA
TB757 Cequivalent = 38.73 F Ileakage = 1.34 mA
TB725 Cequivalent = 43.82 F Ileakage = 1.16 mA
TB657
TB757
TB725
Major inferences from the tests conducted on CMET capacitors.
1. The capacitance values of the CMET SCs show considerable dependence on the magnitude of the
charging or discharging current.
2. The initial voltage drop during the charging and discharging cycle (indicating DC ESR) seems to be
little higher than the corresponding drops obtained in the commercial SCs of respective values.
3. The time domain and frequency domain characteristics of CMET capacitors clearly illustrates the
fractional behavior associated with their porous electrodes. It was also noted that an adaptive fractional
order model is required for clearly depicting the characteristics of these SCs over wide range of
operating conditions. The fractional behavior varies with the voltage level, frequency range and the
magnitude of the charging/discharging current (α value varies in 0.5-0.9 range).
4. The frequency response analysis (FRA) predicts the requirement of a zone wise fractional order model,
for effectively characterizing the behavior of SCs over the complete frequency range. The FRA
characteristics can be represented almost accurately in the Zone 1 and Zone 3 regions using a simple
fractional order model (series connected resistance and a constant phase element). The representation
of the Zone 2 (semi-circle region) is not possible with such a model. However, a randles circuit
can be employed for fitting the characteristics in this zone. It is to be noted that the region 2
occupies a considerable frequency range of the CMET FRA characteristics, which is indicating
the presence of a faradaic nature of charge storage. For availing the benefits of an EDLC from
the CMET capacitors, the advisable frequency range of operation is less than 10 Hz.
5. It has to be noted that, the capacitance value measured from the first charging cycle is considerably
higher than the consecutive cycles. However, the value of discharging capacitance is lowest during the
first cycle of discharge. The repeatability (consistency) of the charging and discharging capacitance
irrespective of the cycle number can be observed after 2-3 cycles. This is in line with our claims for
modifying the parameter identification of the supercapacitors after pulse conditioning rather than from
the initial cycle.
Chapter 4
Design of Supercapacitor Packs with suitable voltage
balancing, protection circuits and Power electronic
Interfacing converter
Need for Voltage Balancing Circuit

Thinner dielectric layer and the resultant high electric field limits the voltage rating of the
supercapacitors to 2.7 V. (This voltage limits should be strictly followed to prevent the electrolyte
breakdown when subjected to higher electric fields). However, most of applications require a much
higher voltage rating, which demands stacking the capacitors in series. If the value of series
connected capacitances are different because of the manufacturing tolerance, voltage mismatch
results across the stack. The voltage unbalance also occurs due to factors such as variable
temperature gradient, ageing, variable ESR and leakage current. Voltage imbalance within a
supercapacitor string is undesirable as few supercapacitors might be overcharged or negatively
charged resulting in premature ageing, shelf life degradation or permanent damage to the
supercapacitors. Because of this mismatched voltages, we have to stop charging the stack when
one of the series connected capacitor reaches the rated voltage. This results in inefficient use of
the energy storage system.
Hence, optimum design and utilization of a supercapacitor-based system requires a voltage
balancing (VB) circuit. The desired features of the voltage balancing circuit vary depending on the
application demands. For example, for an energy harvesting application, reducing the leakage
offered by the VB circuit should be kept as the priority as compared to the dynamic response.
However, for a pulse power application like Electric Vehicles (EV), fast balancing is more critical
than the leakage offered by the circuit. Considering the above-mentioned aspects, in order to
optimize the usage of a supercapacitor system, detailed modelling, characterization and analysis is
required. Many works, which are related to this regard, is available in the literature. A brief review
of some of the important works and the gaps in the research is given in the next section.
Brief review of the voltage balancing circuits from the literature

Various voltage-balancing circuits have been reported in the literature, which can be
classified into passive and active balancing circuits [39-42]. In passive balancing circuits,
uncontrolled dissipation of supercapacitor charge takes place. Bleeding resistors are connected
across each supercapacitor cell to dissipate excess charge [39-41]. These circuits are highly
inefficient as dissipation takes place continuously during charging and discharging. This limits
their usage in low power and high charge-discharge rate applications [41]. Connecting zener
diodes across supercapacitor cells solves this problem by dissipating excess charge only when the
cell voltage exceeds clamping voltage of zener diode [41]. In spite of this, limitations such as
excessive thermal dissipation and uncontrolled voltage balancing capability make them unfit for a
wide variety of applications.
These problems can be overcome by employing active voltage balancing circuits [40,42-
55]. In these circuits, excess charge from one or multiple supercapacitor cells is actively
transported to lower charged supercapacitor cells. One such method is balancing through shunting
of charge. Switched resistor based voltage balancing is one such example [42]. In this circuit, a
resistor is connected parallel to each cell through a switch. Whenever the voltage across a cell
exceeds a predefined voltage level, the switch turns on and excess charge gets dissipated through
a resistor. Analog ICs and transistors can also be used in conjunction with each other to dissipate
excess charge from a supercapacitor [43]. Voltage balancing through shunting is the simplest and
cheapest method to implement, thus remaining popular in low-cost applications. They are modular
in nature, thereby ensuring convenient assembly, disassembly and debugging of the circuits. In
spite of these advantages, they are inefficient as excess charges are dissipated and not recovered.
A more efficient method of balancing charges is by using energy converters [40], [42], [44-
50]. Various DC-DC converter topologies such as Boost [44], Buck-Boost [45-46], Fly back [47]
and Cuk [48] converters have been used for voltage balancing. Lee proposed a fuzzy logic based
individual cell equalizer using a Cuk converter [48]. He further improved this technique by
proposing a Quasi-Resonant Zero-Current-Switching bidirectional converter based battery voltage
equalization technique [46]. In a step-up converter based active balancing circuit [44], boost
converters are connected across each cell and excess energy from one cell is transported to the
whole pack through the step up converter. Major drawback of this topology is the design gets
complicated if the string length is large. This problem is eliminated in multi-winding transformer
based balancing circuits [42-50] which have a single primary winding for the whole pack with
secondary winding taps across each cell. This arrangement makes the circuit non-modular. Excess
energy from a cell is transported to the primary winding which transfers it back to the whole pack.
The ramp converter [51] is a slight improvement on the multi-winding transformer based circuit
as one secondary winding is used across two cells instead of one. Lack of modularity in ramp
converter and multi-winding transformer based circuits can be overcome by employing primary
windings across each cell instead of a common primary. The cost and bulkiness of these circuits
described above can be brought down by using a switched transformer based balancing circuit
[42]. In this circuit, the output of an isolated converter is selectively connected across the
lowermost charged supercapacitor cell. The input of the converter is the total supercapacitor pack
voltage.
Two major drawbacks common to all energy converter based balancing circuits are
complex control and bulkiness. These drawbacks are overcome by switched capacitor based
balancing circuits [52-55]. In ladder type switched capacitor circuits [52], a parallel capacitor is
switched alternately between two adjacent cells to balance their charges. In ladder type circuits, if
an additional capacitor is switched alternately between the top most and the bottom most cells,
then the balancing speed increases [55]. In double-tiered switched capacitor circuits [54], multiple
tiers of capacitors are employed parallel to the supercapacitor string. This increases the quantity
of charge transfer thereby increasing the speed of balancing. Newer switched capacitor topologies
with lesser equivalent ESR of balancing capacitors have also been implemented [53]. These
circuits exhibit faster balancing due to lower equivalent ESR. The switched capacitor circuits can
be operated using simple control circuits. Employing film capacitors make these circuits less bulky
and robust but increase the cost of the system. The modularity of the balancing circuit is also
compromised in chain structured and double-tiered switched capacitor based voltage-balancing
topologies.
The decision of the type of the voltage balancing circuit is hence a trade-off between the
complexity and the efficiency requirement. Such decisions are hence mostly relied on the
requirement of the applications. The following section presents the design, implementation and
analysis of some simple voltage balancing circuits suitable for applications that demand cost
effective, less complex and modular balancing structures. Mainly three voltage-balancing circuits
are analyzed and compared: Resistive balancing, LP2996-IC based balancing and Transistor based
switched resistor circuit balancing. The frequency response and rest time characteristics of the
power packs made with these voltage-balancing circuits are also analyzed.
Design and analysis of the voltage balancing circuits

(1). Resistive Voltage Balancing
In this scheme, identical resistances are connected across the supercapacitors for balancing
the charge. A simple schematic representation of resistive balancing is given in Fig.4.1.
10 V
1A
4V
2V 10 F
1A
11 F 2V 10 F R
1.818 V
0.1 A
2.22 V 8F
9F
2V
R
10 F
2V
Fig.4.1 (a).Voltage unbalance from capacitance tolerance (b) Resistive Voltage Balancing
The value of the resistance should be chosen in such a way that both the leakage offered
by the circuit and the time taken for balancing will be optimum. A lower value of resistance results
in considerably high leakage current to flow continuously, which is not desirable. On the other
hand, extremely high value of resistance value (MΩs) requires considerable time to balance out
the charge, compromising the actual purpose of the circuit. A thumb rule for choosing the
resistance is based on the following equation. The value of the passive resistance should be at least
Rleakage/50, such the leakage difference between the different capacitors are balanced out.
Vrated
Rpassive 
Ileakage, nom  50
(2). LP2996 IC based voltage-balancing circuit
LP2996 is a linear regulator IC, capable of regulating the output voltage across each rails.
The connection diagram for balancing the voltage across two series connected ultra-capacitors
with the LP2996 IC is as shown in Fig.4.2. The internal circuit of the LP2996 contains mainly two
MOSFET switches and an op-amp comparator. Each capacitor is connected across the MOSFET
switch. The voltage across each capacitor is sensed and compared with a reference voltage.
Depending on the voltage variations, the respective switches are turned ON or OFF, providing
path for the excess charge to redistribute among the capacitors. Several experiments are conducted
to verify the performance of the balancing circuit. It has been found that, irrespective of the loading
condition, during charging, IC is capable of balancing the capacitors with less than 1% voltage
difference. However, the voltage across the capacitances were not properly balanced during
discharging condition. It may also result in a negative voltage formation across some of the
capacitors, especially when the value of individual capacitor in the packs are considerably low
(say, less than 10F). Additionally, this circuit is suitable for balancing only even number of
supercapacitors and the range of operation of the circuit is dependent on the minimum voltage
requirement for operating the IC.
LP2996
SC1
SC2
Fig.4.2. LP2996 based voltage-balancing circuit

(3). Transistor based voltage-balancing circuit
Considering the observations from the above-mentioned voltage balancing circuits, an

easily implementable, 3-stage modular transistor based active balancing circuit for supercapacitor
power packs is also designed and developed. The basic schematic of the scheme (designed for a
pack with 14 series connected SC) is shown in Fig.4.3. The voltage across each of the
supercapacitor in the pack is sensed and compared with the rated reference voltage. The scaled
down value of the sensed voltage is obtained from a resistor divider circuit and a low voltage drop
out (LDO) regulator IC, TLV74310P, generates the reference voltage. The output of the
comparator drives a 3-stage transistor based current sinking circuit. When the voltage across any
of the supercapacitors in the stack exceeds the rated value, the output of the Op-amp becomes high.
Consequently, the transistors Q1, Q2 and Q3 turn ON, dissipating the extra charge in the resistor.
Discrete transistors (2N2222 and 2N3906) have been used to implement this logic and TL331,
rail-to-rail comparator IC has been used as the comparator. A high current rating (Inom = 2A)
Darlington IC MJD112 has been used to sink current through a 1Ω bleeding resistor.
Over Voltage Protection Circuit: Unit 1

R4 Q2
R11
R1 (2N3906)
R5 R7 R8
R3 Q3
TL331 (MJD112)
SC1 Q1
R2 (2N2222) R6
14 SC in series
Vref R9
(TLV74310P)
R4 Q2
R11
R1 (2N3906)
R5 R7 R8 Q3
R3
TL331 (MJD112)
Q1
SC14 (2N2222)
R2 R6
Vref R9
(TLV74310P)
Over Voltage Protection Circuit: Unit 14
Fig.4.3. Transistor based active voltage balancing circuit
During our analysis it has been observed that, a transistor based switched resistor circuit
can give acceptable performance for certain applications, provided the tolerance between the
supercapacitors are less. Additionally, for low power applications of supercapacitors such circuits
can be a possible option. The design criteria for such voltage balancing circuits like the current
rating, leakage incurred because of the balancing circuit, time taken for balancing etc. should be
thoroughly studied depending upon the application demands. A brief discussion of some of these
criteria with respect to a transistor-based circuit is carried out and is presented below:
(a) Requirement of multi-stage triggering
In the transistor-based voltage balancing circuit, multiple transistor stages have been
implemented for sinking the current. Three transistors Q1, Q2 and Q3 implement the multiple
stages (Fig.4.3). A high comparator output turns ON Q1, which in turn trigger Q2 and further Q3.
This multiple stage network ensures a smooth variation of the voltage across the supercapacitors.
If the supercapacitor is connected directly to a low value of resistance, high current will be drawn
resulting in an immediate drop of the voltage and balancing circuit will turn OFF. Again the
capacitor voltage rises back and continuous the cycle. This results in the formation of a high
frequency zigzag ripple (Voltage chattering) across the supercapacitor. To limit this, normal
procedure is to design a hysteresis band with the comparator. Multiple stages of the circuit provide
a smooth delay and base current amplification for ensuring the smooth operation of the circuit.
(b) Hysteresis band design
A hysteresis resistor is included in the comparator circuit to avoid unwanted high frequency
triggering of the comparator IC. In other words, if the sensed voltage is almost equal to the
reference voltage, unwanted triggering can take place because of the noise in the circuit. The
resistor provides a hysteresis band thereby ensuring the triggering of the comparator only after the
upper and lower voltage limit values defined by the band. The design of the hysteresis band for a
prototype (Fig.4.3), which is developed in our lab, is as follows:
When the output of comparator is low, the hysteresis resistor, R11 is parallel to R2 thereby
lowering the sensed voltage by a small fraction. Therefore, the comparator will now trigger to ON
state at a voltage slightly above the triggering voltage with only R1 and R2 as rail resistance. When
the output of comparator is low, R11 is parallel to R1 thereby increasing the sensed voltage by a
small fraction. Therefore, the comparator will now trigger to OFF state at the lower band voltage.
(c) Current rating of the voltage balancing circuit
The current rating of the voltage balancing circuit should be decided mainly based on the
pattern of the charging and discharging currents and the maximum tolerance of the
supercapacitors. The following analysis can be used for a general case where the supercapacitor is
charged from a constant voltage source through a resistor [Ref]:
dv1
I  I eq  C1
dt
dv
I  I eq  C2 2
dt
Subtracting the above equations give:
dv2 dv
2 I eq  C2  C1 1
dt dt
when v1 = v 2
 C  C1  dv2
I eq   2 
 2  dt
dr
I eq   I
dr  2
 C  C2 
where d r   1 
 C2 
Based on this analysis, say for a load demand of 22 A, the current sinking capability of 2A is
required for the voltage balancing circuit. Considering this, we choose a Darlington IC, MJD112
with a current rating of 2A in our circuit. The circuit can be employed to balance a load demand
of maximum 22A, provided the tolerance limit of the capacitor is less than 20%.
Shortcomings of the transistor based voltage-balancing circuit

1. Voltage overshoot across supercapacitor
The current transistor voltage balancing circuit is basically an overvoltage protection

circuitry. When the voltage across any of the supercapacitor exceeds the reference voltage, the
comparator sent a trigger signal to the transistor network for sinking the excess charge through a
resistor. (For optimum use of the supercapacitor, it is preferable to keep the reference voltage same
as the rated capacitor voltage). The rate of voltage equalization and the current bypassed by the
voltage balancing circuit is then a function of the sinking resistor and the voltage across the
respective supercapacitor. As a result, depending on the tolerance of the supercapacitors, the
source current and the bypass current may not be equal. If the source current is more than the
sinking current, then the extra current flows to the supercapacitor resulting in further rise of the
supercapacitor voltage. Repeated violation of the voltage rating can considerably reduce the life
and performance of the supercapacitor. To avoid such mishaps, the power pack designer will be
forced to operate below the rated voltage, resulting in underutilization of the supercapacitor.
Referring to Fig. 4.4, it can be observed that when the capacitor voltage, Vc1 across the
reaches the reference threshold voltage, the sinking transistor is triggered into ON state. At this
instant, as the sinking current is less than the source current, some portion of source current is
forcibly fed into the supercapacitor C1. This leads to an undesirable rise of voltage across the
supercapacitor C1.
Fig.4.4. Voltage overshoot of capacitor with the voltage balancing circuit
2. Voltage chattering of the supercapacitors
This overshoot of the capacitor voltage can be prevented if the sinking resistor is designed
such that the maximum possible current can be bypassed at any instant. For doing this, either the
sinking switch should be oversized or multiple lower rated switches should be connected in
parallel. However, this results in sudden discharge of the capacitor voltage under all circumstances.
If the hysteresis band is kept tight, then this will lead to continuous high frequency chattering of
the voltage.
Suggestions for possible modifications to the transistor based voltage-balancing circuit
Solution 1: Variable Resistance circuit
Existing circuit controls the switch in saturation or cut off state, yet dissipates charge in the
sinking resistor. Instead, if we can make the transistor operates in the active region and control the
resistance of the transistor junction based on the source current, voltage overshoot and chattering
can be minimized. The role of this control technique is to ensure that, once the voltage across any
of the supercapacitor exceeds the rating, then the whole source current should be bypassed by the
balancing circuitry. If the source current varies exponentially, then the transistor resistance should
be controlled to sink this exponential current.
Solution 2: Variable reference voltage circuit
This configuration is a modification of the existing circuitry which promotes the circuit
from being an over voltage protection circuitry to a continuous voltage balancing circuit. For many
applications, this modification is not probably preferable, as continuous balancing through a
dissipative circuit makes the system lossy. However, this circuit can act as a negative voltage
protection circuit and speed up the time taken for balancing.
Experimental details of the SC pack prototypes made and tested in the lab
Several SC packs of varying rating (5 V to 48V) were made and tested in the lab. Most of
the packs have been built with one of the above-mentioned voltage balancing circuits. Few packs
(where the capacitance tolerance is very less) were built without any voltage balancing circuit.
Various performance analysis tests were conducted and a probabilistic study of the requirement of
the voltage balancing circuit for various applications is conducted. The details of the SC packs
made as a part of this project is tabulated in the following table.
Table.4.1: Photographs and details of the SC packs made in the lab
Photograph of the Pack Brief details of the pack

22 V Pack with resistive voltage
balancing.
This pack is made of 25F, 2.5V
Powerstore/Eaton supercapacitors,
where 9 of them are connected in
series.
8 V pack with resistive voltage

balancing.
This pack is made of 10F, 2.5V
Panasonic supercapacitors, where
4 of them are connected in series
and two such series connected
packs are connected in parallel.
48 V Pack with resistive voltage
balancing.
This pack is made of 50F, 3V AVX
supercapacitors, where 18 of them
are connected in series.
5 V Pack with LP2996 based

voltage balancing.
This pack is made of 25F, 2.5 V
Panasonic supercapacitors. 3 SCs
are connected in parallel and two
such parallel-connected modules
are again connected in series.
17 V Pack with resistive

balancing.
CMET supercapacitors. 7 SCs are
connected in series and two such
series-connected modules are
connected in parallel.
17 V Pack with resistive

balancing.
CMET supercapacitors. 7 SCs are
connected in series and two such
series-connected modules are
connected in parallel.
36 V Pack with transistor based
voltage balancing circuit.
Pack is made of 300F, 2.7V,
PowerStor/Eaton supercapacitors,
300 F, 2.7V, PowerStor where 14 such SCs are connected
Supercapacitors
in series with a modular transistor
based voltage-balancing circuit.
Transistor Based
Balancing Modules
36 V Pack with transistor based

voltage balancing circuit.
Pack is made of 400F, 2.7V,
PowerStor/Eaton supercapacitors,
where 14 such SCs are connected
in series with a modular transistor
based voltage-balancing circuit.
42 V Pack without any voltage

balancing circuit.
Pack is made of 350F, 3 V, Tecate
group supercapacitors, where 14
such SCs are connected in series.
Design and development of a suitable power electronic interface for SC pack
The voltage of SC pack varies during charging and discharge. However, most of the
applications of the SC demand constant voltage. This requirement is fulfilled by interfacing the
SC pack through a power electronic interface. Different power electronic converter topologies are
suitable in this regard, out of which a bidirectional buck-boost converter based interface is the
simplest and commonly used configuration. As part of this project, a 200 W bidirectional buck-
boost converter is implemented. The converter interfaces 42 V- Tecate SC pack. The input voltage
of the SC is allowed to vary from 25V- 36V, while the output voltage is kept constant. The SC
pack discharged in the boost mode and charges in the buck mode operation. Additionally, the
converter is employed with input and output voltage and current sensors for testing any power
management algorithm. The specifications of the converter is as follows:
Specifications of Bidirectional Boost Converter employed for hardware testing
Maximum Voltage Gain: 2.5
Input voltage range: 25V-36V
Output voltage: 48V (For a specific application)
Maximum Power tested (W): 200 W
Switch specifications: 200V, 30 A, MOSFET
Switching Frequency: 30 kHz
Controller: DSP TMS320F28335
Driver: SI8261
Inductor: 400 μH, 25 A
Input capacitor: 220 μF, 50 V, Electrolytic
Output capacitor: 1000 μF, 63 V, Electrolytic
The basic schematic of the circuit and hardware set up of the circuit is shown in Fig.4.5 and Fig.4.6
respectively.
BOOST
C1 L1 S2
C2
C2 48 V
SC Pack C1 S1
25V-36 V Load
C14
BUCK
Fig.4.5. Bidirectional buck boost converter interfacing an SC pack

SC PACK
DSO
INDUCTOR
CCS STUDIO
BUCK-BOOST CONVERTER
POWER SOURCE
POWER CIRCUIT
CURRENT SENSORS
VOLTAGE SENSORS
DRIVER CIRCUIT
AUXILLARY POWER CIRCUIT
Fig.4.6. Hardware set up of bidirectional buck-boost converter
The buck-boost converter is tested under various conditions to verify the bidirectional operation,
efficiency and load regulation characteristics. The hardware results of the converter while operating in boost
mode and buck mode operation in open loop is given in Fig.4.7 and Fig.4.8 respectively. The efficiency
and load regulation of the converter in both the operation modes are verified and tabulated in Table 4.2 and
Table 4.3.
Gate signal from DSP Gate signal from DSP
Inductor current, IL = 1.09A

F = 30 kHz F = 30 kHz
Gate signal from DSP Gate signal from DSP
Inductor current, IL = 4.07 A Inductor current, IL = 4.236 A
F = 30 kHz F = 30 kHz
Gate signal from DSP
Inductor current, IL = 4.68 A
F = 30 kHz
Fig.4.7. Hardware results of bidirectional buck boost converter corresponding to different loads
While operating in the boost converter mode
Gate signal from Driver Gate signal from Driver
Inductor current, IL = 0.8A Inductor current, IL = 0.96A
F = 30 kHz F = 30 kHz
Gate signal from Driver Gate signal from Driver
Inductor current, IL = 0.93A Inductor current, IL = 1.5 A
F = 30 kHz F = 30 kHz
Gate signal from Driver
F = 30 kHz
Fig.4.8. Hardware results of bidirectional buck boost converter corresponding to different loads
While operating in the buck converter mode
Table.4.2: Hardware results of Boost converter during varying loads, input voltage and duty
Duty Vi/p (V) Ii/p (A) Vo/p (V) Io/p (A) η= Po/p / Pi/p
Ratio
0.4 30 1.06 48 0.5 75.4%
0.4 30 1.6 47.84 0.9 89.7%
0.4 30 1.94 47.5 1 81.6%
0.4 30 2.55 47.29 1.4 86.5%
0.4 30 3.99 46.39 2.2 85.26%
0.45 30 4.7 50.36 2.3 82.14%
0.45 30 5.33 49.8 2.7 84.09%
0.45 25 1.47 43.23 0.7 82.3%
0.45 25 1.82 43.13 0.9 85.31%
0.45 25 2.24 42.83 1.1 84.13%
0.45 25 2.73 42.5 1.4 87.18%
0.45 25 3.54 41.85 1.8 85.12%
0.45 25 4.83 40.9 2.4 81.29%
0.45 25 5.6 40.77 2.8 81.54%
0.45 25 7.6 39.59 3.9 81.26%
Table.4.3: Hardware results of Buck converter during varying loads and input voltage
Duty Vi/p (V) Ii/p (A) Vo/p (V) Io/p (A) η= Po/p / Pi/p
Ratio
0.5 30 0.46 14.24 0.5 75.4%
0.5 30 0.53 47.84 0.9 89.7%
0.5 30 0.66 47.5 1 81.6%
0.5 29 0.95 47.29 1.4 86.5%
0.5 29 1.23 46.39 2.2 85.26%
0.5 29 1.43 50.36 2.3 82.14%
0.5 28 1.57 49.8 2.7 84.09%
0.5 48 0.8 43.23 0.7 82.3%
0.5 48 1.2 43.13 0.9 85.31%
0.5 48 1.7 42.83 1.1 84.13%
0.5 48 2.0 42.5 1.4 87.18%
0.5 47 2.7 41.85 1.8 85.12%
0.5 47 3.4 40.9 2.4 81.29%
GATE SIGNAL FROM DSP
INDUCTOR CURRENT
SC CHARGING
OUTPUT VOLTAGE
Fig.4.9. Charging of the Tecate group SC pack through the converter while operating in the buck
mode
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PROJECT COMPLETION REPORT for the project titled DESIGN AND

Technical Report · March 2020

Vivek Agarwal Geethi Krishnan

SEE PROFILE SEE PROFILE

Modelling of ultra capacitors using fractional order modelling View project

Fractional Calculus and it's applications View project

The user has requested enhancement of the downloaded file.

DESIGN AND DEVELOPMENT OF POWER PACKS

Department of Electrical Engineering

Bhaba Atomic Research Centre (BARC), Mumbai

PRODUCT A: Series Connection of two super capacitors-charge balancing scheme

Major outcomes/accomplishments of the project

Problems targeted Solutions developed/ Accomplishments

o Standardizing characterization 1. Devised a method for differentiating charge

List of papers presented in National/Int’l conference

2. G. Krishnan, S. Das and V. Agarwal, "State of Charge Estimation of Supercapacitors with

3. G. Krishnan, S. Das, V.Agarwal, “Analysis of Variable Fractional Order Behavior of

4. G. Krishnan, V. Gupta, S. Das, V. Agarwal, “Development of a transistor based dissipative

1000 CURRENT COLLECTOR

100 POSITIVE ELECTRODE

Fig.2.1. Simplest fractional order model of an SC

Sample R(Ω) Cα((F/s(1- α)) α R (Ω) C (F)

25F, 2.5V 0.02 20.10 0.83 0.06 36.59 Time (s)

By Grunwald_Letnikov definition (G-L)

Caputo definition is given by the following equation

Fig.2.4. Gamma Function

The expansion of the function as an infinite series is as follows:

Fig. 2.6. Schematic representation of Constant resistance charge/discharge test

Using the above,

To the above series, add and subtract 1 to get,

B. Constant current charge-discharge test

Fig. 2.7. Schematic representation of Constant current charge/discharge test

1 Ich  I ch 1 1  I ch  tn 

Experimental analysis of the Fractional order behavior of the commercial SCs

No Capacitance (F) Voltage (V) Manufacturer Other datasheet information

FO behavior observed in the experimental results of various commercial SCs

Case 3: FO behavior observed during electrochemical impedance spectroscopy test

Representing the charge redistribution characteristics of a supercapacitor

Sample Condition before α τ

Power and energy equation and charge-discharge efficiency of supercapacitor

The energy stored in the SC from time t = 0 to t = t1 can be given as

Dependence of FOM Parameters on the SC Operating Point

Case 2: Dependence of FOM parameters on frequency

Case 3: Dependence of FOM parameters on current

Online parameter identification of FOM

TABLE 2.9: DEPENDENCE OF IDENTIFIED FOM PARAMETERS ON ‘T’ AND ‘L’

Computation of FO derivative Computation of α

YES Computation of Cα and R

Fig. 2.16. Experimental set up used for online identification of FOM

TABLE 2.10: FOM PARAMETERS IDENTIFIED FROM OFFLINE TESTS

Zone1 Zone2 Zone3 Zone4

Method 2: FOM based SOC estimation

Differentiating the characteristics of charge redistribution from the leakage of

First discharge-Redis Cycle

𝐼𝑙𝑒𝑎𝑘𝑎𝑔𝑒 = 𝐶𝑒𝑞𝑢𝑖𝑣𝑎𝑙𝑒𝑛𝑡 × 𝑠𝑙𝑜𝑝𝑒

Modified parameter identification method after initial conditioning of the

Voltage Q extracted CC Mode (cycle) Voltage Q extracted CC Mode (cycle)

Table 3.3: Results of the test conducted as per Table.3

STEP1 Qchg = 64.69 C, Vfinal = 2.49 V

Fig.3.5. (a) Capacitance versus voltage (b) Capacitance versus current

Empirical estimation of UCTY

Table.3.7. Experimental results comparing UCTYMeasured and UCTYPredicted