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An Area Efficient Fault Tolerant Parallel FIR Filter Design

Article  in  Journal of Advanced Research in Dynamical and Control Systems · May 2017

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Jour of Adv Research in Dynamical & Control Systems, Vol. 9, No. 3, 2017

An Area Efficient Fault Tolerant Parallel

FIR Filter Design
Gowrikumari Nanireddy, PG Scholar, 2nd M.Tech, [VLSI &ES], Department of ECE, QIS Institute of Technology, Ongole, AP,
India. E-mail:gowrikumari001@gmail.com
Koteswara Rao Vaddempudi, M.Tech,[Ph.D], SMIEEE, FIETE, PMACM, MACCS, MVSI, Associate Professor, Department of
ECE, QIS Institute of Technology, Ongole, AP, India. E-mail:vaddempudi@yahoo.com, vkrao1984@gmail.com
Dr.M.S.S. Rukmini, M.E., Ph.D., Professor Department of ECE, Vignan’s University, (VFSTR University), Vadlamudi, Guntur
Dt. AP, India. E-mail:mssrukmini@yahoo.co.in
Abstract--- The reliability of any Communication system or digital signal processing system mostly depends on the
design of filters that are fault tolerant. FIR filters with error correction codes that operate in parallel have been
developed that increase the redundancy and size of the system. These filters used error correction codes that have
forward error correction capability and as such fault tolerance that increased the chip size. The proposed method
uses less number of redundant modules than the existing ones and reduces the area of such filters by approximately
21.18% that reduces the cost of the system implementation almost by the same amount.
Keywords--- Error Correction Codes (ECCs), FIR Filters, Soft Errors.

I. Introduction
In applications like automotive, medical and space fields, the use of electronic circuits is tremendously
increasing. The reliability of these circuits in these applications is critical and need to have a certain degree of fault
tolerance. In advanced CMOS technologies, manufacturing variations and also soft errors occur and as such,
additional arrangements have to be made for providing fault tolerance. Apart from the modifications of the
manufacturing processes of these circuits to reduce the errors, adding redundancy either at the logic level or system
level reduces the errors without affecting the system functionality [2]. Authors of [1] proposed a simple technique
that uses parallel filters and provides protection using the concept of error correction codes (ECCs). This method
uses parallel filters having the same response and process different input signals. The error correction codes in this
method are applied considering the output of each filter equivalent to a single bit. When a large number of parallel
filters are employed, this implementation becomes more efficient.
Triple modular redundancy (TMR) triplicates the design. In order to correct the errors TMR adds voting logic in
general. The algorithmic and structural properties can be exploited for implementing fault tolerance. Specific
techniques have been proposed for such implementations in signal processing circuits [3]. FIR filters are the most
commonly used digital filters in signal processing circuits. Authors of [4] proposed the usage of the reduced
precision replicas for reducing the cost of implementing modulo redundancy in FIR filters. Authors of [5] proposed
a method to use the relationship between the input sequence and the memory elements of FIR filter to detect the
errors. Authors of [6] exploited the properties of FIR filter at a word level to achieve the fault tolerance.
Authors of [7] proposed to use residue number systems to protect filters whereas authors of [8] proposed to use
arithmetic codes to protect the filters. Authors of [9] proposed different implementation structures for the FIR filters
in order to correct the errors using only one redundant module. Authors of [10] proposed a higher order FIR filter
using higher radix algorithms. It has become common to use several filters in parallel in systems like filter banks
[11] and also in many modern communication systems [12]. Authors of [13] proposed a scheme for the protection of
these filters by considering the parallel filters as a single block to be protected. Two parallel filters having the same
response for processing different input signals were proposed in [13]. In this method it was shown that single error
can be corrected with one redundant copy of the filter which reduces the cost of implementation significantly as
compared with the TMR implementation.

II. Existing System

The existing scheme is shown in Fig.1. It is based on four FIR filters having the same response [H]. These four
filters are given with different inputs x1, x2, x3 and x4 each of which are of n bit size. These four inputs are coded to
get x5, x6 and x7 as given in (1) to (3).

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Jour of Adv Research in Dynamical & Control Systems, Vol. 9, No. 3, 2017

x5 = x1+x2+x3 (1)
x6 = x1+x2+x4 (2)
x7 = x1+x3+x4 (3)
In parallel to the above four filters another three redundant filters having the same response as the previous ones
are added in parallel. The inputs to these redundant filters are x5, x6 and x7. The outputs from these seven filters y1, y2,
y3, y4, z1, z2 and z3 are applied to the single fault correction block. The outputs with correction, if any, are obtained as
yc1, yc2, yc3 and yc4. The scheme is shown in Fig. 1.
Functional FIR
filter Modules

x1 y1 yc1
H
y2 yc2
x2
H
y3 yc3
x3
H

Single Fault Correction Module

x4 y4 yc4
H

Coding
z1
x5=x1+x2+x3 H

z2
x6=x1+x2+x4 H

z3
x7=x1+x3+x4 H

Redundant FIR
filter Modules

Fig. 1: Existing Scheme with Four Filters and Three Redundant Modules
The correction block acts as a hamming decoder considering y1, y2, y3, and y4 as data bits and z1, z2 and z3 as
parity bits. Based on this concept, the syndrome is generated. This block can correct one error output at the
maximum from any one of y1, y2, y3 and y4. The corrected outputs are obtained as yc1, yc2, yc3 and yc4. Table I shows
the error location and the corrected outputs.
Table I: Error Location in the Filter Output and Corrected Outputs
s1 s2 s3 Error bit position Action, if any, in hamming decoder Corrective action in existing scheme
000 No error None None
111 d1 Correct d1 Yc1[n]=z1[n]‒y2[n]‒y3[n]
110 d2 Correct d2 Yc2[n]=z2[n]‒y1[n]‒y4[n]
101 d3 Correct d3 Yc3[n]=z3[n]‒y1[n]‒y4[n]
011 d4 Correct d4 Yc4[n]=z3[n]‒y1[n]‒y3[n]
100 p1 Correct d5 -
010 p2 Correct d6 -
001 p3 Correct d7 -
This method presumes that fault may occur in the output of any one of the four filters at a time and hence
corrects the same, providing fault tolerance for a single faulty output from any one of the filters.

III. Proposed Scheme

The proposed scheme employs only two redundant filters instead of three in the existing scheme and as such
reduces the area on the chip. It can correct error in the outputs of the filters only in any one of the outputs y1, y2, y3
and y4 at a time. It employs six FIR filters having the same response out of which, four are functional modules and
the remaining two are redundant modules. The scheme is implemented as shown in Fig.2.

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Jour of Adv Research in Dynamical & Control Systems, Vol. 9, No. 3, 2017

Functional FIR
filter Modules
x1 y1 yc1
H
x2 y2 yc2
H

Single Fault Correction Module

x3 y3 yc3
H
x4 y4 yc4
H

Coding
z1
x5=x1+x2 H
z2
x6=x3+x4 H

Redundant FIR
filter Modules

Fig. 2: Proposed Scheme with Four Filters and Two Redundant Modules
The existing scheme is designed based on the principle of Hamming code. But it is not the real implementation
of the hamming code to correct any single bit of error occurrence in the outputs of the functional filters. It can
correct the output of a single filter in case it goes in error. The disadvantage of the scheme is that for every four
filters; three numbers of redundant filters are to be used increasing the required area on the chip approximately by
75%.
The proposed scheme uses only two redundant filters in addition to the four functional filters with the capability
of correcting the output of any one filter at a time if goes in error. For implementation of the proposed scheme, only
50% extra area is required on chip as compared to 75% extra area for the existing scheme.
The proposed scheme is divided into four blocks
A. Functional FIR filter modules block.
B. Coding block.
C. Redundant FIR filter modules block.
D. Single fault correction module block.
A. Functional FIR Filter Modules Block
In this block four identical parallel FIR filters are employed, each having an input x[n] and output y[n]. The
outputs of these functional FIR filter modules y1, y2 , y3 and y4 are obtained implementing the following equation.
∞
y[n] = ∑ x[n − l ].h[l ] (4)
l =0

where x[n], y[n], and h[l] are the input signals, output signal and impulse response of the filter respectively [14].
If the impulse response h[l] is non zero, the filter is FIR filter, else IIR filter.
B. Coding Block
In this block, the required inputs for the redundant FIR filter modules are computed from the inputs given to the
functional FIR filter modules, as given in
x5 =x1+x2 (5)
x6= x3+x4 (6)
C. Redundant FIR Filter Modules Block
Two redundant FIR filter modules, which are identical to the ones used in the functional FIR filters module, are
employed in parallel in this block.

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The outputs of the redundant FIR filter modules are implemented by the following equations
∞
z1[n] = ∑ x1[n − l ] + x2 [n − l ].h[l ] (7)
l =0

This is equivalent to z1[n] = y1[n]+y2[n], if no error occurs in the output of filters

∞
z2 [n] = ∑ x3[n − l ] + x4 [n − l ].h[l ] (8)
l =0

This is equivalent to z2[n] = y3[n]+y4[n], if there is no error in the output of the corresponding filters.
D. Single Fault Correction Module
The six outputs y1, y2, y3, y4, z 1 and z2, obtained from these six parallel filters are applied to the single fault
correction module which gives the final corrected outputs yc1, yc2, yc3 and yc4 as explained below.
The parity code used for correction of the outputs is generated by the following algorithm.
p1=y1+y3 (9)
p2=y2+y4 (10)
p3=y3+y4 (11)
With the assumption that error may occur in the computation of y1, y2, y3 or y4, only in one at a time and the
redundant filter outputs never goes wrong, the following algorithm is developed for correcting the outputs of the
functional FIR filter modules one at a time.
1) No error condition: As z1 contains y1 and y2, z2 contains y3 and y4, testing the condition (z1+z2=p1+p2)
confirms that there is no error in the outputs of the any of the functional FIR filter modules and requires no
correction.
2) Correction of error in y1: If (p3=z2), then the outputs y3 and y4 have no error. Followed by this test, if (p1-
y3=z1-y2) then there is no error in y3 and y2. Then if error occurs in y1, if any, can be corrected by yc1=z1-y2.
3) Correction in y2 and y3: If (p2-y4=z1-y1), then there is no error in y1 and y4. Then error may lie in y2 and/or
y3, if any, and can be corrected as yc2<=z1-y1 and yc3<=z2-y4.
4) Correction in y4: If p3! =z2, and p2-y2=z2-y3, then there is no error in y3. Error, if any, may lie in y4. It can be
corrected as yc4=z2-y3.
All these test conditions and corrective actions are summarized in the table II.
Table II: Corrective Action and Final Outputs
Condition tested Probable fault Final outputs after correction, if any
(z1+z2)=(p1+p2) No error yc1=y1
yc2=y2
yc3=y3
yc4=y4
p3=z2 yc1=z1-y2
Then if ( p1-y3=z1-y2) p1 yc2=y2
yc3=y3
yc4=y4
(p2-y4=z1-y1) y2 and/or y3 yc1=z1
yc2=z1-y1
yc3=z2-y4
yc4=y4
If (p3!=z2) y4 yc1=y1
(p2-y2=z2-y3) yc2=y2
yc3=y3
yc4=z2-y3
The proposed method is advantageous in that it uses only two redundant modules instead of three in the existing
method and savings in area on the chip is achieved.

IV. Simulation Results

Both the existing and proposed schemes are implemented in Xilinx ISE 14.7 software in Verilog targeted to
Virtex-4, XC4VLX80. All the filter modules are implemented with 4th order and 4 bit sampled inputs.

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Jour of Adv Research in Dynamical & Control Systems, Vol. 9, No. 3, 2017

The test bench wave form for the proposed method is shown in Fig. 3.
For the simulation, the inputs x1, x2, x3, and x4 are taken as 2, 3, 4, and 5 respectively. The filter coefficients for
each filter are taken as 4, 3, 8 and 9. Accordingly the outputs yc1, yc2, yc3 and yc4 are obtained as 48, 72, 96 and 120
respectively.

Fig. 3: Test Bench Wave Form of the Proposed Scheme

The test bench wave form for the correction module alone is shown in Fig. 4. In this wave form the outputs of all
filters in the proposed scheme are given as inputs. They are 48, 72,

Fig. 4: Test Bench Wave Form of the Correction Module Alone in the proposed scheme
96 and 120 respectively. In the first instance no fault is introduced and hence the outputs are same as inputs. In
the second instance y1 is given as 49 instead of 48, which is corrected and given as 48 at the output. Accordingly
when inputs with errors are given in the following instances as 76, 97, and 121 respectively, they have been
corrected as 72, 96, and 120 respectively and given at the outputs.
The device utilization summary is shown in Table III. It can be observed from the device utilization summary
that there is a significant reduction in the area by 21.18% in the proposed method as compared to the existing
method.
Table III: Device Utilization Summary
Device Utilization Summary
Logic Utilization Existing method Proposed method % decrease
Number of Slices 203 160 21.18
Number of Slice Flip Flops 117 96 17.948
Number of 4 input LUTs 315 250 20.635
Number of bonded IOBs 58 58 0
Number of DSP48s 18 14 22.22
The performance summary is given below. As both the existing and proposed schemes are parallel
implementation of same filters, no change in the delay/speed is observed.
Minimum period : 0.582ns
Maximum Frequency : 1717.475MHz
Minimum input arrival time before clock : 7.449ns
Maximum output required time after clock : 3.879ns

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V. Conclusion and Future Scope

The fault tolerant parallel filter system is implemented in Xilinx ISE 14.7, targeted to Virtex-4, XC4VLX80 and
found to have given significant reduction in area which reduces the cost of implementation. Faults were introduced
in all the outputs of the functional filters and found that the fault in every output is corrected. The filters are
implemented for four bit inputs with fourth order. Further work in this direction can be done to implement higher
order filters with efficient methods to further reduce area, performance and power so that they find good practical
application.

Acknowledgment
The authors hereby acknowledge their gratitude to the management of QIS institute of Technology, Ongole to
have provided laboratory facility for implementing this project.

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