5B-4

58-4

 

     





A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for
 
 
  
MOSFET and FinFET Technologies Using Machine Learning
   
 
  
Mohamed Saleh Abouelyazid
"# 
Sherif Hammouda $%
Y ehea Ismail


Siemens EDA

Siemens EDA 
American University in Cairo

American University in Cairo 
Cairo, Egypt 
Cairo, Egypt

Cairo, Egypt "  !
sherif_hammouda@mentor. com ! ! 
y. ismail@aucegypt.edu
  !
mohmed_saleh@mentor. com




Abstract -! "
  " "  #
A novel machine learning modeling methodology for
86  9
86  79


parasitic



capacitance 

extraction 
of "      " 
middle-end-of-tine metal  7
#    !  $%  
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) | 978-1-6654-2135-5/22/$31.00 ©2022 IEEE | DOI: 10.1109/ASP-DAC52403.2022.9712514

layers around FinFETs and MOSFETs is developed. Due to the


 
increasing
" #
complexity   and 

parasitic 

extraction 


#
accuracy 6 
 & " "       !


requirements of middle-end-of-tine patterns in advanced process
86  9 86  9
 '" 
 
 
 # 
nodes, most of the current parasitic extraction tools rely on field­
 + +
!  
"     



$
solvers to extract middle-end-of-tine parasitic capacitances. As a 
 '
result, 
a 
lot 
of " '
time, " "#'
memory,  
and
"
computational  

resources  
are

" $  " "  #! 
"   
consumed. The proposed modeling methodology overcomes these
'% 86     9
 "#! 
"
"  
" 
problems by providing compact models that predict middle-end­  
/0
of-line
 



 
 #$ 
"
"  
parasitic capacitances efficiently. The compact models are  6  6  


 (   
pre-characterized and 
#   $ '
technology-dependent. Also,  #
they

can   %  4
   
 


# & "  !

 6  4 ,
handle the increasing accuracy requirements in advanced process
 $
nodes.  
The  
proposed "  #
methodology 

scans #
layouts 
for !
'
devices, 6  7 


extracts  " 

geometrical   
features 
of 

each !

device 
using  a ! 
novel 4 4 ,
 " #     6 
geometry-based pattern    '
representation,  
and  
uses  
the 
 
extracted
    & "
  " $)
features as inputs to the required machine learning models. Two 6 
"
 
machine  
learning "  
methods  
are  
used 
 *
including: 
support !

vector % 

     )+$  
!  "  6    7
regressions and neural networks. The testing covered more than 
,- !
 !       ./"
40M devices in several different real designs that belong to 28om
/ 0
(b)
 
and 0"
7nm 

process 
#
technology  $
nodes.  
The  
proposed "  #
methodology
+!3!
). /0++'
Fig. 1. Some MEOL parasitic capacitances arotmd (a) typical FinFET,
" 
managed  to ! 
provide  
outstanding  
results 
as
" 
compared  
to field­
294 / 0)
+'!
[7], and (b) MOSFET structures.
! )!   1-$.2'   !132'
solvers with an average error< 0.2%, a standard deviation< 3%,

solvers  
and  
stored 
in 
a  
library 
to 
be 
later  
used 
by 
and a speed up of lOOX.
  4--5$ parasitic
,!,
extraction tools. During a layout parasitic extraction process,
,"
extraction tools perform pattern matching operations to match
%!
I. %INTRODUCTION
&'()'%)& - 
the pre-characterized patterns *!
with layout patterns. #*
However,
 
this approach suffers from several  
 "" "  problems  ?
including: 301)
'
The 
massive 
improvement  in  
semiconductor  
industries 
pattern 
mismatches that 
impact 
the 
accuracy " of , 
extracted
  " "
enabled the integration of more systems and functionalities on 
capacitances, =02) ""
insufficient 
pattern 
coverage,   and <0
3) 
the
!
*  "
the same chip. Such integrations are empowered by the feature 
consumption " of 
large @!
diskspace.  As a 
result, -
the pre­

scaling  and 
the  
introduction " of ++'!
FinFETs. 'The 
continuous 
characterization approach results in poor parasitic capacitance
 *" ""
scaling down of technologies resulted in parasitic effects such ,*, 3AB294!
extraction accmacy with error percentages exceeding 10% [7].
  
as interconnect resistances and capacitances to dominate circuit ) " -
On the other hand, the approaches that rely on field-solvers to
"
performances, 
increasing  the 
importance " of 
interconnect ,
extract ).
MEOL 
patterns ""
suffer "
from 
three 
main  
problems

parasitic ,!
extraction. '
The 
parasitic ""
effects 
that 
are  
associated  ?30=0, <0
including: 1) capacity limitations, 2) excessive runtime, and 3)
*
with the  - -)"-.
Middle-End-Of-Lines /).0 ( MEOL), *
which  are 
the "2842742:4!
the consumption of many computational resources [ 4], [ 6], [9].
 
interconnects connecting devices to upper metal layers, have a '
To 
cope *
with 
the 
increasing ,
complexity   and 
accuracy
1
major 
impact 
on 
circuit "
performances  in   
advanced 
process C   
requirements in advanced process technology nodes, there is a
 *2345264!+!3*).
nodes as shown in [1]-[5]. Fig. 1 shows some MEOL parasitic 
strong  
need 
to 
develop 
accurate  
and "
fast ).
MEOL  
models 
that
"++' )
+'!
capacitances in case of FinFETs and MOSFETs, respectively.  * """"274!
can deal with different geometrical changes efficiently [6].
," -
Usually, commercial parasitic extraction tools use field-solvers '
The  
contributions " of 
this 
paper ?
are: 30
1) 
a *
new  
modeling
,).!
to extract the MEOL parasitics to achieve high accuracy levels.       !
methodology based on machine learning methods is developed.
#*" -*  
However, field-solvers are slow, have a limited capacity, and '
The  
methodology  
provides 
accurate  
and 
compact 
parasitic
"274!
consume a lot of computational resources [6].  ").  "
capacitance models for MEOL around the devices for a ce1tain

""* ). 2345
Several efforts were done to implement MEOL models [1]­ 
process 
technology  !
node. '
The  
proposed  
methodology  is
284
[ 4], 29452:4!
[7]-[9]. #*
However, most "
of 
these ""
efforts  ;
didn't  
provide a  
applied "
for -  
rule-based ,
extraction !
tools. %It "
significantly

general methodology to model MEOL, and they still 
     ).     rely 
on 
improves 
the 
parasitic 
capacitance ,
extraction 
accuracy "of
" - "2<452642:4-
either field-solvers and analytical formulas [3]-[5], [9] or pre­ ).  
MEOL patterns by increasing the pattern coverage, considering

layout 
parasitic ,
extraction  
models *
without  
considering any  !'
the metal connectivity, and mitigating pattern mismatches. The

layout geometries [1], [2]. Some of the efforts " 
 234 2=4! 
 "  "" focused  on  
proposed  
methodology  
provides  a 
compact  
model 
that 
deals
 ").2942>4*
implementing a library of MEOL patterns [7], [8], where the *).!
 
with many MEOL patterns. Such a compact capacitance model
",  " -
parasitic capacitances of those patterns are extracted by field- 
can 
replace  
thousands " of - 
pre-characterized 
pattems  
and

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©2022IEEE
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 5B-4
58-4
    ! =0 '*  
provide more accmate results. 2) Two machine learning


 ( #


@/ 0 .
           ).
approaches are used and tested to implement the MEOL
  &&*@/&&0
J  
parasitic capacitance models including Nemal Networks (NN) +
 /
G(0!'"  /.0
and supp01t vector regressions (SVR). The inputs of the models
).!<0').  + - K
are the MEOL pattems. 3) The MEOL pattems are represented 

 ( 
-  ! # 
using a novel geometry-based pattern representation. "
'      "*!
 %%   
The paper is organized as follows. Section II provides a
@   -     , 
netlist

background on rule-based parasitic capacitance extraction
 !
%%%   -   +!=!-  ,"*!
methods. Section III describes the proposed connectivity-based Fig. 2. A typical rule-based parasitic capacitance extraction flow.
&& !
%G ,!
NN compact models. Section IV provides experimental results. '  "      ). 

G ! The inputs of the compact model are MEOL geometrical
Section V provides the conclusion. *- " 
properties, while the output is a cettain pre-identified coupling
 ! '      
capacitance component. The proposed methodology uses a
%%! HIJ()& -  ,/0
II. BACKGROUND novel geometry-based representation to extract (represent) the
C "").  
 
 


 

A. Rule-Based Capacitance Extraction
required featmes of MEOL patterns to be used as inputs to the
 !@,-  
compact models. Unlike existing pre-characterized models, the
'-  ,      ""  
The current rule-based parasitic capacitance extraction tools proposed methodology can efficiently decrease pattem
=!6, ,        " ). !
use 2.5D extraction methods to extract interconnect parasitics, mismatches and handle many varieties of MEOL patterns.
*" -- < # ").,
while they use field-solvers or pre-characterized 3D patterns to Hence, the accmacy and nmtime ofMEOL parasitic extraction
, ).  274 294 23A4 2334! ' -   " !
extract MEOL structmes [6], [7], [10], [11]. The rule-based processes are significantly improved.
,  "*  *+!<  "*"
parasitic capacitance extraction method consists of two main As shown in Fig. 3, the proposed modeling flow consists of
?30- =0          
phases: 1) a pre-characterization phase and 2) a layout parasitic three main phases in order to create parasitic capacitance
,*+!=!'-  ").!'"
extraction phase as shown in Fig. 2. The pre-characterization machine leaming models for MEOL patterns. The first phase
-  "  !'  
phase aims to generate a pre-characterized library of parasitic aims to prepare training data. This is done by generating many
" !%=  ).  /!!
capacitance formulas and patterns. It generates many 2D and MEOL patterns, applying systematic process variations (e.g.,
<   *   ,  0   ,   " ).
3D metal patterns with many anangements, extracts their etching), and extracting parasitic capacitances of MEOL
   " -    "    " -    " 
parasitic capacitances using field-solvers to obtain reference patterns using a field-solver to obtain reference parasitic
     "  "     ! '      ,
parasitic numbers, and performs cmve fitting operations in capacitance numbers. The second phase aims to extract
 ""! "").!'  
order to create a formula for each capacitance component. All featmes of MEOL patterns. This is done by representing each
"      -       ).     -   !
formulas are stored in a pre-characterized library to be later MEOL pattem using a novel geometry-based representation.
  ,!)             
used by extraction tools. On the other hand, the layout parasitic Evenhtally, the third phase aims to train and create machine
,   ").!
extraction phase aims to calculate the parasitic capacitances by leaming models for MEOL parasitic capacitances.
" 
scanning the given layouts, fractming them into patterns, and
*"  
 
  

A. Generate Training A1EOL Patterns
matching each layout pattern with a capacitance formula that is
  -  ! '    " =6I ).  "
stored in the conesponding pre-characterized library. The training patterns consists of 25K MEOL patterns for
' =!6 ,       -     /0       ! 
The 2.5D extraction methods are used in rule-based each device (transistor) type in a certain process node. Each
, " ! '   )."  
extraction for interconnects. They discretize layout MEOL pattern consists of several metal layers that construct
  = -   ,      " *
interconnects into 2D cross-section patterns in x and y gate, somce, and drain terminals of a certain device as shown
! ' "  = -      +! 3! '        
directions. Then, for each 2D cross-section, the plate and in Fig. 1. They are created by scanning many real layout
"/0 -    
fringing capacitances (per unit length) are calculated using pre­ designs including cache memory, digital to analog convetter,
  =  "! '         !   
characterized 2D capacitance formulas. The normalized and voltage controlled oscillator layouts. Also, additional
        1 ).  *      ""
capacitances are multiplied by the conesponding projection MEOL patterns were randomly generated covering different
/0            " 3L  3AL "   
(overlapping) length in order to obtain the total coupling dimensions from 1X to lOX of the minimum technological
2334!
=!6, ; ! '       ). 
capacitance values [11]. Such 2.5D extraction methods aren't dimensions. To obtain realistic and practical MEOL training
  " , ).     *  "       ? -
suitable for extracting MEOL parasitic capacitances in patterns, two main factors need to be considered: the multi­
    =-  " !
advanced process nodes because the 2D cross-section patterns dielectric environment and the multi finger devices.
  < "      K "/@0
ignore many 3D fringing parasitic capacitances such as gate Process node specifications (Metal stack)
     *  +! 3 274 294 2334! &   J).
end to metal as shown in Fig. 1 [6], [7], [11]. Note that the
  ,     " <  4*
increasing layout complexities increased the portion of 3D

"        K' 
fi·inging parasitic capacitances in the conesponding total
!    " -   ,  + -
capacitance. As a result, most of rule-based extraction tools  .*
"<" -,).274294! ).
prefer using 3D field-solvers to extractMEOL pattems [6], [7]. K 

- 
' 
%%%! ).#%&.(&%&J).
   representation
III. MEOLMACHINE LEARNING MODELS
).    
 3*'
Phase3: Training
A novelMEOL parasitic capacitance modeling methodology
      ! '    "#- &) C 
using machine learning is introduced. The proposed 
        -  M
methodology aims to provide a compact multi-dimensional
  "   /0  /!! &-  K- $

model for each device (transistor) type (e.g., N-type and P­  
0      !     *  
type) in a certain process node. Each compact model would +! <! '  "  ).  
 "- ! Fig. 3. The process of implementing MEOL parasitic capacitance
replace thousands of pre-characterized patterns.  !
models.

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 5B-4
58-4
1) ! "#$ G "" 
Multi-Dielectric Environment:
- 
Multi-dielectric 
process @
stacks 
became 
very 
common  in
  
advanced process technology nodes, where each metal 
    *   layer
6  # 6  #

may 
overlap *
with 
multiple 
planar  
and "
conformal 
dielectrics 
* "" /%0!- /0
each with a different dielectric constant (�:r). Using the multi­ " .
G

dielectric 
characteristics 
as 
inputs 
to 
the 
capacitance  
models
* 
would "
significantly 
complicate 
the  
modeling !
process.

So, 
in 6  # 6  #
 
order to  
consider 
the - 
multi-dielectric 
characteristics *
without
 
using them as inputs to the parasitic capacitance models, each
Diffusion and raised source dram (RSD) 
""   /(
0

process  node /
(metal @0
stack)  
should 
have 
its *
own  !
models. (b / 0)
+  
Furthermore, since each device type, in a certain process node, Fig. 5. Examples of training MEOL patterns showing (a) MOSFETs
+!6!,").*/0)
+'
* ""    / 0++'!
and (b) FinFETs.
may overlap with different dielectrics, each device type must
* !
also have its own parasitic capacitance model. ). C !
given MEOL pattern and the required capacitance component.
&2) ' !"$
Multi-Finger Devices: +!7*," )."
Fig. 6 shows an example of the proposed MEOL feature vector
-"
Multi-finger 
devices 
contain 
multiple 
gates  
and ).
MEOL    * 
that is used to predict a coupling capacitance between gate and
!
patterns. 'The ).
MEOL 
training 
patterns  
should  
consider 
the !
source nets.

position " of 
gates, *
where a 
gate 
may be 
part "
of 
a -" 
multi-finger A -  
geometry-based "
feature 
representation  is  
proposed  to
!
device. ' The 
spatial 
position "of 
gates 
may 
impact  ,
the extract geometrical properties of MEOL patterns  
  " ).  including  a
").!+!8
calculations of MEOL parasitic coupling capacitances. Fig. 4 * !'
whole pattern, aggressor polygons, and victim polygons. The
*
shows 
three  
identical 
gates *
with a ""
different 
spatial 
position  -   "
proposed geometry-based representation is done in four main
*
within a multi-finger device. Fig. 4 (a) shows 
 -" ! +! 8 /0 * a 
single 
gate !'"). "
steps. The first step aims to scan MEOL patterns and fracture
)
+'+!8/ 0*)
+' " 
MOSFET, Fig. 4 (b) shows a gate MOSFET on the edge of a their 
polygons 
into C 
quadrilateral or 
triangular 
polygons, !!
e.g.,
-" *+!8/0* 
multi-finger device, while Fig.4 (c) shows an intermediate gate  !' 
rectangles and triangles. The second step aims to represent each
)
+'"-" !'* 
MOSFET as a part of a multi-finger device. The results show polygon /(or " 
fractured 0
polygon)  by 
the 
spatial 
position "of 
its

that 
the 
coupling 
capacitance *
between  the 
source  
and 
gate * "
vertices, where the spatial position is measured from the center
  !+!6*,
varies based on the gate location. Fig. 5 shows some examples " !%* 
of the corresponding gate. In other words, the spatial position
")." ++' )
+'! "
of MEOL patterns for both FinFET and MOSFET technologies. of 
a ,
vertex  is 
its 
displacement " from the 
center " of 
the
 !'  
B. 
 ( 

 



 corresponding gate. The third step aims to represent vias and
Generate Reference Parasitic Capacitances "!+" 
fins. For vias, each set of symmetrical vias is grouped into a
"
After 
generating ).
MEOL 
training 
patterns, 
their 
parasitic !'/ 
cluster. The spatial position (displacement "
from the center " of

capacitance "
reference  
numbers 
are , 
extracted 
using  
Calibre  0  "
the corresponding gate) and the dimensions of via clusters are
,'<<" -23=4!'"  
xACT3D, 3D field-solver [12]. The reference numbers are used  "!) "
used as a representation of vias. On the other hand, the fins are
). !
to train MEOL machine learning models.  
represented  by "
fin * 
width, "fin 
spacing,   and "
fins !
count.

Eventually, the fourth step aims to concatenate 
 "     all "
feature
C.  '
 

 MEOL Feature Extraction " 
vectors together creating a final input vector that is used as an
% ""). 
input 
to 
the C 
required 
machine 
learning  !
model.  %
It 
is *
worth
In order to create an efficient MEOL parasitic capacitance
  """  -
mentioning that such geometrical representation captures non­
model, its inputs must provide sufficient information about the
 !'"*    *!
input ).
MEOL !
pattern. #
Hence, 
the 
inputs 
must  
manhattan geometries. The flow is described below.
include
"*). 1) '
 )$
Fracturing Polygons:
geometrical properties of the whole MEOL pattern, aggressor
 !'" %)."
In MEOL patterns, some polygons may have more than four
polygons, and victim polygons. The geometrical properties of
 !!'- !%
the *
whole 
pattern 
help 
in 
determining 
the 
pattern 
vertices, e.g., T-shaped polygons. In such cases, the polygons
structures,
* 
are " 
fractured 
into C 
quadrilateral  or 
triangular !
polygons. '
while the geometrical properties of aggressor  
   "  and 
The
victim
 "  ,- 
polygons 
help 
in  "
identifying 
the C 
required 
parasitic 
fracturing is done by scanning the polygons in the x-direction
coupling
 / 0!%"*
capacitance 
component, *
which 
is *
between 
the 
aggressor  
(perpendicular to gate). In case of capturing any polygon with
and
 
more 
than 84 
vertices, 
the 
polygon  is " 
fractured 
vertically 
the !
victim. '
The 
geometrical 
properties 
are  
represented 
as
by
"!#""* *
shown  in +!
Fig. 9!
7. '
Then, 
the 
polygons  are  
scanned in -
the y­
feature vectors. Hence, there is a feature vector for the whole
"" " 
direction /
(parallel 
to 0!
gate). %
In 
case "
of 
capturing 
any 
polygon
pattern, a feature vector for aggressor polygons, and a feature
"!" *8" !
with more than 4 vertices, the polygon is fractured horizontally.
vector for victim polygons. All feature vectors have the same
c::::J ""/P 0
K    
!
size.  
Eventually, 
the 
three "
feature 
vectors 
are  
concatenated Diffusion (source/drain)
"""
together conforming a final feature vector that represents the - G/ ""0
Via (diffusion contact) O
J Whole pattern
$  -Gate 
Cgs: gate to source coupling capacitance 3   representation
$  -Metal!
Cds: gate to drain coupling capacitance O *
J
J
J


Aggressor polygon

representation

 
 
Drain

Source 

 *   * A!AA:9(' Cgs Cds
 * 
� K & 


L
* +++. ('  * A!A3379(' * +++,- ('
0.0097jF   G
Victim polygons
�
gate to source capacitance
/0/ 0/0
(a ) (b) (c) 
representation
Fig. 4. Examples of MEOL coupling capacitances in case of (a) a single
+!8!,")."/0
  !
LM)  !
' !
'!
"!
N
)
+'/ 0 "-"  /0 Feature vector� [whole pattern vector, aggressor vector, victim vector] 

Fig. 6. An example of the proposed MEOL feature vector that is used

MOSFET, (b) a gate at the edge of a multi-finger device, and (c) a gate
 "-" !', =>  +!7!," )." 
in the middle of a multi-fmger device. The experiment used 28nm node
* !  )
+'!
to predict gate to source coupling capacitance in a MOSFET.
with minimum dimensions.

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 5B-4
1 K
' "n �;���;�:n:�� ��
+ ?K3K= K<
mdPJ TABLE I
'H.%
58-4

U
6  K< K= '(%&%&J#$K(K('(
)+).K(
%'%K%'&

TRAINING HYPER PARAMETERS OF MEOL PARASITIC CAPACITANCES
+,-  &&).
!
NNMODELS
/ 0 K3 "   7 
80% ( 20K patterns)
Parameter Value
  >AB/=AI0
 Traininl! set
+!9!,"",- !    =AB/6I0
Fig. 7. An example of fracturing a polygon in x-direction. Test set 20% ( 5K patterns)
O
(  6AA
500
& 

'
 / ( 
0  
) Batch size
7   3AB/=I0
2) Creating a Feacture Vector for Each MEOL Layer Validation set 10% (2K patterns)
" "  ).  "     
 C
Mean square error
After fracturing all MEOL polygons for each layer in a Loss function
   3-<
 ). !        1e 3
-
Learnin�:: rate
certain MEOL pattern. Each polygon is represented by the O
"( $

""* Batch normalization


YES
6AA
spatial position of its four vertices, where the spatial position is
 ""  Epochs 500
"(   
measured from the center of the corresponding gate in the given Ootimizer Adam
).!#   +!3A*,""""
MEOL pattern. Hence, each polygon is represented by a vector Frg. 10 shows an example of the final mput feature vector for
", ",! ).!
of eight values that represent x and y locations of each vertex. a certain MEOL pattern.
+,). *6 
For example, an MEOL layer with 5 polygons is represented
   " 8A    *  +! >! %  " !  

 


 
by a vector of 40 indices as shown in Fig. 8. In case of D. MEOL Parasitic Capacitance Models
  8 
triangular polygons, they are represented by 4 vertices, but the '*         ).
*! Two modeling approaches are used to create MEOL
last two vertices have the same position.  !'"&-
1  /

 '$ parasitic capacitance models. The first approach uses Neural­
&*@ /&&0   *     
3) Representing Vias and Fins:
).     ! (  Networks (NN) models, while the second approach uses

G(/
G(0!' "
MEOL patterns may contain many vias. Representing all
** "" Support Vector Regressions (SVR). There is a model for each
       ! '  " 
vias with their vertices would significantly increase the feature
!# * device type in a certain process node. The inputs of both
      "    
vector size. Hence, vias are grouped into clusters, where each
 "       "  methods are the concatenated feature vectors that include
  "  ).  
set of symmetrical vias are clustered together conforming a
,/0"!  , geometrical representations of an MEOL pattern, aggressor
 *+!3A!
matrix (or a vector) of vias. Each cluster is represented by six
?"/, ,0 polygons, and victim polygons as shown in Fig. 10.
parameters: the spatial position of its center (in x and y axes),  3
 356 $
   "   ,-     "  - 1) Neural Networks Model:
the number of vias in x-direction, the number of vias in y­ '&&  
* "   The NN architectures are obtained using neural architecture
direction, the width of the corresponding vias, and the spacing 23<4!" " 
*      *  +! :! )  search [ 13]. As of the search space, the number of hidden layers
between the corresponding vias as shown in Fig. 9. On the  " 3  8   " "  
 "  ?"*  varies from 1 to 4, the activation function of each layer
other hand, fins are represented by three parameters: fin width,  *        "  
" "! alternates between relu and tanh, the number of neurons per
 "P7*
fin spacing, and fins count.
2 
## 3#4 (  )$ hidden layer varies from n/6 to n, where n is the input vector
      "   
4) Maximum Number of MEOL Polygons:
) , "" size, and the initialization parameter of each layer alternates
* !" &&
Obtaining the maximum number of polygons for each layer
/!! "" 30). between glorot_normal and he_normal. A fully connected NN
  !  !'
(e.g., diffusion, poly, and metall) in MEOL patterns helps in
 "     " ).   is considered. A grid search is used as a search strategy. The
*C"*
identifying the input vector size of MEOL machine learning
 !' ,   "  "  ). lowest mean square error of test sets with smallest architecture
  !' %&&-
models. The maximum number of polygons for each MEOL
 "  @   is used as an evaluation method. Table I summarizes NN hyper­
!+!33*&&
layer is identified by checking the corresponding layout design
   " ).! parameters. Fig. 11 shows the most common NN architecture
  ").=> 9
rules and by observing many fractured MEOL training patterns.
%  " )
+' /=>   0  , that is obtained for MEOL patterns in 28nm and 7nm process
 !%" *P8P8 P6
In case of MOSFETs (28nm process node), the maximum
 "" "" - "" nodes. It consists of three hidden layers with n/4, n/4, and n/5
!'""
numbers of fractured polygons for gate, field-poly, diffusion,
 3997 7!" neurons, respectively. The activation function of the layers are
 *
and metall layers are 7, 7, 6, and 6, respectively. As of vias, the
,   "    8! )     tanh, tanh, and relu, respectively, while the initializations are
 !
maximum number of via clusters is 4. On the other hand, in
"++'/9 0,  golort_normal, golort_normal, and he_normal, respectively.
/AA0
case of FinFETs (7nm process node), the maximum numbers
" "   "  " - ""   =?G/"0 (0,0) 3?G/0
of fractured polygons for gate, field-poly, diffusion, raised C2: Via Cluster (left) C1: Via Cluster (right)
= � .1 .1 3
 /(
0  " 
C2 center I • 1 1 • 1 C1 center
-- --
�
source drain (RSD), device local interconnect, and field local
<7==7 7!" /,==0 /,330
interconnect layers are 3, 6, 2, 2, 6, and 6, respectively. As of (x2,y2) 1 (x 1,y 1)
. I
�
V1a count (x)� 1 I .
  ,   "    8!  
I
G/0Q6 1 • 1
G/,0Q3
vias, the maximum number of via clusters is 4. All previous
1
: :G/,0Q3
Via count (x)� 1
Via count (y)� 5 - - - -Via count (y)� 5
  "  "  * ).   G/0Q6
steps are performed for the whole MEOL pattern, aggressor
 !'"  7  !
L
polygons, and victim polygons. The final input vector size is Via feature vector�
  ? 2,33/,0/0* +3
[ x 1,y 1, via count(x), via count (y), via width , via spacing For C 1
calculated by:  ,==/,0/0* 4+=
, x2,y2, via count(x), via count (y), via width , via spa cing] For C 2 
input size= 3 +F+
(v � }

       

 /30
Fig. 9 . An example showing the feature vector of MEOL vias.
vector size(i) (1)
+!:!,*"").!

Q  
*, ").G

••
where x is the number of MEOL layers, V is the via vector  .+ G + G3
*+"!    "
size, while F is the fin vector size.
/AA0 K=/,==0
0 ) P2(
: .. 4 � :r ?- ?- K=/,<<0P2(x3,y3)
 
1: 2fl
3
�?
I
t _-:.: ; I

: t-:.-:.: � .
I

-
I K=/,880
.+ G +
 "
G=

r2(� l:y1) P2(x4,y4)

1 1
K=/,330
6 P#  7
L
�====• 7
"
Gate/poly feature Vector-
2,33,==,<<,88+K3? .+ G +
[x 1, y 1, x2, y2, x3, y3, x4, y4 ForP1: Center
 pol ygon  "
G<
,33,==,<<,88+K=?3 
, x 1, y 1, x2, y2, x3, y3, x4, y4 For P2: 1�1 right pol ygon
,33,==,<<,884+K<?3 "   !
L2G3G=G<4 
, x 1, y 1, x2, y2, x3, y3, x4, y4 ] For P 3: 1�1 left polygon  Final input feature vector� [Vector1, Vector2, Vector3]
+! >!  , "  ).     +!3A!,*""
Fig. 8. An Example of representing MEOL layer polygons using a Fig. 10. An example showing the generating of the final input vector
"!  ").,!
vector of vertices. that is used for MEOL parasitic capacitance extraction.

374
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 5B-4
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Feature Vectors '   36 
The proposed models are tested over more than 15M devices
Q# vector size (n)� 3 x m
%/0Q<V#
Input  several
in  designs
  ?
including:  oscillators,
ring -
voltage­
Q  &Q 88P8P6
Neurons� n n/4 n/4 n/5   oscillator,
 and
  digital
 to
 analog
 converter
 designs.
!
controlled
  Q
0 
0 
Activation � tanh tanh relu
+!3=* 

�-
Fig. 12 shows the error histograms across all designs using the
NN models, SVR models, and Calibre xRC as a rule­
 && 
G(   ,(-
proposed

IAgg·���f-
     tool
 with
* a pre-characterized
-  library.
 !'  show
*
c"'
based The results
6 i i i i  the
that   NN
 proposed && models
  have
 a superior
 accuracy
 as


Cop�"�": '""'
I 7
" r 'Q/0
  ,(! "
Vi<tim•
� %," cooplmg ( Cg')
WlliCO

compared
NN
to Calibre xRC. Also, the prediction runtime of the
&& 
G( " ,( 3!A6L 
and SVR models are faster than Calibre xRC by 1.OSX and
+!33!,"&&").
Fig. 11. An example of the most common NN architecture for MEOL 1.3X, respectively. Moreover, the prediction runtime of the NN
3!<L! "&&
,!
parasitic capacitance extraction.   SVR
and
G( models
  are
 faster
" than
 Calibre
  xACT3D,
,'< 3D
<" -
field­
&
2) 7 / $
Support Vector Regressions:  :9L 3A6L!
solver, by 97X and 105X, respectively.
   
G(-!'
A grid search is used to obtain SVR hyper-parameters. The
@ is
kernel  set
 to
 the
    function
radial basis " because
 MEOL
).     -#  3
,- !"
parasitic capacitance extraction is a non-linear problem. As of '   ).        
/0"
the search space, the regularization parameter (C) varies from 9 *++'!').
3=A"A!33 "
1 to 20, gamma varies from 0.1 to 1, and epsilon varies from "9 ""  /(
0
A!A6A!6!'*C" 
0.05 to 0.5. The lowest mean square error of test sets is used as "" /!! 0 
 evaluation
an  method.
 ! The
'   
most common 
hyper parameters "   !
, "" ).   
  ").=> 9
that are obtained for MEOL patterns in 28nm and 7nm process     , ""  ! ' 
 ?>/0A!<
nodes are: 8 as a regularization parameter (C), 0.3 as a gamma,   "  ).   36AI! ' 
 A!3!
and 0.1 as an epsilon.   " ""  
 ).
%G! EXPERIMENTAL
IV. (
.'

LK(%&'.RESULTS    ! '   "
 ",  ,'<
' * ?=> 9!'
The testing covered two process nodes: 28nm and 7nm. The < " -  % L/(0 6-=7>A =!6AJ# * >
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testing methodology aims to select MEOL patterns in several K   37J " (!'   " , 
 designs
real  (not
/ part
 of
" the
 training
 sets)
0 and
  extract
, them
 >!3!'" 7>3!
 the
using  proposed ). NN
  MEOL && models,
  the
 proposed
  MEOL
). " " &&  ,

G(  ,'<"<" -

SVR models, Calibre xACT3D as a reference 3D field-solver  " 
23=4 ,(-  "=> 
[12], Calibre xRC as a rule-based tool for 28nm process node  * 39A 39A   3<7  ! '
2384  ,'  ,2364*
[14], and Calibre xACT as a hybrid extraction tool [15], which " !'
, MEOL
extracts ). layers
 using
 a field-solver,
" - for
" 7nm
9 process
 ", 3<!>%
 !  ,'<!
node. All errors are measured relative to Calibre xACT3D. L/(06-=7>A=!6AJ# 37J"(!
A.
& "

7 )TU6BU3!7B" !

Outliers> 15%1 error represents 1.6% of the dataset.
    &.#  3
Testing Results on 28nm Process Node
   ?=!=6B
Standard deviation: 2.25%
' proposed
The   MEOL
). modeling
  methodology
  is
 tested
  on
 8
=> process
28nm  node,
  which
* is
 a MOSFET
)
+' technology.
!  The
' =
). 
MEOL " 28nm
layers of => process
 are
 ""  / ""
diffusion, via (diffusion
0 gate,
contact),  field
"  poly,
 and
  metall.
3! Two
'* different
"" MEOL
). A
0
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models are implemented to cover two different device types. 00 �00���7MN�O�NM7���00�0 0

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The total number of training MEOL patterns are SOK. They are 
Errors 1\

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obtained from different real designs including cache memory,
/0
(a)
& "

 ).

digital to analog converters, and other MEOL patterns that are
)TU6BU>!9B" !
Outliers> 15%1 error represents 8.7% of the dataset.
8
   ?<!6B
  generated.
 ! The
' parasitic
 capacitance
 reference
" Standard deviation: 3.5%
randomly
 ",  ,'<
numbers of the patterns are extracted using Calibre xACT3D, =
< field-solver,
3D " - on
 Intel
% Xeon(R)
L/(0 ES-2680,
6-=7>A =!6AJ#
2.50GHz with* 8>
K and
CPUs   16G
37J of
" RAM.
(!'  runtime
The total  of
" extracting
, the
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patterns is 4.3 hours. The input vector size of the models is 696.
As of the fully connected NN models architecture, the two
"" && *  
  have
models  the
 same
 !
architecture. The ' NN
&& architecture
 (b)
/ 0
" *398398 38A
& "

consists of three hidden layers with 174, 174, and 140 neurons, )TU6BU3:!9B" !
Outliers> 15%1 error represents 19.7% of the dataset.
<
!'" 
respectively. The activation functions are tanh, tanh, and relu,
   ?6!<B
Standard deviation: 5.3%
!'"* 
respectively. The total training runtime of the two models is =
<!7%L/(06-=7>A=!6AJ# 37J"
3.6 hours using Intel Xeon(R) ES-2680, 2.50GHz, and 16G of 3
(!
RAM .
A
 of
As " SVR

G( models,
  the
 two
* SVR
G( models
  have
 the
 same

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- which
hyper-parameters * are:
? 8> as
 a regularization
 parameter
 
/0A!< A!3!' 
(C), 0.3 as a gamma, and 0.1 as an epsilon. The total training
(c)
/0
"* 3!9%L/(06-
runtime of the two models is 1.7 hours using Intel Xeon(R) ES- +!3=!"=> /0 
Fig. 12. Error histograms of 28nm process node using (a) the proposed
=7>A=!6AJ# 37J"(!
2680, 2.50GHz, and 16G of RAM . && / 0 
G(  /0-  
NN models, (b) the proposed SVR models, and (c) a rule-based tool.!

375
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 5B-4
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C     ! '* "" 
& "
)TU6BU=!98B" !
1:l 8M
>
"'
required machine learning models. Two different machine

   ?=!63B         ). 
<=! 7
fl 6M learning methods are used to create MEOL parasitic
  ?      
i5 4M
.

8
§'=
capacitance models: support vector regressions and neural
*@! '         *
0 A
�2M networks. The proposed methodology is tested over two
  ?=> 9!' 
0 process nodes including: 28nm and 7nm. The testing covered
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������� ���������������� devices in several real designs with more than 40M devices.
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 The proposed methodology provided outstanding results as

Errors 1\
   " - *    S A!=B 
/0 compared to field-solvers with an average error < 0.2%, a
(a)
   S<B  "3AAL!
& "

"' )TU6BU>!9B" ! standard deviation< 3%, and a speed up of 100X.
Outliers> 15%1 error represents 8.7% of the dataset.
§ 7
0)
6M
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Standard deviation: 3.64% (+(&

·f:l 8
4M REFERENCES
[= 234 #!(J!+!I@O!X!' '!-
!IYKJ?.
"""
S [1] H. Ren, G. F. Kokai, W. J. Tumer, and T.-S. Ku, "ParaGraph: Layout
0
2M K    K K   J &
i:l
A Parasitics and Device Parameter Prediction using Graph Neural
0 &*@Z&+&+ 9-0 8: ! #
 (
Networks," in ]0]0 57th ACl'vf!IEEE Design Automation Conference
-:B
->B
-9B
-7B
-6B
-8B
-<B
-=B
-3B
S-3AB
-3AB

AB
3B
=B
<B
8B
6B
7B
9B
>B
:B
3AB
T3AB
I

s
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V •
oo�oo����MN-o-NM����oo�oo
�� I I I I I I I I

I ��
 2=4 H!
@K!H!I! 
!XY.K?
z / 0
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. --P "8AZ7
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u 3A!3A37P1!!=A36!A6!A<<!
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-3AB
-:B
->B
-9B
-7B
-6B
-8B
-<B
-=B
-3B

3AB
S-3AB

AB
3B
=B
<B
8B
6B
7B
9B
>B
:B

T3AB
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+!3<!"9 /0  J.-P. Raskin, "Parasitic Gate Capacitance Model for Triple-Gate
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  !"!7A!33!<93A5
&& / 0 
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G( - [6] W. Yu, M. Song, and M. Yang, "Advancements and Challenges on
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 70 
( ! #
 ( ;7! 
parameters which are: 8 as a regularization parameter ( C), 0.3
 A!3!' Asia and South Pacific Design Automation Conference (ASP-DAC),
X!=A=3!>835>87!
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"* 3!9%L/(06-=7>A 294 .!
[!.O!O $!LY).J- K
of the two models is 1. 7 hours using Intel Xeon( R) ES-2680, [7]
 , G" "    
=!6AJ# 37J"(! Capacitance Extraction Verification for Design Enablements in
   ++' 'Z  &+. : :


2.50GHz, and 16G of RAM.
'   =A  Advanced FinFET Technology," in ]018 IEEE International
(   !"
 7 7
  ;!77 
The proposed models are tested over more than 20M devices
"
( K..@ ! Conference on Electron Devices and Solid State Circuits (EDSSC),
X!=A3>!35=! ?3A!33A:P

!=A3>!>8>9A9A!
from ring oscillators, SRAM, and PLL clock generator designs. Jun. 2018, pp. 1-2. doi: 10.1109/EDSSC.2018.8487070.
+!3<*  2>4 .!-X!

Y,"- 
Fig. 13 shows the error histograms across all designs using the [8] L.-J. Sun et a/., "Extraction of geometry-related interconnect variation
  Z:  !" !
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  &&  
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results show that the proposed NN models has a good accuracy
* &&  
"K( -J+ -
Simulations of Parasitic Capacitances Related to Multiple-Gate Field­
 ,'! " "" ' Z &++. : 
  
Effect Transistors Architectures," in ]008 IEEE Topical Meeting on
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   ' 7)#X!=AA>!
NN and SVR models are faster than Calibre xACT by 91X and
&& 
G( " ,' :3L  3><53>7! ?3A!33A:P
%!=AA>!6=!
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.!

Y& ('  
1OOX, respectively. Moreover, the prediction nmtime of the [10] L. Sun et a/., "A Novel Customized RC Tightened Comer Modeling
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&&  
G(    "    ,'< <   

K%
    
Methodology Using Statistical SPICE Simulation in Advanced
field-solver, by 101X and llOX, respectively.
" - 3A3L 33AL! ++''Z&+. 20 : :

 ( 
FinFET Technology," in ]018 14th IEEE Intemational Conference on
77

 :
  0) ;:7:  )! =A3>
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!358! ?3A!33A:P%
%'!=A3>!>678:7A!
pp. 1-4. doi: 10.1109/ICSICT.2018.8564960.
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!#  $!%Y-H 
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Machine Leaming Compact Models for Interconnect Parasitic
,   Z  &+& 8: 1 ?60  
0
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 ( ! ;!  ! =A=3 ! 357! ?
 "  " ++'  Leaming for CAD (MLCAD), Aug. 2021, pp. 1-6. doi:
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developed for middle end of line patterns around FinFETs and
)
+'     ! '  23=4 10.1109/MLCAD52597.2021. 9531300.
Y  ,' < U
  % 
"*!Z
MOSFETs using machine learning methods. The current [12] "Calibre xACT 3D I Siemens Digital Industries Software."
," --  ?PP !*!!P-
PP - P-
https:/Ieda. sw. siemens. com/en-US/ic/calibre-design/circuit­
extraction tools either rely on field-solvers or pre-characterized "P,-< P/ X!3:=A=30!
   , ). ! ' -  verification/xact-3d/ (accessed Jul. 19, 2021).
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( 

 "" " , [ 13] P. Liashchynskyi and P. Liashchynskyi, "Grid Search, Random Search,
J?H"&
Z@",&+>+9, 
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