Fabrication of CMUTs

Sensors and transducers

DR jose joseph
Department of SOESA

Harisankar R
hari.es22@duk.ac.in
Fabrication of CMUTs
(i) sacrificial release
The vacuum is created during a surface micromachining process by
etching a sacrificial layer between the top plate and the substrate.

a) On the wafer, a silicon nitrite insulating layer is first applied, then a

layer of sacrificial polysilicon. To define fin areas between cells, a
sacrificial layer is designed.
b) Other sacrificial layer of polysilicons is further deposited.
c) To create a channel into the cell for the sacrificial polysilicon etch,
we once more deposit a layer of sacrificial polysilicon..
d) Place the silicon nitride top plate layer and design it. In
order to access the sacrificial etch channel, a hole is cut in
the silicon nitride's top layer.
e) The sacrificial polysilicon layer is subsequently removed using a KOH
wet etch. KOH passes into the cell through an etch channel after
entering through pores in the top layer of silicon nitride.
created by a second polysilicon sacrificial deposition. The structure of
silicon nitride remains intact as KOH has a better selectivity for
polysilicon compared to silicon nitride.
f) The sacrificial releasing stage leaves a space, and it is vented to
atmosphere. Then gap is sealed with executing low pressure
chemical vapour deposition of silicon nitride .This closes the
 narrow etch channel When sealing a gap, LPCVD is performed at a
relatively low pressure in order to properly fill the vacuum..
g) Finally, aluminum is deposited to form the top electrode,
electrical contact, and interconnection.

ii) Wafer Bonding

Here, silicon on insulator and micromachining are combined
(SOI)
The CMUT is created using technology. Wafer bonding offers
the benefits of homogeneity and control, particularly with
regard to plate thickness, currently known as the device layer
of SOI wafer.

a) a) The first wafer is a high-grade, heavily-doped Si wafer. Both prime

and SOI wafers have sufficient carrier densities to prevent operation-
related depletion.
b) Thermal oxidation on the si substrate.
c) After that, the main plate's thermal oxidation determines the height
of the CMUT gap. Lithographically determined gap dimensions and
geometry are then transferred by wet or dry etching to oxide up to
Si.
d) Another thermal oxidation.
is employed to hide the exposed silicon and stop shorts between the
gap's bottom.
and the conductive plate that will be created from the SOI wafer in
the end.
e) The RCA is given a thorough cleaning, and the SOI plate is then
connected to it directly afterward. During
bonding: When an SOI wafer and an oxidised silicon wafer come into
contact, weak hydrogen bonds and van der Waals forces hold the
two wafers together. Then another thermal oxidation is used to
create a covalent link between the two plates.
(1100 °C roughly).
f) The following action entails releasing the CMUT wafer by removing
the handle and latent oxide (BOX) from the SOI wafer.
g) The bulk of the SOI handle is removed using mechanical grinding,
and the remaining handle is stripped using a wet etch in KOH or
TMAH up to the BOX as an etch stop..
h) A second wet etch in HF acid is used to remove the BOX layer; this
time, the Si device layer serves as the etch stop.
i) By etching via all the way to the Si wafer, top-side connections to
the bottom electrode are created.
j) Sputtering is used to deposit metal (aluminium).
k) The metal pads are separated using a device isolation etch, and the
device is electrically insulated by performing an etch down through a
conductive silicon wafer..
l) The sidewalls of the wafer edge can then be passivated via low
temperature oxide or nitride deposition, preventing shorts caused by
surface conduction.