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    Krumpus H.
    15 views52 pages
    The document describes the basic design and operation of a random access memory (RAM). RAM uses an array of latch circuits to store data at addressable locations. It has an address decoder, data input and output lines, and strobe lines to write data into or read data out of the latches based on the address. RAM allows fast random access of stored data using an address and can be read from and written to dynamically.

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    week9 (2)

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    The document describes the basic design and operation of a random access memory (RAM). RAM uses an array of latch circuits to store data at addressable locations. It has an address decoder, data input and output lines, and strobe lines to write data into or read data out of the latches based on the address. RAM allows fast random access of stored data using an address and can be read from and written to dynamically.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    15 views52 pages

    Week 9

    Uploaded by

    Krumpus H.
    The document describes the basic design and operation of a random access memory (RAM). RAM uses an array of latch circuits to store data at addressable locations. It has an address decoder, data input and output lines, and strobe lines to write data into or read data out of the latches based on the address. RAM allows fast random access of stored data using an address and can be read from and written to dynamically.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 52

    A 1-Bit Memory

    This stuff is truly


    unforgettable!

    OR + NOT = NOR
    A 1-Bit Memory
    Setting a 1-Bit Memory
    Initializing a 1-Bit Memory
    From S-R Latches to D-Latches

    >

    Worksheet!
    A Random Access Memory (RAM)

    1 2 address 00
    bits
    0 3 data
    1 bits (out)
    01
    3 data
    1 bits (in)
    0 10
    Read 11
    1 Write
    A Random Access Memory (RAM)

    2 address 00
    bits
    3 data
    bits (out)
    01
    3 data
    bits (in)
    1 1 0 10
    Read 11
    Write
    A Random Access Memory (RAM)

    1 2 address
    bits
    0 3 data
    1
    bits (out) 1
    3 data
    bits (in)
    0
    1 1 0
    1 Read
    Write
    A Random Access Memory (RAM)

    D D D
    2 address D Q D Q D Q
    bits Latch Latch Latch
    Strobe Strobe Strobe

    D D D
    D Q D Q D Q
    3 data Latch Latch Latch 3 data
    bits (in) Strobe Strobe Strobe bits (out)
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Read Strobe Strobe Strobe
    Write
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Strobe Strobe Strobe
    A Random Access Memory (RAM)

    D D D
    Decoder

    2 address D Q D Q D Q
    bits Latch Latch Latch
    Strobe Strobe Strobe

    D D D
    D Q D Q D Q
    3 data Latch Latch Latch 3 data
    bits (in) Strobe Strobe Strobe bits (out)
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Read Strobe Strobe Strobe
    Write
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Strobe Strobe Strobe
    A Random Access Memory (RAM)

    D D D
    Decoder

    2 address D Q D Q D Q
    bits Latch Latch Latch
    Strobe Strobe Strobe

    D D D
    D Q D Q D Q
    3 data Latch Latch Latch 3 data
    bits (in) Strobe Strobe Strobe bits (out)
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Read Strobe Strobe Strobe
    Write
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Strobe Strobe Strobe
    A Random Access Memory (RAM)

    D D D
    Decoder

    2 address D Q D Q D Q
    bits Latch Latch Latch
    Strobe Strobe Strobe

    D D D
    D Q D Q D Q
    3 data Latch Latch Latch 3 data
    bits (in) Strobe Strobe Strobe bits (out)
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Read Strobe Strobe Strobe
    Write
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Strobe Strobe Strobe
    A Random Access Memory (RAM)

    D D D
    Decoder

    2 address D Q D Q D Q
    bits Latch Latch Latch
    Strobe Strobe Strobe

    D D D
    D Q D Q D Q
    3 data Latch Latch Latch 3 data
    bits (in) Strobe Strobe Strobe bits (out)
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Read Strobe Strobe Strobe
    Write
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Strobe Strobe Strobe
    A Random Access Memory (RAM)

    D D D
    Decoder

    2 address D Q D Q D Q
    bits Latch Latch Latch
    Strobe Strobe Strobe

    D D D
    D Q D Q D Q
    3 data Latch Latch Latch 3 data
    bits (in) Strobe Strobe Strobe bits (out)
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Read Strobe Strobe Strobe
    Write
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Strobe Strobe Strobe
    A Random Access Memory (RAM)

    D D D
    Decoder

    2 address D Q D Q D Q
    bits Latch Latch Latch
    Strobe Strobe Strobe

    D D D
    D Q D Q D Q
    3 data Latch Latch Latch 3 data
    bits (in) Strobe Strobe Strobe bits (out)
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Read Strobe Strobe Strobe
    Write
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Strobe Strobe Strobe
    A Random Access Memory (RAM)

    D D D
    Decoder

    2 address D Q D Q D Q
    bits Latch Latch Latch
    Strobe Strobe Strobe

    D D D
    D Q D Q D Q
    3 data Latch Latch Latch 3 data
    bits (in) Strobe Strobe Strobe bits (out)
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Read Strobe Strobe Strobe
    Write
    D D D
    D Q D Q D Q
    Latch Latch Latch
    Strobe Strobe Strobe
    Small Memory, “Big”
    Memory…
    8 address
    2 address bits
    bits
    3 data 3 data X data X data
    bits (in) bits (out) bits (in) bits (out)

    Read
    Write Read
    Write

    X
    A “Calculator”

    Instruction Register Load 5 into Register 0

    Register 0 0

    Register 1 0

    Register 2 0

    Register 3 0
    A “Calculator”

    Instruction Register Load 5 into Register 0

    Register 0 5

    Register 1 0

    Register 2 0

    Register 3 0
    A “Calculator”

    Instruction Register Register2=Register0+Register1

    Register 0 5

    Register 1 0

    Register 2 0

    Register 3 0
    A “Calculator”

    Instruction Register Register2=Register0+Register1

    Register 0 5

    Register 1 0

    Register 2 5

    Register 3 0
    A “Calculator”

    Instruction Register Register2=Register0+Register2

    Register 0 5

    Register 1 0

    Register 2 5

    Register 3 0
    A “Calculator”

    Instruction Register Register2=Register0+Register2

    Register 0 5

    Register 1 0

    Register 2 10

    Register 3 0
    A “Calculator”

    Instruction Register Register2=Register0+Register2

    Register 0 5 00000101

    Register 1 0 00000000

    Register 2 10 00001010

    Register 3 0 00000000
    00 add A “Calculator”
    01 subtract
    10 multiply
    11 divide

    Instruction Register Register2=Register0+Register2

    Register 0 5 00000101

    Register 1 0 00000000

    Register 2 10 00001010

    Register 3 0 00000000
    00 add A “Calculator”
    01 subtract
    10 multiply
    11 divide

    Instruction Register Register2=Register0+Register2 00______

    Register 0 5 00000101

    Register 1 0 00000000

    Register 2 10 00001010

    Register 3 0 00000000
    00 add A “Calculator”
    01 subtract
    10 multiply
    11 divide

    Instruction Register
    Register2=Register0+Register2 0010____

    Register 0 5 00000101

    Register 1 0 00000000

    Register 2 10 00001010

    Register 3 0 00000000
    00 add A “Calculator”
    01 subtract
    10 multiply
    11 divide

    Instruction Register
    Register2=Register0+Register2 001000__

    Register 0 5 00000101

    Register 1 0 00000000

    Register 2 10 00001010

    Register 3 0 00000000
    00 add A “Calculator”
    01 subtract
    10 multiply
    11 divide

    Instruction Register
    Register2=Register0+Register2 00100010

    Register 0 5 00000101

    Register 1 0 00000000

    Register 2 10 00001010

    Register 3 0 00000000
    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0

    Program Counter 00000000 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00000000 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000000

    Register 2 00000001

    Register 3 00000000
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0

    Program Counter 00000000 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00000000 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000000

    Register 2 00000001

    Register 3 00000000
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0

    Program Counter 00000000 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00000000 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000000

    Register 2 00000001

    Register 3 00000000
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0

    Program Counter 00000000 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00110010 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000000

    Register 2 00000001

    Register 3 00000000
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0

    Program Counter 00000000 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00110010 Register3=Register0+Register2 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000000

    Register 2 00000001

    Register 3 00000000
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0

    Program Counter 00000000 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00110010 Register3=Register0+Register2 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000000

    Register 2 00000001

    Register 3 00000011
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Program Counter Incremented
    Binary Base 10

    00110010 00000000 0

    Program Counter 00000001 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00110010 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000000

    Register 2 00000001

    Register 3 00000011
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0

    Program Counter 00000001 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00110010 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000000

    Register 2 00000001

    Register 3 00000011
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply
    11 divide What is Memory Location

    this Binary Base 10

    command 00110010 00000000 0

    Program Counter 00000001 saying? 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00011010 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000000

    Register 2 00000001

    Register 3 00000011
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0

    Program Counter 00000001 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00011010 Register1=Register2+Register2 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000000

    Register 2 00000001

    Register 3 00000011
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0

    Program Counter 00000001 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00011010 Register1=Register2+Register2 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000010

    Register 2 00000001

    Register 3 00000011
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Program Counter Incremented
    Binary Base 10

    00110010 00000000 0

    Program Counter 00000010 00011010 00000001 1

    10001100 00000010 2

    Instruction Register 00011010 00000011 3

    00000100 4
    Register 0 00000010

    Register 1 00000010

    Register 2 00000001

    Register 3 00000011
    11111111 255

    Central Processing Unit (CPU) Memory


    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0
    8 bit
    00000010 00011010 00000001 1
    Program Counter address
    10001100 00000010 2

    Instruction Register 00011010 00000011 3

    00000100 4
    Register 0 00000010
    8 bit 8 bit data
    Register 1 00000010 data in out

    Register 2 00000001

    Register 3 00000011 Read


    11111111 255
    Write
    Central Processing Unit (CPU) Memory
    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0
    8 bit
    00000010 00011010 00000001 1
    Program Counter address
    10001100 00000010 2

    Instruction Register 00011010 00000011 3

    00000100 4
    Register 0 00000010
    8 bit 8 bit data
    Register 1 00000010 data in out

    Register 2 00000001 1

    Register 3 00000011 Read


    11111111 255
    Write
    Central Processing Unit (CPU) Memory
    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0
    8 bit
    00000010 00011010 00000001 1
    Program Counter address
    10001100 00000010 2

    Instruction Register 00011010 00000011 3

    00000100 4
    Register 0 00000010
    8 bit 8 bit data
    Register 1 00000010 data in out

    Register 2 00000001 1

    Register 3 00000011 Read


    11111111 255
    Write
    Central Processing Unit (CPU) Memory
    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0
    8 bit
    00000010 00011010 00000001 1
    Program Counter address
    10001100 00000010 2

    Instruction Register 00011010 00000011 3

    00000100 4
    Register 0 00000010
    8 bit 8 bit data
    00000010 10001100
    Register 1 data in out

    Register 2 00000001 1

    Register 3 00000011 Read


    11111111 255
    Write
    Central Processing Unit (CPU) Memory
    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0
    8 bit
    00000010 00011010 00000001 1
    Program Counter address
    10001100 00000010 2

    Instruction Register 00011010 00000011 3

    00000100 4
    Register 0 00000010
    8 bit 8 bit data
    00000010 10001100
    Register 1 data in out

    Register 2 00000001

    Register 3 00000011 Read


    11111111 255
    Write
    Central Processing Unit (CPU) Memory
    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0
    8 bit
    00000010 00011010 00000001 1
    Program Counter address
    10001100 00000010 2

    Instruction Register 10001100 00000011 3

    00000100 4
    Register 0 00000010
    8 bit 8 bit data
    Register 1 00000010 data in out

    Register 2 00000001

    Register 3 00000011 Read


    11111111 255
    Write
    Central Processing Unit (CPU) Memory
    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0
    8 bit
    00000010 00011010 00000001 1
    Program Counter address
    10001100 00000010 2

    Instruction Register 10001100 00000011 3

    00000100 4
    Register 0 00000010
    8 bit 8 bit data
    Register 1 00000010 data in out

    Register 2 00000001

    Register 3
    00000011 Read
    11111111 255
    Write
    Central Processing Unit (CPU) Memory
    00 add A Computer!
    01 subtract
    10 multiply Memory Location
    11 divide Binary Base 10

    00110010 00000000 0
    8 bit
    00000010 00011010 00000001 1
    Program Counter address
    10001100 00000010 2

    Instruction Register 10001100 00000011 3


    1
    00000100 4
    Register 0 00000010
    8 bit 8 bit data
    Register 1 00000010 data in out

    Register 2 00000001

    Register 3
    00000011 Read
    11111111 255
    Write
    Central Processing Unit (CPU) Memory
    The von Neumann “Architecture”
    John von Neumann

    Ripple-carry adder
    Lots of latches!
    Multiplier,
    Registers, etc.

    CPU
    central processing unit
    RAM
    random access memory

    Progra 00110010
    m
    Counte 00011010
    rInstruction
    Register
    10001100

    r0
    Large but
    r1
    A few fast slow memory
    registers
    r2
    …
    r15
    2006
    Intel Core 2 Duo
    3 GHz clock
    64-bit processor
    291 million transistors
    65 nm wires

    It doesn’t
    look all that
    fast to me!
    A Short Aside…
    CPU Main Memory Disk Drive
    (RAM)

    16 Registers (“Bytes”) 109 “Bytes” of 1012 “Bytes” of


    memory memory

    1 cycle 200 cycles ? cycles


    Actual <10-9 sec <10-7 sec <10-2 sec
    time:
    If “cycle”
    1 sec
    = 1 sec

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