library ieee;

use ieee.std_logic_1164.all;

entity dec7 is
port (
b: in std_logic_vector (3 downto 0);
f: out std_logic_vector (6 downto 0));
end dec7;

architecture structural of dec7 is

begin
f <= "0111111" when b = "0000" else --0
"0000110" when b = "0001" else --1
"1011011" when b = "0010" else --2
"1001111" when b = "0011" else --3
"1100110" when b = "0100" else --4
"1101101" when b = "0101" else --5
"1111100" when b = "0110" else --6
"0000111" when b = "0111" else --7
"1111111" when b = "1000" else --8
"1100111" when b = "1001" else --9
"0000000";
end structural;