TUGAS 8

Dibuat untuk memenuhi tugas Mata Kuliah Desain Sistem Digital yang diampu oleh :
Dr. Tuti Suartini, M.Pd.
Muhammad Adli Rizqulloh, S.Pd., M.T

Disusun oleh :

Ikhsan Viantoro 2000064

TEKNIK ELEKTRO
DEPARTEMEN PENDIDIKAN TEKNIK ELEKTRO
FAKULTAS PENDIDIKAN TEKNOLOGI DAN KEJURUAN
UNIVERSITAS PENDIDIKAN INDONESIA
BANDUNG
2022
Tugas
Implementasikan konfigurasi hasil optimasi fungsi logika dari buku reference dari contoh
problem 8.19 untuk kel 1, problem 8.20 kelompok 2 dst, sampai kelompok 7, untuk kelompok
8 laporan terjemahan dan PPT di upload di GCR. Masing- masing individu mengupload hasil
pekerjaannya sesuai kelompoknya.

Penyelesaian
Problem: Find the minimum-cost implementation for the function

𝑓𝑓(𝑥𝑥1 , … , 𝑥𝑥4 = ���

𝑥𝑥1 ���
𝑥𝑥3 ���
𝑥𝑥4 + 𝑥𝑥3 𝑥𝑥4 + ���
𝑥𝑥1 𝑥𝑥
���2 𝑥𝑥4 + 𝑥𝑥1 𝑥𝑥2 ���
𝑥𝑥3 𝑥𝑥4

assuming that there are also don’t-cares defined as 𝐷𝐷 = ∑(9, 12, 14)
Solution: This is the same function used in Examples 8.23 and 8.24. In those examples, we
found that the minimum-cost SOP implementation is
𝑓𝑓 = 𝑥𝑥3 𝑥𝑥4 + 𝑥𝑥
���1 ���
𝑥𝑥3 ���
𝑥𝑥4 + ���
𝑥𝑥2 𝑥𝑥4 + 𝑥𝑥1 𝑥𝑥4

which requires four AND gates, one OR gate, and 13 inputs to the gates, for a total cost of 18.
The minimum-cost POS implementation is

���3 + 𝑥𝑥4 )( ���

𝑓𝑓 = (𝑥𝑥 𝑥𝑥1 + 𝑥𝑥4 )( 𝑥𝑥1 + ���
𝑥𝑥2 + 𝑥𝑥3 + ���)
𝑥𝑥4
which requires three OR gates, one AND gate, and 11 inputs to the gates, for a total cost of 15.
We can also consider a multilevel realization for the function. Applying the factoring
concept to the above SOP expression yields
𝑓𝑓 = (𝑥𝑥1 + ���
𝑥𝑥2 + 𝑥𝑥3 )𝑥𝑥4 + 𝑥𝑥
���1 ���
𝑥𝑥3 𝑥𝑥
���4

This implementation requires twoAND gates, two OR gates, and 10 inputs to the gates, for a
total cost of 14. Compared to the SOP and POS implementations, this has the lowest cost in
terms of gates and inputs, but it results in a slower circuit because there are three levels of gates
through which the signals must propagate.
Solution tersebut disimulasikan kedalam software Xilinx ISE yang hasilnya ditampilkan
sebagai berikut:
a. This is the same function used in Examples 8.23 and 8.24. In those examples, we found that
the minimum-cost SOP implementation is
𝑓𝑓 = 𝑥𝑥3 𝑥𝑥4 + 𝑥𝑥
���1 ���
𝑥𝑥3 ���
𝑥𝑥4 + ���
𝑥𝑥2 𝑥𝑥4 + 𝑥𝑥1 𝑥𝑥4

• Kode Verilog
module SOP_Verilog(
input X1,
input X2,
input X3,
input X4,
output Y
);

assign Y = (X3 & X4) + ~(X1 & X3 & X4) + (~X2 & X4) + (X1 & X4);

endmodule

• Kode VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SOP_VHDL is
port(
X1 : in std_logic;
X2 : in std_logic;
X3 : in std_logic;
X4 : in std_logic;
Y : out std_logic);

end SOP_VHDL;

architecture Behavioral of SOP_VHDL is

signal a: std_logic;
signal b: std_logic;
signal c: std_logic;
signal d: std_logic;
signal e: std_logic;
signal f: std_logic;
signal g: std_logic;
signal h: std_logic;
signal i: std_logic;
signal j: std_logic;
signal k: std_logic;

begin
a <= not(X1);
b <= not(X2);
c <= not(X3);
d <= not(X4);
e <= X3 and X4; --operasi pertama
f <= a and c;
g <= f and d; -- operasi kedua
h <= b and X4; -- operasi ketiga
i <= X1 and X4; -- operasi keempat
j <= e or g; -- OR antara pertama dan kedua
k <= h or i; -- OR antara ketiga dan keempat
Y <= j or k;

end Behavioral;
 • Skematik

b. Which requires four AND gates, one OR gate, and 13 inputs to the gates, for a total cost of
18.
The minimum-cost POS implementation is

𝑓𝑓 = (𝑥𝑥
���3 + 𝑥𝑥4 )( ���
𝑥𝑥1 + 𝑥𝑥4 )( 𝑥𝑥1 + ���
𝑥𝑥2 + 𝑥𝑥3 + ���)
𝑥𝑥4

• Kode Verilog
module POS_Verilog(
input X1,
input X2,
input X3,
input X4,
output Y
);

assign Y = (~X3 + X4) & (~X1 + X4) & (X1 + ~X2 + X3 + ~X4);

endmodule
• Kode VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity POS_VHDL is
port(
X1 : in std_logic;
X2 : in std_logic;
X3 : in std_logic;
X4 : in std_logic;
Y : out std_logic);

end POS_VHDL;

architecture Behavioral of POS_VHDL is

signal a: std_logic;
signal b: std_logic;
signal c: std_logic;
signal d: std_logic;
signal e: std_logic;
signal f: std_logic;
signal g: std_logic;
signal h: std_logic;
signal i: std_logic;
signal j: std_logic;

begin
a <= not(X1);
b <= not(X2);
c <= not(X3);
d <= not(X4);
e <= c or X4; -- kurung pertama
f <= a or X4; -- kurung kedua
g <= X1 or b;
h <= X3 or d;
i <= g or h; -- kurung ketiga
j <= e and f; -- AND pertama dan kedua
Y <= i and j;

end Behavioral;

• Skematik
c. We can also consider a multilevel realization for the function. Applying the factoring
concept to the above SOP expression yields
𝑓𝑓 = (𝑥𝑥1 + ���
𝑥𝑥2 + 𝑥𝑥3 )𝑥𝑥4 + 𝑥𝑥
���1 ���
𝑥𝑥3 𝑥𝑥
���4
• Kode Verilog
module SOP_Verilog2(
input X1,
input X2,
input X3,
input X4,
output Y
);

assign Y = (X1 | ~X2 | X3) & X4 | ~(X1 & X3 & X4);

endmodule

• Kode VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SOP_VHDL2 is
port(
X1 : in std_logic;
X2 : in std_logic;
X3 : in std_logic;
X4 : in std_logic;
Y : out std_logic);

end SOP_VHDL2;

architecture Behavioral of SOP_VHDL2 is

signal a: std_logic;
signal b: std_logic;
signal c: std_logic;
signal d: std_logic;
signal e: std_logic;
signal f: std_logic;
signal g: std_logic;
signal h: std_logic;
signal i: std_logic;

begin
a <= not(X1);
b <= not
c <= not(X3);
d <= not(X4); (X2);
e <= X1 or b;
f <= e or X3; -- yang didalam kurung
g <= f and X4; --ini buat operasi pertama
h <= a and c;
i <= h and d; --ini buat operasi kedua
Y <= g or i;

end Behavioral;
• Skematik