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  • DLD Assimgment No 2

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    lucky tube
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    This document outlines four tasks to implement a NOR gate using different logic gates. Task 1 uses a NOT gate, Task 2 uses an OR gate, Task 3 uses an AND gate, and Task 4 uses a NAND gate. Each task follows the same steps: writing the IC numbers, drawing the pin configuration, performing binary testing, drawing the logic diagram, and setting the jumpers.

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    basic electronics

    Original Title

    DLD ASSIMGMENT NO 2 ,

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    This document outlines four tasks to implement a NOR gate using different logic gates. Task 1 uses a NOT gate, Task 2 uses an OR gate, Task 3 uses an AND gate, and Task 4 uses a NAND gate. Each task follows the same steps: writing the IC numbers, drawing the pin configuration, performing binary testing, drawing the logic diagram, and setting the jumpers.

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    © All Rights Reserved
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    16 views23 pages

    DLD Assimgment No 2

    Uploaded by

    lucky tube
    This document outlines four tasks to implement a NOR gate using different logic gates. Task 1 uses a NOT gate, Task 2 uses an OR gate, Task 3 uses an AND gate, and Task 4 uses a NAND gate. Each task follows the same steps: writing the IC numbers, drawing the pin configuration, performing binary testing, drawing the logic diagram, and setting the jumpers.

    Copyright:

    © All Rights Reserved
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    of 23

    DLD ASSIMGMENT NO:2

    NAME: Ifra Iftikhar


    SECTION: B5
    R0LL NO: L1S22BSCS0011

    TASK 1 : NOR GATE IMPLENATION


    WITH NOT GATE
    STEP 1: WRITE IC NMBERS:
    0V

    STEP 2: WRITE IC NMBERS WITH


    PIN CONFIGRATION.
    0V
    STEP 3: BINARY TESTIG.

    0V

    STEP 4: LOGIC DIAGRAM


    0V
    STEP 5 : JUMPER SETTING
    FOR NOT GATE:
    0V 0V
    0V 0V

    TASK 2: NOR GATE


    IMPLENTENTATION WITH OR GATE.
    STEP 1 : WRITE IC NUMBER.
    0V

    0V

    STEP 2 : WRITE IC WITH PIN


    CONFIGURATION

    0V

    0V
    STEP 3: BINARY TESTING
    0V

    0V

    STEP 4: LOGIC DIAGRAM


    0V

    0V
    STEP 5: JUMPER SETTING

    FOR OR GATE:
    0V

    0V

    0V

    0V
    0V

    0V

    0V

    0V

    TASK 3: NOR GATE IMPLENTATION


    WITH AND GATE.

    STEP 1: WRITE IC NUMBERS.


    0V

    0V
    STEP 2: WRITE IC WITH PIN
    CONFIGGRATION.

    0V

    0V

    STEP 3: BINARY TESTING.


    0V

    0V

    STEP 4: LOGIC DIAGRAM


    0V

    0V

    STEP 5: JUMPER SETTING


    0V

    0V

    FOR AND GATE


    0V

    0V

    0V

    0V

    0V

    0V

    0V

    0V
    TASK 4: NOR GATE IMPLENTATION
    WITH NAND GATE.
    Step 1: WRITE IC NUMBERS

    0V

    0V
    STEP 2: IC WITH PIN CONFIGURAION

    0V

    0V
    STEP 3: BINARY TESTING

    0V

    0V

    STEP 4 :LOGIC DIAGRAM:


    0V

    0V

    STEP 5: JUMPER SETTING.


    FOR NAND GATES:
    0V 0V

    0V 0V
    0V
    0V

    0V 0V

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