Neutral-Point-Less (NPL) Multilevel Inverter

2022 IEEE/AIAA Transportation Electrification Conference and Electric Aircraft Technologies Symposium (ITEC+EATS) | 978-1-6654-0560-7/22/$31.00 ©2022 IEEE | DOI: 10.1109/ITEC53557.2022.9813762

Topology with Single DC-link Capacitor: H-type

Inverter
Mikayla Benson*, Xiaofeng Dong†, Musab Guven*, Kangbeen Lee*, Jinyeong Moon†, and Woongkul Lee*
*Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI, USA
†
Department of Electrical and Computer Engineering, Flordia State University, Tallahassee, Florida, USA
†
j.moon@fsu.edu, *leewoong@msu.edu

Abstract- High-voltage and high-power multilevel inverters

(MLIs) have gained attention as the transportation
electrification trend is rapidly expanding towards high-capacity
mass transit systems such as electric aircraft, trains, and ships.
Conventional MLIs such as neutral point clamped (NPC) and T-
type inverters provide high-voltage and high-power operation
capabilities but require stacked dc-link capacitors with neutral
point connection for zero voltage vector. This neutral point
connection to the stacked dc-link capacitor generates a neutral
current oscillating at three times the fundamental frequency,
causing capacitor voltage imbalance and overvoltage stress on
capacitors and switching devices. This paper proposes a neutral-
point-less (NPL) MLI topology with a small and single dc-link
capacitor, the H-type inverter, and its operating principle is
introduced. The performance of the H-type inverter is
investigated through simulation and compared to the
conventional three-level T-type inverter. The simulation results
show that the H-type inverter has 75% reduced dc-link
capacitor current and voltage ripple, as well as less current
waveform distortion, which will lead to smoother power output
and a higher volumetric power density by substantially reducing
the required capacitor size. Simulation of the inverter shows
that it operates with an efficiency of 99.23% while operating
with a switching frequency of 10 kHz. The prototype of the H-
type inverter operates as proposed at low power.
Keywords—DC-link capacitor, H-type Inverter, multilevel
inverters, neutral-point-less, ripple voltage.
I. INTRODUCTION
Multilevel inverters (MLIs) are well-suited for high-power
and high-voltage applications as they reduce harmonics,
electromagnetic interference (EMI) noise, and switching and
electric machine iron losses compared to conventional two-
level inverters. Recently, MLIs for high-power electric
propulsion systems in heavy-duty electric vehicles (EVs) and
aircraft (i.e., hundreds of kilowatts to multi-megawatt) have
gained attention as the electrical system voltage level is
continuously increasing over 400 V to reduce conduction loss
and mass/volume of the inverter. Higher dc-link voltages up
to 1.5 kV are being considered for high-power electric
propulsion systems (e.g., heavy-duty trucks, off-road
vehicles, urban air mobility, and electric aircraft) and
extremely fast charging applications [1]-[5].
The conventional MLIs require the middle point (M)
connection to the stacked dc-link capacitors, as shown in Fig.
1 [6]. This stacked dc-link capacitor generates a neutral
Fig. 1. Example structure of high-power and high-voltage electric
propulsion system in electric aircraft with conventional three-level
T-type inverter.
current at three times the fundamental frequency along this
middle point, leading to undesirable capacitor voltage
fluctuation and requiring additional complexities to balance
this voltage [7]-[9]. This neutral current continuously drifts
the capacitor voltage to unacceptable levels, causing
overvoltage damage to switching devices, output voltage and
current distortion, and high voltage stress on capacitors [10]-
[11]. Dynamic operating conditions of electrified
transportation systems can worsen the neutral potential
fluctuation and drift phenomenon. Therefore, oversizing the
dc-link capacitor is inevitable to maintain the voltage stable,
which contributes to most of the size and weight of the
overall inverter unit [12]. Additionally, a meticulously
designed busbar must be employed to reduce parasitic
inductances in the major and minor power loops in the
traditional MLIs due to this undesirable neutral point
connection [13]. As a result, despite their attractive benefits,
the commercial use of MLIs today is restricted to high-power
grid applications (e.g., photovoltaic, wind turbine, or high-
voltage DC transmission) with fixed fundamental frequency
either at 50 or 60 Hz.
This paper proposes a novel neutral-point-less (NPL) MLI
topology with a small and single dc-link capacitor, the H-type
inverter, and its operating principle is introduced. The
performance of the H-type inverter is investigated through
simulation and compared to the conventional three-level T-
type inverter. The simulation results show that the H-type
inverter has 75% reduced dc-link capacitor ripple current and
voltage, as well as less current waveform distortion, which
will lead to smoother power output and a higher volumetric
power density by substantially reducing the required
capacitor size.

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 TABLE I. FOUR SWITCHING STATES OF PROPOSED H-TYPE INVERTER.
State Vout_1 Vout_2 S1 S2 S3 S4 S5 S6
PN +VDC/2 –VDC/2 on off off on off off
ZZ (+iph) 0 0 off off off off on off
ZZ (–iph) 0 0 off off off off off on
NP –VDC/2 +VDC/2 off on on off off off

(a) (b) A. Switch Configuration

(c)
Fig. 2. Single phase-leg of the proposed H-type inverter in (a) H-
type layout and (b) condensed layout. (c) The basic structure of
high-power and high-voltage electric propulsion system in electric
aircraft with proposed three-level H-type inverter.
This paper is organized as follows: Section II introduces
the new NPL MLI topology, called the H-type inverter, and
the operating principle of the inverter. Section III shows the
simulation results of the proposed H-type inverter. Section IV
shows the experimental results of the prototype of the H-type
inverter. The conclusion is drawn in section V.
II. PROPOSED H-TYPE INVERTER TOPOLOGY
A single phase-leg out of three from the proposed H-type
inverter is illustrated in two different structures with identical
electrical connections and functionalities, as shown in Fig.
2(a) and (b). The name of the new NPL MLI inverter, H-type,
comes from its H shape highlighted in yellow, which shows
two phase-legs interconnected to each other through a
bidirectional switch (e.g., common-drain MOSFETs,
common-source MOSFETs, and RB-IGBTs). From Fig. 2(b),
it can be found that the H-type inverter has the same number
of active switches as the conventional active neutral point
clamped (ANPC) three-level inverter but has a single, not
stacked, dc-link capacitor for multilevel operation.
It is also important to mention that the one phase-leg of the
H-type inverter has two equal and opposite three-level output
voltage levels, providing a balanced six-phase output as
illustrated in Fig. 2(c). The H-type inverter is suitable for
various high-power and high-voltage variable-frequency
drive (VFD) applications due to the three-level output voltage
without any neutral current, which depends on the operating
frequency. The other benefits of the H-type inverter are an
increased efficiency with low switching frequency, low
harmonics from multilevel operation, and more than 75%
reduction in dc-link capacitor volume, leading to a higher
power density for the entire unit.
The proposed H-type inverter requires six active switching
devices, which can be implemented with two SiC half-bridge
(HB) modules and one bidirectional (BD) SiC or IGBT
module (Fig. 2). A common-drain BD switch configuration is
selected in the H-type inverter to reduce the required number
of isolated power supplies. The sources of the BD module
will be attached to the center point of each HB module. This
configuration allows the two equal and opposite phase
currents to alternate their flow path between the HB modules
during the zero vector, which was used to eliminate the
middle point connection to the center of the dc-link
capacitors. This configuration requires six isolated gate driver
circuits for each switch and three isolated power supplies.
Since one H-type inverter module with six active switches
generates two equal and opposite output voltage channels (see
Fig. 3), this topology only requires three active switches for
each three-level output voltage, which is the absolute
minimum number of switches needed to achieve multilevel
operation known to date. While the H-type inverter has
eighteen active switches, the total KVA rating of switches,
which is directly proportional to the cost of the total devices,
is 17% lower than that of the conventional T-type and ANPC
MLIs for the same power rating. Furthermore, there is a
greater cost reduction opportunity with the newly proposed
H-type inverter considering the dc-link capacitor size
reduction by over 75%.
B. Switching States and Commutation
In this section, the switching states and commutation of the
H-type inverter are investigated in detail to show the three-
level output voltage generation with a single dc-link
capacitor. The H-type inverter produces four switching states,
labeled as positive and negative (PN), zero and zero (ZZ), and
negative and positive (NP). Each state has two output
voltages associated with the level, as shown in Table I, which
also includes the state of the switches to achieve each level.
For PN and NP, the voltage level at each output equals half
the dc-link voltage, VDC/2, with Vout_1 being positive and Vout_2
being negative for PN and the opposite polarity for NP. These
states and the current paths are illustrated during operation
with Phase A1 and A2 in Fig. 4. The PN and NP states only
require two switches in the on-state to achieve each voltage
level, while the ZZ state only requires one. PN (Fig. 3(a)) is
achieved with S1 and S4 in the on-state, NP (Fig. 3(b))
requires S2 and S3, and the two ZZ states require either S5
(Fig. 3(c)), with a positive phase current or S6 (Fig. 3(d)),
with a negative current.

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 (a) (b)

(c) (d)
Fig. 3. Four switching states of H-type inverter for three-level
operation. (a) PN; (b) NP; (c) ZZ (+iph); (d) ZZ (–iph).

Fig. 4. Phase A1 and A2 output voltages of the H-type inverter

with the four different switching states.

(a) (b)
Fig. 6. Comprehensive performance comparison of the MLIs. (a)
conventional three-level T-type inverter with 800 μF stacked dc-link
capacitors (left); (b) proposed three-level H-type with 200 μF single
dc-link capacitor (right).

PWM signals per phase, totaling twelve channels for a three-

phase system.

III. H-TYPE INVERTER SIMULATION RESULTS

A. Preliminary Simulation and Performance Comparison

Fig. 5. Multicarrier sine PWM for the proposed H-type inverter.
C. Modulation Techniques for H-type Inverter
The H-type inverter can operate with a simple
multicarrier sine-PWM (SPWM) technique. Since S1/S4 and
S2/S3 have the same and synchronized PWM signals and S5/S6
are the complementary signals of the previous sets, a
conventional three-phase multicarrier SPWM is employed as
shown in Fig. 5. The H-type inverter requires four channels of
with Conventional MLI Topology
The H-type inverter was modeled in MATLAB Simulink to
validate the multilevel operation capability with a single and
extremely small dc-link capacitor compared to the
conventional three-level MLI, as shown in Fig. 6. One of the
conventional three-level MLI, the T-type inverter, exhibits a
dc-link voltage oscillation at three times the fundamental
frequency (375 Hz) due to the neutral current, as shown in the
top right waveform. This leads to severe phase current and
output voltage distortion. With a 75% smaller dc-link
capacitor size, the proposed H-type inverter does not produce
any neutral current but only switching ripples in the dc-link
capacitor, ensuring balanced and low harmonic three-level
operation.

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 Fig. 7. DC-link capacitor voltage ripple of the H-type and T-type
inverter vs. capacitance for two different loads (shown in Table
2).
Fig. 8. DC-link capacitor current of the H-type and T-type
inverter vs. capacitance for two different loads (shown in Table
2).
TABLE 2. SELECTED THREE DIFFERENT RL LOAD PARAMETERS
FOR H-TYPE INVERTER SIMULATION.
Load Number Resistance Inductance
1 1.146 Ω 280 μH
2 0.573 Ω 140 μH
B. DC-link Voltage and Ripple Estimation
The simulation was also run at 900 V with various RL
loads and dc-link capacitor values to investigate the
performance of the inverter to varying dc-link capacitance
and load levels. The simulation was executed at two different
RL loads, summarized in Table 2. In Fig. 7, the voltage ripple
of the dc-link is compared for both topologies with varying
capacitance. The H-type inverter ripple is 75% smaller than
the T-type inverter for all data points at three different load
conditions, showing that the H-type inverter can operate with
a singular, small capacitor. The dc-link current for the two
inverter topologies for the same load points and capacitor
values are also compared, as plotted in Fig. 8. The simulation
results show that the H-type inverter has up to 65% lower dc-
link RMS current than the T-type for the same loading
condition. The lower capacitor RMS current will reduce the
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Fig. 9. DC-link capacitor voltage ripple at varying modulation index
and switching frequencies for the H-type inverter.
Fig. 10. DC-link capacitor current at varying modulation index and
switching frequencies for the H-type inverter.
voltage stress on both switching devices and capacitors,
leading to higher reliability.
C. Switching Frequency and Modulation Index
The MATLAB Simulink model was also used to
investigate the performance of the proposed H-type inverter
with different switching frequencies and modulation indices.
The simulation was run with Load 1 (Table 2), a 200 μF dc-
link capacitor with modulation index values from 0.3 to 1,
and switching frequencies from 10 kHz to 50 kHz. The
estimated dc-link voltage ripples are plotted in Fig. 9, which
shows the dc-link ripple voltage linearly increasing with the
modulation index. This is due to the fact that the dc-link RMS
ripple current proportionally increases with the modulation
index. However, the voltage ripple only varies by
approximately 1 V as the switching frequency increases for
the same modulation index. The dc-link RMS current is
shown in Fig. 10 and increases as both the modulation and
switching frequency increase. Therefore, it is more
advantageous to use a higher switching frequency with the H-
type inverter, as increased switching frequency can reduce the
size of passive components, such as capacitors and inductors,
 TABLE 3. SELECTED DEVICE CHARACTERISTICS OF THE H-TYPE TABLE 4. DEVICE CHARACTERISTICS OF THE PROTOTYPE H-TYPE
INVERTER IN PSIM SIMULATION. INVERTER SWITCHES.
Parameter Value Parameter Value
Device Part Number ROHM-BMS400D12P3G002 Part Number UF3SC120040B7S
Material SiC Material SiC
Breakdown Voltage, VDS 1.2 kV Transistor Polarity N-channel
Current Rating, IDS 400 A Breakdown Voltage, VDS 1.2 kV
On Resistance, RON 6.5 mΩ Continuous Drain Current, ID 47 A
Operating Temperature -40 - 175 ˚C
TABLE 5. EXPERIMENT PARAMETERS OF THE H-TYPE INVERTER.
Parameter Value
Max. Output Power, Sn 25 kW
Switching Frequency, fsw 10 - 50 kHz
Max. DC-Link Voltage, Vdc 900 V
DC-Line Capacitance, Cdc 200 µF
Load Resistance, RL 40 Ω
Load Inductance, LL 17 mH

Fig. 11. Efficiency at full load and half load for 10 kHz and 50
kHz switching frequency of the proposed H-type inverter.

leading to a smaller and lighter unit, which will increase the

overall power density.
D. Efficiency Simulation
A PSIM simulation model of the H-type inverter at rated
voltage (900 V) is designed to evaluate the efficiency and
power losses of the proposed MLI topology. To accurately
estimate the power losses, a SiC device thermal model was
used with a 1.2 kV voltage rating, and the detailed device
characteristics are summarized in Table 3. The load
conditions were 280 μH and 1.146 Ω for the full load
condition of 400 kW and 140 μH and 0.573 Ω for the half
load of 200 kW. Using SPWM modulation, the switching
frequency was set to 10 kHz and 50 kHz, with the modulation
index set to 1. The estimated efficiencies of the H-type
inverter are 99.23 % at full load and 99.52% at half load for
the 10 kHz case, while the 50 kHz switching frequency
performs at 98.41% and 98.76%, respectively, as shown in
Fig. 11. The decrease in the efficiency of the inverter with the
50 kHz frequency comes from the five times increased
number of switching events.
Fig. 12. H-type inverter prototype setup with a motherboard to
IV. PROTOTYPING AND EXPERIMENTAL RESULTS house the DSP, three inverter leg daughtercards, and an
interchangeable dc-link daughtercard (top), connected to a six-
phase RL load (bottom).
The prototype version of the 1.2 kV SiC-based H-type
inverter was designed, assembled, and connected to an RL capacitance values to validate the multilevel operation with a
load, as shown in Fig. 12. Six single SiC MOSFET switches small dc-link capacitor. The PCB unit is screwed to a steel
were used, and the device characteristics are shown in Table box with fans for cooling and terminal blocks for the low
4. The printed circuit board (PCB) setup includes a voltage DC input, high voltage DC input, and phase outputs.
motherboard, which houses the DSP and auxiliary power, and The phase outputs are fed to a six-phase RL load.
daughtercards for the inverter legs and dc-link capacitor. The H-type inverter was tested at a low power test point,
Each inverter leg daughtercard houses the six SiC MOSFETs and the testing conditions used in this paper are shown in
and six isolated gate driver circuits. Multiple dc-link Table 5. The results in Fig. 13 show the voltage and current
daughtercards were created to quickly switch between dc-link outputs of one three-phase set, and the other three-phase set is

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Fig. 13. Three-phase multilevel output of the H-type inverter at 100
V dc-link voltage.
Fig. 14. Phase current, phase voltage and DC-link voltage of the H-
type inverter at 100 V dc-link voltage.
equal and opposite to the three-phase set shown. The
multilevel operation can be seen with the five distinct voltage
levels per phase and minimal distortion. Fig. 14 shows the
phase A output voltage and current and the DC-link voltage.
It can be seen that the phase current has a pure sinusoidal
shape with noise, indicating that the H-type inverter operates
with minimal phase current distortion. The noise in this
waveform is apparent due to the low current magnitude being
measured. The DC-link voltage remains constant for this test
due to the high RL load, and low operating point, which is to
be expected as the voltage ripple at 900 V and a much smaller
load was only 20 V.
V. CONCLUSIONS
In this paper, a novel neutral-point-less (NPL) MLI called
the H-type inverter is proposed, which eliminates the middle
point connection allowing for a 75% decrease in capacitor
size, over 50% reduction in voltage ripple, and less phase
current distortion as compared with a traditional T-type
inverter in simulation. The small, single capacitor leads to a
higher power density with the decrease in weight from
smaller capacitors. The H-type inverter operates with
traditional modulation methods, such as SPWM, and does not
require complex modulation methods in order to balance the
dc-link voltages, as seen in traditional MLIs. The inverter
operates with an efficiency of 99.23% at 10 kHz and 98.41%
at 50 kHz under full load conditions. The proposed H-type
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inverter prototype was built and run at a low power test point
and verified that the topology operates with minimal phase
voltage and current distortion with a single, extremely small
dc-link capacitor.
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