Datasheet

MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION ●2 clock generating circuits

The 3822 group is the 8-bit microcomputer based on the 740 fam- (connect to external ceramic resonator or quartz-crystal oscillator)
ily core technology. ●Power source voltage
The 3822 group has the LCD drive control circuit, an 8-channel In high-speed mode .................................................. 4.0 to 5.5 V
A-D converter, and a serial I/O as additional functions. In middle-speed mode ............................................... 2.5 to 5.5 V
The various microcomputers in the 3822 group include variations (Extended operating temperature version:
of internal memory size and packaging. For details, refer to the 2.0 to 5.5 V, Ta= – 20 to 85°C
section on part numbering. 3.0 to 5.5 V, Ta= – 40 to – 20°C)
For details on availability of microcomputers in the 3822 group, re- (One time PROM version: 2.5 to 5.5 V)
fer to the section on group expansion. (M version: 2.2 to 5.5 V)
(H version: 2.0 to 5.5 V)
FEATURES In low-speed mode .................................................... 2.5 to 5.5 V
●Basic machine-language instructions ...................................... 71 (Extended operating temperature version:
●The minimum instruction execution time ........................... 0.5 µs 2.0 to 5.5 V, Ta= – 20 to 85°C
(at 8 MHz oscillation frequency) 3.0 to 5.5 V, Ta= – 40 to – 20°C)
●Memory size (One time PROM version: 2.5 to 5.5 V)
ROM ................................................................. 4 K to 48 K bytes (M version: 2.2 to 5.5 V)
RAM ................................................................. 192 to 1024 bytes (H version: 2.0 to 5.5 V)
●Programmable input/output ports ............................................ 49 ●Power dissipation
●Software pull-up/pull-down resistors (Ports P0-P7 except port P40 ) In high-speed mode .......................................................... 32 mW
●Interrupts ................................................. 17 sources, 16 vectors (at 8 MHz oscillation frequency, at 5 V power source voltage)
(includes key input interrupt) In low-speed mode ............................................................ 45 µW
●Timers ........................................................... 8-bit ✕ 3, 16-bit ✕ 2 (at 32 kHz oscillation frequency, at 3 V power source voltage)
●Serial I/O ...................... 8-bit ✕ 1 (UART or Clock-synchronized) ●Operating temperature range................................... – 20 to 85°C
●A-D converter ................................................. 8-bit ✕ 8 channels (Extended operating temperature version: – 40 to 85 °C)
●LCD drive control circuit
Bias ................................................................................... 1/2, 1/3 APPLICATIONS
Duty ........................................................................... 1/2, 1/3, 1/4 Camera, household appliances, consumer electronics, etc.
Common output .......................................................................... 4
Segment output ........................................................................ 32
PIN CONFIGURATION (TOP VIEW)

P34/SEG12
P35/SEG13
P36/SEG14
P37/SEG15
P00/SEG16
P01/SEG17
P02/SEG18
P03/SEG19
P04/SEG20
P05/SEG21
P06/SEG22
P07/SEG23
P10/SEG24
P11/SEG25
P12/SEG26
P13/SEG27
P14/SEG28
P15/SEG29
P16/SEG30
P17/SEG31
SEG10
SEG11
SEG8
SEG9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG7 65 40 P20
SEG6 66 39 P21
SEG5 67 38 P22
SEG4 68 37 P23
SEG3 69 36 P24
SEG2 70 35 P25
SEG1 71 34 P26
SEG0 72 33 P27
VCC 73 M38224M6HXXXFP 32 VSS
VREF 74 31 XOUT
AVSS 75 30 XIN
COM3 76 29
P70/XCOUT
COM2 77 28 P71/XCIN
COM1 78 27 RESET
COM0 79 26 P40
VL3 80 25 P41/φ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
P57/ADT
P51/INT3
P50/INT2
P44/RXD
P43/INT1
P42/INT0
VL2
VL1
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P56/TOUT
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P47/SRDY
P46/SCLK
P45/TXD
Package type : 80P6N-A (80-pin plastic-molded QFP)

Fig. 1 M38224M6HXXXFP pin configuration
(The pin configuration of 80D0 is same as this.)
3822 Group
PIN CONFIGURATION (TOP VIEW)
P34/SEG12
P35/SEG13
P36/SEG14
P37/SEG15
P00/SEG16
P01/SEG17
P02/SEG18
P03/SEG19
P04/SEG20
P05/SEG21
P06/SEG22
P07/SEG23
P10/SEG24
P11/SEG25
P12/SEG26
P13/SEG27
P14/SEG28
P15/SEG29
SEG10
SEG11
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG9 61 40 P16/SEG30
SEG8 62 39 P17/SEG31
SEG7 63 38 P20
SEG6 64 37 P21
SEG5 65 36 P22
SEG4 66 35 P23
SEG3 67 34 P24
SEG2 68 33 P25
SEG1
SEG0
69
70
M38223M4MXXXGP 32
31
P26
P27
VCC
VREF
71
72
M38224M6HXXXHP 30
29
VSS
XOUT
AVSS 73 28 XIN
COM3 74 27 P70/XCOUT
COM2 75 26 P71/XCIN
COM1 76 25 RESET
COM0 77 24 P40
VL3 78 23 P41/φ
VL2 79 22 P42/INT0
VL1 80 21 P43/INT1
20
10
11
12
13
14
15
16
17
18
19
4
1
2
3
5
6
7
8
9
P55/CNTR1
P61/AN1
P53/RTP1
P51/INT3
P50/INT2
P44/RXD
P45/TXD
P63/AN3
P62/AN2
P56/TOUT
P54/CNTR0
P57/ADT
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P60/AN0
P52/RTP0
P47/SRDY
P46/SCLK
Package type : 80P6S-A/80P6Q-A

(80-pin plastic-molded QFP)
Fig. 2 M38223M4MXXXGP/M38224M6HXXXHP pin configuration
2
FUNCTIONAL BLOCK DIAGRAM (Package type : 80P6Q-A)
Main Clock Main Clock Reset Input (5V) (0V)

Input XIN Output XOUT RESET VCC VSS
28 29 25 71 30
Fig. 3 Functional block diagram

Data bus
Clock generating C P U 80
circuit VL 1
A ROM RAM 79 VL 2
78 VL 3
X
LCD display 77
LCD COM0
XCIN XCOUT φ Y RAM 76
drive control COM1
Sub-Clock Sub-Clock (16 bytes) 75
circuit COM2
Input Output S 74
COM3
PCH PCL 70 SEG0
Timer X(16)
69 SEG1
PS Timer Y(16) 68 SEG2
Timer 1(8) Timer 2(8) 67 SEG3
66 SEG4
Timer 3(8) 65 SEG5
64 SEG6
63 SEG7
62 SEG8
61 SEG9
60 SEG10
59 SEG11
A-D
converter(8) SI/O(8)
TOUT
CNTR0,CNTR1
Real time port function
XCOUT RTP0,RTP1
XCIN
P5(8) P4(8) P2(8) P1(8) P0(8)
φ
P7(2) P6(8) P3(4)
INT0,INT1
ADT
INT2,INT3
Key on wake up
26 27 1 2 3 4 5 6 7 8 72 73 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 55 56 57 58 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
I/O Port P7 I/O Port P6 VREF I/O Port P5 I/O Port P4 Input Port P3 I/O Port P2 I/O Port P1 I/O Port P0
AVSS
(0V)
3

3822 Group
3822 Group
PIN DESCRIPTION
Table 1 Pin description (1)
Pin Name Function

Function except a port function
VCC, VSS Power source •Apply voltage of power source to VCC , and 0 V to VSS . (For the limits of V CC, refer to “Recom-
mended operating conditions”).
VREF Analog refer- •Reference voltage input pin for A-D converter.
ence voltage
AVSS Analog power •GND input pin for A-D converter.
source •Connect to VSS .
RESET Reset input •Reset input pin for active “L”.
XIN Clock input •Input and output pins for the main clock generating circuit.
•Feedback resistor is built in between XIN pin and X OUT pin.
XOUT Clock output •Connect a ceramic resonator or a quartz-crystal oscillator between the X IN and XOUT pins to set
the oscillation frequency.
•If an external clock is used, connect the clock source to the XIN pin and leave the X OUT pin open.
•This clock is used as the oscillating source of system clock.
VL1 –VL3 LCD power •Input 0 ≤ V L1 ≤ VL2 ≤ VL3 ≤ V CC voltage.
source
•Input 0 – VL3 voltage to LCD.
COM0 –COM3 Common output •LCD common output pins.
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
SEG0 –SEG11 Segment output •LCD segment output pins.
P00/SEG16 – I/O port P0 •8-bit output port. •LCD segment output pins
P07/SEG23 •CMOS compatible input level.
•CMOS 3-state output structure.
P10/SEG24 – I/O port P1 •I/O direction register allows each port to be individually
P17/SEG31 programmed as either input or output.
•Pull-down control is enabled.
P20 – P2 7 I/O port P2 •8-bit I/O port. •Key input (key-on wake-up) interrupt
•CMOS compatible input level. input pins

•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
P3 4/SEG 12 – Input port P3 •4-bit input port. •LCD segment output pins
P3 7/SEG 15 •CMOS compatible input level.
•Pull-down control is enabled.
4
3822 Group
Table 2 Pin description (2)
Pin Name Function

Function except a port function
P40 Input port P4 •1-bit Input port.
•CMOS compatible input level.
P41 /φ I/O port P4 •7-bit I/O port. •φ clock output pin
P42 /INT0 , •CMOS compatible input level. •Interrupt input pins
P43 /INT1 •CMOS 3-state output structure.
P44 /RXD, •Serial I/O function pins
P45 /TXD, programmed as either input or output.
P46 /SCLK,
P47 /SRDY •Pull-up control is enabled.
P50 /INT2 , I/O port P5 •8-bit I/O port. •Interrupt input pins
P51 /INT3 •CMOS compatible input level.
P52 /RTP0 , •CMOS 3-state output structure. •Real time port function pins
P53 /RTP1 •I/O direction register allows each pin to be individually
P54 /CNTR0 , •Timer X, Y function pins
P55 /CNTR1 •Pull-up control is enabled.
P56/T OUT •Timer 2 output pins

P57 /ADT •A-D trigger input pins
P60 /AN0– I/O port P6 •8-bit I/O port. •A-D conversion input pins
P67 /AN7 •CMOS compatible input level.
P70 /XCOUT, I/O port P7 •2-bit I/O port. •Sub-clock generating circuit I/O pins.
P71 /XCIN •CMOS compatible input level. (Connect a resonator. External clock
•CMOS 3-state output structure. cannot be used.)
5
3822 Group
PART NUMBERING
Product M3822 4 M 6 H XXX FP
Package type
FP : 80P6N-A package
GP : 80P6S-A package
HP : 80P6Q-A package
FS : 80D0 package
ROM number
Omitted in One Time PROM version shipped in blank and EPROM version.
Normally, using hyphen.

When electrical characteristic, or division of identification code using
alaphanumeric character
– :Standard
D : Extended operating temperature version
M :M version
H : H version
ROM/PROM size
1 : 4096 bytes 9: 36864 bytes
2 : 8192 bytes A: 40960 bytes
3 : 12288 bytes B: 45056 bytes
4 : 16384 bytes C: 49152 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
The first 128 bites and the last 2 bytes of ROM are
reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
Fig. 4 Part numbering
6
3822 Group
GROUP EXPANSION (STANDARD, ONE TIME Memory Size

PROM VERSION, EPROM VERSION) ROM size ............................................................. 8 K to 48 K bytes
Mitsubishi plans to expand the 3822 group (Standard, One Time RAM size ............................................................ 384 to 1024 bytes
PROM version, EPROM version) as follows:
Package
Memory Type 80P6N-A .................................... 0.8 mm-pitch plastic molded QFP
Support for Mask ROM, One Time PROM, and EPROM versions 80P6S-A .................................. 0.65 mm-pitch plastic molded QFP
80P6Q-A .................................... 0.5 mm-pitch plastic molded QFP
80D0 ....................... 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Expansion Plan

ROM size (bytes)
Under development
48K M38227EC
32K
28K
24K
20K
Mass product
16K M38223M4/E4
12K
Mass product
8K M38222M2
4K
192 256 384 512 640 768 896 1024
RAM size (bytes)
Note: Products under development or planning: the development schedule and specifications
may be revised without notice.
Fig. 5 Memory expansion plan
Currently products are listed below.

Table 3 List of products As of August 2000
ROM size (bytes)
Product RAM size (bytes) Package Remarks
ROM size for User in ( )
M38222M2-XXXFP 80P6N-A Mask ROM version
8192
M38222M2-XXXGP 384 80P6S-A Mask ROM version
(8062)
M38222M2-XXXHP 80P6Q-A Mask ROM version
M38223M4-XXXFP Mask ROM version
80P6N-A
M38223E4FP One Time PROM version (blank)
M38223M4-XXXGP 16384 Mask ROM version
512 80P6S-A
(16254)
M38223E4GP One Time PROM version (blank)
M38223M4-XXXHP Mask ROM version
80P6Q-A
M38223E4HP One Time PROM version (blank)
M38223E4FS 80D0 EPROM version
M38227ECFP 80P6N-A One Time PROM version (blank)
49152
M38227ECHP (49022) 1024 80P6Q-A One Time PROM version (blank)
M38227ECFS 80D0 EPROM version
7
3822 Group
GROUP EXPANSION Package

(EXTENDED OPERATING TEMPERATURE 80P6N-A .................................... 0.8 mm-pitch plastic molded QFP
VERSION)
Mitsubishi plans to expand the 3822 group (extended operating
temperature version) as follows:
Memory Type
Support for Mask ROM version.
Memory Size
ROM size ........................................................................ 48 K bytes
RAM size ....................................................................... 1024 bytes
ROM size (bytes)

Mass product
48K M38227MCD
32K
28K
24K
20K
16K
12K
8K
4K
192 256 384 512 640 768 896 1024
RAM size (bytes)
Fig. 6 Memory expansion plan for extended operating temperature version
Table 4 List of products for extended operating temperature version As of August 2000
ROM size (bytes)
M38227MCDXXXFP 49152(49022) 1024 80P6N-A Mask ROM version
8
3822 Group
GROUP EXPANSION (M VERSION) Package

Mitsubishi plans to expand the 3822 group (M version) as follows: 80P6N-A .................................... 0.8 mm-pitch plastic molded QFP
80P6S-A .................................. 0.65 mm-pitch plastic molded QFP
Memory Type 80P6Q-A .................................... 0.5 mm-pitch plastic molded QFP
Memory Size
ROM size ........................................................... 16 K to 24 K bytes
RAM size .............................................................. 512 to 640 bytes
ROM size (bytes)
48K
32K
28K
Mass product
24K M38224M6M
20K
Mass product
16K M38223M4M
12K
8K
4K
192 256 384 512 640 768 896 1024
RAM size (bytes)
Fig. 7 Memory expansion plan for M version
Table 5 List of products for M version As of August 2000

ROM size (bytes)
M38223M4MXXXFP 80P6N-A Mask ROM version
16384
M38223M4MXXXGP 512 80P6S-A Mask ROM version
(16254)
M38223M4MXXXHP 80P6Q-A Mask ROM version
M38224M6MXXXFP 24576 80P6N-A Mask ROM version
640
M38224M6MXXXHP (24446) 80P6Q-A Mask ROM version
9
3822 Group
GROUP EXPANSION (H VERSION) Package

Mitsubishi plans to expand the 3822 group (H version) as follows: 80P6N-A .................................... 0.8 mm-pitch plastic molded QFP
80P6Q-A .................................... 0.5 mm-pitch plastic molded QFP
Memory Type
Memory Size
ROM size ........................................................... 16 K to 48 K bytes
RAM size ............................................................ 512 to 1024 bytes
ROM size (bytes)

Mass product
48K M38227MCH
Mass product
32K M38227M8H
28K
Mass product
24K M38224M6H
20K
Mass product
16K M38223M4H
12K
8K
4K
192 256 384 512 640 768 896 1024
RAM size (bytes)
Fig. 8 Memory expansion plan for H version
Table 6 List of products for H version As of August 2000

ROM size (bytes) ROM
size for User in ( )
M38223M4HXXXFP 16384 80P6N-A Mask ROM version
512
M38223M4HXXXHP (16254) 80P6Q-A Mask ROM version
640
1024
M38227MCHXXXFP 49152 80P6N-A Mask ROM version
M38227MCHXXXHP (49022) 80P6Q-A Mask ROM version
10
3822 Group
FUNCTIONAL DESCRIPTION [Stack Pointer (S)]

CENTRAL PROCESSING UNIT (CPU) The stack pointer is an 8-bit register used during subroutine calls
The 3822 group uses the standard 740 family instruction set. Re- and interrupts. This register indicates start address of stored area
fer to the table of 740 family addressing modes and machine (stack) for storing registers during subroutine calls and interrupts.
instructions or the 740 Family Software Manual for details on the The low-order 8 bits of the stack address are determined by the
instruction set. contents of the stack pointer. The high-order 8 bits of the stack ad-
Machine-resident 740 family instructions are as follows: dress are determined by the stack page selection bit. If the stack
The FST and SLW instruction cannot be used. page selection bit is “0” , the high-order 8 bits becomes “0016”. If
The STP, WIT, MUL, and DIV instruction can be used. the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
[Accumulator (A)] The operations of pushing register contents onto the stack and
The accumulator is an 8-bit register. Data operations such as data popping them from the stack are shown in Figure 10.
transfer, etc., are executed mainly through the accumulator. Store registers other than those described in Figure 10 with pro-
gram when the user needs them during interrupts or subroutine
[Index Register X (X)] calls.
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of [Program Counter (PC)]
register X and specifies the real address. The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL . It is used to indicate the address of the
[Index Register Y (Y)] next instruction to be executed.
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b7 b0
A Accumulator
b7 b0
X Index register X
b7 b0
Y Index register Y
b7 b0
S Stack pointer
b15 b7 b0
PCH PCL Program counter
b7 b0
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig.9 740 Family CPU register structure
11
3822 Group
On-going Routine
Interrupt request
(Note) M (S) (PCH)
Execute JSR (S) (S) – 1

Push return address
M (S) (PCH) on stack
M (S) (PCL)
(S) (S) – 1
Push return address (S) (S) – 1
on stack Push contents of processor
M (S) (PCL)
M (S) (PS) status register on stack
(S) (S)– 1
(S) (S) – 1
Subroutine Interrupt
Service Routine I Flag is set from “0” to “1”
Execute RTS Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return (S) (S) + 1
address from stack POP contents of
(PCL) M (S) processor status
(PS) M (S) register from stack
(S) (S) + 1
(S) (S) + 1
(PCH) M (S)
(PCL) M (S)
POP return
address
(S) (S) + 1 from stack
(PCH) M (S)
Note: Condition for acceptance of an interrupt Interrupt enable flag is “1”

Interrupt disable flag is “0”
Fig. 10 Register push and pop at interrupt generation and subroutine call
Table 7 Push and pop instructions of accumulator or processor status register

Push instruction to stack Pop instruction from stack
Accumulator PHA PLA
Processor status register PHP PLP
12
3822 Group
[Processor status register (PS)] •Bit 4: Break flag (B)

The processor status register is an 8-bit register consisting of 5 The B flag is used to indicate that the current interrupt was
flags which indicate the status of the processor after an arithmetic generated by the BRK instruction. The BRK flag in the processor
operation and 3 flags which decide MCU operation. Branch opera- status register is always “0”. When the BRK instruction is used to
tions can be performed by testing the Carry (C) flag , Zero (Z) flag, generate an interrupt, the processor status register is pushed
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, onto the stack with the break flag set to “1”.
V, N flags are not valid. •Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
•Bit 0: Carry flag (C) between accumulator and memory. When the T flag is “1”, direct
The C flag contains a carry or borrow generated by the arithmetic arithmetic operations and direct data transfers are enabled
logic unit (ALU) immediately after an arithmetic operation. It can between memory locations.
also be changed by a shift or rotate instruction. •Bit 6: Overflow flag (V)
•Bit 1: Zero flag (Z) The V flag is used during the addition or subtraction of one byte
The Z flag is set if the result of an immediate arithmetic operation of signed data. It is set if the result exceeds +127 to -128. When
or a data transfer is “0”, and cleared if the result is anything other the BIT instruction is executed, bit 6 of the memory location
than “0”. operated on by the BIT instruction is stored in the overflow flag.
•Bit 2: Interrupt disable flag (I) •Bit 7: Negative flag (N)
The I flag disables all interrupts except for the interrupt The N flag is set if the result of an arithmetic operation or data
generated by the BRK instruction. transfer is negative. When the BIT instruction is executed, bit 7 of
Interrupts are disabled when the I flag is “1”. the memory location operated on by the BIT instruction is stored
•Bit 3: Decimal mode flag (D) in the negative flag.
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 8 Set and clear instructions of each bit of processor status register
C flag Z flag I flag D flag B flag T flag V flag N flag
Set instruction SEC – SEI SED – SET – –
Clear instruction CLC – CLI CLD – CLT CLV –
13
3822 Group
[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B 16.
b7 b0
CPU mode register
(CPUM (CM) : address 003B 16)
Processor mode bits

b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN –XCOUT oscillating function
Main clock (X IN – XOUT ) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN )/2 (high-speed mode)
1 : f(XIN )/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN –XOUT selected (middle-/high-speed mode)
1 : XCIN –XCOUT selected (low-speed mode)
Fig. 11 Structure of CPU mode register
14
3822 Group
MEMORY Zero Page

Special Function Register (SFR) Area The 256 bytes from addresses 000016 to 00FF 16 are called the
The Special Function Register area in the zero page contains con- zero page area. The internal RAM and the special function regis-
trol registers such as I/O ports and timers. ter (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
RAM and register addresses in the zero page area. Access to this area
RAM is used for data storage and for stack area of subroutine with only 2 bytes is possible in the zero page addressing mode.
calls and interrupts.
Special Page
ROM The 256 bytes from addresses FF0016 to FFFF 16 are called the
The first 128 bytes and the last 2 bytes of ROM are reserved for special page area. The special page addressing mode can be
device testing and the rest is user area for storing programs. used to specify memory addresses in the special page area.
Access to this area with only 2 bytes is possible in the special
Interrupt Vector Area page addressing mode.
The interrupt vector area contains reset and interrupt vectors.
RAM area
000016
RAM size Address
(bytes) XXXX16 SFR area
004016 Zero page

192 00FF16 LCD display RAM area
005016
256 013F16
384 01BF16 010016
RAM
512 023F16
640 02BF16
768 033F16
XXXX16
896 03BF16
1024 043F16 Reserved area
084016
Not used
ROM area
ROM size Address Address YYYY16

(bytes) YYYY16 ZZZZ16
Reserved ROM area
4096 F00016 F08016 (128 bytes)
8192 E00016 E08016
ZZZZ16
12288 D00016 D08016
16384 C00016 C08016
20480 B00016 B08016
24576 A00016 A08016
ROM
28672 900016 908016
32768 800016 808016 FF0016
36864 700016 708016

600016 608016 FFDC16
40960
45056 500016 508016 Special page
Interrupt vector area
49152 400016 408016
FFFE16
Reserved ROM area
FFFF16
Fig. 12 Memory map diagram
15
3822 Group
000016 Port P0 (P0) 002016 Timer X (low) (TXL)

000116 Port P0 direction register (P0D) 002116 Timer X (high) (TXH)
000216 Port P1 (P1) 002216 Timer Y (low) (TYL)
000316 Port P1 output control register (P1D) 002316 Timer Y (high) (TYH)
000416 Port P2 (P2) 002416 Timer 1 (T1)
000516 Port P2 direction register (P2D) 002516 Timer 2 (T2)
000616 Port P3 (P3) 002616 Timer 3 (T3)
000716 002716 Timer X mode register (TXM)
000816 Port P4 (P4) 002816 Timer Y mode register (TYM)
000916 Port P4 direction register (P4D) 002916 Timer 123 mode register (T123M)
000A16 Port P5 (P5) 002A16 φ output control register (CKOUT)
000B16 Port P5 direction register (P5D) 002B16
000C16 Port P6 (P6) 002C16
000D16 Port P6 direction register (P6D) 002D16
000E16 Port P7 (P7) 002E16
000F16 Port P7 direction register (P7D) 002F 16
001016 003016
001116 003116
001216 003216
001316 003316
001416 003416 A-D control register (ADCON)
001516 003516 A-D conversion register (AD)
001616 PULL register A (PULLA) 003616
001716 PULL register B (PULLB) 003716
001816 Transmit/Receive buffer register (TB/RB) 003816 Segment output enable register (SEG)
001916 Serial I/O status register (SIOSTS) 003916 LCD mode register (LM)
001A16 Serial I/O control register (SIO1CON) 003A16 Interrupt edge selection register (INTEDGE)
001B16 UART control register (UARTCON) 003B16 CPU mode register (CPUM)
001C16 Baud rate generator (BRG) 003C16 Interrupt request register 1(IREQ1)
001D16 003D16 Interrupt request register 2(IREQ2)
001E16 003E16 Interrupt control register 1(ICON1)
001F16 003F 16 Interrupt control register 2(ICON2)
Fig. 13 Memory map of special function register (SFR)
16
3822 Group
I/O PORTS
Direction Registers (ports P2, P4 1-P47, and b7 b0
PULL register A
P5-P7) (PULLA: address 001616 )
The 3822 group has 49 programmable I/O pins arranged in seven P00–P07 pull-down
I/O ports (ports P0–P2, P4 1–P4 7 and P5-P7). The I/O ports P2, P10–P17 pull-down
P41–P4 7 and P5-P7 have direction registers which determine the P20–P27 pull-up
P34–P37 pull-down
input/output direction of each individual pin. Each bit in a direction P70, P71 pull-up
register corresponds to one pin, and each pin can be set to be in- Not used (return “0” when read)
put port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin. b7 b0
PULL register B
If data is read from a pin set to output, the value of the port output (PULLB : address 001716)
latch is read, not the value of the pin itself. Pins set to input are P41–P43 pull-up
floating. If a pin set to input is written to, only the port output latch P44–P47 pull-up
P50–P53 pull-up
is written to and the pin remains floating.
P54–P57 pull-up
P60–P63 pull-up
Direction Registers (ports P0 and P1) P64–P67 pull-up
Ports P0 and P1 have direction registers which determine the in- Not used (return “0” when read)
put/output direction of each individual port. 0: Disable

1: Enable
Each port in a direction register corresponds to one port, each port
can be set to be input or output. When “0” is written to the bit 0 of Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
a direction register, that port becomes an input port. When “1” is
written to that port, that port becomes an output port. Bits 1 to 7 of
Fig. 14 Structure of PULL register A and PULL register B
ports P0 and P1 direction registers are not used.
Ports P3 and P40

These ports are only for input.
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports except for port P4 0 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
17
3822 Group
Table 9 List of I/O port function

Pin Name Input/Output I/O Format Non-Port Function Related SFRs Diagram No.
P00 /SEG16 – Port P0 Input/output, CMOS compatible LCD segment output PULL register A (1)
P07 /SEG23 individual ports input level Segment output enable
CMOS 3-state output register
P10 /SEG24 – Port P1
P17 /SEG31
P20 –P27 Port P2 Input/output, CMOS compatible Key input (key-on PULL register A (2)
individual bits input level wake-up) interrupt Interrupt control register 2
CMOS 3-state output input
P34 /SEG12 – Port P3 Input CMOS compatible LCD segment output PULL register A (3)
P37 /SEG15 input level Segment output enable
register
P40 Port P4 Input CMOS compatible (4)

input level
P41 /φ Input/output, CMOS compatible φ clock output PULL register B (5)

individual bits input level φ output control register
P42 /INT0, CMOS 3-state output
External interrupt input PULL register B (2)
P43 /INT1 Interrupt edge selection
register
P44 /RXD Serial I/O function I/O PULL register B (6)
P45 /TXD Serial I/O control register (7)
P46 /SCLK Serial I/O status register (8)
P47 /SRDY UART control register (9)
P50 /INT2 , Port P5 Input/output, CMOS compatible External interrupt input PULL register B (2)
P51 /INT3 individual bits input level Interrupt edge selection
CMOS 3-state output register
P52 /RTP0 , Real time port PULL register B (10)
P53 /RTP1 function output Timer X mode register
P54 /CNTR0 Timer X function I/O PULL register B (11)
Timer X mode register
P55 /CNTR1 Timer Y function input PULL register B (12)
Timer Y mode register
P56/T OUT Timer 2 function output PULL register B (13)
Timer 123 mode register
P57 /ADT A-D trigger input PULL register B (12)

P60 /AN0– Port P6 Input/output, CMOS compatible A-D conversion input A-D control register (14)
P67 /AN7 individual bits input level
CMOS 3-state output
P70 /XCOUT Port P7 Input/output, CMOS compatible Sub-clock PULL register A (15)
individual bits input level
generating circuit I/O CPU mode register (16)
P71 /XCIN CMOS 3-state output
COM0–COM3 Common Output LCD common output LCD mode register (17)
SEG 0–SEG11 Segment Output LCD segment output (18)
Notes1: How to use double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate po-
tential, a current will flow VCC to V SS through the input-stage gate.
18
3822 Group
(1) Ports P0, P1 (2) Ports P2, P42, P43, P50, P51
VL2/VL3
Pull-up control
VL1/VSS
Segment output enable bit
(Note) Direction register
Direction register
Data bus Port latch

Data bus Port latch
Key input (Key-on wake-up) interrupt input

INT0–INT3 interrupt input
Pull-down control
Note: Bit 0 of direction register.
(3) Ports P34–P37 (4) Port P40

VL2/VL3
Data bus
VL1/VSS
Data bus
Pull-down control
(5) Port P41 (6) Port P44
Pull-up control Pull-up control
Serial I/O enable bit

Receive enable bit
Direction register
Direction register
Data bus Port latch

Data bus Port latch
φ output control bit

φ
Serial I/O input
Fig. 15 Port block diagram (1)
19
3822 Group
(7) Port P45 (8) Port P46

Serial I/O clock-
Pull-up control synchronized selection bit
P45/TxD P-channel output disable bit Serial I/O enable bit Pull-up control
Transmit enable bit Serial I/O mode selection bit
Direction register
Direction register
Data bus Port latch

Data bus Port latch
Serial I/O output

Serial I/O clock output
Serial I/O clock input
(9) Port P47 (10) Ports P52, P53
Pull-up control Pull-up control

Serial I/O mode selection bit
SRDY output enable bit
Direction register
Direction register
Data bus Port latch Data bus Port latch
Real time port control bit

Serial I/O ready output Data for real time port
(11) Port P54 (12) Ports P55, P57
Pull-up control
Pull-up control
Direction register
Direction register
Data bus Port latch

Data bus Port latch
Timer X operating mode bit

(Pulse output mode selection)
Timer output CNTR1 interrupt input
A-D trigger interrupt input
CNTR0 interrupt input
20
3822 Group
(13) Port P56 (14) Port P6
Pul-up control
Pull-up control
Direction register
Direction register
Data bus Port latch

Data bus Port latch
TOUT output control bit

Timer output A-D conversion input
Analog input pin selection bit
(15) Port P70 (16) Port P71
Port XC switch bit + Pull-up control Port XC switch bit + Pull-up control
Port XC switch bit Port XC switch bit
Direction register Direction register
Data bus Port latch Data bus Port latch
Oscillation circuit
Port P71 Sub-clock generating circuit input
Port XC switch bit
(17) COM0–COM3 (18) SEG0–SEG11
VL2/VL3
VL3
The voltage applied to the sources of

VL1/VSS P-channel and N-channel transistors
VL2 The gate input signal of each transistor is is the controlled voltage by the bias
controlled by the LCD duty ratio and the value.
VL1
bias value.
21
3822 Group
INTERRUPTS 2. The interrupt disable flag is set and the corresponding

Interrupts occur by seventeen sources: eight external, eight inter- interrupt request bit is cleared.
nal, and one software. 3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt ■Notes on interrupts
enable bit, and the interrupt disable flag except for the software When setting the followings, the interrupt request bit may be set to
interrupt set by the BRK instruction. An interrupt occurs if the cor- “1”.
responding interrupt request and enable bits are “1” and the •When setting external interrupt active edge
interrupt disable flag is “0”. Related register: Interrupt edge selection register (address 3A 16)
Interrupt enable bits can be set or cleared by software. Timer X mode register (address 27 16)
Interrupt request bits can be cleared by software, but cannot be Timer Y mode register (address 2816 )
set by software. •When switching interrupt sources of an interrupt vector address
The BRK instruction cannot be disabled with any flag or bit. The I where two or more interrupt sources are allocated
flag disables all interrupts except the BRK instruction interrupt. Related register: A-D control regsiter (address 3416 )
When several interrupts occur at the same time, the interrupts are When not requiring for the interrupt occurrence synchronized with
received according to priority. these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
Interrupt Operation ➁Set the interrupt edge select bit or the interrupt source select bit
Upon acceptance of an interrupt the following operations are auto- to “1”.
matically performed: ➂Set the corresponding interrupt request bit to “0” after 1 or more
1. The contents of the program counter and processor status instructions have been executed.
register are automatically pushed onto the stack. ➃Set the corresponding interrupt enable bit to “1” (enabled).
Table 10 Interrupt vector addresses and priority

Vector Addresses (Note 1) Interrupt Request
Interrupt Source Priority Remarks
High Low Generating Conditions
Reset (Note 2) 1 FFFD 16 FFFC16 At reset Non-maskable
INT 0 2 FFFB16 FFFA16 At detection of either rising or External interrupt
falling edge of INT0 input (active edge selectable)
INT 1 3 FFF916 FFF816 At detection of either rising or External interrupt
Serial I/O 4 FFF716 FFF616 At completion of serial I/O data Valid when serial I/O is selected
reception reception
Serial I/O 5 FFF516 FFF416 At completion of serial I/O trans- Valid when serial I/O is selected
transmission mit shift or when transmission
buffer is empty
Timer X 6 FFF316 FFF216 At timer X underflow
Timer Y 7 FFF116 FFF016 At timer Y underflow
Timer 2 8 FFEF16 FFEE16 At timer 2 underflow
Timer 3 9 FFED16 FFEC16 At timer 3 underflow
CNTR 0 10 FFEB 16 FFEA16 At detection of either rising or External interrupt
falling edge of CNTR0 input (active edge selectable)
CNTR 1 11 FFE916 FFE816 At detection of either rising or External interrupt
falling edge of CNTR1 input (active edge selectable)
Timer 1 12 FFE716 FFE616 At timer 1 underflow
INT 2 13 FFE516 FFE416 At detection of either rising or External interrupt
INT 3 14 FFE316 FFE216 At detection of either rising or External interrupt
Key input 15 FFE116 FFE016 At falling of conjunction of input External interrupt
(Key-on wake-up) level for port P2 (at input mode) (Valid at falling)
ADT 16 FFDF 16 FFDE16 At falling of ADT input Valid when ADT interrupt is se-
lected, External interrupt
(Valid at falling)
A-D conversion At completion of A-D conversion Valid when A-D interrupt is se-
lected
BRK instruction 17 FFDD 16 FFDC16 At BRK instruction execution Non-maskable software interrupt
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
22
3822 Group
Interrupt request bit

Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Interrupt request

Reset
Fig. 18 Interrupt control
b7 b0
Interrupt edge selection register
(INTEDGE : address 003A 16)
INT0 interrupt edge selection bit

Not used (return “0” when read) 0 : Falling edge active

1 : Rising edge active
b7 b0 b7 b0
Interrupt request register 1 Interrupt request register 2
(IREQ1 : address 003C 16) (IREQ2 : address 003D 16)
INT0 interrupt request bit CNTR0 interrupt request bit

INT1 interrupt request bit CNTR1 interrupt request bit
Serial I/O receive interrupt request bit Timer 1 interrupt request bit
Serial I/O transmit interrupt request bit INT2 interrupt request bit
Timer X interrupt request bit INT3 interrupt request bit
Timer Y interrupt request bit Key input interrupt request bit
Timer 2 interrupt request bit ADT/AD conversion interrupt request bit
Timer 3 interrupt request bit Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7 b0 b7 b0
Interrupt control register 1 Interrupt control register 2
(ICON1 : address 003E 16) (ICON2 : address 003F 16 )
INT0 interrupt enable bit CNTR0 interrupt enable bit

INT1 interrupt enable bit CNTR1 interrupt enable bit
Serial I/O receive interrupt enable bit Timer 1 interrupt enable bit
Serial I/O transmit interrupt enable bit INT2 interrupt enable bit
Timer X interrupt enable bit INT3 interrupt enable bit
Timer Y interrupt enable bit Key input interrupt enable bit
Timer 2 interrupt enable bit ADT/AD conversion interrupt enable bit
Timer 3 interrupt enable bit Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 19 Structure of interrupt-related registers
23
3822 Group
Key Input Interrupt (Key-on wake-up) “1” to “0”. An example of using a key input interrupt is shown in
A Key-on wake-up interrupt request is generated by applying a Figure 20, where an interrupt request is generated by pressing
falling edge to any pin of port P2 that have been set to input mode. one of the keys consisted as an active-low key matrix which inputs
In other words, it is generated when AND of input level goes from to ports P20–P23.
Port PXX
“L” level output
PULL register A bit 2 = “1” Port P27 Key input interrupt request
direction register = “1”
✽ ✽✽ Port P27
latch
P27 output
Port P26
✽ ✽✽ Port P26
latch
P26 output
Port P25
✽ ✽✽ Port P25
latch
P25 output
Port P24
✽ ✽✽ Port P24
latch
P24 output
Port P23
direction register = “0” Port P2
✽ ✽✽ Port P23 Input reading circuit
P23 input latch
Port P22
✽ ✽✽ Port P22
latch
P22 input
Port P21
✽ ✽✽ Port P21
latch
P21 input
Port P20
✽ ✽ Port P20
latch
P20 input
✽ P-channel transistor for pull-up

✽✽ CMOS output buffer
Fig. 20 Connection example when using key input interrupt and port P2 block diagram
24
3822 Group
TIMERS responding to that timer is set to “1”.

The 3822 group has five timers: timer X, timer Y, timer 1, timer 2, Read and write operation on 16-bit timer must be performed for
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, both high and low-order bytes. When reading a 16-bit timer, read
timer 2, and timer 3 are 8-bit timers. the high-order byte first. When writing to a 16-bit timer, write the
All timers are down count timers. When the timer reaches “00 16”, low-order byte first. The 16-bit timer cannot perform the correct
an underflow occurs at the next count pulse and the correspond- operation when reading during the write operation, or when writing
ing timer latch is reloaded into the timer and the count is during the read operation.
continued. When a timer underflows, the interrupt request bit cor-
Real time port

control bit “1” Data bus
Q D P52 data for real time port
P52
“0” Latch
P52 direction register
P52 latch
Real time port
control bit “1”
Q D P53 data for real time port
P53
“0” Latch Real time port
P53 direction register control bit “0”
P53 latch Timer X mode register
“1” write signal
f(XIN)/16
(f(XIN)/16 in low-speed mode✽)
Timer X stop Timer X write
control bit control bit
CNT R0 active Timer X operat-
edge switch bit ing mode bits Timer X (low) latch (8) Timer X (high) latch (8)
“00”,“01”,“11”
“0” Timer X
P54/CNTR0 Timer X (low) (8) Timer X (high) (8) interrupt
“10” request
“1”
Pulse width CNT R0
measurement interrupt
mode CNTR0 active Pulse output mode request
edge switch bit “0”
QS
T Timer Y operating mode bits
“1” “00”,“01”,“10” CNTR1
P54 direction register Q
P54 latch Pulse width HL continuously measurement mode interrupt
request
Rising edge detection “11”
Pulse output mode Period
measurement mode
Falling edge detection
f(XIN)/16
(f(XCIN)516 in low-speed mode✽)
Timer Y stop
CNTR1 active control bit
edge switch bit “00”,“01”,“11” Timer Y (low) latch (8) Timer Y (high) latch (8)
“0” Timer Y
P55/CNTR1 Timer Y (low) (8) Timer Y (high) (8) interrupt
request
“10” Timer Y operating
“1” mode bits
f(XIN)/16 Timer 1
(f(XCIN)/16 in low-speed mode]) interrupt
Timer 1 count source Timer 2 count source Timer 2 write request
selection bit selection bit control bit
“0” Timer 1 latch (8) Timer 2 latch (8)
“0”
Timer 2
XCIN Timer 1 (8) Timer 2 (8) interrupt
“1” request
“1”
f(XIN)/16
(f(XCIN)/16 in low-speed mode✽)
TOUT output TOUT output

active edge control bit
TOUT output switch bit
control bit “0”
QS
P56/TOUT
T
“1”
P56 direction register P56 latch Q “0” Timer 3 latch (8)
Timer 3
Timer 3 (8) interrupt
f(XIN)/16(f(XCIN)/16 in low-speed mode✽) request
“1”
✽ Internal clock φ =XCIN /2 Timer 3 count
source selection bit
Fig. 21 Timer block diagram
25
3822 Group
Timer X ●Real time port control

Timer X is a 16-bit timer that can be selected in one of four modes While the real time port function is valid, data for the real time port
and can be controlled the timer X write and the real time port by are output from ports P5 2 and P5 3 each time the timer X
setting the timer X mode register. underflows. (However, after rewriting a data for real time port, if
the real time port control bit is changed from “0” to “1”, data are
(1) Timer Mode output independent of the timer X operation.) If the data for the
The timer counts f(XIN)/16 (or f(X CIN)/16 in low-speed mode). real time port is changed while the real time port function is valid,
the changed data are output at the next underflow of timer X.
(2) Pulse Output Mode Before using this function, set the corresponding port direction
Each time the timer underflows, a signal output from the CNTR0 registers to output mode.
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode, ■Note on CNTR 0 interrupt active edge
set the corresponding port P5 4 direction register to output mode. selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
(3) Event Counter Mode switch bit.
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P5 4 direction register to input mode. b7 b0
Timer X mode register
(TXM : address 002716)
(4) Pulse Width Measurement Mode
The count source is f(XIN )/16 (or f(XCIN)/16 in low-speed mode). If Timer X write control bit
0 : Write value in latch and counter
CNTR0 active edge switch bit is “0”, the timer counts while the in- 1 : Write value in latch only
Real time port control bit
put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while 0 : Real time port function invalid
the input signal of CNTR 0 pin is at “L”. When using a timer in this 1 : Real time port function valid
P52 data for real time port
mode, set the corresponding port P5 4 direction register to input P53 data for real time port
mode. Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
●Timer X write control
1 0 : Event counter mode
If the timer X write control bit is “0”, when the value is written in the 1 1 : Pulse width measurement mode
CNT R0 active edge switch bit
address of timer X, the value is loaded in the timer X and the latch 0 : Count at rising edge in event counter mode
at the same time. Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
If the timer X write control bit is “1”, when the value is written in the measurement mode
address of timer X, the value is loaded only in the latch. The value Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
in the latch is loaded in timer X after timer X underflows. Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
If the value is written in latch only, when writing in the timer latch at measurement mode
the timer underflow, the value is set in the timer and the latch at Rising edge active for CNTR0 interrupt
Timer X stop control bit
one time. Additionally, unexpected value may be set in the high-or- 0 : Count start
der counter when the writing in high-order latch and the underflow 1 : Count stop
of timer X are performed at the same timing.
Fig. 22 Structure of timer X mode register
26
3822 Group
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7 b0
(1) Timer Mode Timer Y mode register
(TYM : address 002816)
The timer counts f(XIN)/16 (or f(X CIN)/16 in low-speed mode).
Not used (return “0” when read)
Timer Y operating mode bits
(2) Period Measurement Mode b5 b4
0 0 : Timer mode
CNTR 1 interrupt request is generated at rising/falling edge of 0 1 : Period measurement mode
CNTR1 pin input signal. Simultaneously, the value in timer Y latch 1 0 : Event counter mode
1 1 : Pulse width HL continuously measurement
is reloaded in timer Y and timer Y continues counting down. Ex- mode
cept for the above-mentioned, the operation in period CNT R1 active edge switch bit
0 : Count at rising edge in event counter mode
measurement mode is the same as in timer mode. Measure the falling edge to falling edge
period in period measurement mode
The timer value just before the reloading at rising/falling of CNTR1 Falling edge active for CNTR1 interrupt
pin input signal is retained until the timer Y is read once after the 1 : Count at falling edge in event counter mode
Measure the rising edge period in period
reload. measurement mode
The rising/falling timing of CNTR1 pin input signal is found by Rising edge active for CNT R1 interrupt
Timer Y stop control bit
CNTR 1 interrupt. When using a timer in this mode, set the corre- 0 : Count start
1 : Count stop
sponding port P55 direction register to input mode.
(3) Event Counter Mode

The timer counts signals input through the CNTR1 pin. Fig. 23 Structure of timer Y mode register
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P5 5 direction register to input mode.
(4) Pulse Width HL Continuously Measurement

Mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P55 direction register to input mode.
■Note on CNTR1 interrupt active edge selection

CNTR 1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR 1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
27
3822 Group
Timer 1, Timer 2, Timer 3

Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer b7 b0
latch value is not affected by a change of the count source. How- Timer 123 mode register
(T123M :address 002916)
ever, because changing the count source may cause an
inadvertent count down of the timer, rewrite the value of timer TOUT output active edge switch bit
whenever the count source is changed. 0 : Start at “H” output
1 : Start at “L” output
TOUT output control bit
●Timer 2 write control 0 : TOUT output disabled
1 : TOUT output enabled
If the timer 2 write control bit is “0”, when the value is written in the Timer 2 write control bit
address of timer 2, the value is loaded in the timer 2 and the latch 0 : Write data in latch and counter
1 : Write data in latch only
at the same time. Timer 2 count source selection bit
If the timer 2 write control bit is “1”, when the value is written in the 0 : Timer 1 output
address of timer 2, the value is loaded only in the latch. The value 1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
in the latch is loaded in timer 2 after timer 2 underflows. Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
●Timer 2 output control (or f(XCIN)/16 in low-speed mode)
When the timer 2 (T OUT) is output enabled, an inversion signal Timer 1 count source selection bit
0 : f(XIN)/16
from the TOUT pin is output each time timer 2 underflows. (or f(XCIN)/16 in low-speed mode)
In this case, set the port shared with the TOUT pin to the output 1 : f(XCIN)
mode.
Note: Internal clock φ is f(XCIN)/2 in the low-speed mode.

■Notes on timer 1 to timer 3
When the count source of timer 1 to 3 is changed, the timer count-
ing value may be changed large because a thin pulse is generated
in count input of timer . If timer 1 output is selected as the count Fig. 24 Structure of timer 123 mode register
source of timer 2 or timer 3, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a thin
pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
28
3822 Group
SERIAL I/O (1) Clock Synchronous Serial I/O Mode

Serial I/O can be used as either clock synchronous or asynchro- Clock synchronous serial I/O can be selected by setting the mode
nous (UART) serial I/O. A dedicated timer (baud rate generator) is selection bit of the serial I/O control register to “1”.
also provided for baud rate generation. For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Data bus
Serial I/O control register Address 001A16

Address 001816
Receive buffer register Receive buffer full flag (RBF)
P44/RXD Receive shift register Receive interrupt request (RI)
Shift clock
Clock control circuit
P46/SCLK
Serial I/O
clock selection bit
BRG count source selection bit Frequency division ratio 1/(n+1)
f(XIN) Baud rate generator 1/4
(f(XCIN) in low-speed mode) Address 001C16
1/4
P47/SRDY1 Falling-edge detector Clock control circuit

F/F
Shift clock Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD Transmit shift register Transmit interrupt request (TI)
Transmit buffer register Transmit buffer empty flag (TBE)

Serial I/O status register Address 001916
Address 001816
Data bus
Fig. 25 Block diagram of clock synchronous serial I/O
Transfer shift clock

(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD D0 D1 D2 D3 D4 D5 D6 D7
Serial input RXD D0 D1 D2 D3 D4 D5 D6 D7
Receive enable signal SRDY
Write signal to receive/transmit

buffer register (address 001816)
TBE = 0 RBF = 1
TBE = 1 TSC = 1
TSC = 0 Overrun error (OE)
detection
Notes 1 : T he transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE=1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : T he receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 26 Operation of clock synchronous serial I/O function
29
3822 Group
(2) Asynchronous Serial I/O (UART) Mode ter, but the two buffers have the same address in memory. Since
Clock asynchronous serial I/O mode (UART) can be selected by the shift register cannot be written to or read from directly, transmit
clearing the serial I/O mode selection bit of the serial I/O control data is written to the transmit buffer, and receive data is read from
register to “0”. the receive buffer.
Eight serial data transfer formats can be selected, and the transfer The transmit buffer can also hold the next data to be transmitted,
formats used by a transmitter and receiver must be identical. and the receive buffer register can hold a character while the next
The transmit and receive shift registers each have a buffer regis- character is being received.
Data bus
Address 001816
Serial I/O control register Address 001A16
OE Receive buffer register Receive buffer full flag (RBF)
Character length selection bit Receive interrupt request (RI)
P44/RXD STdetector 7 bits Receive shift register
8 bits 1/16
PE FE SP detector UART control register
Clock control circuit Address 001B16
Serial I/O synchronous clock selection bit

P46/SCLK
BRG count source selection bit Frequency division ratio 1/(n+1)

f(XIN)
Baud rate generator
(f(XCIN) in low-speed mode)
Address 001C16
1/4
ST/SP/PA generator
1/16 Transmit shift register shift completion flag (TSC)

Transmit interrupt source selection bit
P45/TXD Transmit shift register Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register Transmit buffer empty flag (TBE)
Address 001816 Serial I/O status register Address 001916
Data bus
Fig. 27 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0 TBE=0
TSC=0
TBE=1 TBE=1 TSC=1✽
Serial output TXD ST D0 D1 SP ST D0 D1 SP

1 start bit ✽Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1 RBF=1
Serial input RXD ST D0 D1 SP ST D0 D1 SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 28 Operation of UART serial I/O function
30
3822 Group
[Transmit Buffer/Receive Buffer Register

(TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is
write-only and the receive buffer register is read-only. If a charac-
ter bit length is 7 bits, the MSB of data stored in the receive buffer
register is “0”.
[Serial I/O Status Register (SIOSTS)] 001916

The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE. Writ-
ing “0” to the serial I/O enable bit (SIOE) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A16

The serial I/O control register contains eight control bits for the se-
rial I/O function.
[UART Control Register (UARTCON) ]001B16

The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45 /TXD pin.
[Baud Rate Generator (BRG)] 001C16

The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
■Notes on serial I/O

When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
➀Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O transmit interrupt enable bit to “1” (enabled).
31
3822 Group
b7 b0 b7 b0
Serial I/O status register Serial I/O control register
(SIOSTS : address 001916) (SIOCON : address 001A16)
Transmit buffer empty flag (TBE) BRG count source selection bit (CSS)
0: Buffer full 0: f(XIN) (f(XCIN) in low-speed mode)
1: Buffer empty 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Receive buffer full flag (RBF) Serial I/O synchronization clock selection bit (SCS)
0: Buffer empty 0: BRG output divided by 4 when clock synchronized serial
1: Buffer full I/O is selected.
BRG output divided by 16 when UART is selected.
Transmit shift register shift completion flag (TSC) 1: External clock input when clock synchronized serial I/O is
0: Transmit shift in progress selected.
1: Transmit shift completed External clock input divided by 16 when UART is selected.
Overrun error flag (OE) SRDY output enable bit (SRDY)

0: No error 0: P47 pin operates as ordinary I/O pin
1: Overrun error 1: P47 pin operates as SRDY output pin
Parity error flag (PE) Transmit interrupt source selection bit (TIC)
0: No error 0: Interrupt when transmit buffer has emptied
1: Parity error 1: Interrupt when transmit shift operation is completed
Framing error flag (FE) Transmit enable bit (TE)

0: No error 0: Transmit disabled
1: Framing error 1: Transmit enabled
Summing error flag (SE) Receive enable bit (RE)

0: (OE) U (PE) U (FE) =0 0: Receive disabled
1: (OE) U (PE) U (FE) =1 1: Receive enabled
Not used (returns “1” when read) Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)

b7 b0 UART control regi ster 0: Serial I/O disabled
(pins P44–P47 operate as ordinary I/O pins)
(UART CON : address 001B16) 1: Serial I/O enabled
Character length selection bit (CHAS) (pins P44–P47 operate as serial I/O pins)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)

0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)

0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)

0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)

0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Fig. 29 Structure of serial I/O control registers
32
3822 Group
A-D CONVERTER
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains b7 b0
A-D control register
the result of an A-D conversion. When reading this register during (ADCON : address 003416)
an A-D conversion, the previous conversion result is read. Analog input pin selection bits
0 0 0 : P60/AN0
0 0 1 : P61/AN1
[A-D Control Register (ADCON)] 003416 0 1 0 : P62/AN2
The A-D control register controls the A-D conversion process. Bits 0 1 1 : P63/AN3
0 to 2 of this register select specific analog input pins. Bit 3 signals 1 0 0 : P64/AN4
the completion of an A-D conversion. The value of this bit remains 1 0 1 : P65/AN5
1 1 0 : P66/AN6
at “0” during an A-D conversion, then changes to “1” when the A- 1 1 1 : P67/AN7
D conversion is completed. Writing “0” to this bit starts the A-D AD conversion completion bit
conversion. Bit 4 controls the transistor which breaks the through 0 : Conversion in progress
1 : Conversion completed
current of the resistor ladder. When bit 5, which is the AD external VREF input switch bit
trigger valid bit, is set to “1”, this bit enables A-D conversion even 0 : OFF
by a falling edge of an ADT input. Set ports which share with ADT 1 : ON
pins to input when using an A-D external trigger. AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
[Comparison Voltage Generator] Interrupt source selection bit
The comparison voltage generator divides the voltage between 0 : Interrupt request at A-D
conversion completed
AVSS and VREF by 256, and outputs the divided voltages. 1 : Interrupt request at ADT
input falling
[Channel Selector] Not used (returns “0” when read)
The channel selector selects one of the input ports P6 7/AN7–P6 0/

AN 0, and inputs it to the comparator.
Fig. 30 Structure of A-D control register
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500 kHz during A-D conversion.
Use the clock divided from the main clock XIN as the internal clock
φ.
Data bus
b7 b0
A-D control register
P57/ADT
A-D control circuit ADT/A-D interrupt request

P60/AN0
P61/AN1
Channel selector
P62/AN2 A-D conversion

Comparator register
P63/AN3
8
P64/AN4
P65/AN5 Resistor ladder
P66/AN6
P67/AN7
AVSS VREF
Fig. 31 A-D converter block diagram
33
3822 Group
LCD DRIVE CONTROL CIRCUIT enable bit is set to “1” after data is set in the LCD mode register,
The 3822 group has the built-in Liquid Crystal Display (LCD) drive the segment output enable register and the LCD display RAM, the
control circuit consisting of the following. LCD drive control circuit starts reading the display data automati-
●LCD display RAM cally, performs the bias control and the duty ratio control, and
●Segment output enable register displays the data on the LCD panel.
●LCD mode register
●Selector Table 11 Maximum number of display pixels at each duty ratio
●Timing controller
Duty ratio Maximum number of display pixel
●Common driver
64 dots
●Segment driver 2
or 8 segment LCD 8 digits
●Bias control circuit
96 dots
A maximum of 32 segment output pins and 4 common output pins 3
can be used.
Up to 128 pixels can be controlled for LCD display. When the LCD 128 dots
4
b7 b0
Segment output enable register
(SEG : address 003816)
Segment output enable bit 0

0 : Input port P34–P37
1 : Segment output SEG12–SEG15
0 : I/O port P00,P01
1 : Segment output SEG16, SEG17
0 : I/O port P02–P07
0 : I/O port P10,P11
1 : Segment output SEG24, SEG25
0 : I/O port P12
1 : Segment output SEG26
0 : I/O port P13–P17
(Do not write “1” to this bit.)
b7 b0
LCD mode register
(LM : address 003916)
Duty ratio selection bits

0 0 : Not used
0 1 : 2 (use COM0, COM1)
1 0 : 3 (use COM0–COM2)
1 1 : 4 (use COM0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
(Do not write “1” to this bit)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (or f(XCIN)/8192 in low-speed
mode)
Note: LCDCK is a clock for a LCD timing controller.
Fig. 32 Structure of segment output enable register and LCD mode register
34
Data bus
LCD enable bit
Address Address Address Duty ratio selection bits

LCD display RAM
004016 004116 004F16
LCD circuit divider LCDCK count source
division ratio selection bits selection bit
2 “0” f(XCIN)/32
2 LCD
Bias control bit divider f(XIN)/8192( or f(XCIN)/8192 in
“1” low-speed mode)
Fig. 33 Block diagram of LCD controller/driver

Selector Selector Selector Selector Selector Selector
Timing controller LCDCK
Segment Segment Segment Segment Segment Segment Common Common Common Common
driver driver driver Bias control driver driver driver driver
driver driver driver
SEG0 SEG1 SEG2 SEG3 P34/SEG12 P16/SEG30 P17/SEG31 VSS VL1 VL2 VL3 COM0 COM1 COM2 COM3
35

3822 Group
3822 Group
Bias Control and Applied Voltage to LCD Table 12 Bias control and applied voltage to VL1–VL3
Power Input Pins Bias value Voltage value
To the LCD power input pins (VL1 –VL3 ), apply the voltage shown VL3 =VLCD
in Table 12 according to the bias value. 1/3 bias VL2 =2/3 VLCD
Select a bias value by the bias control bit (bit 2 of the LCD mode VL1 =1/3 VLCD
register).
VL3 =VLCD
1/2 bias
VL2 =VL1=1/2 V LCD
Common Pin and Duty Ratio Control
Note 1: V LCD is the maximum value of supplied voltage for the
The common pins (COM 0–COM 3) to be used are determined by
LCD panel.
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
Table 13 Duty ratio control and common pins used
LCD mode register).
Duty Duty ratio selection bit
Common pins used
ratio Bit 1 Bit 0
2 0 1 COM0 , COM1 (Note 1)
3 1 0 COM0–COM2 (Note 2)
4 1 1 COM0–COM3
Notes1: COM2 and COM 3 are open.
2: COM3 is open.
Contrast control Contrast control
VL3 VL3
R1 R4
VL2 VL2
R2
VL1 VL1
R3 R5
R1 = R2 = R3 R4 = R5
1/3 bias 1/2 bias
Fig. 34 Example of circuit at each bias
36
3822 Group
LCD Display RAM LCD Drive Timing

Address 004016 to 004F16 is the designated RAM for the LCD dis- The LCDCK timing frequency (LCD drive timing) is generated in-
play. When “1” are written to these addresses, the corresponding ternally and the frame frequency can be determined with the
segments of the LCD display panel are turned on. following equation;
(frequency of count source for LCDCK)

f(LCDCK) =
(divider division ratio for LCD)
f(LCDCK)
Frame frequency =
(duty ratio)
B it
7 6 5 4 3 2 1 0
Address
004016 SEG1 SEG0
004116 SEG3 SEG2
004216 SEG5 SEG4
004316 SEG7 SEG6
004416 SEG9 SEG8
004516 SEG11 SEG10
004616 SEG13 SEG12
004716 SEG15 SEG14
004816 SEG17 SEG16
004916 SEG19 SEG18
004A16 SEG21 SEG20
004B16 SEG23 SEG22
004C16 SEG25 SEG24
004D16 SEG27 SEG26
004E16 SEG29 SEG28
004F16 SEG31 SEG30
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
Fig. 35 LCD display RAM map
37
3822 Group
Internal logic
LCDCK timing
1/4 duty Voltage level
VL3
COM0 VL2=VL1
VSS
COM1
COM2
COM3
SEG0 VL3
VSS
OFF ON OFF ON
1/3 duty
VL3
COM0 VL2=VL1
VSS
COM1
COM2
SEG0 VL3
VSS
ON OFF ON OFF ON OFF
1/2 duty
VL3
COM0 VL2=VL1
VSS
COM1
SEG0 VL3
VSS
ON OFF ON OFF ON OFF ON OFF
Fig. 36 LCD drive waveform (1/2 bias)
38
3822 Group
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
COM0 VL2
VL1
VSS
COM1
COM2
COM3
VL3
SEG0
VSS
OFF ON OFF ON
1/3 duty
VL3
COM0 VL2
VL1
VSS
COM1
COM2
VL3
SEG0
VSS
ON OFF ON OFF ON OFF
1/2 duty
VL3
VL2
COM0 VL1
VSS
COM1
VL3
SEG0
VSS
ON OFF ON OFF ON OFF ON OFF
Fig. 37 LCD drive waveform (1/3 bias)
39
3822 Group
φ CLOCK SYSTEM OUTPUT FUNCTION

The internal system clock φ can be output from port P4 1 by setting
the φ output control register. Set bit 1 of the port P4 direction reg-
ister to “1” when outputting φ clock.
b7 b0
φ output control register
(CKOUT : address 002A16)
φ output control bit

0 : port function
1 : φ clock output
Fig. 38 Structure of φ output control register
40
3822 Group
RESET CIRCUIT
Power on
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H” Power
source
level (the power source voltage should be between VCC(min.) and RESET VCC voltage
5.5 V, and the quartz-crystal oscillator should be stable), reset is 0V
released. After the reset is completed, the program starts from the Reset input
voltage VIL spec.
address contained in address FFFD 16 (high-order byte) and ad-
0V
dress FFFC 16 (low-order byte). Make sure that the reset input
voltage meets V IL spec. when a power source voltage passes
VCC(min.).
RESET VCC
Power source voltage

detection circuit
Fig. 39 Reset Circuit Example
XIN
RESET
Internal Reset address from

reset vector table
Address
? ? ? ? FFFC FFFD ADH, ADL
Data ADH
ADL
SYNC
XIN : about 8000 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) =8•f(φ)

2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 40 Reset Sequence
41
3822 Group
Address Register Contents

(1) Port P0 direction register 000116 0016
(5) Port P5 direction register 000B16 0016
(6) Port P6 direction register 000D16 0016
(7) Port P7 direction register 000F16 0016
(8) PULL register A 001616 0 0 0 0 1 0 1 1
(9) PULL register B 001716 0016
(10) Sirial I/O status register 001916 1 0 0 0 0 0 0 0
(11) Sirial I/O control register 001A16 0016
(12) UART control register 001B16 1 1 1 0 0 0 0 0
(13) Timer X(Low) 002016 F F1 6
(14) Timer X(High) 002116 F F1 6
(15) Timer Y(Low) 002216 F F1 6
(16) Timer Y(High) 002316 F F1 6
(17) Timer 1 002416 F F1 6
(18) Timer 2 002516 0116
(19) Timer 3 002616 F F1 6
(20) Timer X mode register 002716 0016
(21) Timer Y mode register 002816 0016
(22) Timer 123 mode register 002916 0016
(23) φ output control register 002A16 0016
(24) A-D control register 003416 0 0 0 0 1 0 0 0
(25) Segment output enable register 003816 0016
(26) LCD mode register 003916 0016
(27) Interrupt edge selection register 003A16 0016
(28) CPU mode register 003B16 0 1 0 0 1 0 0 0
(29) Interrupt request register 1 003C16 0016
(30) Interrupt request register 2 003D16 0016
(31) Interrupt control register 1 003E16 0016
(32) Interrupt control register 2 003F16 0016
(33) Processor status register (PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(34) Program counter (PCH) Contents of address FFFD16
(PCL) Contents of address FFFC16
Note: The contents of all other registers and RAM are undefined after reset, so they must be
initialized by software.
✕: undefined
Fig. 41 Initial status of microcomputer after reset
42
3822 Group
CLOCK GENERATING CIRCUIT Oscillation Control

The 3822 group has two built-in oscillation circuits. An oscillation (1) Stop Mode
circuit can be formed by connecting a resonator between XIN and If the STP instruction is executed, the internal clock φ stops at an
XOUT (XCIN and X COUT). Use the circuit constants in accordance “H” level, and X IN and XCIN oscillators stop. Timer 1 is set to
with the resonator manufacturer's recommended values. No exter- “FF16 ” and timer 2 is set to “0116 ”.
nal resistor is needed between XIN and XOUT since a feed-back Either X IN or X CIN divided by 16 is input to timer 1 as count
resistor exists on-chip. However, an external feed-back resistor is source, and the output of timer 1 is connected to timer 2. The bits
needed between XCIN and XCOUT. of the timer 123 mode register except bit 4 are cleared to “0”. Set
To supply a clock signal externally, input it to the XIN pin and make the timer 1 and timer 2 interrupt enable bits to disabled (“0”) be-
the X OUT pin open. The sub-clock X CIN-XCOUT oscillation circuit fore executing the STP instruction. Oscillator restarts at reset or
cannot directly input clocks that are externally generated. Accord- when an external interrupt is received, but the internal clock φ is
ingly, be sure to cause an external resonator to oscillate. not supplied to the CPU until timer 2 underflows. This allows timer
Immediately after poweron, only the XIN oscillation circuit starts for the clock circuit oscillation to stabilize.
oscillating, and XCIN and XCOUT pins function as I/O ports.
(2) Wait Mode
Frequency Control If the WIT instruction is executed, the internal clock φ stops at an
(1) Middle-speed Mode “H” level. The states of XIN and XCIN are the same as the state be-
The internal clock φ is the frequency of XIN divided by 8. fore the executing the WIT instruction. The internal clock restarts
After reset, this mode is selected. at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
(2) High-speed Mode clock is restarted.
The internal clock φ is half the frequency of XIN.
(3) Low-speed Mode

●The internal clock φ is half the frequency of XCIN.
●A low-power consumption operation can be realized by stopping
the main clock X IN in this mode. To stop the main clock, set bit 5
XCIN XCOUT XI N XOUT
of the CPU mode register to “1”.
When the main clock X IN is restarted, set enough time for oscil-
Rf Rd
lation to stabilize by programming.
Note: If you switch the mode between middle/high-speed and low-
speed, stabilize both X IN and X CIN oscillations. The CCIN CCOUT CI N COUT
sufficient time is required for the sub-clock to stabilize, es-
pecially immediately after poweron and at returning from
stop mode. When switching the mode between middle/high- Fig. 42 Ceramic resonator circuit
speed and low-speed, set the frequency on condition that
f(XIN) > 3f(X CIN).
XCIN XCOUT XIN XOUT
Rf Rd Open
External oscillation circuit

CCIN CCOUT
VCC
VSS
Fig. 43 External clock input circuit
43
3822 Group
XCIN XCOUT
“1” “0”
Port XC switch bit
Timer 1 count Timer 2 count

XIN XOUT Internal system clock selection bit source selection source selection
(Note) bit bit
Low-speed mode “1”
“1” “0”
Timer 1 Timer 2
1/2 1/4 1/2
“0” “0”
Middle-/High-speed mode “1”
Main clock division ratio selection bit

“1” Middle-speed mode
Timing φ
“0” (Internal system clock)
High-speed mode
or Low-speed mode
Main clock stop bit
Q S S Q Q S
R STP instruction WIT R R STP instruction

instruction
Reset
Interrupt disable flag I
Interrupt request
Note : When using the low-speed mode, set the port XC switch bit to “1” .
Fig.44 Clock generating circuit block diagram
44
3822 Group
Reset
CM6
Middle-spe ed mode (f(φ) = 1 MHz) High-speed mode (f(φ) = 4 MHz)
“1” “0”
CM7 = 0 (8 MHz selected) CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed) CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating) CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz sto pped) CM4 = 0 (32 kHz sto pped)
C
“0”
“0
” “0 M4 “0”
4 CM”
“1
CM “0
” ” 6
“1
” 6
CM4
CM4
“1 M ”
“1”
“1”
C “0
” ”
“1
CM6
Middle-spe ed mode (f(φ) = 1 MHz) High-speed mode (f(φ) = 4 MHz)
CM7 = 0 (8 MHz selected) “1” “0”
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed) CM6 = 0 (High-speed)
CM4 = 1 (32 kHz oscillatin g) CM4 = 1 (32 kHz oscillating)
“0”
“0”
CM7
CM7
“1”
“1”
CM6
Low-spee d mode (f(φ) = 16 kHz) L ow-speed mode (f(φ) =16 kHz)
“1” “0” CM7 = 1 (32 kHz selected)
CM7 = 1 (32 kHz sele cted)
CM6 = 1 (Middle-speed) CM6 = 0 (High-speed) b7 b4
CM4 = 1 (32 kHz oscillatin g) CM4 = 1 (32 kHz oscillating) CPU mode register
(CPUM : address 003B16)
C
“0 M5
“0”
“0”
” CM4 : Port Xc switch bit

“0 CM”
5
“1 0: I/O port
CM “0
” ” 6
“1 1: XCIN, XCOUT
” 6
CM5
CM5
“1 CM ” CM5 : Main clock (XIN–XOUT) stop bit

“1”
“1”
” “0 0: Oscillating
“1 ”
1: Stopped
CM6 : Main clock division ratio selection bit
CM6 L ow-speed mode (f(φ) =16 kHz)
0: f(XIN)/2 (high-speed mode)
Low-speed mode (f(φ) = 1 6 kHz)
CM7 = 1 (32 kHz sele cted) “1” “0” 1: f(XIN)/8 (middle-speed mode)
CM7=1(3 2 kHz selected)
CM6 = 1 (Middle-speed) CM6=0(High -spe ed) CM7 : Internal system clock selection bit
CM5 = 1 (8 MHz stopped ) CM5=1(8 MHz stop ped) 0: XIN–XOUT selected
CM4 = 1 (32 kHz oscillatin g) CM4=1(3 2 kHz oscillating) (middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : T he all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is
ended.
3 : T imer and LCD operate in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-speed mode.
7 : T he example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 45 State transitions of system clock
45
3822 Group
NOTES ON PROGRAMMING A-D Converter

Processor Status Register The comparator uses internal capacitors whose charge will be lost
The contents of the processor status register (PS) after a reset are if the clock frequency is too low.
undefined, except for the interrupt disable flag (I) which is “1”. Af- Make sure that f(X IN) is at least 500 kHz during an A-D conver-
ter a reset, initialize flags which affect program execution. sion.
In particular, it is essential to initialize the index X mode (T) and Do not execute the STP or WIT instruction during an A-D conver-
the decimal mode (D) flags because of their effect on calculations. sion.
Interrupt Instruction Execution Time

The contents of the interrupt request bits do not change immedi- The instruction execution time is obtained by multiplying the fre-
ately after they have been written. After writing to an interrupt quency of the internal clock φ by the number of cycles needed to
request register, execute at least one instruction before perform- execute an instruction.
ing a BBC or BBS instruction. The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Decimal Calculations The frequency of the internal clock φ is half of the X IN frequency.
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),

and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions

The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the S RDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
46
3822 Group
DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD

The following are necessary when ordering a mask ROM produc- The built-in PROM of the blank One Time PROM version and built-
tion: in EPROM version can be read or programmed with a general-
1.Mask ROM Order Confirmation Form ✽ purpose PROM programmer using a special programming
2.Mark Specification Form✽ adapter. Set the address of PROM programmer in the user ROM
3.Data to be written to ROM, in EPROM form (three identical cop- area.
ies) or one floppy disk
Table 14 Programming adapter
✽For the mask ROM confirmation and the mark specifications, re- Package Name of Programming Adapter
fer to the “Mitsubishi MCU Technical Information” Homepage 80P6N-A PCA4738F-80A
(http://www.infomicom.mesc.co.jp/). 80P6S-A PCA4738G-80A
80P6Q-A PCA4738H-80A
80D0 PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 46 is recommended to verify programming.
Programming with PROM

programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher

than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 46 Programming and testing of One Time PROM version
47
3822 Group
Table 15 Absolute maximum ratings (Standard, One Time PROM version)

Symbol Parameter Conditions Ratings Unit
VCC Power source voltage All voltages are based on VSS. –0.3 to 7.0 V
VI Input voltage P00–P07, P10–P17 , P20–P27, Output transistors are cut off.
–0.3 to VCC +0.3 V
P34–P37, P40–P47 , P50–P57
P60–P67, P70, P7 1
VI Input voltage VL1 –0.3 to VL2 V
VI Input voltage VL2 VL1 to VL3 V
VI Input voltage VL3 VL2 to VCC +0.3 V
VI Input voltage RESET, XIN –0.3 to V CC +0.3 V
VO Output voltage P0 0–P07, P10–P17 At output port –0.3 to V CC +0.3 V
At segment output –0.3 to VL3 +0.3 V
VO Output voltage P3 4–P37 At segment output –0.3 to VL3 +0.3 V
VO Output voltage P20–P27, P41–P47 ,P50–P57 , –0.3 to VCC +0.3 V
P60–P67, P70, P7 1
VO Output voltage SEG0–SEG 11 –0.3 to VL3 +0.3 V
VO Output voltage XOUT –0.3 to V CC +0.3 V
Pd Power dissipation Ta = 25°C 300 mW
Topr Operating temperature –20 to 85 °C
Tstg Storage temperature –40 to 125 °C
Table 16 Recommended operating conditions (Standard, One Time PROM version)

(V CC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol Parameter Unit
Min. Typ. Max.
High-speed mode f(XIN) = 8 MHz 4.0 5.0 5.5
VCC Power source voltage Middle-speed mode f(XIN) = 8 MHz 2.5 5.0 5.5 V
Low-speed mode 2.5 5.0 5.5
VSS Power source voltage 0 V
VREF A-D conversion reference voltage 2.0 VCC V
AVSS Analog power source voltage 0 V
VIA Analog input voltage AN0–AN 7 AVSS VCC V
VIH “H” input voltage P00–P07, P10 –P17 ,P34 –P37 , P40, P41 , P45, P47, P5 2, P53, 0.7VCC VCC V
P56,P60–P67,P70,P71 (CM4= 0)
VIH “H” input voltage P20–P27, P42 –P44 ,P46 ,P50, P51 , P54, P55 , P57 0.8VCC VCC V
VIH “H” input voltage RESET 0.8VCC VCC V
VIH “H” input voltage XIN 0.8VCC VCC V
VIL “L” input voltage P00–P07, P10 –P17 ,P34 –P37 , P40, P41 , P45, P47, P5 2, P53, 0 0.3 VCC V
P56,P60–P67,P70,P71 (CM4= 0)
VIL “L” input voltage P20–P27, P42 –P44 ,P46 ,P50, P51 , P54, P55 , P57 0 0.2 VCC V
VIL “L” input voltage RESET 0 0.2 VCC V
VIL “L” input voltage XIN 0 0.2 VCC V
48
3822 Group
Table 17 Recommended operating conditions (Standard, One Time PROM version)

(VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Min. Typ. Max.
ΣI OH(peak) “H” total peak output current P00–P07, P1 0–P17, P20–P27 (Note 1) –40 mA
ΣI OH(peak) “H” total peak output current P41–P47, P5 0–P57, P60–P67, P7 0, P71 (Note 1) –40 mA
ΣI OL(peak) “L” total peak output current P00–P07, P1 0–P17, P20–P27 (Note 1) 40 mA
ΣI OL(peak) “L” total peak output current P41–P47, P5 0–P57, P60–P67, P7 0, P71 (Note 1) 40 mA
ΣI OH(avg) “H” total average output current P00–P07, P1 0–P17, P20–P27 (Note 1) –20 mA
ΣI OH(avg) “H” total average output current P41–P47, P5 0–P57, P60–P67, P7 0, P71 (Note 1) –20 mA
ΣI OL(avg) “L” total average output current P00–P07, P1 0–P17, P20–P27 (Note 1) 20 mA
ΣI OL(avg) “L” total average output current P41–P47, P5 0–P57, P60–P67, P7 0, P71 (Note 1) 20 mA
I OH(peak) “H” peak output current P00–P07, P1 0–P17 (Note 2) –2 mA
I OH(peak) “H” peak output current P20–P27, P4 1–P47, P50 –P57 , P60–P67, P7 0, P71 –5 mA
(Note 2)
I OL(peak) “L” peak output current P00–P07, P1 0–P17 (Note 2) 5 mA
I OL(peak) “L” peak output current P20–P27, P4 1–P47, P50 –P57 , P60–P67, P7 0, P71 10 mA
(Note 2)
I OH(avg) “H” average output current P00–P07, P1 0–P17 (Note 3) –1.0 mA
I OH(avg) “H” average output current P20–P27, P4 1–P47, P50 –P57 , P60–P67, P7 0, P71 –2.5 mA
(Note 3)
I OL(avg) “L” average output current P00–P07, P1 0–P17 (Note 3) 2.5 mA
I OL(avg) “L” average output current P20–P27, P4 1–P47, P50 –P57 , P60–P67, P7 0, P71 5.0 mA
(Note 3)
f(CNTR 0) Input frequency for timers X and Y (4.0 V ≤ VCC ≤ 5.5 V) 4.0 MHz
f(CNTR 1) (duty cycle 50%) (2.5 V ≤ VCC ≤ 4.0 V) (2✕VCC)-4 MHz
High-speed mode
8.0 MHz
(4.0 V ≤ VCC ≤ 5.5 V)
f(XIN ) Main clock input oscillation frequency High-speed mode
(Note 4) (4✕VCC)-8 MHz
(2.5 V ≤ VCC ≤ 4.0 V)
Middle-speed mode 8.0 MHz
f(XCIN ) Sub-clock input oscillation frequency (Notes 4, 5) 32.768 50 kHz
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value mea-
sured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50 %.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN ) < f(XIN)/3.
49
3822 Group
Table 18 Electrical characteristics (Standard, One Time PROM version)

(VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol Parameter Test conditions Unit
Min. Typ. Max.
IOH = –2.5 mA VCC–2.0 V
“H” output voltage
VOH IOH = –0.6 mA
P00–P07, P10–P17 VCC–1.0 V
VCC = 2.5 V
IOH = –5 mA VCC–2.0 V
VOH IOH = –1.25 mA VCC–0.5 V
P20–P27, P41–P47 , P50–P57, P60 –P67,
P70, P71 (Note) IOH = –1.25 mA VCC–1.0 V
VCC = 2.5 V
IOL = 5 mA 2.0 V
“L” output voltage IOL = 1.25 mA 0.5 V
VOL
P00–P07, P10–P17 IOL = 1.25 mA
1.0 V
VCC = 2.5 V
IOL = 10 mA 2.0 V
“L” output voltage
VOL P20–P27, P41–P47 , P50–P57, P60 –P67, IOL = 2.5 mA 0.5 V
P70, P71 (Note) IOL = 2.5 mA 1.0 V
VCC = 2.5 V
VT+ – VT– Hysteresis
INT0–INT 3, ADT, CNTR0, CNTR1, P20 –P27 0.5 V
VT+ – VT– Hysteresis SCLK, RXD 0.5 V

VT+ – VT– Hysteresis RESET RESET : VCC = 2.5 V to 5.5 V 0.5 V
I IH “H” input current VI = VCC
5.0 µA
P00–P07, P10–P17 , P34–P37 Pull-downs “off”
VCC = 5 V, V I = VCC
30 70 140 µA
Pull-downs “on”
6.0 25 45 µA
Pull-downs “on”
P20–P27, P40–P47 , P50–P57, P60 –P67, 5.0 µA
P70, P71 (Note)
I IH “H” input current RESET VI = VCC 5.0 µA

I IH “H” input current XIN VI = VCC 4.0 µA
I IL “L” input current VI = VSS
–5.0 µA
P00–P07, P10 –P17 , P34–P37,P4 0
IIL “L” input current VI = VSS –5.0 µA
P20–P27, P41–P47 , P50–P57, P60 –P67, Pull-ups “off”
P70, P71 (Note) VCC = 5 V, VI = VSS
–30 –70 –140 µA
Pull-ups “on”
VCC = 3 V, VI = VSS
–6.0 –25 –45 µA
Pull-ups “on”
I IL “L” input current RESET VI = VSS –5.0 µA
I IL “L” input current XIN VI = VSS –4.0 µA
Note: When “1” is set to port X C switch bit (bit 4 at address 003B16) of the CPU mode register, the drive ability of port P70 is different from the value above
mentioned.
50
3822 Group
Table 19 Electrical characteristics (Standard, One Time PROM version)

Limits
Min. Typ. Max.
VRAM RAM retention voltage At clock stop mode 2.0 5.5 V
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz 6.4 13 mA
Output transistors “off”
A-D converter in operating
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz 1.6 3.2 mA
A-D converter stopped
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped 25 36 µA
f(XCIN) = 32.768 kHz
I CC Power source current • Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped 7.0 14 µA
f(XCIN) = 32.768 kHz (in WIT state)
f(XIN) = stopped µA
15 22
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped 4.5 9.0 µA
All oscillation stopped Ta = 25 °C 0.1 1.0
(in STP state) µA
Output transistors “off” Ta = 85 °C 10
Table 20 A-D converter characteristics (Standard, One Time PROM version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, 4 MHz ≤ f(XIN ) ≤ 8 MHz, middle-/high-speed mode, unless otherwise noted)
Limits
Min. Typ. Max.
– Resolution 8 Bits
Absolute accuracy VCC = VREF = 5V ±2 LSB
– (excluding quantization error)
f(XIN) = 8 MHz 12.5
t CONV Conversion time µs
(Note)
RLADDER Ladder resistor 12 35 100 kΩ
I VREF Reference power source input current VREF = 5 V 50 150 200 µA
IIA Analog port input current 5.0 µA
Note: When an internal trigger is used in middle-speed mode, it is 14 µs.
51
3822 Group
Table 21 Timing requirements 1 (Standard, One Time PROM version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Min. Typ. Max.
t w(RESET) Reset input “L” pulse width 2 µs
t c(X IN) Main clock input cycle time (XIN input) 125 ns
t wH(XIN) Main clock input “H” pulse width 45 ns
t wL(XIN) Main clock input “L” pulse width 40 ns
t c(CNTR) CNTR0, CNTR1 input cycle time 250 ns
t wH(CNTR) CNTR0, CNTR1 input “H” pulse width 105 ns
t wL(CNTR) CNTR0, CNTR1 input “L” pulse width 105 ns
t wH(INT) INT0 to INT3 input “H” pulse width 80 ns
t wL(INT) INT0 to INT3 input “L” pulse width 80 ns
t c(S CLK) Serial I/O clock input cycle time (Note) 800 ns
t wH(SCLK) Serial I/O clock input “H” pulse width (Note) 370 ns
t wL(S CLK) Serial I/O clock input “L” pulse width (Note) 370 ns
t su(RXD–SCLK) Serial I/O input set up time 220 ns
t h(SCLK–R XD) Serial I/O input hold time 100 ns
Note: When bit 6 of address 001A 16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A 16 is “0” (UART).
Table 22 Timing requirements 2 (Standard, One Time PROM version)

Limits
Min. Typ. Max.
t c(XIN) Main clock input cycle time (XIN input) 125 ns
t c(CNTR) CNTR0, CNTR1 input cycle time 500/(VCC-2) ns
t wH(CNTR) CNTR0, CNTR1 input “H” pulse width 250/(VCC-2)-20 ns
t wL(CNTR) CNTR0, CNTR1 input “L” pulse width 250/(VCC-2)-20 ns
t c(SCLK) Serial I/O clock input cycle time (Note) 2000 ns
t wL(SCLK) Serial I/O clock input “L” pulse width (Note) 950 ns
tsu(RXD–SCLK) Serial I/O input set up time 400 ns
t h(SCLK–RX D) Serial I/O input hold time 200 ns
52
3822 Group
Table 23 Switching characteristics 1 (Standard, One Time PROM version)

Limits
Min. Typ. Max.
t wH(SCLK) Serial I/O clock output “H” pulse width t C (SCLK )/2–30 ns
t wL(S CLK) Serial I/O clock output “L” pulse width t C (SCLK )/2–30 ns
t d(SCLK–TX D) Serial I/O output delay time (Note 1) 140 ns
t v(S CLK–TXD) Serial I/O output valid time (Note 1) –30 ns
t r(SCLK) Serial I/O clock output rising time 30 ns
t f(SCLK) Serial I/O clock output falling time 30 ns
t r(CMOS) CMOS output rising time (Note 2) 10 30 ns
t f(CMOS) CMOS output falling time (Note 2) 10 30 ns
Notes 1: When the P45 /TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: X OUT and XCOUT pins are excluded.
Table 24 Switching characteristics 2 (Standard, One Time PROM version)

Limits
Min. Typ. Max.
t wH(SCLK) Serial I/O clock output “H” pulse width t C (SCLK)/2–50 ns
twL(S CLK) Serial I/O clock output “L” pulse width t C (SCLK)/2–50 ns
Notes 1: When the P45 /TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
53
3822 Group
Table 25 Absolute maximum ratings (Extended operating temperature version)

VCC Power source voltage All voltages are based on VSS. –0.3 to 6.5 V
VI Input voltage P00–P07, P10–P17 , P20–P27, Output transistors are cut off.
–0.3 to VCC +0.3 V
P34–P37, P40–P47 , P50–P57
P60–P67, P70, P7 1
VI Input voltage RESET, XIN –0.3 to V CC +0.3 V
VO Output voltage P0 0–P07, P10–P17 At output port –0.3 to V CC +0.3 V
At segment output –0.3 to VL3 V
VO Output voltage P3 4–P37 At segment output –0.3 to VL3 V
VO Output voltage P20–P27, P41–P47 ,P50–P57 , –0.3 to VCC +0.3 V
P60–P67, P70, P7 1
VO Output voltage SEG0–SEG 11 –0.3 to VL3 V
VO Output voltage XOUT –0.3 to V CC +0.3 V
Table 26 Recommended operating conditions (Extended operating temperature version)

(VCC = 2.0 to 5.5 V, Ta = –20 to 85 °C, and V CC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted)
Limits
Min. Typ. Max.
High-speed mode f(X IN) = 8 MHz 4.0 5.0 5.5
Middle-speed mode Ta = –20 to 85°C 2.0 5.0 5.5
VCC Power source voltage f(XIN) = 8 MHz Ta = –40 to –20°C 3.0 5.0 5.5 V
Low-speed mode Ta = –20 to 85°C 2.0 5.0 5.5
Ta = –40 to –20°C 3.0 5.0 5.5
VIA Analog input voltage AN 0–AN 7 AVSS VCC V
VIH “H” input voltage P00 –P07, P10–P17,P3 4–P37, P4 0, P41, P45 , P47, P52, P5 3, 0.7VCC VCC V
P56,P60–P67,P70 ,P71 (CM 4 = 0)
VIH “H” input voltage P20 –P27, P42–P44,P4 6,P5 0, P51, P5 4, P55, P57 0.8VCC VCC V
VIL “L” input voltage P00 –P07, P10–P17,P3 4–P37, P4 0, P41, P45 , P47, P52, P5 3, 0 0.3 VCC V
P56,P60–P67,P70 ,P71 (CM 4 = 0)
VIL “L” input voltage P20 –P27, P42–P44,P4 6,P5 0, P51, P5 4, P55, P57 0 0.2 VCC V
54
3822 Group
Table 27 Recommended operating conditions (Extended operating temperature version)

(VCC = 2.0 to 5.5 V, Ta = –20 to 85 °C, and V CC = 3.0 to 5.5 V, Ta = –40 to –20° C, unless otherwise noted)
Limits
Min. Typ. Max.
(Note 2)
(Note 2)
(Note 3)
(Note 3)
f(CNTR 1) (duty cycle 50%) (2.0 V ≤ VCC ≤ 4.0 V) VCC MHz
High-speed mode
8.0 MHz
(4.0 V ≤ VCC ≤ 5.5 V)
(Note 4) 2✕VCC MHz
(2.0 V ≤ VCC ≤ 4.0 V)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value mesured
over 100 ms. The total peak current is the peak value of all the currents.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(X CIN) < f(XIN )/3.
55
3822 Group
Table 28 Electrical characteristics (Extended operating temperature version)

(VCC =2.0 to 5.5 V, Ta = –20 to 85 °C, and V CC = 3.0 to 5.5 V, Ta = –40 to –20 °C, unless otherwise noted)
Limits
Min. Typ. Max.
I OH = –2.5 mA VCC–2.0 V
VOH I OH = –0.6 mA
P00–P07 , P10–P17 VCC–0.9 V
VCC = 3.0 V
I OH = –5 mA VCC–2.0 V
VOH I OH = –1.25 mA VCC–0.5 V
P20–P27 , P41–P47, P50 –P57, P60–P67 ,
P70, P7 1 (Note) I OH = –1.25 mA VCC–0.9 V
VCC = 3.0 V
I OL = 5 mA 2.0 V
VOL “L” output voltage I OL = 1.25 mA 0.5 V
P00–P07 , P10–P17 I OL = 1.25 mA
1.1 V
VCC = 3.0 V
I OL = 10 mA 2.0 V
VOL P20–P27 , P41–P47, P50 –P57, P60–P67 , I OL = 2.5 mA 0.5 V
P70, P7 1 (Note) I OL = 2.5 mA 1.1 V
VCC = 3.0 V
VT+ – V T– Hysteresis
INT 0–INT3, ADT, CNTR0, CNTR1, P2 0–P27 0.5 V
VT+ – V T– Hysteresis SCLK , RXD 0.5 V

VT+ – V T– Hysteresis RESET RESET : VCC = 2.0 V to 5.5 V 0.5 V
5.0 µA
P00–P07 , P10–P17, P34 –P37 Pull-downs “off”
VCC = 5 V, V I = V CC
30 70 170 µA
Pull-downs “on”
VCC = 3 V, V I = V CC
6.0 25 55 µA
Pull-downs “on”
P20–P27 , P40–P47, P50 –P57, P60–P67 , 5.0 µA
P70, P7 1 (Note)

IIL “L” input current VI = VSS
–5.0 µA
P00 –P07 , P10–P17, P34 –P37,P40
I IL “L” input current VI = VSS –5.0 µA
P20–P27 , P41–P47, P50 –P57, P60–P67 , Pull-ups “off”
P70, P7 1 (Note) VCC = 5 V, VI = V SS
–30 –70 –140 µA
Pull-ups “on”
VCC = 3 V, VI = V SS
–6.0 –25 –45 µA
Pull-ups “on”
Note: When “1” is set to port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above men-
tioned.
56
3822 Group
Table 29 Electrical characteristics (Extended operating temperature version)

(VCC =2.0 to 5.5 V, Ta = –20 to 85 °C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20 °C, unless otherwise noted)
Limits
Min. Typ. Max.
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz 6.4 13 mA
f(XCIN) = 32.768 kHz 1.6 3.2 mA
(in STP state) µA
Table 30 A-D converter characteristics (Extended operating temperature version)

(VCC = 3.0 to 5.5 V, VSS =AVSS = 0 V, Ta = –40 to 85 °C, 4 MHz ≤ f(X IN) ≤ 8 MHz, in middle/high-speed mode unless otherwise noted)
Limits
Min. Typ. Max.
Absolute accuracy VCC = VREF = 4.0V to 5.5V ±2 LSB
– (excluding quantization error) f(XIN) = 8 MHz
VCC = VREF = 3.0 V to 4.0V
f(XIN) = 2 ✕ VCC MHz
12.5
t CONV Conversion time f(XIN) = 8 MHz µs
(Note)
57
3822 Group
Table 31 Timing requirements 1 (Extended operating temperature version)

Limits
Min. Typ. Max.
Table 32 Timing requirements 2 (Extended operating temperature version)

(VCC = 2.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and V CC = 3.0 to 4.0 V, Ta = –40 to –20 °C, unless otherwise noted)
Limits
Min. Typ. Max.
t c(CNTR) CNTR0, CNTR1 input cycle time 900/(VCC–0.4) ns
t wH(CNTR) CNTR0, CNTR1 input “H” pulse width 450/(VCC–0.4)–20 ns
t wL(CNTR) CNTR0, CNTR1 input “L” pulse width 450/(VCC–0.4)–20 ns
58
3822 Group
Table 33 Switching characteristics 1 (Extended operating temperature version)

Limits
Min. Typ. Max.
Notes 1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Table 34 Switching characteristics 2 (Extended operating temperature version)

(VCC = 2.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and V CC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20 °C, unless otherwise noted)
Limits
Min. Typ. Max.
59
3822 Group
Table 35 Absolute maximum ratings (M version)

VCC Power source voltage All voltages are based on V SS. –0.3 to 7.0 V
VI Input voltage P00–P07 , P10–P17, P20 –P27, Output transistors are cut off.
–0.3 to V CC +0.3 V
P34–P37 , P40–P47, P50 –P57
P60–P67 , P70, P71
VI Input voltage RESET, XIN –0.3 to VCC +0.3 V
VO Output voltage P00–P07 , P10–P17 At output port –0.3 to VCC +0.3 V
At segment output –0.3 to V L3 +0.3 V
VO Output voltage P34–P37 At segment output –0.3 to V L3 +0.3 V
VO Output voltage P20–P27 , P41–P47,P5 0–P57, –0.3 to V CC +0.3 V
P60–P67 , P70, P71
VO Output voltage SEG0–SEG11 –0.3 to V L3 +0.3 V
VO Output voltage XOUT –0.3 to VCC +0.3 V
Table 36 Recommended operating conditions (M version)

Limits
Min. Typ. Max.
60
3822 Group

Limits
Min. Typ. Max.
VIH “H” input voltage P00 –P07, P10–P17 ,P34–P37 , P40, P41, P4 5, P47, 0.7VCC VCC V
P52 , P53,P56,P60–P67,P70,P7 1 (CM4= 0)
VIH “H” input voltage P20–P27 , P42–P44,P4 6,P5 0, P51, P54 , P55, P57 0.8VCC VCC V
VIL “L” input voltage P00–P07 , P10–P17,P3 4–P37, P40 , P41, P45 , P47, P52, P53, 0 0.3 VCC V
P56,P60–P67,P70,P7 1 (CM4 = 0)
VIL “L” input voltage P20–P27 , P42–P44,P4 6,P5 0, P51, P54 , P55, P57 0 0.2 VCC V

Limits
Min. Typ. Max.
VIH “H” input voltage P00 –P07, P10–P17 ,P34–P37 , P40, P41, P4 5, P47, 0.8VCC VCC V
P52 , P53,P56,P60–P67,P70,P7 1 (CM4= 0)
VIH “H” input voltage P20–P27 , P42–P44,P4 6,P5 0, P51, P54 , P55, P57 0.95VCC VCC V
VIL “L” input voltage P00–P07 , P10–P17,P3 4–P37, P40 , P41, P45 , P47, P52, P53, 0 0.2 VCC V
P56,P60–P67,P70,P7 1 (CM4 = 0)
VIL “L” input voltage P20–P27 , P42–P44,P4 6,P5 0, P51, P54 , P55, P57 0 0.05 VCC V
61
3822 Group

Limits
Min. Typ. Max.
(Note 2)
(Note 2)
(Note 3)
(Note 3)
f(CNTR 1) (duty cycle 50%) (2.2 V ≤ VCC ≤ 4.0 V) (10✕VCC-4)/9 MHz
High-speed mode
8.0 MHz
(4.0 V ≤ VCC ≤ 5.5 V)
(Note 4) (20✕VCC-8)/9 MHz
(2.2 V ≤ VCC ≤ 4.0 V)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value
measured over 100 ms. The total peak current is the peak value of all the currents.
4: When the oscillation frequency has a duty cycle of 50%.
62
3822 Group
Table 40 Electrical characteristics (M version)

Limits
Min. Typ. Max.
IOH = –2.5 mA VCC–2.0 V
VOH IOH = –0.6 mA
P00–P07, P10–P17 VCC–1.0 V
VCC = 2.5 V
P20–P27, P41–P47 , P50–P57, P60 –P67,
VCC = 2.5 V
IOL = 5 mA 2.0 V
“L” output voltage IOL = 1.25 mA 0.5 V
VOL
P00–P07, P10 –P7 IOL = 1.25 mA
1.0 V
VCC = 2.5 V
IOL = 10 mA 2.0 V
P70, P71 (Note) IOL = 2.5 mA 1.0 V
VCC = 2.5 V

5.0 µA
30 70 140 µA
Pull-downs “on”
6.0 25 45 µA
Pull-downs “on”
P20–P27, P40–P47 , P50–P57, P60 –P67, 5.0 µA
P70, P71 (Note)

–5.0 µA
P00–P07, P10 –P17 , P34–P37,P4 0
–30 –70 –140 µA
Pull-ups “on”
VCC = 3 V, VI = VSS
–6.0 –25 –45 µA
Pull-ups “on”
Note: When “1” is set to the port X C switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P7 0 is different from the value above
mentioned.
63
3822 Group
Table 41 Electrical characteristics (M version)

Limits
Min. Typ. Max.
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz 6.4 13 mA
f(XCIN) = 32.768 kHz 1.6 3.2 mA
15 22
(in STP state) µA
Table 42 A-D converter characteristics (M version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, 4 MHz ≤ f(X IN) ≤ 8 MHz, in middle/high-speed mode, unless otherwise noted)
Limits
Min. Typ. Max.
Absolute accuracy VCC = VREF = 5V ±2 LSB
– (excluding quantization error)
t CONV Conversion time f(XIN) = 8 MHz 12.5 µs
(Note)
64
3822 Group
Table 43 Timing requirements 1 (M version)

Limits
Min. Typ. Max.
Table 44 Timing requirements 2 (M version)

Limits
Min. Typ. Max.
65
3822 Group
Table 45 Switching characteristics 1 (M version)

Limits
Min. Typ. Max.
Table 46 Switching characteristics 2 (M version)

Limits
Min. Typ. Max.
66
3822 Group
Table 47 Absolute maximum ratings (H version)

VCC Power source voltage All voltages are based on V SS. –0.3 to 6.5 V
VI Input voltage P00–P07 , P10–P17, P20 –P27, Output transistors are cut off.
–0.3 to V CC +0.3 V
P34–P37 , P40–P47, P50 –P57
P60–P67 , P70, P71

VI Input voltage RESET, XIN –0.3 to VCC +0.3 V
VO Output voltage P00–P07 , P10–P17 At output port –0.3 to VCC +0.3 V
At segment output –0.3 to VL3 V
VO Output voltage P34–P37 At segment output –0.3 to VL3 V
VO Output voltage P20–P27 , P41–P47,P5 0–P57, –0.3 to V CC +0.3 V
P60–P67 , P70, P71
VO Output voltage SEG0–SEG11 –0.3 to V L3 V
VO Output voltage XOUT –0.3 to VCC +0.3 V
Table 48 Recommended operating conditions (H version)

Limits
Min. Typ. Max.
VIH “H” input voltage P00 –P07 , P10–P17,P3 4–P37, P4 0, P41, P45 , P47, P52, P5 3, 0.7VCC VCC V
P56,P60–P67,P70,P7 1 (CM 4= 0)
VIH “H” input voltage P20 –P27 , P42–P44,P4 6,P5 0, P51, P5 4, P55, P57 0.8VCC VCC V
VIL “L” input voltage P00 –P07 , P10–P17,P3 4–P37, P4 0, P41, P45 , P47, P52, P5 3, 0 0.3 VCC V
P56,P60–P67,P70,P7 1 (CM 4= 0)
VIL “L” input voltage P20 –P27 , P42–P44,P4 6,P5 0, P51, P5 4, P55, P57 0 0.2 VCC V
67
3822 Group
Table 49 Recommended operating conditions (H version)

(VCC = 2.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Min. Typ. Max.
(Note 2)
(Note 2)
(Note 3)
(Note 3)
f(CNTR 1) (duty cycle 50%) (2.0 V ≤ VCC ≤ 4.0 V) VCC MHz
High-speed mode
8.0 MHz
(4.0 V ≤ VCC ≤ 5.5 V)
(Note 4) 2✕VCC MHz
(2.0 V ≤ VCC ≤ 4.0 V)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value
measured over 100 ms. The total peak current is the peak value of all the currents.
68
3822 Group
Table 50 Electrical characteristics (H version)

Limits
Min. Typ. Max.
IOH = –2.5 mA VCC–2.0 V
VOH IOH = –0.6 mA
P00–P07, P10–P17 VCC–1.0 V
VCC = 2.5 V
P20–P27, P41–P47 , P50–P57, P60 –P67,
VCC = 2.5 V
IOL = 5 mA 2.0 V
VOL “L” output voltage IOL = 1.25 mA 0.5 V
P00–P07, P10 –P7 IOL = 1.25 mA
1.0 V
VCC = 2.5 V
IOL = 10 mA 2.0 V
P70, P71 (Note) IOL = 2.5 mA 1.0 V
VCC = 2.5 V

5.0 µA
30 70 140 µA
Pull-downs “on”
6.0 25 45 µA
Pull-downs “on”
P20–P27, P40–P47 , P50–P57, P60 –P67, 5.0 µA
P70, P71 (Note)

–5.0 µA
P00–P07, P10 –P17 , P34–P37,P4 0
–30 –70 –140 µA
Pull-ups “on”
VCC = 3 V, VI = VSS
–6.0 –25 –45 µA
Pull-ups “on”
I IL “L” input current RESET VI = VSS 5.0 µA
Note: When “1” is set to the port X C switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P7 0 is different from the value above
mentioned.
69
3822 Group
Table 51 Electrical characteristics (H version)

(VCC =2.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Min. Typ. Max.
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz 6.4 13 mA
f(XCIN) = 32.768 kHz 1.6 3.2 mA
15 22
(in STP state) µA
Table 52 A-D converter characteristics (H version)

(VCC = 2.2 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle/high-speed mode unless otherwise noted)
Limits
Min. Typ. Max.
Absolute accuracy VCC = VREF = 4.0 V to 5.5 V ±2 LSB
– (excluding quantization error) f(XIN) = 8 MHz
VCC = VREF = 2.2 V to 4.0V
f(XIN) = 2 ✕ VCC MHz
12.5
t CONV Conversion time f(XIN) = 8 MHz µs
(Note)
70
3822 Group
Table 53 Timing requirements 1 (H version)

Limits
Min. Typ. Max.
Table 54 Timing requirements 2 (H version)

Limits
Min. Typ. Max.
71
3822 Group
Table 55 Switching characteristics 1 (H version)

Limits
Min. Typ. Max.
Notes1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and X COUT pins are excluded.
Table 56 Switching characteristics 2 (H version)

Limits
Min. Typ. Max.
Notes1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and X COUT pins are excluded.
Measurement output pin
100 pF 1 kΩ
Measurement output pin
100 pF
CMOS output
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register

(address 001B16) is “1”. (N-channel open-
drain output mode)
Fig. 47 Circuit for measuring output switching characteristics
72
3822 Group
tC(CNTR)
tWH(CNTR) tWL(CNTR)
CNTR0, CNTR1
0.8VCC 0.2VCC
tWH(INT) tWL(INT)
INT0–INT3 0.8VCC 0.2VCC
tW(RESET)
RESET 0.8VCC
0.2VCC
tC(XIN)
tWH(XIN) tWL(XIN)
XIN 0.8VCC
0.2VCC
tC(SCLK)
tf tWL(SCLK) tr tWH(SCLK)
SCLK
0.2VCC 0.8VCC
tsu(RXD-SCLK) th(SCLK-RXD)
RX D 0.8VCC
0.2VCC
td(SCLK-TXD) tv(SCLK-TXD)
T XD
Fig. 48 Timing diagram
73
3822 Group
PACKAGE OUTLINE
80P6N-A MMP Plastic 80pin 14✕20mm body QFP
EIAJ Package Code JEDEC Code Weight(g) Lead Material
QFP80-P-1420-0.80 – 1.58 Alloy 42 MD
e
HD
D
ME
80 65
b2
1 64
I2
Recommended Mount Pad

Dimension in Millimeters
Symbol
HE
Min Nom Max

E
A – – 3.05
A1 0 0.1 0.2
A2 – 2.8 –
b 0.3 0.35 0.45
c 0.13 0.15 0.2
24 41 D 13.8 14.0 14.2
E 19.8 20.0 20.2
e – 0.8 –
25 40 A
HD 16.5 16.8 17.1
L1 HE 22.5 22.8 23.1
L 0.4 0.6 0.8
L1 – 1.4 –
A2
x – – 0.2
y – – 0.1
c
F 0° – 10°
e
A1
b x M L b2 – 0.5 –
y Detail F I2 1.3 – –
MD – 14.6 –
ME – 20.6 –
80P6S-A MMP Plastic 80pin 14✕14mm body QFP

EIAJ Package Code JEDEC Code Weight(g) Lead Material
QFP80-P-1414-0.65 1.11 Alloy 42 MD
e
HD
D
ME
80 61
b2
1 60
I2
Recommended Mount Pad

Symbol
Min Nom Max
HE
E
A – – 3.05
A1 0 0.1 0.2
A2 – 2.8 –
b 0.25 0.3 0.4
20 41
c 0.13 0.15 0.2
D 13.8 14.0 14.2
E 13.8 14.0 14.2
21 40 A e – 0.65 –
L1 HD 16.5 16.8 17.1
HE 16.5 16.8 17.1
L 0.4 0.6 0.8
L1 – 1.4 –
A2
F x – – 0.13
y – – 0.1
c
e b x M 0° – 10°
y b2 – 0.35 –
A1
L
Detail F I2 1.3 – –
MD – 14.6 –
ME – 14.6 –
74
3822 Group
80P6Q-A MMP Plastic 80pin 12✕12mm body LQFP

EIAJ Package Code JEDEC Code Weight(g) Lead Material MD
LQFP80-P-1212-0.5 – 0.47 Cu Alloy
e
HD
ME
D
b2
80 61
l2
1 60 Recommended Mount Pad
Symbol
Min Nom Max
A – – 1.7
HE
E
A1 0 0.1 0.2
A2 – 1.4 –
b 0.13 0.18 0.28
c 0.105 0.125 0.175
20 41
D 11.9 12.0 12.1
E 11.9 12.0 12.1
21 40 e – 0.5 –
HD 13.8 14.0 14.2
A
HE 13.8 14.0 14.2
L1 L 0.3 0.5 0.7
F L1 – 1.0 –
e
Lp 0.45 0.6 0.75
A3 – 0.25 –
A2
A3
x – – 0.08
y – – 0.1
b 0° – 10°
A1
x M y L
c
b2 – 0.225 –
Detail F Lp I2 0.9 – –
MD – 12.4 –
ME – 12.4 –
75
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
Keep safety first in your circuit designs!

• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
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Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
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• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2001 MITSUBISHI ELECTRIC CORP.

Specifications subject to change without notice.
REVISION HISTORY 3822 GROUP DATA SHEET
Rev. Date Description

Page Summary
1.0 01/20/98 First Edition
2.0 10/23/00 1 “●Memory size” of “FEATURES” is partly revised.
1 “●Serial I/O” of “FEATURES” is partly revised.
1 “●A-D converter” of “FEATURES” is added.
1 “●2 clock generating circuits” of “FEATURES” is partly revised.
1 “●Power source voltage” of “FEATURES” is partly revised.
1 “●Power dissipation” of “FEATURES” is partly added.
1 Product name into Figure 1 is revised.
2 Product name into Figure 2 is revised.
3 Figure 3 is partly revised.
4 “Function” of “Vcc, Vss” into Table 1 is partly revised.
5 “Function except a port function” into Table 2 is partly revised.
7 Explanations of “GROUP EXPANSION (STANDARD, ONE TIME PROM VER-
SION, EPROM VERSION)” are partly revised.
7 Table 3 is partly revised.
8 Explanations of “GROUP EXPANSION (EXTENDED OPERATING TEMPERA-
TURE VERSION)” are partly revised.
9 “GROUP EXPANSION (M VERSION)” is added.
9 Figure 7 is added.
9 Table 5 is added.
10 “GROUP EXPANSION (H VERSION)” is added.
10 Table 6 is added.
11–13 Explanations of “CENTRAL PROCESSING UNIT (CPU)” are added.
22 Explanations of “Interrupt Control” is partly added.
22 Explanations of “Interrupt Operation” is partly revised.
22 Explanations of “■Notes” are partly revised.
24 Explanations of “Key Input Interrupt (Key-on wake up)” are partly revised.
26 Explanations of “●Timer X write control” are partly revised.
26 Explanations of “●Real time port control” are partly revised.
33 Explanations of “[Channel Selector]” are partly added.
33 Explanations of “[Comparator and Control Circuit]” are partly added.
(1/2)
REVISION HISTORY 3822 GROUP DATA SHEET
Rev. Date Description

Page Summary
2.0 10/23/00 35 Figure 33 is partly revised.
40 Explanations of “φ CLOCK SYSTEM OUTPUT FUNCTION” are partly revised.
41 Explanations of “RESET CIRCUIT” are partly revised.
43 Explanations of “CLOCK GENERATING CIRCUIT” are partly eliminated.
46 Explanations of “Decimal Calculations” are partly eliminated.
47 Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly added.
50 Test conditions of IIL of P0 0–P07, P10–P17, P34–P37, P40 is added.
52 Limit of tC(CNTR) into Table 21 is revised.
52 Limit of tWH(CNTR) into Table 21 is revised.
52 Limit of tWL(CNTR) into Table 21 is revised.
52 Limit of tC(CNTR) into Table 22 is revised.
52 Limit of tWH(CNTR) into Table 22 is revised.
52 Limit of tWL(CNTR) into Table 22 is revised.
54–72 Tables 25 to 56 are added.
74, 75 “PACKAGE OUTLINE” is added.
2.1 01/31/01 13 Explanations of “•Bit 3: Decimal mode flag (D)” are partly added.
22 Explanations of “■Notes on interrupts” are revised.
31 “■Notes on serial I/O” is added.
47 Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly revised.
(2/2)

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MITSUBISHI MICROCOMPUTERS

DESCRIPTION ●2 clock generating circuits

PIN CONFIGURATION (TOP VIEW)

Package type : 80P6N-A (80-pin plastic-molded QFP)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PIN CONFIGURATION (TOP VIEW)

Package type : 80P6S-A/80P6Q-A

Fig. 2 M38223M4MXXXGP/M38224M6HXXXHP pin configuration

Main Clock Main Clock Reset Input (5V) (0V)

Fig. 3 Functional block diagram

P5(8) P4(8) P2(8) P1(8) P0(8)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Pin Name Function

•CMOS 3-state output structure.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 2 Pin description (2)

Pin Name Function

P56/T OUT •Timer 2 output pins

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Product M3822 4 M 6 H XXX FP

Normally, using hyphen.

Fig. 4 Part numbering

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION (STANDARD, ONE TIME Memory Size

Memory Expansion Plan

192 256 384 512 640 768 896 1024

RAM size (bytes)

Fig. 5 Memory expansion plan

Currently products are listed below.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION Package

Memory Expansion Plan

ROM size (bytes)

192 256 384 512 640 768 896 1024

RAM size (bytes)

Fig. 6 Memory expansion plan for extended operating temperature version

Currently products are listed below.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION (M VERSION) Package

Memory Expansion Plan

ROM size (bytes)

192 256 384 512 640 768 896 1024

RAM size (bytes)

Fig. 7 Memory expansion plan for M version

Currently products are listed below.

Table 5 List of products for M version As of August 2000

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION (H VERSION) Package

Memory Expansion Plan

ROM size (bytes)

192 256 384 512 640 768 896 1024

RAM size (bytes)

Fig. 8 Memory expansion plan for H version

Currently products are listed below.

Table 6 List of products for H version As of August 2000

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION [Stack Pointer (S)]

Fig.9 740 Family CPU register structure

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Execute JSR (S) (S) – 1

Note: Condition for acceptance of an interrupt Interrupt enable flag is “1”

Table 7 Push and pop instructions of accumulator or processor status register