energies

Article
Analysis of Power Loss and Improved Simulation
Method of a High Frequency Dual-Buck
Full-Bridge Inverter
Zhun Meng, Yifeng Wang *, Liang Yang and Wei Li
School of Electrical Engineering and Automation, Tianjin University, Tianjin 300072, China;
quakermaster@hotmail.com (Z.M.); zyangliang@tju.edu.cn (L.Y.); liweitju@hotmail.com (W.L.)
* Correspondence: wayif@tju.edu.cn; Tel.: +86-132-0769-7161; Fax: +86-022-2740-1479

Academic Editor: Gabriele Grandi

Received: 24 January 2017; Accepted: 2 March 2017; Published: 6 March 2017

Abstract: A high frequency dual-buck full-bridge inverter for small power renewable energy
application is proposed in this paper. A switching frequency of 400 kHz is achieved with the
adoption of the SiC power device. A two-pole two-zero (2P2Z) compensator is employed in the
outer voltage loop to generate the current reference for inner current loop. A 3P3Z compensator is
adopted in the inner current loop to track the current reference. A systematic way for calculating
the losses of high frequency inverter is presented, and the losses of the components are thoroughly
analyzed. The turn-on and turn-off procedures of the inverter are discussed in detail. The losses
caused by high frequency are calculated accurately, and the loss distribution is established as well.
The procedure of the loss analysis gives a practical example for calculating the loss of similar type
inverters. Moreover, deviation between pulse width modulation (PWM) control signal and switching
response in high frequency switching is thoroughly analyzed. The influence of deviation is verified by
designed experiment. Hence, a compensation method is proposed in order to minimize the influence.
The compensation effect is validated by experiment and simulation. Finally, a 1-kW prototype is
built to verify the feasibility of the theoretical analyses. The grid-connected maximum output power
experiment is completed at 1 kW with the efficiency of 96.1% and the total harmonic distortion (THD)
of 1.8%. The comparison experiments of power loss between Si and SiC power devices are carried
out. The experiment results confirm the loss calculation method to be valid.

Keywords: SiC power device; grid-connected generation; dual-buck inverter; high frequency
conversion; loss analysis; simulation

1. Introduction
In order to make the social development less fossil fuel-dependent and more environment-friendly,
renewable energy becomes an important alternative energy source [1,2]. With the development of
distributed renewable energy generation, small-scale inverter becomes a focus of research. Being able to
convert all kinds of distributed energy into a unified AC power, the grid-connected inverter extensively
broadens the application range of renewable energies, and thus acts as an indispensable role in the
renewable energy generation system [3,4].
For the rapid development of the new power devices, the wide band gap power devices, such as
SiC and GaN, begin to replace the traditional Si power devices. Its outstanding performance, including
high switching speed, low switching loss, high stability in high temperature operating and so on,
makes the high frequency inverter a new research hot spot. A three-level SiC inverter is proposed
in [5]. By employing the SiC MOSFET and FPGA control platform, a 100 kHz switching frequency is
achieved. GaN high-electron mobility transistors (HEMT) power devices are adopted in a single-phase

Energies 2017, 10, 311; doi:10.3390/en10030311 www.mdpi.com/journal/energies

Energies 2017, 10, 311 2 of 18

T-Type inverter in [6]. Switching performance and efficiency performance are analyzed among Si, SiC
and GaN HEMT. The results demonstrate the advantage of the wide band gap power devices in high
frequency inverting. It can be seen that all these inverters adopt the wide band gap power devices and
have a working frequency, which is much higher than the traditional ones. As a result, the THD of the
inverters is significantly reduced and the output power quality is improved obviously. Meanwhile,
smaller components can be used and the volume of the inverter is significantly decreased, which
broaden the application range of the inverter. On the other hand, as frequency increases, the losses of
the inverter under high frequency circumstances become a major problem, which is not discussed in
detail in this paper.
With the application of high frequency switching, loss analysis is even more important, because
it can offer a guideline for the system efficiency improvement [7–14]. In [7], a detailed investigation
into loss distribution for diverse components is conducted, which includes losses of switches, diodes,
inductors and capacitors. In [8,9], the switch and diode losses of several inverter topologies are
studied and compared, which gives an evident insight into the loss distribution for each low-frequency
topology. Nevertheless, this comparison may show less accuracy when it comes to high frequency
case, because more details of the switching procedure must be taken into account in the high frequency
operation, which will affect the losses and are not included in this literature. In [10], the mechanism
reflecting the relation between transition characteristics and power losses is discussed. Diode losses
based on traditional Si semi-conductor are analyzed as well. In [11], comparative experiments of
losses between Si and SiC power devices are carried out, which proves that the SiC devices are
superior in switching speed, operating temperature and switching losses than the traditional Si.
Although the loss analyses previously mentioned are very comprehensive and detailed, all these
works are also based on traditional low frequency simplified method, which show less accuracy for
the high frequency loss analysis. This is because some losses, overlooked in low frequency condition,
may become an indispensable part of the total losses in high frequency implementation. Hence,
deviations will be introduced if low frequency loss calculation method is implanted directly into the
high frequency operation.
Moreover, the influence of the high frequency switching is not confined to losses analysis.
The impact of high frequency on the simulation model is also noteworthy. Model of the wide band
gap power devices are established in [15–19]. A compact model of the SiC metal-oxide-semiconductor
field-effect transistor (MOSFET) is built including the carrier-trap influences in [15], the simulation
results is verified by the experiments. Jun Wang et al. [16] discusses a 10-kV 4H-SiC MOSFET and key
characteristics are extensively investigated. A simple behavioral SPICE model for the SiC MOSFETs is
proposed to predict their realistic application prospect. The impact of nonlinear junction capacitance
on switching transient is studied in [17], and a simulation circuit for switching transient analysis is
built. A dynamic model of GaN cascaded current aperture vertical electron transistor (CAVET) is
established in ATLAS-SPICE-integrated simulator. The simulation model successfully models and
projects the switching performance of the GaN CAVET. These simulation models are very thorough.
However, most of the researches concentrate on the component level influence. The impact of high
frequency switching on the output of the converter is not detailed discussed. On the other hand, the
component level model is too complicated and time-consuming for converter analysis. The influence
of high frequency switching on the inverter simulation model is rarely studied.
In this paper, a high frequency single phase dual-buck full-bridge grid-connect inverter for small
power renewable energy is proposed. The SiC components, as the power devices, are employed to
achieve high switching frequency and to limit the conversion loss simultaneously. For the controller,
the proposed inverter adopts a current voltage dual-loop. The 3P3Z compensator is adopted in the
inner current loop in order to track the current reference which is generated by the 2P2Z compensator.
The 2P2Z compensator is employed in the outer voltage loop in order to regulate the DC bus voltage
by balancing the input and output power. A systematic way for calculating the losses of high switching
frequency inverter is presented. The losses of each component in the inverter are thoroughly analyzed.
Energies 2017, 10, 311 3 of 18

The switching procedure and the corresponding losses are discussed in detail. The high frequency
losses are also taken into account during the analysis. The distribution of the losses is established
based on the presented method. Moreover, the deviation between PWM control signal and switching
Energies 2017, 10, 311 3 of 18
response, which emerges in high frequency switching, is thoroughly analyzed. A designed experiment
verifies the
Theinfluence
high frequencyof deviation.
losses are Thus, a compensation
also taken method
into account during is proposed
the analysis. in order to
The distribution minimize the
of the
losses is established based on the presented method. Moreover, the deviation between
influence of deviation. Experiment and simulation confirm the compensation effect. Finally, a 1-kW PWM control
prototypesignal
is made and switching response, which emerges in high frequency switching, is thoroughly analyzed.
and a 400 kHz switching frequency is achieved. The comparison experiments of the
A designed experiment verifies the influence of deviation. Thus, a compensation method is proposed
power losses are carried
in order to minimizeout between Si and
the influence of SiC powerExperiment
deviation. devices toand verify the lossconfirm
simulation calculation
the method.
The results proved theeffect.
compensation loss Finally,
analysis is valid.
a 1-kW prototype is made and a 400 kHz switching frequency is
achieved. The comparison experiments of the power losses are carried out between Si and SiC power
2. Circuitdevices
Configuration
to verify theand
loss Control
calculationMethod
method. The results proved the loss analysis is valid.

2. Circuit
2.1. Operation Configuration and Control Method
Principles
2.1. Operation
The topology ofPrinciples
the dual-buck full-bridge inverter is presented in Figure 1a. The inverter can be
regarded as two individual
The topology of thebuck converters.
dual-buck full-bridgeBuck 1 consists
inverter is presentedof inS1Figure
, S3 , D
1a. Li1 , connecting
andinverter
1 The can be to the
regarded as Buck
DC bus positively. two individual buckofconverters.
2 consists S2 , S4 , DBuck 1 consists
and L , of S1, S3, D1 and
connecting to Li1, connecting
the bus to the DCThe output
negatively.
2 i2
bus positively. Buck 2 consists of S2, S4, D2 and Li2, connecting to the bus negatively. The output
inductorsinductors
of the buck converters Li1 and Li2 constitute a LCL filter with Cf , L
of the buck converters Li1 and Li2 constitute a LCL filter with Cf, Lg1 and g1. and Lg2 .
Lg2

(a) (b)
Figure 1. The topology and key waveforms of the proposed inverter: (a) the topology of the inverter;
The(b)
Figure 1. and topology and keyofwaveforms
the key waveforms the inverter. of the proposed inverter: (a) the topology of the inverter;
and (b) the key waveforms of the inverter.
To drive the inverter, the unipolar modulation has been adopted and the waveforms of the
driving signal are shown in Figure 1b. In one AC cycle, both bucks work in their own half cycles
To drive the inverter,
separately. When Buck the unipolar
1 works, Smodulation has been adopted and the waveforms of the driving
3 keeps turn-on in the half AC cycle and S1 switches at high

signal arefrequency
shown in Figure
to follow 1b. In one
a sinusoidal AC cycle,
reference both
in order bucks the
to generate work in their
positive half ofown halfcurrent
the grid cyclesig. separately.
When Buck D1 offers the free-wheeling
1 works, S3 keeps path when in
turn-on S1 turns off. Unlike
the half the H-bridge
AC cycle and Sinverter,
1 switchesno switches
at high arefrequency
at to
the same leg. Accordingly, the dead time is no longer needed. Moreover, the free-wheeling current is
follow a sinusoidal reference in order to generate the positive half of the grid current ig . D1 offers
running through D1 instead of the body diode. Because the independent diodes have a better
the free-wheeling
performance,path
the when S1 turns
total losses of the off. Unlike
inverter thereduced.
can be H-bridge inverter,principle
The operation no switches
of Buckare
2 isat the same
leg. Accordingly, the dead
similar to Buck timenotisbe
1 and will nodiscussed
longer further.
needed. Moreover, the free-wheeling current is running
through D1 instead of the body diode. Because the independent diodes have a better performance, the
2.2. Control Theory
total losses of the inverter can be reduced. The operation principle of Buck 2 is similar to Buck 1 and
The control
will not be discussed system structure of the inverter is shown in Figure 2. For the renewable energy
further.
distributed generation application, two-stage system structure is often adopted. The gird-connected
inverter as the post-stage is responsible for transferring the energy into power grid. The inverter can
2.2. Control Theory
stabilize the DC bus voltage by balancing the input and output power. A voltage-current dual loop
The is employed
control to fulfillstructure
system the function ofwhich is mentioned
the inverter is above.
shown in Figure 2. For the renewable energy
A notch filter is used to filter out the ripple in the bus voltage Vbus. By comparing with the bus voltage
distributed generation application, two-stage system structure is often adopted. The gird-connected
reference Vbus_ref, the bus voltage error is acquired and compensated by a 2P2Z compensator. Then, the
inverter as the post-stage
current is responsible
reference amplitude for by
iref is generated transferring the energy
the 2P2Z compensator. The into powersignal
grid voltage grid. The inverter can
is injected
stabilize the
intoDC bus voltage
a second-order by balancing
generalized integratorthe inputphase
software andlock
output power. A voltage-current
loop (SOGI-SPLL) to generate the phase dual loop is
employedreference which
to fulfill theisfunction
used to synchronize
which isirefmentioned
with the grid voltage.
above.The instantaneous current reference iref_inst
A notch filter is used to filter out the ripple in the bus voltage V bus . By comparing with
the bus voltage reference V bus_ref , the bus voltage error is acquired and compensated by a 2P2Z
compensator. Then, the current reference amplitude iref is generated by the 2P2Z compensator.
The grid voltage signal is injected into a second-order generalized integrator software phase lock loop
Energies 2017, 10, 311 4 of 18

(SOGI-SPLL) to generate the phase reference which is used to synchronize iref with the grid voltage.
Energies 2017, 10, 311 4 of 18
The instantaneous current reference iref_inst is compensated by a 3P3Z compensator. The result goes
throughisacompensated
feedback linearization module and
by a 3P3Z compensator. The becomes
result goesthe dutyacycle
through which
feedback is used module
linearization to generate
and PWM
signal tobecomes
controlthe thedutyinverter. The isdetail
cycle which ofgenerate
used to the control
PWMmethod
signal to is described
control in another
the inverter. article
The detail of theand will
control2017,
Energies
not be discussed method
10, 311is described in another article and will not be discussed further.
further. 4 of 18

is compensated by a 3P3Z compensator. The result goes through a feedback linearization module and
becomes the duty cycle which is used to generate PWM signal to control the inverter. The detail of the
control method is described in another article and will not be discussed further.

Figure
Figure 2. 2. Controlstructure
Control structure ofofthe
theinverter.
inverter.
3. Loss Analysis
3. Loss Analysis
The loss analysis is an essential way to improve the system efficiency. For low frequency
Theinverter,
loss analysis is an essential Figure
way 2. Control structure
theof the inverter.
the traditional calculation andto improve
approximation system
method areefficiency.
proven to For low frequency
be effective. However,inverter,
when
the traditional high speed switching is adopted, the losses, which are overlooked
calculation and approximation method are proven to be effective. However, when high in low frequency condition,
3. Loss Analysis
may become
speed switching an indispensable
is adopted, part ofwhich
the losses, the totalarelosses and causeinthe
overlooked inaccurate
low frequency of loss analysis. In
condition, thisbecome
may
The the
section, losslosses
analysis is an essential
of inverter way to improve
are systematically analyzed.the The
system efficiency.
switching For low
procedure, frequency
including the
an indispensable part of the total losses and cause the inaccurate of loss analysis. In this section, the
inverter, the traditional
miller effect, is discussedcalculation
in detail.and
Theapproximation
high frequencymethod loss is are proven to
thoroughly be effective.
analyzed, someHowever,
of which
losses of inverter
when
are nothigh
taken
are
speed systematically
intoswitching
analyzed.
is adopted,
consideration in low the
Thewhich
losses,
frequency
switching procedure,
are overlooked
applications. Moreover,
including
in the
low frequency
loss
the miller
condition,
distribution based
effect, is
discussed
may in detail.
become anThe high frequency
indispensable part of loss
the is
total thoroughly
losses and analyzed,
cause the some
inaccurate
on the new method can offer a more accurate and detailed guide line for the improvement of high of
of which
loss are
analysis. not
In taken
this into
section,
consideration the
in losses
low of inverter
frequency
frequency application. are systematically
applications. analyzed.
Moreover, the The
loss switching
distributionprocedure,
based including
on the the
new method
miller
can offer effect,
Before
a more is discussed
the analysis,
accurate indetailed
detail.
andseveral The highline
assumptions
guide frequency
arefor theloss
made is thoroughly
inimprovement
order to simplify analyzed,
of the some of which
procedure:
high frequency application.
are not taken into consideration in low frequency applications. Moreover, the loss distribution based
Before the analysis, several assumptions are made in order to simplify
1. The influence of some parasitic parameters such as leakage inductance is not considered. the procedure:
on the new method can offer a more accurate and detailed guide line for the improvement of high
2. The temperature influence on device parameters is not discussed. If the parameter is
1. frequency
The application.
influence of some parasitic parameters such as leakage inductance is not considered.
temperature dependent, the calibration is only based on the datasheet. The analysis is conducted
Before the analysis, several assumptions are made in order to simplify the procedure:
2. The temperature
considering influence
the inverteron device temperature
operating parametersisis60not
°C.discussed. If the parameter is temperature
1.3. The
dependent,Theinfluence of some
of theparasitic
the calibration
parameters is onlyparameters
symmetry based on such
theare
components assame
leakage
andinductance
datasheet. The
match the is
analysis notisconsidered.
conducted considering
datasheet.
2.4.inverter
the The temperature
The losses influence
of the symmetry
operating temperatureon device parameters
is 60 ◦are
components C. consideredis tonot discussed.
be the same. If the parameter is
temperature dependent, the calibration is only based on the datasheet. The analysis is conducted
3. The parameters
3.1. High
of
Side MOSFET
considering
the Loss
symmetry
the inverter
components are same and match the datasheet.
operating temperature is 60 °C.
4. The
3. losses of the symmetry
The parameters components
of the symmetry are considered
components are same andtomatch
be the
thesame.
datasheet.
Basing on operation principles in Section 2, the high side MOSFETs S3, S4 are working at AC
4. The losses of the symmetry components are considered to be the same.
frequency. Comparing with the conduction loss, the switching loss can be ignored for their low
3.1. Highswitching
Side MOSFET Loss
frequency. The D-S current of the high side MOSFET S3 ihi_S3 is shown in Figure 3.
3.1. High Side MOSFET Loss
Basing on operation principles in Section 2, the high side MOSFETs S3 , S4 are working at AC
Basing on operation principles in Section 2, the high side MOSFETs S3, S4 are working at AC
frequency. Comparing with the conduction loss, the switching loss can be ignored for their low
frequency. Comparing with the conduction loss, the switching loss can be ignored for their low
switching frequency.
switching The The
frequency. D-SD-S
current ofofthe
current thehigh sideMOSFET
high side MOSFET S3 iShi_S3
3 ihi_S3 is shown
is shown in 3.
in Figure Figure 3.

Figure 3. The D-S current of the high side MOSFET S3.

Figure 3. The D-S current of the high side MOSFET S3.

Figure 3. The D-S current of the high side MOSFET S3 .
Energies 2017, 10, 311 5 of 18

Energies 2017, 10, 311 5 of 18

When S3 is turned on, the switching of the low side MOSFET S1 divides ihi_S3 into two parts.
When SWhen 1 turns on, i
S3 is turned
hi_S3 on, theiswitching
rises, hi_S3 flowsofthrough
the low side S1 , and
MOSFET the current
S1 divides is iin rising
hi_S3 into twoperiod; WhenS1
parts.when
turns off, ihi_S3
S1 turns falls,
on, ihi_S3 ihi_S3
rises, flows
ihi_S3 flows throughDS11, and
through and the thecurrent
currentisisininrising falling period.
period; when TheS1switching of S1
turns off, ihi_S3
causes
falls,the
ihi_S3fluctuation
flows through of ihi_S3 Tgridthe
D1,. and is the girdisperiod.
current in falling T(n)period.
is the nthThe switching
switching period of thethe
of S1 causes low
switch S1 of
sidefluctuation and the duty cycle is d(n), the nth conducting time
ihi_S3. Tgrid is the gird period. T(n) is the nth switching period of the is d(n)T(n). i is the nth
low side switch S1
hir_S3(n) rising
and of
period theihi_S3
dutywhich
cycle isisd(n),
also the
the nth conducting
turn-on currenttime of Sis1 . d(n)T(n).
ihid_S3(n) iis is the nth
the falling
hir_S3(n) periodrisingwhich
period is of ihi_S3
also the
which is alsocurrent
free-wheeling the turn-on
of D1 .current
Ns is theof Snumber
1. ihid_S3(n)of
isSthe
1 falling
switching period
period which
which is also
is the free-wheeling
contained in one AC
current
period. Theofconduction
D1. Ns is the number
loss of the of S1 side
high switching
MOSFET period S3 P which is contained in one AC period. The
hicon_S3 can be divided into two parts:
conduction loss of the high side MOSFET S3 Phicon_S3 can be divided into two parts:
Ns Z d(n) T (n)
1
1[ ∑Ns( d (n)T (n ) i2hir 2

Phircon_S3 = (t) RDS_S3 dt)] (1)
Phircon_S3 T=grid n= [ 1 (0 ihir(n)((nt)) RDS_S3 dt )] (1)
Tgrid n =1
0

Ns Z [1−d(n)] T (n)
1
1[ ∑N(s [1-d (n )]T (n ) 2ihid
2
Phidcon_S3 T=grid n=[
Phidcon_S3 = (n) (t ) RDS_S3 dt )]

(2)
(
0 ihid(n ) (t ) RDS_S3dt )] (2)
Tgrid n =1
1 0

Phicon_S3 = Phircon_S3 + Phidcon_S3 (3)

Phicon_S3 = Phircon_S3 + Phidcon_S3 (3)
where Phircon_S3 is the ihi_S3 rising period loss and Phidcon_S3 is the falling period loss, RDS_S3 is the D-S
where Pof
resistance is thecan
S3 which
hircon_S3 ihi_S3berising period
obtained fromlossdatasheet.
and Phidcon_S3 is the falling period loss, RDS_S3 is the D-S
resistance of S3 which can be obtained from datasheet.
3.2. Low Side MOSFET Loss
3.2. Low Side MOSFET Loss
The conduction loss of the low side MOSFET S1 , Plocon_S1 can be easily deduced from Equation (1).
The conduction
The conduction current loss
is the ofsame
the low
as Pside MOSFET S1, Plocon_S1 can be easily deduced from Equation
hircon_S3 and the only difference is the D-S resistance. RDS_S1 is
(1). The conduction current is the same
the D-S resistance of S1 . Plocon_S1 can be calculatedas Phircon_S3 and
as: the only difference is the D-S resistance. RDS_S1
is the D-S resistance of S1. Plocon_S1 can be calculated as:
Ns Z d (n) T (n)
1
1 Ns( d (n )T (n ) i2hir
Plocon _ S1 T=grid [n∑
2
Plocon_S1 =
[ (0 ihir(n)(n()t()tR) R DS_S1 dt )]
DS_S1dt )] (4)
(4)
Tgrid n =1 0
= 1

According to the operation principles, low side MOSFETs S , S are working at 400 kHz. Figure 4a
According to the operation principles, low side MOSFETs1S1, 2S2 are working at 400 kHz. Figure
shows the voltage waveforms
4a shows the voltage of Sof
waveforms 1 during thethe
S1 during turn-on
turn-ontransition
transitionand
and the Figure4b
the Figure 4bisisthe
thesimplified
simplified
diagram of the transition.
diagram of the transition.

(a) (b)
Figure 4. The waveforms during turn-on transition: (a) the measured waveform during the turn-on
Figure 4. The waveforms during turn-on transition: (a) the measured waveform during the turn-on
transition; and (b) the simplified diagram of the turn-on transition.
transition; and (b) the simplified diagram of the turn-on transition.

As Figure 4b shows, an approximation is made in order to simplify the analysis. The D-S current
ofAs
S1 iFigure 4b shows, to
on_S1 is considered anbe
approximation is made
a constant current afterin order
ion_S1 to simplify
is fully turn-on.the
Whenanalysis. The
a signal D-Stocurrent
starts turn
of Son iS
1 on_S1
1 , is
there considered
is a time to
delaybe a constant
before G-S current
voltage of after
S 1 v i is fully
increases
on_S1
GS_S1 turn-on.
to the gate When a
thresholdsignal starts
voltage Vth.to
turn on Sthe
Then, 1 , there is acapacitance
output time delay of before
S1, CG-S
OSS_S1voltage to Sbe
begins of 1 vcharged.
GS_S1 increases to thecapacitance
The output gate threshold
loss Pvoltage
OSS_S1

V thcan be calculated
. Then, the output as: capacitance of S1 , COSS_S1 begins to be charged. The output capacitance loss
POSS_S1 can be calculated as:
Energies 2017, 10, 311 6 of 18

Z VDCBus
POSS_S1 = f SW × vDS_S1 COSS_S1 (vDS_S1 )dvDS_S1 (5)
0

where f SW is the switching frequency of S1 , V DCBus is the input DC bus voltage and vDS_S1 is the
D-S voltage of S1 . The output capacitance COSS_S1 is a vDS_S1 related parameter which is provided by
the datasheet.
When vGS_S1 reaches V th , the ion_S1 starts to rise linearly. After the rising period, ion_S1 turns on
completely, the vGS_S1 reaches the turn-on miller plateau voltage V mp_on and the voltage vDS_S1 starts
to decrease. The miller plateau is caused by the charging or discharging procedure of the capacitance
between G-D,Energies
which 10,C
2017,is GD [20]. In actual waveform, as Figure 4a shows, miller plateau
311 6 of 18have a slope.

The steepness of the slope is depending on the value of CGD and CGS , where CGS is the capacitance
V
0 , the
DCBus
between G-S. Typically, CGD is larger = fSW C
POSS_S1than × GS vDS_S1 COSS_S1 (vDS_S1 )dappears
phenomenon vDS_S1 as a plateau.(5)The duration
time can be considered as the charging time to charge
where fSW is the switching frequency of S1, VDCBus is the GD Q input DC bus voltage and vto
, which is the gate drain
DS_S1 is the charge.
D-S
At the end of the miller plateau, the vGS_S1 reduces to zero and the turn-on procedure
voltage of S 1. The output capacitance C OSS_S1 is a v DS_S1 related parameter which is provided by theis completed.
datasheet.
During the turn-on transition, the turn-on loss Pon can be divided into two parts: Pon1 and Pon2 .
When vGS_S1 reaches Vth, the ion_S1 starts to rise linearly. After the rising period, ion_S1 turns on
The vGS_S1 is constant
completely,and the viGS_S1
S1 is linearly
reaches changed
the turn-on millerduring ton1 . Similarly,
plateau voltage iS1 isvconstant
thevoltage
Vmp_on and the DS_S1 starts toand vGS_S1 is
linearly changed within
decrease. ton2 . plateau
The miller The turn-on
is causedloss
by the S1 Pon_S1
ofcharging can be deduced
or discharging procedureform
of the Equation
capacitance (6).
between G-D, which is CGD [20]. In actual waveform, as Figure 4a shows, miller plateau have a slope.
The steepness
Ns V of the slope is depending on the value ofNs CGD and CGS, where CGS is the capacitance
DCBus Ion_S1(n)
1 G-S. Typically, 1 VDCBus Ion_S1(n) QGS2 RGon QGD RGon
= Tgrid
Pon_S1 between ∑ 2
CGD is(larger
ton1 + CGS), =
ton2
than
Tgrid ∑
the phenomenon appears as a( plateau.
2 Vmp_on +Vth + Vmp_on )
The duration (6)
time can ben=considered
1 as the charging time to charge Qn =, 1which is the gate to drain2 charge.
GD

At the end of the miller plateau, the vGS_S1 reduces to zero and the turn-on procedure is
where Ion_S1(n)completed.
is the nth Duringswitching
the turn-on period turn-on
transition, current
the turn-on loss PonofcanSbe QGS2 represents
1 . divided into two parts:the
Pon1 corresponding
and
charge duringPon2ton1
. Thewhich
vGS_S1 is constant
can be and iS1 is linearly
calculated changed during
according to theton1. Similarly,
transferthe iS1 is constant and
characteristic vGS_S1 of devices,
figure
is linearly changed within ton2. The turn-on loss of S1 Pon_S1 can be deduced form Equation (6).
RGon is the gate loop resistance during turn-on period.
Ns
1 VDCBus I on_S1(n)
Ns
1 VDCBus I on_S1( n ) QGS2 RGon QGD RGon
Figure 5a shows the waveforms P =
on_S1
T
 (t + t ) =
2 S1 during
of 
T the turn-off
2
on1( +
V transition
on2
+V V
) and the Figure 5b is the
(6) mp_on th
grid n =1 grid n =1 mp_on

simplified diagram of the transition. A similar approximation is made 2 which considers the D-S turn-off
current of S1 where
ioff_S1Ion_S1(n)
to beis constant
the nth switching
before period
toff2turn-on
. When current of S1. QGS2
the signal represents
starts the corresponding
to turn off S1 , vGS_S1 starts to
charge during ton1 which can be calculated according to the transfer characteristic figure of devices,
decrease. TheRvGon
GS_S1 begins to increases when
is the gate loop resistance during turn-on
v GS_S1 reaches
period.
the turn-off miller plateau voltage V mp_off .
At the end of the plateau, v
Figure 5a showsGS_S1 stops increasing and
the waveforms of S1 during the i turn-off transition and the Figure 5b is the transition is
off_S1 starts to decrease. The turn-off
simplified diagram of the transition. A similar
completed when vGS_S1 goes down to V th and ioff_S1 decreases approximation is made whichThe
to zero. considers the D-S
turn-off turn-
loss Poff_S1 can be
off current of S1 ioff_S1 to be constant before toff2. When the signal starts to turn off S1, vGS_S1 starts to
regarded as two parts: P
decrease. The voff1
during t off1 and
GS_S1 begins to increases
P
when off2 during t
vGS_S1 reachesoff2
which can be calculated by
the turn-off miller plateau voltage Vmp_off.
Equation (7).
At the end of the plateau, vGS_S1 stops increasing and ioff_S1 starts to decrease. The turn-off transition is
completed Ns VDCBus
when Ioff_S1
vGS_S1 goes(ndown Ns V
to Vth and ioff_S1 decreases zero.Ioff_S1
toDCBus The (turn-off
n) QGDloss
RGoffPoff_S1 can beRGoff
1
= Tgrid
Poff_S1 regarded ∑
)
( t off1 + t off2 ) =
as two parts:2 Poff1 during toff1 and Poff2 during
1
Tgrid ∑ ( Vmp_off
toff2 which can 2be calculated
+ Q(7). GS2
by EquationVmp_off +Vth ) (7)
n=1 n=1 2
1 Ns VDCBus I off_S1(n ) 1 Ns VDCBus I off_S1(n ) QGD RGoff QGS2 RGoff
P =  (t + t ) =  ( + )
of2 S1 . RVGoff isVthe+gate
off_S1 off1 off2
T 2 T V (7)
where Ioff_S1(n) is the nth switching period turn-off current
grid n =1 loop resistance during
grid n =1 mp_off mp_off th

2
turn-off period. The total loss of S1 Ploss_S1 is regarded as:
where Ioff_S1(n) is the nth switching period turn-off current of S1. RGoff is the gate loop resistance during
turn-off period. The total loss of S1 Ploss_S1 is regarded as:
Ploss_S1 = Plocon_S1 + POSS_S1 + Pon_S1 + Poff_S1 (8)
Ploss_S1 = Plocon_S1 + POSS_S1 + Pon_S1 + Poff_S1
(8)

(a) (b)
Figure 5. The voltage and current waveforms during turn-off transition: (a) the measured waveform
Figure 5. Theduring
voltage and current
the turn-off waveforms
transition; duringdiagram
and (b) the simplified turn-off transition:
of the (a) the measured waveform
turn-off transition.
during the turn-off transition; and (b) the simplified diagram of the turn-off transition.
Energies 2017, 10, 311 7 of 18
Energies 2017, 10, 311 7 of 18

3.3. Free-Wheeling Diode Loss

3.3. Free-Wheeling Diode Loss
The conduction loss of the free-wheeling diode D1, Pdcon_D1 can be deduced from Equation (2),
The conduction loss of the free-wheeling diode D1 , Pdcon_D1 can be deduced from Equation (2),
which is shown in Equation (9):
which is shown in Equation (9):
1 Ns [1-d (n )]T (n )
1Tgrid N
Pdcon_D1 = [ s (Z [1−d(n)]Tihid
(n(n) )U f dt )] (9)
0
Pdcon_D1 = [ ∑n =1( ihid(n) Uf dt)] (9)
Tgrid n=1 0
Uf is the forward voltage of the diode. The turn-on loss of the diode Pond_D1 can be represented as
(10): Uf is the forward voltage of the diode. The turn-on loss of the diode Pond_D1 can be represented
as (10):
1 Ns 1 11 NNs s 11
Pond _ =
Pond_D1 D1 = 1 Ns 1 U I
Tgrid

Tgrid∑n =21 U
t
d don(n) r ≈
2 d Idon(n) tr ≈ TTgrid n
∑= 2 22

UUDCBus I off _ S1(n-1) ton1t
DCBus Ioff_S1 (n−1) on1
(10)
(10)
n=1 grid n=2

where UUddisisthethe
voltage on the
voltage ondiode. Idon(n) is
the diode. the nth
Idon(n) is thediode nthturn-on
diodecurrent which
turn-on can bewhich
current approximated
can be
as the (n − 1)th
approximated turn-off
as the current
(n − 1)th turn-off S1 Ioff_S1(n
of current . tr is. the
of S−11)Ioff_S1(n−1) rising
tr is the time
rising of of
time theS1S1which
the which can be
can be
approximated as ton1
approximated .The
.The
on1 turn-on
turn-on loss
loss of
of the
the diode
diode P Poffd_D1
offd_D1 cancanbe be represented
represented asas (11):
(11):
Ns Ns
1 1 Ns 1 1U i 11 Ns 11
Poffd_D1 ==
Poffd _ D1
Tgridn∑
Tgrid
 U
1 2
id t
RM(n)
d RM(n) rr
t rr =
= 
∑ UUDCBus
grid nn==1122
TTgrid
iRM(n)
DCBus iRM(tnrr) trr (11)
(11)
=n1=2

IIRM
RMisisthe
thediode
diodepeak
peakreverse
reversecurrent
currentand
andtrrtrrisisthe
thereverse
reverserecovery
recoverytime.
time.

3.4. Inductor
3.4. Inductor Loss
Loss
The copper
The copper loss PLCu offilter
LCuof filterinductor
inductorcan
canbe
becalculated
calculatedas
as

11
Z TT
0
grid
grid 2
PPLCu=
LCu = iLiL2(t()t)RRLLddt
t (12)
(12)
TTgrid 0
grid

where iiLL is
where is the
the inductor
inductor current
current and
and the RLL isisthe
the R theresistance
resistance ofof the
the inductor
inductor winding.
winding.
Figure 6 shows the trajectory of inductor current i on the B-H
Figure shows the trajectory of inductor current iLL on the B-H plane during one plane during oneswitching
switchingcycle.
cycle.
At the end of the switching cycle, the iiLL is is not
not the
the same
same as as the initial
initial value
value because
because the
the inverter
inverter is
is
working in in continuous
continuouscurrent
currentmode
modeininorder
order to follow the the
to follow sinusoidal reference.
sinusoidal The work
reference. modemode
The work leads
to the to
leads unclosed B-H curve
the unclosed B-Hascurve
Figureas6 Figure
shows. 6Accordingly, the traditional
shows. Accordingly, hysteresis loss
the traditional calculation
hysteresis loss
based on closed
calculation basedB-Hon curve
closedisB-H
not suitable
curve is for
notinverter
suitablehysteresis
for inverter losshysteresis
calculation.
lossThe unclosed B-H
calculation. The
curve should be adopted [21–23].
unclosed B-H curve should be adopted [21–23].

Figure
Figure 6.
6. The
The B-H
B-H curve
curve during
during on
on switch
switch cycle.
cycle.

Magnetic flux density B can be obtained by integral of the inductor voltage uL. The magnetic flux
Magnetic flux density B can be obtained by integral of the inductor voltage uL . The magnetic flux
density at tn can be calculated as:
density at tn can be calculated as:
11
Z tn
tn

N⋅A
BB((tnt ))==
N · A 00 uL dt
uL dt (13)
(13)
n
Energies 2017, 10, 311 8 of 18

where N is the number of winding turns and A is the cross-section area of the inductor core. iL (tn ) is
the inductor current at tn , the magnetic field intensity H(t1 ) can be obtained by:

NiL (t1 )
H ( tn ) = (14)
l
where l is the length of the equivalent magnetic circuit. The hysteresis loss Physis can be calculated as:

Ns Z BP Z BE
1
Tgird ∑
Physis = HdB− HdB (15)
n=1 BS BP

3.5. Capacitor Loss

The loss which is caused by the leakage current of the capacitor Pcleak can be calculated as:

Pcleak = Uc · Icleak (16)

Uc is the voltage on the capacitor, and Icleak is the leakage current of the capacitor, which is a Uc
related parameter and can be found in the datasheet.
Rcs is the resistance of the capacitor lead and electrode, Irip is the ripple current of the capacitor,
and the loss on these conductors can be represented as:

2
Pcs = Irip Rcs (17)

RESR is the equivalent series resistance of the capacitor, which can be deduced form dissipation
factor tanδ:
tan δ
RESR = (18)
2π f C
where f is the frequency which the ESR is calculated at. C is the capacitance of the capacitor. The ESR
loss of the capacitor can be calculated as:

2
PESR = Irip RESR (19)

The total losses on the capacitor is

Pcloss = Pcleak + Pcs + PESR (20)

3.6. Loss Calculation Results

Based on the previous methods, the calculation results of the Full SiC power devices inverter
losses are shown in Figure 7 as calculation Example 1.
As we can see from Figure 7, the switching loss takes the major part of the total loss. The output
capacitance loss POSS , which is often overlooked in low frequency loss analysis, is over 1% and should
be taken account in high frequency application. For the special characteristic of the SiC diode, the
reverse recovery time trr is consider to be 0. Hence, the free-wheeling diode turn-off loss Pdoff is 0.
This superiority, which is proven in later experiment, is vital for the total loss of the inverter. Finally,
the calculation efficiency is 97.32% at rated power of 1 kW.
Two comparative calculation examples are set up. In Example 2, the free-wheeling diodes D1 , D2
are replaced by two normal Si diodes. In Example 3, all the power devices are replaced by the normal
Si devices. The loss distribution of the comparative calculation examples are shown in Figure 8.
As Figure 8a shows, when the SiC diodes are replace by the normal Si diodes, the total loss on the
diodes is over 50%. The turn-on loss and the turn-off loss of the diodes contribute the most part of the
losses increase. As a result, the calculation efficiency of Example 2 is down to 93.57% at 1 kW.
Energies 2017, 10, 311 9 of 18
Energies 2017, 10, 311 9 of 18
Energies 2017,
Energies 10, 10,
2017, 311311 9 of9 18
of 18

Figure 7. Loss distribution of Example 1.

Figure 7. Loss distribution of Example 1.
Figure 7. Loss
Figure 7. distributionof
Loss distribution ofExample
Example1.1.

(a) (b)
(a)
Figure 8. Loss distributions (b) Example 2; and
of the comparative calculation examples: (b)
(a)
(a)
(b) Example 3.
Figure 8. Loss distributions of the comparative calculation examples: (a) Example 2; and
Figure 8. Loss distributions of the comparative calculation examples: (a) Example 2; and
Figure
(b)(b) 8. Loss3.distributions of the comparative calculation examples: (a) Example 2; and (b) Example 3.
Example
Example
After 3. power devices are replaced by the Si devices. The losses of the switches become the
all the
major part of the total losses. Consequently, as Figure 8 shows, the total loss of Example 3 is almost
After
After
three allallthe
times the power
power
larger than devices
devices
Example are
are replaced
2.replaced
replaced by the
by
by
The calculationtheefficiency
the Sidevices.
Si
Si devices.
devices. Thelosses
of The
Examplelosses isof
3 of thethe
85.27% switches
switches
at 1 kW. become
become thethe
major part
major part of
Theof the total
theloss
total losses.
totalcomparison Consequently,
losses. Consequently, as
is shown in Figure Figure
Figure 8 shows,
8 shows,
9. For Example the total
the2,total loss of
loss oflosses
the diode Example
Example 3 is almost
3 is almost
contribute the
three times
three times
most. larger
larger
For larger
Examplethan
than
than Example
3,Example
losses2.
Example
the 2.
2. The
onThe
The calculation
the calculation
calculation
switches efficiencyof
efficiency
are efficiency
numerous. ofExample
of
The Example
Example 3 33
total losses is
isis 85.27%
85.27%
85.27%
difference at
atat 11 kW.
1 kW. kW.the
between
TheThe
Full total
SiCtotal
and loss
losscomparison
Full comparison
Si power deviceisisshown
is overin
shown Figure
Figure
Figure
five 9.These
9.
times.9. ForExample
For Example 2,2,
results are the
confirmeddiode
thediode
diode losses
losses
losses
in later contribute
contribute
contribute
comparative thethe
experiments,
most.
most. For
For Example
Example which indicate
3,3,the
the lossesthat
losses on
on thethe Si power devices
switches
switches are not suitable
arenumerous.
are numerous. Thetotal
The forlosses
total high
losses frequency application.
difference
difference between
betweenthethe
Full
Full SiC
SiC andFull
and FullSiSipower
powerdevice
deviceisis over
over five times.
times. These
Theseresults
resultsare
areconfirmed
confirmed inin
later comparative
later comparative
experiments,
experiments,
experiments, whichindicate
which indicatethat
thatthe
the Si
Si power devices
devicesare
arenot
notsuitable
suitablefor
suitable high
for
for frequency
high
high frequency
frequency application.
application.
application.

Figure 9. Loss comparison between calculation examples.

Figure 9. Loss comparison between calculation examples.

Figure 9.
Figure 9. Loss
Loss comparison between calculation
comparison between calculation examples.
examples.
Energies 2017, 10, 311 10 of 18
Energies 2017, 10, 311 10 of 18

4. Improved
4. Improved Simulation
Simulation Method
Method
A simulation
A simulation modelisisoften
model oftenbuilt
builtininsoftware
software environment
environment in in order
ordertotoverify
verifythe
thevalidity
validityofof
theoretical
theoretical analyses
analyses and and accelerate
accelerate the compensator
the compensator tuning.tuning.
In lowIn low frequency
frequency converting,
converting, the
the simplified
simplified component models are considered to be effective and timesaving. However,
component models are considered to be effective and timesaving. However, as the switching frequency as the
switching frequency increases, some details of the switching procedure may have a
increases, some details of the switching procedure may have a serious influence on the simulation,serious influence
on the
which couldsimulation,
make the which
results could
become make the results
inaccurate, even become inaccurate,
unreliable. even unreliable.
The inconsistency between The the
inconsistency between the simulation results and experiment results emerges during the design
simulation results and experiment results emerges during the design process. The deviation between
process. The deviation between PWM control signal and switching response in high frequency
PWM control signal and switching response in high frequency switching is consider to be the reason
switching is consider to be the reason which cause the inconsistency. The influence of the deviation
which cause the inconsistency. The influence of the deviation on the simulation is verified by experiment.
on the simulation is verified by experiment. Moreover, based on the theoretical analysis and test
Moreover, based on the theoretical analysis and test results, a compensator method is proposed in
results, a compensator method is proposed in order to minimize the deviation which is caused by the
order to minimize the deviation which is caused by the influence. Consequently, the simulation results
influence. Consequently, the simulation results are significantly improved. The improved simulation
aremodel
significantly
is used improved. The
in prototype improved
design simulation
to verify model is used
the compensators. in prototype
The method design
is proven toeffective
to be verify the
compensators. The method is proven
by the experiments in later section. to be effective by the experiments in later section.

4.1.4.1.
Influence of High
Influence Frequency
of High FrequencySwitching
Switching
A simulation
A simulation model
model is isbuilt
builtininsoftware
softwareenvironment
environment of PSIM. The
of PSIM. Theparameters
parametersofofthe
the components
components
andand
control compensator are the same as the experimental prototype. The grid-connecting
control compensator are the same as the experimental prototype. The grid-connecting power power
experiments are carried out. The 3P3Z compensator in the current loop, which is designed
experiments are carried out. The 3P3Z compensator in the current loop, which is designed to follow to follow
thethe
current reference,
current reference,are aretuned
tunedand andtested
testedononthe
the simulation
simulation model.
model. AsAsFigure
Figure10a10ashows,
shows,thethe
compensation
compensation effect is is
effect desirable.
desirable.However,
However,during
during the
the experiment,
experiment, thethesame
samecompensator,
compensator,which
which has
has
thethe
same parameters,
same parameters, causes
causes thethecurrent
currentoscillation
oscillationduring
during zero-crossing procedure.
zero-crossing procedure.

(a) (b)
Figure 10. Simulation and Experiment results comparison: (a) simulation waveform before
Figure 10. Simulation and Experiment results comparison: (a) simulation waveform before improving;
improving; and (b) experiment waveform.
and (b) experiment waveform.

The same simulation method is used in the previous 50 kHz inverter design and no similar issue
The same
arises. Throughsimulation
analysis,method is usedbetween
the deviation in the previous 50 kHz
PWM control inverter
signal design and
and switching no similar
response issue
in high
arises. Through
frequency analysis,
switching, deviation
is the main reasonbetween PWM the
which causes control signal to
simulation andbeswitching
inaccurate.response in high
frequency switching, is the main reason which causes the simulation to be inaccurate.
4.2. Equivalent Opening Time
4.2. Equivalent Opening Time
Figure 11 shows the waveforms of a complete switching cycle. The PWM signal is considered to
beFigure
an ideal11square
showswave. the waveforms
When the risingof a complete
edge of theswitching
PWM signal cycle.begins
The PWMto turnsignal
on theisswitch,
considered
there to
is a turn-on propagation delay t
be an ideal square wave. When the rising edge of the PWM signal begins to turn on the switch, the
pg_on before the G-S voltage starts to rise. The delay is caused by there
is adrive
turn-oncircuits when converting
propagation the PWM
delay tpg_on beforesignal into voltage
the G-S drive signal.
startsWhen VGSThe
to rise. rises, the D-S
delay voltageby
is caused VDSthe
starts
drive to descend.
circuits when The time, which
converting the PWMis fromsignal
10% Vinto
GS todrive
90% V DS, is defined
signal. When as V GStherises,
turn-on
the delay td_on.
D-S voltage
V DSThe time,
starts towhich is form
descend. The90% VDSwhich
time, to 10%isVfrom
DS, is the
10%rise time
V GS to t90%
rise. The
V DSturn-off propagation
, is defined delay tpg_off
as the turn-on delay,
turn-off delay t doff and fall time tfall can be obtained by similar definitions. The equivalent opening
td_on . The time, which is form 90% V DS to 10% V DS , is the rise time trise . The turn-off propagation
time
delay t is define as thedelay
, turn-off period
t which the V
and fall DS fall below 90% then rise over 90%. As Figure 11 shows, the
time t can be obtained by similar definitions. The equivalent
pg_off doff fall
opening time is define as the period which the V DS fall below 90% then rise over 90%. As Figure 11
Energies 2017, 10, 311 11 of 18

shows, the relationship between PWM opening time tPMW and the equivalent opening time tEQ can be
represented as Eqaution (21)
Energies 2017, 10, 311 11 of 18

tEQ = tPWM + [tpg_off − tpg_on ] + [td_off (VDS ) − td_on (VDS )] + trise (VDS ) + tfall (VDS ) (21)
relationship between PWM opening time tPMW and the equivalent opening time tEQ can be represented
as Eqaution (21)
The equivalent opening time tEQ can be regarded as the actual respond of the switch under the
EQ = t PWM
control of PWM tsignal. + [t pg_off −circuits,
In practical t pg_on ] + [ttpg_on
d_off (V DS ) −
and t d_on (V
tpg_off DS )]
are + t riseand
small ) + t fall (VDSto) be equal.
(VDSassumed (21)Hence,
Equation (21) can be simplified as:
The equivalent opening time tEQ can be regarded as the actual respond of the switch under the
control of PWM signal. In practical circuits, tpg_on and tpg_off are small and assumed to be equal. Hence,
tEQ = tPWM + td_off (VDS ) − td_on (VDS ) + trise (VDS ) + tfall (VDS ) = tPWM + te (VDS ) (22)
Equation (21) can be simplified as:

where te is the total t EQ =extend

t PWM +time (VDS ) − is
t d_off which t d_on (VDS ) +
caused byt rise
the DS ) + t fall
(Vdelay in(V = t PWM + t eprocedure.
DS )switching
the (VDS ) td_on
(22) , td_off ,
tfall and trise are all V DS related parameters provided by the datasheet. It is obvious that the PWM
where te is the total extend time which is caused by the delay in the switching procedure. td_on, td_off, tfall and
opening time
trise are all Vis extended during the switching procedure. The proportions of the deviation in the
DS related parameters provided by the datasheet. It is obvious that the PWM opening time is
equivalent opening
extended during the time tEQ under
switching different
procedure. switching frequencies
The proportions of the deviation and in duty cycles are
the equivalent shown in
opening
Tabletime1. tEQ under different switching frequencies and duty cycles are shown in Table 1.

Figure 11. Waveforms of the switching operation.

Figure 11. Waveforms of the switching operation.
Table 1. The proportion of the deviation.
Table 1. The proportion of the deviation.
te fsw Duty Cycle tPWM(ns) tEQ(ns) te/tEQ
te f sw 2%
Duty Cycle 400
tPWM(ns) 492 tEQ(ns) 18.70% te /tEQ
50 kHz 50% 10,000 10,092 0.91%
2% 400 492 18.70%
80% 16,000 16,092 0.57%
92 ns 50 kHz 50% 10,000 10,092 0.91%
2%
80% 50
16,000 142 16,092 64.79% 0.57%
92 ns 400 kHz 50% 1250 1342 6.86%
2%
80% 2000 50 2092 142 4.40% 64.79%
400 kHz 50% 1250 1342 6.86%
80% 2000 2092 4.40%
As Table 1 shows, when the switching frequency is low, the proportion of te in tEQ is very small.
During the practical circuit design, this deviation is often ignored. However, in high frequency
implementation,
As Table 1 shows, thiswhen
time deviation may even
the switching larger than
frequency tPWM. the
is low, When the fsw is atof
proportion 400tekHz,
in tEQat 2% dutysmall.
is very
cycle,
During thepractical
the proportion of te isdesign,
circuit over 50%. tPWM
this is extended
deviation is about
often two times. This
ignored. deviation
However, in may
highlead to
frequency
the inconsistency
implementation, thisbetween the output
time deviation andeven
may control signal.
larger thanThis difference
tPWM . When has
theanferroris accumulation
at 400 kHz, at 2%
sw
effect, which can cause the error response of the controller. As a result, the compensator, which is
duty cycle, the proportion of te is over 50%. tPWM is extended about two times. This deviation may lead
tested in the simulation and consider to be valid, will fail on the prototype.
to the inconsistency between the output and control signal. This difference has an error accumulation
In order to verify the analysis, an off-grid DC experiment is set up, for the deviation is more
effect, which can cause the error response of the controller. As a result, the compensator, which is
obvious when the duty cycle is constant. The difference between the output currents can prove the
tested in the simulation
pervious analysis. Theand consider
prototype to be to
connects valid,
a 100will fail oninstead
Ω resistor the prototype.
of the gird, then runs at 50 kHz
In order to verify the analysis, an off-grid DC experiment
and 400 kHz respectively. A constant duty cycle is given to the inverter is set inup, for to
order therundeviation is more
the inverter
obvious
in DC when
outputthemode.
duty Thecycleoutput
is constant.
current iThe
test isdifference
tested at each between the output
duty cycle currents
at different can prove
switching
frequency.analysis.
the pervious Meanwhile, Thetheprototype
same test isconnects
carried out toona 100 Ω resistormodel.
the simulation insteadAsofFigure 12 shows,
the gird, thentheruns at
output
50 kHz andcurrent
400 kHz at the same duty cycle
respectively. of simulation
A constant duty and experiment
cycle is givenare torepresented
the inverter by in
two respective
order to run the
curves.
inverter There
in DC is almost
output mode.no difference
The outputbetween
currenttheiexperiment
is testedresults
at eachand simulation
duty cycle atresults whenswitching
different the
test
Energies 2017, 10, 311 12 of 18

Energies 2017, 10, 311 12 of 18

frequency. Meanwhile, the same test is carried out on the simulation model. As Figure 12 shows, the
Energies 2017, 10, 311 12 of 18
output current at the same duty cycle of simulation and experiment are represented by two respective
switching frequency is at 50 kHz as Figure 12a shows. Because the proportion of the deviation in low
curves. There is almost no difference between the experiment results and simulation results when the
switchingisfrequency
frequency very small,is atwhich
50 kHzcan
as Figure 12a shows.
be ignored Because analysis.
in traditional the proportion of thewhen
However, deviation in low
the switching
switching
frequency frequency
is very is atwhich
small, 50 kHz asbe
can Figure
ignored12ain
shows. Because
traditional the proportion
analysis. However, of the the
when deviation in low
switching
frequency is at 400 kHz as Figure 12b shows, there are significant differences between the simulation
frequency
frequency is very small, which can be ignored in traditional analysis. However, when the switching
results and istheat 400 kHz as Figure
experiment 12bWhen
results. shows,thethere
testare significant
duty cycle isdifferences
under 45%, between the simulation
the experiment output
frequency
results andis at
the400 kHz
experimentas Figure 12b
results. shows,
When thethere
test are
duty significant
cycle is differences
under 45%, thebetween the simulation
experiment output
current is apparently larger than the simulation results at the same duty cycle. This phenomenon can
results and the experiment results. simulation
When the test duty cycle is duty
under 45%,This
thephenomenon
experiment output
becurrent is apparently
explained larger than
as the control PWMthe signal in the results
prototypeat the
is same
extended cycle.
by the delays which wecan talked
current is apparently
be explained larger PWM
as the control than the simulation
signal results atisthe
in the prototype same duty
extended by thecycle.
delaysThis phenomenon
which we talked can
above. The phenomenon is more obvious at low duty cycle which is consistent with previous
beabove.
explained as the controlisPWM
The phenomenon moresignal
obviousin the prototype
at low is extended
duty cycle which by the delayswith
is consistent which we talked
previous
analysis.
above. The phenomenon is more obvious at low duty cycle which is consistent with previous analysis.
analysis.

(a) (b)(b)
Figure12.
Figure 12. Theoutput
output current responds between simulation and experiment at different frequencies:
Figure 12. The
The output current
current responds
responds between
between simulation
simulation and
and experiment
experiment at
at different
different frequencies:
frequencies:
(a)50
(a) 50kHz;
kHz;and
and (b)
(b) 400
400 kHz.
kHz.
(a) 50 kHz; and (b) 400 kHz.

4.3.Compensating
4.3. CompensatingMethod
Method
4.3. Compensating Method
Different from other researches, the proposed method focuses on the impact of the switching
Different from other researches, the proposed method focuses on the impact of the switching
procedure on from
Different otherpower.
the output researches,
Insteadtheofproposed
simulatingmethod focuses
the complex on the impact
switching procedureof the switching
in detail, a
procedure on the output power. Instead of simulating the complex switching procedure in detail, a
procedure
compensating module is used to improve the simulation results. The proposed method is simpleinand
on the output power. Instead of simulating the complex switching procedure detail,
compensating module is used to improve the simulation results. The proposed method is simple and
a effective.
compensating
Basedmodule is used
on Equation to dimprove
(22), the simulation
EQ is the duty cycle basedresults. The can
on tEQ and proposed methodas:
be calculated is simple and
effective. Based on Equation (22), dEQ is the duty cycle based on tEQ and can be calculated as:
effective. Based on Equation (22), dEQ is the duty cycle based on tEQ and can be calculated as:
d ⋅ tsw + td_off (VDS ) − td_on (VDS ) + trise (VDS ) + tfall (VDS )
d EQ = d ⋅ tsw + td_off (VDS ) − td_on (VDS ) + trise (VDS ) + tfall (VDS ) (23)
d = =d · tsw + td_off (VDS ) − td_ontsw(VDS ) + trise (VDS ) + tfall (VDS )
dEQ EQ (23)
(23)
tsw
sw t
where tsw is the switching period, and dPWM is the duty cycle of the input PWM. The compensator is
where
addedttsw
sw is the switching
between period,module
the Linearization and dPWM
andisisPWM
PWM the
theduty
duty cycle
cycle of
generating of the
the input
module input PWM.
(Figure 13).The compensator is
added between the Linearization module and PWM PWM generating
generating module
module (Figure
(Figure 13).
13).

Figure 13. Location of the compensator.

Figure 13. Location of the compensator.

The linearization module [24–26] is used to generate the duty cycle dPWM for controlling the
switches. The duty cycle dPWM is compensated by the duty cycle compensator. In order to test the
The linearization
linearization module
module [24–26]
[24–26] isis used
used to
to generate
generate the
the duty
duty cycle
cycle dPWM for controlling the
the
The
compensation effect, the 400 kHz off-grid DC experiment is carried out on thedPWM for controlling
improved simulation
switches. The
switches. The duty
duty cycle
cycle ddPWM
PWM is compensated by the duty cycle compensator. In order to test the
is shown
compensated by14.
theApparently,
duty cyclethe compensator.
model. The simulation results are in Figure compensatorInmodule
order to test the
is able
compensation
compensation effect, the 400 kHz off-grid
off-grid DC
DC experiment
experiment isis carried
carried out
out on
on the
the improved
improved simulation
simulation
to simulate theeffect, the 400
prototype kHz
output current correctly. The deviation of the output current between the
model.
model. The
The simulation
simulation results
results are
are shown
shown in
in
simulation and experiment is minimized successfully.
Figure
Figure 14.
14. Apparently,
Apparently, the
the compensator
compensator module
module is able
is able
to simulate theofprototype
Because output
the deviation, current correctly.
the characteristic The deviation
of compensator at lowofduty
the output current
cycle have between the
to be adjusted.
simulation and experiment is minimized successfully.
Based on the improved simulation model, the characteristic of the inverter is re-analyzed. The
Because of the deviation, the characteristic of compensator at low duty cycle have to be adjusted.
Based on the improved simulation model, the characteristic of the inverter is re-analyzed. The
Energies 2017, 10, 311 13 of 18

to simulate the prototype output current correctly. The deviation of the output current between the
simulation and experiment is minimized successfully.
Because
Energies of the deviation, the characteristic of compensator at low duty cycle have 13toofbe
2017, 10, 311 18
Energies 2017,
adjusted. 10, 311on the improved simulation model, the characteristic of the inverter is re-analyzed.
Based 13 of 18

The compensator
compensator is redesign
is redesign accordingly.
accordingly. The oscillation
The oscillation duringduring zero-crossing
zero-crossing is restrained
is restrained bynew
by the the
compensator is redesign accordingly. The oscillation during zero-crossing is restrained by the new
new compensator
compensator in theinsimulation.
the simulation. The compensation
The compensation effecteffect is proven
is proven byfurther
by the the further experiment.
experiment. The
compensator in the simulation. The compensation effect is proven by the further experiment. The
The output waveforms of the experiments are shown in the
output waveforms of the experiments are shown in the later section. later section.
output waveforms of the experiments are shown in the later section.

Figure
Figure 14.
14. The
The current
current respond
respond between
between improved
improved simulation and experiment.
simulation and experiment.
The

5.
5. Experiment Results
Experiment Results
A 1-kW prototype
A 1-kW prototype is
is built
built in
in the
the laboratory
laboratory (Figure
(Figure 15).
15). The
The parameters
parameters of the components
of the components are
are
laboratory
shown in Table
shown in Table 2. The control platform is TMS320F28377D from Texas Instruments. It is a high
Table 2.
2. The control platform is TMS320F28377D from Texas Texas Instruments. It is a high
Instruments. It
performance dual-core
performance dual-core MCU
MCU running
running at 200200 MHz.
MCU running at at 200 MHz.
MHz.

Figure 15. Experimental prototype.

Figure 15. Experimental prototype.
Figure 15. Experimental prototype.
Table 2. Parameters of the proposed system.
Table 2. Parameters
Table 2. Parameters of
of the
the proposed
proposed system.
system.
Component Manufacture Model Value
Component Manufacture Model Value
S1, S2, S3, S4 Manufacture
Component Wolfspeed C2M0280120DValue
Model
S1, S2, S3, S4 Wolfspeed C2M0280120D
S1 , S2 , S3 ,D 1, D 2
DS14, D2
Wolfspeed C2M0280120D
Wolfspeed
Wolfspeed
CVFD20065A
CVFD20065A
D1 , D2 Li1, Li2 Magnetics CVFD20065A
Wolfspeed 77439A7 800 μH
Li1, Li2 Magnetics 77439A7 800 μH
Li1 , Li2Lg1, Lg2 Magnetics
Magnetics 77439A7
77548A7 215 800
μHµH
Lg1 , Lg2Lg1C , Lg2
f
Magnetics
Magnetics
WIMA
77548A7
77548A7
MKP10
215 215
μH
0.15 μFµH
Cf Cf WIMA WIMA MKP10
MKP10 0.150.15
μF µF

5.1. Grid-Connected Experiment

5.1. Grid-Connected Experiment
Figure 16a shows the measured waveforms at 100 W and Figure 16b is the corresponding simulation
Figure 16a shows the measured waveforms at 100 W and Figure 16b is the corresponding simulation
waveforms. The output current ig can track the grid voltage very well when the power output is low. The
waveforms. The output current ig can track the grid voltage very well when the power output is low. The
power factor is 0.99 and THD is 4.8%. The bus voltage is stabilized at 400 V and the ripple is within ±4 V.
power factor is 0.99 and THD is 4.8%. The bus voltage is stabilized at 400 V and the ripple is within ±4 V.
Energies 2017, 10, 311 14 of 18

5.1. Grid-Connected Experiment

Figure 16a shows the measured waveforms at 100 W and Figure 16b is the corresponding
simulation waveforms. The output current ig can track the grid voltage very well when the power
Energies 2017, 10, 311 14 of 18
output is low. The power factor is 0.99 and THD is 4.8%. The bus voltage is stabilized at 400 V and the
Energies 2017, 10, 311 14 of 18
ripple is within ±4oscillation
The zero-crossing V. The zero-crossing oscillation
which happens which
in pervious happens design
compensator in pervious compensator
is efficiently design
restrained. The is
efficiently
simulation restrained.
waveforms
The zero-crossing The simulation
in Figure
oscillation waveforms
16bhappens
which match the in Figure
experiment
in pervious 16b match
results well.
compensator the experiment results well.
design is efficiently restrained. The
simulation waveforms in Figure 16b match the experiment results well.

(a) (b)
(a) (b)
Figure 16. Experimental waveforms of the inverter at low power: (a) experiment waveform; and
Figure 16. Experimental waveforms of the inverter at low power: (a) experiment waveform; and
(b) simulation
Figure waveform. waveforms of the inverter at low power: (a) experiment waveform; and
16. Experimental
(b) simulation waveform.
(b) simulation waveform.
Figure 17a shows the waveform at 1 kW and Figure 17b is the corresponding simulation
Figure
Figure17a
waveforms. 17ashows
The RMS
shows the
the waveform
value of ig is 4.5 A.at
waveform 11 kW
kW
atAlong and
with
and Figure
the 17b
increase
Figure 17b isthe
ofisthethe corresponding
output simulation
power, thesimulation
corresponding waveform
waveforms. The
of the ig rises
waveforms. RMS
RMSvalue
significantly.
The ofiiggpower
of
valueThe is 4.5 A.
is 4.5 A. Along
factor withand
is 0.99
Along with theincrease
the increase
THD ofofthe
is down the
to output power,
1.8%.power,
output The thethe
efficiencywaveform
of the
waveform
of ig irises
ofinverter
the
the significantly.
is 96.1%
g rises The
The power
at this moment.
significantly. power factor is 0.99
factor is 0.99and
andTHD
THDisisdown
downtoto1.8%.
1.8%. The
The efficiency
efficiency of the
of the
inverter
inverter isis96.1%
96.1%atatthis
thismoment.
moment.

(a) (b)
(a) (b)
Figure 17. Experimental waveforms of the inverter at rated power: (a) experiment waveform; and
(b) simulation
Figure waveform.waveforms of the inverter at rated power: (a) experiment waveform; and
17. Experimental
Figure 17. Experimental waveforms of the inverter at rated power: (a) experiment waveform; and
(b) simulation waveform.
(b)Figure
simulation waveform.
18a shows the waveforms of the switch voltage and grid current at rated power of 1 kW.
Figure 18b is
Figure theshows
18a partial
theenlarged
waveforms waveform of Figure
of the switch 18a. and
voltage ig is grid
the grid current.
current vDS power
at rated is the drain-to-
of 1 kW.
Figure
source
Figure 18b18a
voltage shows
of
is the the
the switch
partial waveforms is the of
S1. vGSwaveform
enlarged the
drive switch
ofsignal Svoltage
of 18a.
Figure 1. Asig theand gridcurrent.
waveform
is the grid current
shows,vDSatisrated
when ispower
above of
theigdrain-to-
1 kW.
zero,Figure
S is 18b
switchedis the
at partial
high enlarged
frequency of waveform
400 kHz. Theof Figure
voltage
source voltage of the switch S1. vGS is the drive signal S1. As the waveform
1 18a.
stress i
ofg is
S 1 the
is grid
400 V; current.
when i
shows, when ig above
g isv DS is the
below
zero, S1 is closed.
drain-to-source voltage
switched at of
high switch S1of
thefrequency . vGS
400iskHz.
the drive signal of
The voltage S1 . As
stress of Sthe
1 is waveform
400 V; when shows, when ig
ig is below
is zero,
aboveThe isrelationships
S1zero,closed. between
S1 is switched efficiency,
at high frequencyTHD ofversus the The
400 kHz. output power
voltage are shown
stress of S1 isin400
Figure
V; when19a,b,ig is
respectively.
below The S1 The
zero,relationshipsTHDbetween
is closed. decreases from 4.8%
efficiency, THDto 1.8% when
versus the output
the output power power growsin
are shown from 10019a,b,
Figure W to
1000 W, while
respectively.
The relationships the efficiency
The THDbetween
decreasesincreases
from 4.8%
efficiency, from
THD 85.2%
to 1.8% to
when
versus 96.1%.
the the Finally,
output
output power the
power efficiency
aregrows
shown fromreaches
100 Wthe
in Figure to
19a,b,
maximum
1000 W, while
respectively. efficiency
The the
THD of 96.1%
efficiency
decreases at rated
increases
from 4.8%power. Thus,
fromto85.2% in small
to 96.1%.
1.8% when renewable
Finally, power
the output energy application,
the efficiency
grows from reaches 100the
W to
proposed
maximum
1000 W, while inverter achieves
efficiency
the efficiency an excellent
of 96.1% at rated
increases from performance,
power.
85.2% to including
Thus, in small
96.1%. relatively
Finally, renewable high
the efficiency conversion
energy efficiency,
application,
reaches the the
maximum
high power
proposed factor achieves
inverter and low THD.
an excellent performance, including relatively high conversion efficiency,
efficiency of 96.1% at rated power. Thus, in small renewable energy application, the proposed inverter
high power
achieves factor and
an excellent low THD. including relatively high conversion efficiency, high power factor
performance,
and low THD.
Energies 2017, 10, 311 15 of 18
Energies 2017, 10, 311 15 of 18
Energies 2017, 10, 311 15 of 18

(a) (b)
(a) (b)
Figure 18. Experimental waveforms: (a) Waveform of the switch voltage and grid current at rated
Figure 18.
Figure Experimental waveforms:
18. Experimental waveforms: (a)
(a)Waveform
Waveform of of the
the switch
switch voltage
voltage and
and grid
grid current
current at
at rated
rated
power; and (b) partial enlarged waveform of the switch voltage and grid current.
power; and
power; and (b)
(b) partial
partial enlarged
enlarged waveform
waveform of
of the
the switch
switch voltage
voltage and
and grid
grid current.
current.

(a) (b)
(a) (b)
Figure 19. Efficiency and grid current THD curves: (a) efficiency under different power level; and (b)
Figure 19. Efficiency and grid current THD curves: (a) efficiency under different power level; and (b)
Figure 19. Efficiency
THD under different and grid
power current THD curves: (a) efficiency under different power level; and
level.
THD under different power level.
(b) THD under different power level.
5.2. Comparison Experiments of Power Loss
5.2. Comparison Experiments of Power Loss
5.2. Comparison Experiments of Power Loss
The comparative experiments are set up in order to verify the loss analyses in Section 3. The
The comparative experiments are set up in order to verify the loss analyses in Section 3. The
powerThedevices
comparative experiments
of Prototype 1 areare
allset
SiCuppower
in order to verifyThe
devices. thefree-wheeling
loss analyses indiodes
SectionD3.1 and
The power
D2 are
power devices of Prototype 1 are all SiC power devices. The free-wheeling diodes D1 and D2 are
devices
replacedofby
Prototype
normal Si1 are all SiC
diodes power devices.
on Prototype 2. All The free-wheeling
the power devices diodes D1 and
are replaced byDnormal
2 are replaced by
Si devices
replaced by normal Si diodes on Prototype 2. All the power devices are replaced by normal Si devices
normal Si diodes
on Prototype on Prototype
3. The 2. All used
power devices the power devices
in each are replaced
Prototype by normal
are shown in TableSi3.devices on Prototype
on Prototype 3. The power devices used in each Prototype are shown in Table 3.
3. The power devices used in each Prototype are shown in Table 3.
Table 3. Power Devices of the Prototype.
Table 3. Power Devices of the Prototype.
Table 3. Power Devices of the Prototype.
Prototype D 1, D 2 S1–S4
Prototype D 1, D 2 S1–S4
1
Prototype CVFD20065A
D1 , D2 C2M0280120D
S1 –S4
1 CVFD20065A C2M0280120D
2 BYV29-600 C2M0280120D
12 CVFD20065A C2M0280120D
BYV29-600 C2M0280120D
2 3 BYV29-600
BYV29-600 IPW60R040C7
C2M0280120D
3 BYV29-600 IPW60R040C7
3 BYV29-600 IPW60R040C7
The efficiency curves of the comparison experiments are shown in Figure 20. Prototype 1, which
The efficiency curves of the comparison experiments are shown in Figure 20. Prototype 1, which
uses power devices that are full comparison
SiC components, reaches theshown rated power at 1 kW. When the
uses The
power efficiency
devicescurves
that are of full
the SiC components, experiments
reaches are the rated power in Figureat 120.kW.Prototype
When the 1,
temperature
which uses of
power the components
devices that is
are stable,
full SiC the efficiency
components, of Prototype
reaches the 1 is
rated96.1%.
power Prototype
at 1 kW. 2, in which
When the
temperature of the components is stable, the efficiency of Prototype 1 is 96.1%. Prototype 2, in which
the diodes are
temperature replaced with Si diodes, reaches the rated power of 1 kW. However, the Si diodes break
the diodes areofreplaced
the components is stable,
with Si diodes, the efficiency
reaches the ratedof Prototype
power of 1 kW. 1 isHowever,
96.1%. Prototype 2, in which
the Si diodes break
down within
the diodes one
areone minute.
replaced The
withThe efficiency
Si diodes, reaches of Prototype 2
the rated 2powerat 1 kW
of 1 isis
kW. 91.83%.
However, The voltage v diode and
down within minute. efficiency of Prototype at 1 kW 91.83%. Thethe Si diodes
voltage vdiodebreak
and
current
down idiode waveforms
within one minute.of the
The free-wheeling
efficiency of diode D1 at2 150
Prototype at 1WkW in is
Prototype
91.83%. 1The
andvoltage
2 are compared
v in
current idiode waveforms of the free-wheeling diode D1 at 150 W in Prototype 1 and 2 are compared diode andin
Figure 21.
current Prototype
idiode waveforms 3 has the highest efficiency when the150
D1 the output power is low because the Si power
Figure 21. Prototype 3 hasofthe
thehighest
free-wheeling
efficiency diode
when at W inpower
output Prototypeis low1 and 2 arethe
because compared
Si power in
devices
Figure used
21. in the
Prototype experiment
3 has the have
highest a lower
efficiency conduction
when the loss
outputthan the
power SiC.
is When
low the
because output
the Si power
power
devices used in the experiment have a lower conduction loss than the SiC. When the output power
rises, Prototype
devices used in 3the3 reaches the highest
experiment efficiency
have aefficiency of 88.9% loss
lower conduction at 500 W. the
Then, the efficiency of Prototype
rises, Prototype reaches the highest of 88.9% at 500than
W. Then, SiC.theWhen the output
efficiency power
of Prototype
3 starts to decrease and the Si switches break down at 600 W. The efficiency of Prototype 3 at 1 kW
3rises, Prototype
starts to decrease 3 reaches
and the theSihighest
switches efficiency
break down of 88.9%
at 600at W.
500 The
W. Then, the efficiency
efficiency of Prototype
of Prototype 3 at 1 kW3
cannot be measured. The experiment proves that the Si power devices are not suitable for high
cannot be measured. The experiment proves that the Si power devices are not suitable for high
switching frequency application.
switching frequency application.
Energies 2017, 10, 311 16 of 18

starts to decrease and the Si switches break down at 600 W. The efficiency of Prototype 3 at 1 kW cannot
be measured. The experiment proves that the Si power devices are not suitable for high switching
frequency
Energies 2017,application.
10, 311 16 of 18

Energies 2017, 10, 311 16 of 18

Figure 20.
Figure 20. Efficiency
Efficiency comparison.
comparison.
Figure 20. Efficiency comparison.

(a)
(a) (b)
(b)
Figure 21.21.
Figure Voltage
Voltageand
andcurrent
currentwaveforms
waveformsof of the
the free-wheeling diodeDD1:1:(a)
free-wheeling diode (a)switching
switchingtransition
transition
ofof
Figure 21. Voltage and current waveforms of the free-wheeling diode D1 : (a) switching transition of
SiCSiC diode;
diode; andand
(b)(b) switchingtransition
switching transitionof
ofSi
Sidiode.
diode.
SiC diode; and (b) switching transition of Si diode.

AsAs Figure
Figure 21bshows,
21b shows,during
duringthe theturn-on
turn-on and
and turn-off
turn-off procedure,
procedure,the thevoltage
voltageand andcurrent
currentofof thethe
Si diode in Prototype 2 have a large overlap area and big reverse recovery current, which means the
Si As Figure
diode in 21b shows,
Prototype 2 during
have a largethe turn-on
overlap and
area turn-off
and big procedure,
reverse recovery the voltage
current, and
which current
means of
thethe
Si diode inlosses
switching
switching Prototype
losses ofof the
the 2diodes
have are
diodes aare
large
veryoverlap
very area and big
large.Comparing
large. Comparing with
withreverse
the
the Si recovery
Sidiode
diode current,
(Figure
(Figure 21a), which
21a),the
theSiC
SiC means
diode
diode
the switching
has a faster losses
switchingof the diodes
speed, which are very large.
contributes to Comparing
a low with
switching
has a faster switching speed, which contributes to a low switching loss. Remarkably, the reverse the
loss. Si diode
Remarkably, (Figure
the 21a),
reverse the
SiC
recovery current of the SiC diode is not zero in the measured high frequency waveforms, but the
diode
recovery has a
currentfaster
of switching
the SiC diodespeed,
is notwhich
zero contributes
in the to
measured a low
high switching
frequency loss. Remarkably,
waveforms, but thethe
reverse
reverse recoverycurrent
recovery loss is significantly
of the SiC smalleristhan
diode not Si
zerodiodein due
the to the extremely
measured high short reverse
frequency recovery
waveforms,
reverse recovery loss is significantly smaller than Si diode due to the extremely short reverse recovery
buttime.
the reverse recovery loss is significantly smaller than Si diode due to the extremely short reverse
time.
recovery The comparisons of experiment and calculation efficiencies are shown in Table 4. For prototype
The time.
comparisons of experiment and calculation efficiencies are shown in Table 4. For prototype
1, the
The calculation
comparisons efficiency at 1 kWand
of experiment is 97.32% and the
calculation corresponding
efficiencies are shownexperiment
in Table efficiency is 96.1%. 1,
4. For prototype
1, the calculation efficiency at 1 kW is 97.32% and the corresponding experiment efficiency is 96.1%.
theThe deviation between experiment and calculation is 1.02% which may be caused by the unmeasured
Thecalculation efficiency
deviation between at 1 kW is
experiment and 97.32% and the
calculation corresponding
is 1.02% which may experiment
be caused by efficiency is 96.1%.
the unmeasured
Thelosses such between
deviation as the losses on the relay,
experiment and fuse and so
calculation is on.
1.02%Thewhich
calculation
may beefficiency
caused of the
by Prototype
unmeasured 2 is
losses such as the losses on the relay, fuse and so on. The calculation efficiency of Prototype 2 is
93.57%
losses such and
asthethelosses
the experiment efficiency
on theefficiency
relay, fuseat at
and1 kW
so on.is The
91.83%. The deviation
calculation efficiency of of
Prototype
Prototype 2 2is is1.74%.
93.57%
Because andthe experiment
efficiency experiment of Prototype 1 kW 2 is
does 91.83%. Thea deviation
not reach temperature of stable
Prototype 2 is 93.57%
state before 1.74%.
the
and the
Because experiment
the efficiency efficiency
experimentat 1 kW
of is 91.83%.
Prototype 2 The
does deviation
not reach of
a Prototype
temperature 2 is 1.74%.
stable stateBecause
before the
the
Si diodes breaks down, the unstable state of the main circuit may cause extra loss in Prototype 2.
efficiency
Si Prototype experiment
diodes breaks down, of Prototype
the the
unstable 2 does not
state ofand reach
thebreaks a temperature
main circuit may stable state before the Si diodes
3 cannot reach rated power down at 600cause
W duringextra thelossexperiment;
in Prototype its 2.
breaks
Prototypedown, 3 the unstable
cannot reach staterated
the of the main and
power circuit may down
breaks cause extra
at 600 loss
W in Prototype
during the 2. Prototypeits
experiment; 3
efficiency is 88.9% at 500 W. Finally, the deviation between experiment and calculation efficiency is
cannot reach
efficiency the rated
is 88.9% atrange, power
500 W. and breaks
Finally, down
thethat at
deviation 600 W
between during the experiment; its efficiency is 88.9%
within acceptable which proves the proposed lossexperiment
calculation and calculation
methodology efficiency is
is valid.
at
within acceptable range, which proves that the proposed loss calculation methodology is acceptable
500 W. Finally, the deviation between experiment and calculation efficiency is within valid.
range, which proves that the proposed loss calculation methodology is valid.
Energies 2017, 10, 311 17 of 18

Table 4. Experiment and calculation efficiency.

Calculation Efficiency Experiment Efficiency

Prototype Deviation
(1 kW) (1 kW)
1 97.32% 96.1% 1.22%
2 93.57% 91.83% 1.74%
3 85.27% 88.9% (at 500 W) Unknown

6. Conclusions
A 400 kHz dual-buck full-bridge inverter is proposed for small power renewable energy
gird-connected generation. A current voltage dual-loop control strategy is employed, including
a 3P3Z compensator in the inner current loop and a 2P2Z compensator in the outer voltage loop.
Consequently, the inverter can deliver grid-tie power and regulate the DC bus voltage simultaneously.
A systematic method for calculating the losses of high frequency inverter is presented. The influences of
high frequency switching on loss analysis are discussed in detail. The loss distribution of the proposed
inverter is obtained through the presented method. The simulation error, which is cause by the
deviation between PWM control signal and switching response, is thoroughly analyzed. An improved
simulation method is proposed in order to minimize the deviation which is caused by the delays of
the switch in high frequency switching procedure. The loss analysis and simulation method are both
validated by corresponding experiments. Finally, the power experiment of the inverter is finished at
rated power of 1 kW, with the power factor above 0.99 and THD of 1.8%. The adoption of SiC power
devices contributes to the highest efficiency of 96.1% at rated power. The experiment results prove that
the proposed loss calculation method and improved simulation method is effective and suitable for
high frequency inverter.

Acknowledgments: This research was supported by the National Natural Science Foundation of China
(Grant: 2015AA050603) and supported by Tianjin Municipal Science and Technology Commission (Grant:
14ZCZDGX00035). The authors would also like to thank the anonymous reviewers for their valuable comments
and suggestions to improve the quality of the paper.
Author Contributions: Zhun Meng and Yi-Feng Wang designed the main parts of the study. Liang Yang and
Wei Li helped in the fabrication.
Conflicts of Interest: The authors declare no conflict of interest.

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