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LOGIC DIAGRAMS
NOR NAND OR AND
1 1 1 1
3 3 3 3
2 2 2 2
5 5 5 5
2 INPUT
4 4 4 4
6 6 6 6
8 8 8 8
10 10 10 10
9 9 9 9
12 12 12 12
11 11 11 11
13 13 13 13
1 1 1 2
2 9 2 9 2 9
3 1
8 8 8
4
3 INPUT
3 3 3 5
4 6 4 6 4 6 9
5 5 5
10 13
11 11 11 11
12 10 12 10 12 10 12
13 13 13 NC = 6, 8
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001B MC14011B MC14023B MC14025B
Quad 2−Input NOR Gate Quad 2−Input NAND Gate Triple 3−Input NAND Gate Triple 3−Input NOR Gate
NC = NO CONNECTION
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2
MC14001B Series
VDD Typ
Characteristic Symbol Vdc Min Max Min (Note 2) Max Min Max Unit
Output Voltage “0” Level VOL 5.0 − 0.05 − 0 0.05 − 0.05 Vdc
Vin = VDD or 0 10 − 0.05 − 0 0.05 − 0.05
15 − 0.05 − 0 0.05 − 0.05
“1” Level VOH 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc
Vin = 0 or VDD 10 9.95 − 9.95 10 − 9.95 −
15 14.95 − 14.95 15 − 14.95 −
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 − 1.5 − 2.25 1.5 − 1.5
(VO = 9.0 or 1.0 Vdc) 10 − 3.0 − 4.50 3.0 − 3.0
(VO = 13.5 or 1.5 Vdc) 15 − 4.0 − 6.75 4.0 − 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 − 3.5 2.75 − 3.5 −
(VO = 1.0 or 9.0 Vdc) 10 7.0 − 7.0 5.50 − 7.0 −
(VO = 1.5 or 13.5 Vdc) 15 11 − 11 8.25 − 11 −
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 –3.0 − –2.4 –4.2 − –1.7 −
(VOH = 4.6 Vdc) 5.0 –0.64 − –0.51 –0.88 − –0.36 −
(VOH = 9.5 Vdc) 10 –1.6 − –1.3 –2.25 − –0.9 −
(VOH = 13.5 Vdc) 15 –4.2 − –3.4 –8.8 − –2.4 −
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc
(VOL = 0.5 Vdc) 10 1.6 − 1.3 2.25 − 0.9 −
(VOL = 1.5 Vdc) 15 4.2 − 3.4 8.8 − 2.4 −
Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
(Vin = 0)
Quiescent Current IDD 5.0 − 0.25 − 0.0005 0.25 − 7.5 mAdc
(Per Package) 10 − 0.5 − 0.0010 0.5 − 15
15 − 1.0 − 0.0015 1.0 − 30
Total Supply Current (Notes 3, 4) IT 5.0 IT = (0.3 mA/kHz) f + IDD/N mAdc
(Dynamic plus Quiescent, 10 IT = (0.6 mA/kHz) f + IDD/N
Per Gate, CL = 50 pF) 15 IT = (0.9 mA/kHz) f + IDD/N
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
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3
MC14001B Series
14 VDD 20 ns 20 ns
VDD
INPUT 90%
INPUT 50%
PULSE 10% 0V
OUTPUT tPHL tPLH
GENERATOR
CL 90% VOH
* 50%
OUTPUT 10%
INVERTING VOL
tTHL tTLH
tPLH tPHL
7 VSS OUTPUT VOH
90%
NON-INVERTING 50%
*All unused inputs of AND, NAND gates must be connected to VDD. 10% VOL
All unused inputs of OR, NOR gates must be connected to VSS. tTLH tTHL
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4
MC14001B Series
CIRCUIT SCHEMATIC
NOR, OR GATES
VDD VDD
14 VDD
1, 6, 8, 13 1, 3, 11
*
2, 5, 9, 12 2, 4, 12
14 VDD
3, 4, 10, 11
VSS
7 VSS 9, 6, 10
VSS
VDD
*Inverter omitted in MC14001B
8, 5, 13
7 VSS
VSS
*Inverter omitted in MC14025B
CIRCUIT SCHEMATIC
NAND, AND GATES
3, 4, 10, 11
2, 4, 12 14 VDD 2, 5, 9, 12
1, 3, 11 1, 6, 8, 13
VSS 7 VSS
* *Inverter omitted in MC14011B
VDD
9, 6, 10
8, 5, 13
7 VSS
VSS
*Inverter omitted in MC14023B
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5
MC14001B Series
20 - 50
18 - 45
TA = - 55°C
16 - 40
ID , DRAIN CURRENT (mA)
14 - 40°C - 35
12 + 25°C - 30 TA = - 55°C
+ 85°C
10 - 25 - 40°C
8.0 + 125°C - 20 + 25°C
+ 85°C
6.0 - 15
4.0 - 10 + 125°C
2.0 - 5.0
0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 - 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10
VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
50 - 100
45 - 90
40 - 80
ID , DRAIN CURRENT (mA)
35 TA = - 55°C - 70
30 - 40°C - 60
TA = - 55°C
25 + 25°C - 50 - 40°C
20 + 85°C - 40 + 25°C
+ 125°C + 85°C
15 - 30
+ 125°C
10 - 20
5.0 - 10
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0 - 2.0 - 4.0 - 6.0 - 8.0 - 10 - 12 - 14 - 16 - 18 - 20
VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
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6
MC14001B Series
4.0 8.0
SINGLE INPUT NOR, OR SINGLE INPUT NOR, OR
3.0 MULTIPLE INPUT NAND, AND 6.0 MULTIPLE INPUT NAND, AND
2.0 4.0
1.0 2.0
0 0
0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)
16 DC NOISE MARGIN
SINGLE INPUT NAND, AND
14 MULTIPLE INPUT NOR, OR The DC noise margin is defined as the input voltage range
V out , OUTPUT VOLTAGE (Vdc)
12 from an ideal “1” or “0” input level which does not produce
SINGLE INPUT NOR, OR output state change(s). The typical and guaranteed limit
10 MULTIPLE INPUT NAND, AND values of the input values VIL and VIH for the output(s) to
8.0
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
6.0 in Figure 11.
Guaranteed minimum noise margins for both the “1” and
4.0
“0” levels =
2.0 1.0 V with a 5.0 V supply
0 2.0 V with a 10.0 V supply
0 2.0 4.0 6.0 8.0 10
2.5 V with a 15.0 V supply
Vin, INPUT VOLTAGE (Vdc)
VO VO
VO VO
VDD VDD
0 Vin 0 Vin
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7
MC14001B Series
ORDERING INFORMATION
Device Package Shipping†
MC14001BDG SOIC−14
55 Units / Rail
NLV14001BDG* (Pb−Free)
MC14001BDR2G SOIC−14
NLV14001BDR2G* (Pb−Free)
2500 Units / Tape & Reel
MC14001BDTR2G TSSOP−14
NLV14001BDTR2G* (Pb−Free)
MC14001BFELG SOEIAJ−14
2000 Units / Tape & Reel
(Pb−Free)
MC14011BDG SOIC−14
55 Units / Rail
NLV14011BDG* (Pb−Free)
MC14011BDR2G SOIC−14
NLV14011BDR2G* (Pb−Free)
2500 Units / Tape & Reel
MC14011BDTR2G TSSOP−14
NLV14011BDTR2G* (Pb−Free)
MC14023BDG SOIC−14
55 Units / Rail
(Pb−Free)
MC14023BDR2G SOIC−14
2500 Units / Tape & Reel
NLV14023BDR2G* (Pb−Free)
MC14023BFELG SOEIAJ−14
2000 Units / Tape & Reel
(Pb−Free)
MC14025BDG SOIC−14
55 Units / Rail
NLV14025BDG* (Pb−Free)
MC14025BDR2G SOIC−14
2500 Units / Tape & Reel
NLV14025BDR2G* (Pb−Free)
MC14071BDG SOIC−14
55 Units / Rail
NLV14071BDG* (Pb−Free)
MC14071BDR2G SOIC−14
2500 Units / Tape & Reel
NLV14071BDR2G* (Pb−Free)
MC14073BDG SOIC−14
55 Units / Rail
(Pb−Free)
MC14073BDR2G SOIC−14
2500 Units / Tape & Reel
(Pb−Free)
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8
MC14001B Series
MC14081BDR2G SOIC−14
NLV14081BDR2G* (Pb−Free)
2500 Units / Tape & Reel
MC14081BDTR2G TSSOP−14
NLV14081BDTR2G* (Pb−Free)
MC14082BDG
SOIC−14 55 Units / Rail
NLV14082BDG*
(Pb−Free)
MC14082BDR2G 2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
14 CASE 751A−03
1
ISSUE L
DATE 03 FEB 2016
SCALE 1:1
D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
0.10 L 0.40 1.25 0.016 0.049
e A1 M
SEATING M 0_ 7_ 0_ 7_
C PLANE
GENERIC
SOLDERING FOOTPRINT* MARKING DIAGRAM*
6.50 14X 14
1.18
XXXXXXXXXG
1 AWLYWW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
TSSOP−14 WB
CASE 948G
14 ISSUE C
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF NOTES:
1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
−U− N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IDENT. F IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 7
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
0.15 (0.006) T U S
A K
MILLIMETERS INCHES
K1
ÉÉÉ
ÇÇÇ
−V− DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
ÇÇÇ
ÉÉÉ
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT XXXX
XXXX
7.06
ALYWG
G
1 1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
0.65 G = Pb−Free Package
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
14X
device data sheet for actual part marking.
14X Pb−Free indicator, “G” or microdot “G”, may
0.36
1.26 or may not be present. Some products may
DIMENSIONS: MILLIMETERS
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASH70246A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.