Chapter Four

Combinational Logic Circuits

Outlines
➢ Definition of combinational circuit
➢ Adder
➢ Subtractor
➢ Encoder
➢ Decoder
➢ Multiplexer
➢ Demultiplexer
Definition of combinational circuit
➢ Combinational logic circuits are circuits that contain different types of logic gates.

Simply, a circuit in which different types of logic gates are combined is known as
a combinational logic circuit.

➢ The output of the combinational circuit is determined from the present

combination of inputs, regardless of the previous input.

➢ The input variables, logic gates, and output variables are the basic components of
the combinational logic circuit.

➢ There are different types of combinational logic circuits, such as Adder, Subtractor,
Decoder, Encoder, Multiplexer, and De-multiplexer.

There are the following characteristics of the combinational logic circuit:

o At any instant of time, the output of the combinational circuits depends only on
the present input terminals.

o The combinational circuit doesn't have any backup or previous memory. The
present state of the circuit is not affected by the previous state of the input.
Half Adder
➢ The half adder is a basic building block having two inputs and two outputs. The
adder is used to perform OR operation of two single-bit binary numbers.

The carry and sum are two output states of the half adder.

Block diagram

Truth Table

➢ The SOP form of the sum and carry are as follows:

Sum=A'B+AB'
Carry = AB
Construction of Half Adder Circuit:
➢ In the block diagram, we have seen that it contains two inputs and two outputs.

The A and B bits are the input states, and carry and sum are the output states of
the half adder.

➢ The half adder is designed with the help of the following two logic gates:

1. 2-input AND Gate.

2. 2-input Exclusive-OR Gate or Ex-OR Gate

1. 2-input Exclusive-OR Gate or Ex-OR Gate

➢ The Sum bit is generated with the help of the Exclusive-OR or Ex-OR Gate.

➢ In the above diagram, 'A' and 'B' are the inputs, and the 'SUMOUT' is the final
outcome after performing the XOR operation of both numbers.
 ➢ The truth table of the EX-OR gate is as follows:

➢ From the above table, it is clear that the XOR gate gives result 1 when both of the inputs
are different. When both of the inputs are the same, the XOR gives the result 0.

2. 2-input AND Gate:

➢ The XOR gate is unable to generate the carry bit. For this purpose, we use another
gate called AND Gate. The AND gate gives the correct result of the carry.

➢ In the above diagram, 'A' and 'B' are the inputs, and 'OUT' is the final outcome after

performing AND operation of both numbers.

 ➢ There is the following truth table of AND Gate:

➢ From the above table, it is clear that the AND gate gives the result 1 when both of the
inputs are 1. When both of the inputs are different and 0, the AND gates give the result
0.

Half-Adder logical circuit:

➢ So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and

provide the sum and carry.

 ➢ There is the following Boolean expression of Half Adder circuit:

Sum= A XOR B =A ⊕B
Carry= A AND B= A.B

Half Subtractors
➢ The half subtractor is also a building block for subtracting two binary numbers.

➢ It has two inputs and two outputs. This circuit is used to subtract two single-bit
binary numbers A and B. The 'diff' and 'borrow' are the two-output state of the

half adder.

Block diagram

Truth Table
 ➢ The SOP form of the Diff and Borrow is as follows:

Diff= A'B+AB'

Borrow = A'B

Construction of Half Subtractor Circuit

➢ In the block diagram, we have seen that it contains two inputs and two outputs.
The Diff and Borrow are the output states of the half subtractor. The half
subtractor is designed with the help of the following logic gates:

1. 2-input AND gate.

2. 2-input Exclusive-OR Gate or Ex-OR Gate
3. NOT or inverter Gate

1. 2-input Exclusive-OR Gate or Ex-OR Gate

The Diff bit is generated with the help of the Exclusive-OR or Ex-OR gate

➢ The above is the symbol of the EX-OR gate. In the above diagram, 'A' and 'B' are
the inputs, and 'Diff' is the final outcome after performing the XOR operation of

both numbers.
➢ The truth table of the EX-OR gate is as follows:
 ➢ From the above table, it is clear that the XOR gate gives the result 1 when both of
the inputs are different. When both of the inputs are the same, the XOR gives the

result 0.

2. 2-input AND gate:

➢ The XOR gate is unable to generate the carry bit. For this purpose, we use another
gate called AND gate.

➢ The AND gate is not enough to give the correct result of 'Borrow'. We will use
the NOT gate with the 'AND' gate to get the correct result.

The above is the symbol of the AND gate. In the above diagram, 'A' and 'B' are the inputs,
and 'OUT' is the final outcome after performing AND operation of both numbers.

There is the following truth table of AND gate:

 ➢ From the above table, it is clear that the AND gate gives the result 1 when both of the
inputs are 1. When both of the inputs are different and 0, the AND gates gives the result
0.

3. NOT or Inverter Gate:

➢ The NOT gate is used to get the inverse output.
➢ We can combine the 'AND' and 'NOT' gates in order to get the combinational gate
'NAND'.

➢ By inverting the input 'A' using 'NOT' gate and then use the output of the 'NOT'
gate as the input of the 'AND' gate, we can get the 'Borrow' bit.
Half-Subtractor logical circuit
➢ So, the Half Subtractor is designed by combining the 'XOR', 'AND', and 'NOT' gates
and provide the Diff and Borrow.

➢ The Boolean expression of the Half Adder circuit is given below:

Diff= A XOR B (A⊕B)

Borrow= not-A AND B (A’. B)

Decoder
➢ A decoder is a combinational circuit having n inputs and to a maximum of m = 2 n
outputs.

➢ The combinational circuit that change the binary information into 2N output lines is known
as Decoders.
➢ The binary information is passed in the form of N input lines. The output lines define the
2N-bit code for the binary information.

There are various types of decoders which are as follows:

2 to 4-line decoder:
➢ In the 2 to 4-line decoder, there is a total of three inputs, i.e., A0, and A1 and E and
four outputs, i.e., Y0, Y1, Y2, and Y3.
➢ For each combination of inputs, when the enable 'E' is set to 1, one of these four
outputs will be 1.
➢ The block diagram and the truth table of the 2 to 4-line decoder are given below.
Block Diagram:

Truth Table:

➢ The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

Y3=E.A1.A0
Y2=E.A1.A0'

Y1=E.A1'.A0
Y0=E.A1'.A0'
 ➢ Logical circuit of the above expressions is given below:

Encoder
➢ The combinational circuits that change the binary information into N output lines
are known as Encoders.
➢ The binary information is passed in the form of 2N input lines. The output lines

define the N-bit code for the binary information.

➢ In simple words, the Encoder performs the reverse operation of the Decoder. At a

time, only one input line is activated for simplicity. The produced N-bit output code
is equivalent to the binary information.
There are various types of encoders which are as follows:

4 to 2-line Encoder:
➢ In 4 to 2-line encoder, there are total of four inputs, i.e., Y0, Y1, Y2, and Y3, and two
outputs, i.e., A0 and A1. In 4-input lines, one input-line is set to true at a time to get
the respective binary code in the output side.

➢ Below are the block diagram of the 4 to 2-line encoder.

Block Diagram:
Multiplexers
➢ The multiplexer is a combinational circuit that has n-data inputs and a single

output. It is also known as the data selector which selects one input from the
inputs and routes it to the output. With the help of the selected inputs, one input

line from the n-input lines is selected. The enable input is denoted by E, which is
used in cascade.

➢ A multiplexer is a combinational circuit that has 2n input lines and a single output
line. Simply, the multiplexer is a multi-input and single-output combinational

circuit.
➢ The binary information is received from the input lines and directed to the output

line. On the basis of the values of the selection lines, one of these data inputs will
be connected to the output.

➢ Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there
is a total of 2N possible combinations of inputs. A multiplexer is also treated

as Mux.
➢ There are various types of the multiplexer which are as follows:

2×1 Multiplexer:
➢ In 2×1 multiplexer, there are only two inputs, i.e., A 0 and A1, 1 selection line, i.e.,
S0 and single outputs, i.e., Y.

➢ On the basis of the combination of inputs which are present at the selection line
S0, one of these 2 inputs will be connected to the output. The block diagram and

the truth table of the 2×1 multiplexer is given below.

 Block Diagram:

Truth Table:

➢ The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

➢ Logical circuit of the above expression is given below:

4×1 Multiplexer:
➢ In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and A3, 2
selection lines, i.e., S0 and S1 and single output, i.e., Y.
➢ On the basis of the combination of inputs that are present at the selection lines

S0 and S1, one of these 4 inputs are connected to the output.

➢ The block diagram and the truth table of the 4×1 multiplexer are given below.
Block Diagram:

Truth Table:

➢ The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

➢ Logical circuit of the above expression is given below:

De-multiplexers
➢ A De-multiplexer is a combinational circuit that has only 1 input line and 2N output
lines.

➢ Simply, the multiplexer is a single-input and multi-output combinational circuit.

The information is received from the single input lines and directed to the output

line.
➢ On the basis of the values of the selection lines, the input will be connected to one
of these outputs. De-multiplexer is opposite to the multiplexer.
➢ Unlike encoder and decoder, there are n selection lines and 2 n outputs. So, there

is a total of 2n possible combinations of inputs. De-multiplexer is also treated

as De-mux.
1×2 De-multiplexer:
➢ In the 1 to 2 De-multiplexers, there are only two outputs, i.e., Y0, and Y1, 1 selection
lines, i.e., S0, and single input, i.e., A.
➢ On the basis of the selection value, the input will be connected to one of the

outputs. The block diagram and the truth table of the 1×2 multiplexer are given

below.

Block Diagram:

Truth Table:
➢ The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A

➢ Logical circuit of the above expressions is given below: