Digital Integrated Circuits (ENCS333) – HW3

JERIES SHEHADEH 1180519

Part 1: CMOS 2-input NAND gate using CMOS 0.35um Process

The NAND gate was built and simulated using PSPICE with CMOS 0.35um process. The
processes were acquired from the following spice models. The following information were added
to obtain a 0.35um process:
For NMOS:
.MODEL MbreakN-X NMOS LEVEL = 3
+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5
+ PHI = 0.7 VTO = 0.8 DELTA = 3.0
+ UO = 650 ETA = 3.0E-6 THETA = 0.1
+ KP = 120E-6 VMAX = 1E5 KAPPA = 0.3
+ RSH = 0 NFS = 1E12 TPG = 1
+ XJ = 500E-9 LD = 100E-9
+ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10
+ CJ = 400E-6 PB = 1 MJ = 0.5 10
+ CJSW = 300E-12 MJSW = 0.5

For PMOS:
.MODEL MbreakP-X PMOS LEVEL = 3
+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6
+ PHI = 0.7 VTO = -0.9 DELTA = 0.1
+ UO = 250 ETA = 0 THETA = 0.1
+ KP = 40E-6 VMAX = 5E4 KAPPA = 1
+ RSH = 0 NFS = 1E12 TPG = -1
+ XJ = 500E-9 LD = 100E-9 12
+ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10
+ CJ = 400E-6 PB = 1 MJ = 0.5
+ CJSW = 300E-12 MJSW = 0.5

After acquiring the process models, the NAND gate design was constructed and its PMOS and
NMOS were sized to get an equal rise and fall time. The devices were simulated and the layout
of the NAND gate design was constructed through a process file marked with cmos.035.rul. Next
a process file tagged with cmos22n.rul was used to migrate the 22nm technology and
accommodate any distance changes between the components. After the migration and design
check for any violations of design ruleswere completed the layout design was finally simulated
to assess its timing (rise and fall) profile. Snapshots of the work are found below:
 Fig 1: Schematics of the designed NAND gate

Fig 2: NAND gate PMOS & NMOS Simulation

Fig 2: CMOS 0.35um NAND Gate Layout Design

 Fig 4: NAND Layout Timing Profile (Simulation)

Part 2: 2-Bit Full Adder CMOS Design

A truth table was used to acquire a gate level representation of the design. The design was gate
level constructed using the DSCH tool and simulated. A Verilog file was extracted from the
design and compiled using a 0.35um CMOS process file delivering a layout for the design which
was finally simulated to assess its timing profile. Snapshots of the work are found below:

Fig 5: 2 Bit Full Adder Truth Table

Fig 6: Gate Level Design – DSCH

 Fig 7: Design Layout – Microwind

Fig 7: Design Layout Simulation (Timing Profile)