ASIC and FPGA

SESSION-1

Dr. Aditya Japa

Assistant professor (ECE)
KL Hyderabad
26/12/2021
Course Objectives
• CO1: Study and design of combinational and sequential circuits using PLDs and
state machines

• CO2: Understand full-custom and semi-custom design methodologies for

designing different PLD architectures

• CO3: To study PLD structures and design process. Study of different CPLD and
FPGA architectures

• CO4: To understand physical process

Course instructor
Name: Dr. Japa Aditya

Qualification: Ph.D. From IIIT Naya Raipur.

Research work: Tunnel FET based Energy Efficient Circuit Design with Enhanced
Hardware security.

Teaching interests: Circuits and Systems for VLSI, Cryptography and hardware security.

Research interests: Emerging semiconductor device technologies (Tunnel FETs, FinFETs,

and NCFETs) based energy efficient circuit design, hardware security modules or
subsystems design.
Evaluation scheme
Programmable Logic Devices
• Programmable logic devices (PLDs) are standard products, but can be
programmed to function in a specific application.

• The programming can be done either by the end user or by the manufacturer.

• The PLDs, which are programmed by the manufacturer, are known as mask-
programmable logic devices (MPLDs).

• The PLDs which are programmed by the end user are called field-programmable
logic devices (FPLDs).
• The architecture of PLDs is very regular and fixed. It cannot be changed
by the end user.

• The PLDs have a wide range of applications, and have a low risk and cost
in manufacturing large volume.

• Hence, the PLDs are cheaper. As the PLDs are premanufactured, tested,
and placed in inventory in advance, the design cycle time is very short.
The PLDs are classified into three categories based on the architecture and
programmability as given below:

• Read only memory (ROM)

• Programmable logic array (PLA)
• Programmable array logic (PAL)
Read only memory (ROM)
• Read only memory (ROM) is a storage device which can be programmed only once.
•As a result, the data remains intact and can be read as many times as possible.

•It consists of an address decoder with n input

lines, and a programmable OR array with m
output lines.
•The decoder produces 2n minterms based on the n
input lines.
•The minterms are ORed through programmable
switches which can be made ON or OFF to select
a particular minterm.
•The programmable switches can be implemented
by either bipolar, CMOS, nMOS, or pMOS
technologies.
Internal architecture
•A ROM which is mask-programmed with the nMOS technology
is shown in Figure.
•The nMOS transistors connect the decoder outputs to the output
lines.
•The output line is normally pulled up to VDD. When the decoder
output goes high, the transistor gate connected to it, will turn ON,
and the corresponding output line goes low.
•The presence of the nMOS transistor determines the pattern of 1s
or 0s in the output lines.
•This pattern is determined by the mask layer which contains only
those transistors where a connection is required.
• Problem 1: Design a combinational circuit using ROM which takes a
3-bit number and produces outputs as the binary equivalent of the
square of input numbers.
Programmable Logic Array
• Programmable logic array (PLA) is an IC chip used for two-level
combinational logic circuits.
• It consists of an AND array followed by an OR array. Both the AND
array and OR array are programmable.
• The AND array, also called
the AND plane, implements
the product terms, and the
OR array, also called the OR
plane, implements the sum
of product (SOP) terms.
• In PLA, both the arrays are
programmable.
Implement the following Boolean functions using
a PLA
Programmable Array Logic
• The programmable array logic (PAL)
is another class of programmable
logic device with the AND array
followed by the OR array.
• In this logic the AND array is
programmable but the OR array is
fixed.
• The PAL architecture is shown in
Figure.
• The OR array has permanently programmed connections as shown by
dots.

• The OR plane cannot be programmed. In this PAL architecture, each OR

gate has two inputs; hence, the SOP must have two product terms.

• Each function must be simplified individually to reduce the product

terms to maximum two.
Implement the following Boolean logic using PAL
Analysis of Clocked Sequential Circuits
• The behavior of a sequential circuit is determined from the inputs, the
outputs, and the states of its flip-flops.

• Both the outputs and the next state are a function of the inputs and the
present state.
Example
• It has one input variable x, one output variable y, and two
clocked RS flip-flops labeled A and B.
• The time sequence of inputs, outputs, and flip-flop states
may be enumerated in a state table.
• The state table for the circuit is shown in Table. It consists of
three sections labeled present state, next state, and output.
• The next state shows the states of flip-flops after the
application of a clock pulse, and the output section lists the
values of the output variables during the present state.
State Diagram
• The information available in a state table may be represented graphically in
a state diagram.

• In this diagram, a state is represented by a circle, and the transition between

states is indicated by directed lines connecting the circles.
State Equations
• A state equation (also known as an application equation) is an algebraic
expression that specifies the conditions for a flip-flop state transition.
• The left side of the equation denotes the next state of a flip-flop and the right
side, a Boolean function that specifies the present state conditions that make
the next state equal to 1.
• A state equation is similar in form to a flip-flop characteristic equation.
State Reduction and Assignment
• Any design process must consider the problem of minimizing the cost of the final
circuit.

• The two most obvious cost reductions are reductions in the number of flip-flops and
the number of gates.

• The reduction of the number of flip-flops in a sequential circuit is referred to as the

state reduction problem.

• State reduction algorithms are concerned with procedures for reducing the number
of states in a state table while keeping the external input-output requirements
unchanged.
Example
• First step is to prepare a state table from
the state diagram to apply the procedure.
• Identifying equivalent states
• Two states are said to be equivalent if, for each member of the set of
inputs, they give exactly the same output and send the circuit either to
the same state or to an equivalent state.
• When two states are equivalent, one of them can be removed without
altering the input-output relationships
• Removing a state
State repeating can be removed
State Assignment
• The cost of the combinational circuit part of a sequential circuit can be
reduced by using the known simplification methods for combinational
circuits.
• However, there is another factor, known as the state assignment problem,
that comes into play in minimizing the combinational gates.
• State assignment procedures are concerned with methods for assigning
binary values to states in such a way as to reduce the cost of the
combinational circuit that drives the flip-flops.
Flip-flop Excitation Tables
• A characteristic table defines the logical property of the flip-flop and
completely characterizes it
Flip-Flop logic diagrams
• During the design process we usually know the transition from present
state to next state and wish to find the flip-flop input conditions that
will cause the required transition.
• For this reason, we need a table that lists the required inputs for a
given change of state. Such a list is called an excitation table.
Design procedure
1. The word description of the circuit behavior is stated. This may be accompanied by a state diagram, a timing diagram, or
other pertinent information.

2. From the given information about the circuit, obtain the state table.

3. The number of states may be reduced by state reduction methods if the sequential circuit can be characterized by input-
output relationships independent of the number of states.

4. Assign binary values to each state if the state table obtained in step 2 or 3 contains letter symbols.

5. Determine the number of flip-flops needed and assign a letter symbol to each.

6. Choose the type of flip-flop to be used.

7. From the state table, derive the circuit excitation and output tables.

8. Using the map or any other simplification method, derive the circuit output functions and the flip-flop input functions.

9. Draw the logic diagram

Design Example
Design of Counters
Verilog programming
• Behavioral or Algorithmic level
• Dataflow level
• Gate level or Structural level
Gate level modelling
module Mux_4to1_gate(
input [3:0] i,
input [1:0] s,
output o
);

wire NS0, NS1;

wire Y0, Y1, Y2, Y3;
not N1(NS0, s[0]);
not N2(NS1, s[1]);
and A1(Y0, i[0], NS1, NS0);
and A2(Y1, i[1], NS1, s[0]);
and A3(Y2, i[2], s[1], NS0);
and A4(Y3, i[3], s[1], s[0]);
or O1(o, Y0, Y1, Y2, Y3);
endmodule
Data flow modelling

module Mux_4to1_df(input [3:0] i, input [1:0] s, output o);

assign o = (~s[1] & ~s[0] & i[0]) | (~s[1] & s[0] & i[1]) | (s[1] & ~s[0] & i[2]) | (s[1]
& s[0] & i[3]);

endmodule
Behavioural level modelling
module Mux_4to1(
input [3:0] i,
input [1:0] s,
output reg o
);

always @(s or i)
begin
case (s)
2'b00 : o = i[0];
2'b01 : o = i[1];
2'b10 : o = i[2];
2'b11 : o = i[3];
default : o = 1'bx;
endcase
end
endmodule
AND gate design
module AND_2_behavioral (output reg Y, input A, B);

always @ (A or B) begin

if (A == 1'b1 & B == 1'b1)

begin
Y = 1'b1;
end

else
Y = 1'b0;
end
endmodule
Full adder design

fulladder( A, B, Cin, S, Cout);

input wire A, B, Cin;
output reg S, Cout;
always @(A or B or Cin)
begin
S = A ^ B ^ Cin;
Cout = A&B | (A^B) & Cin;
end
endmodule
Fulladder fulladder(input wire A, B, Cin, output reg S, output reg Cout);
always @(A or B or Cin)
begin case (A | B | Cin)
3'b000: begin
S = 0; Cout = 0;
end
3'b001:
begin
S = 1; Cout = 0;
end
3'b010:
begin S = 1; Cout = 0;
end
3'b011: begin S = 0; Cout = 1;
end
3'b100: begin S = 1; Cout = 0;
end
3'b101: begin S = 0; Cout = 1;
end
3'b110: begin S = 0; Cout = 1;
end
3'b111: begin S = 1; Cout = 1;
end
endcase
end
endmodule
Blocking and Non-Blocking statements
• Blocking Statements: A blocking statement must be executed before the
execution of the statements that follow it in a sequential block.
• Nonblocking Statements: Nonblocking statements allow you to schedule
assignments without blocking the procedural flow.
• You can use the nonblocking procedural statement whenever you want to make
several register assignments within the same time step without regard to order or
dependence upon each other.
• It means that nonblocking statements resemble actual hardware more than
blocking assignments.
Example
module
block_nonblock();
reg a, b, c, d , e, f ;
// Blocking assignments
initial begin
a = #10 1'b1;// The simulator assigns 1 to a at time 10
b = #20 1'b0;// The simulator assigns 0 to b at time 30
c = #40 1'b1;// The simulator assigns 1 to c at time 70
end
// Nonblocking assignments
initial begin
d <= #10 1'b1;// The simulator assigns 1 to d at time 10
e <= #20 1'b0;// The simulator assigns 0 to e at time 20
f <= #40 1'b1;// The simulator assigns 1 to f at time 40
end
endmodule
Example module non-blocking (clk,a,c);
input clk;
module blocking (clk,a,c); input a;
input clk; output c;
input a; reg c;
output c; reg b;
reg c; always @ (posedge clk )
reg b; begin
always @ (posedge clk ) b <= a;
begin c <= b;
b = a; end
c = b; endmodule
end
endmodule
D-Flip Flop

module RisingEdge_DFlipFlop(D,clk,Q);
input D; // Data input
input clk; // clock input
output Q; // output Q
always @(posedge clk)
begin Q <= D;
end
endmodule
Up counter
module up_counter(input clk, reset, output[3:0] counter );
reg [3:0] counter_up; // up counter
always @(posedge clk or posedge reset)
begin if(reset)
counter_up <= 4'd0;
else
counter_up <= counter_up + 4'd1;
end
assign counter = counter_up;
endmodule
Down counter
module down_counter(input clk, reset, output[3:0] counter );
reg [3:0] counter_down; // down counter
always @(posedge clk or posedge reset)
begin if(reset)
counter_down <= 4‘hf;
else
counter_down <= counter_down - 4'd1;
end
assign counter = counter_down;
endmodule
Up-down counter
module up_down_counter(input clk, reset, up_down, output[3:0] counter );
reg [3:0] counter_up_down; // down counter
always @(posedge clk or posedge reset)
begin
if(reset)
counter_up_down <= 4'h0;
else if(~up_down)
counter_up_down <= counter_up_down + 4'd1;
else
counter_up_down <= counter_up_down - 4'd1;
end
assign counter = counter_up_down;
endmodule
Test bench module updowncounter_testbench();
reg clk, reset,up_down;
wire [3:0] counter;
up_down_counter g1(clk, reset,up_down, counter); initial
begin clk=0;
end
always
#5 clk=~clk;
initial begin reset=1;
up_down =1’b0;
#20;
reset=0;
#200;
up_down=1;
end
endmodule
CO2
Types of ASICs

Full-Custom ASICs: Possibly all logic cells and all mask layers customized

Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all)
mask layers customized
Types of ASICs – Cont’d

• Full-Custom ASICs
• Standard-Cell–Based ASICs
• Gate-Array–Based ASICs
• Channeled Gate Array
• Channel Less Gate Array
• Structured Gate Array
• Programmable Logic Devices
• Field-Programmable Gate Arrays
Types of ASICs – Cont’d
Full-Custom ASICs
 Include some (possibly all) customized logic cells
 Have all their mask layers customized
 Full-custom ASIC design makes sense only
 When no suitable existing libraries exist
 Existing library cells are not fast enough
 The available pre-designed/pre-tested cells consume too much power that a
design can allow
 The available logic cells are not compact enough to fit
 ASIC technology is new or/and so special that no cell library exits.
 Offer highest performance and lowest cost (smallest die size) but at
the expense of increased design time, complexity, higher design cost
and higher risk.
Full-Custom ASICs(HAND HELD)
• All mask layers are customized in a full-custom ASIC
• Generally, the designer lays out all cells by hand
• Some automatic placement and routing may be done
• Critical (timing) paths are usually laid out completely by hand
• Full-custom design offers the highest performance and lowest part cost (smallest
die size) for a given design
• The disadvantages of full-custom design include increased design time,
complexity, design expense, and highest risk
• Microprocessors (strategic silicon) were exclusively full-custom, but designers are
increasingly turning to semicustom ASIC techniques in this area as well
• Other examples of full-custom ICs or ASICs are requirements for high-voltage
(automobile), analog/digital (communications), sensors and actuators, and
memory (DRAM)
Standard-Cell-Based ASICs
• Uses standard cell library as the basic building blocks of chip.
• As compared to full-custom design, cell based design offers much higher productivity
because it uses predesigned cells with layouts.
• Small scale integration logic (NAND, NOR, XOR, AOI, OAI, inverter), Memories and
Processor designs.

• Usually, standard cells are a fixed height with

power and ground routed respectively at the top
and bottom of the cells.
• A single row of nMOS transistors adjacent to
GND and single row of pMOS transistors adjacent
to VDD.
• The polysilicon gate is connected from nMOS to
pMOS transistor.
• To calculate the sizes of cell the following
estimations are made.
• The height of the cell is designed by the sum
of nMOS, pMOS transistor width, separation
of n and p regions, VDD and GND busses
space.
• The horizontal pitch is defined as poly-to-
metal distance.
• It is relatively easy to construct a software
program automatically generate the cells.
Gate-Array-Based ASICs
• In this ASICs, rows of NMOS and rows of
PMOS transistors arrayed in the SOG portion
of the chip.
• These transistors have been personalized by
altering the metallization that is placed on the
top of the transistors
• Figure shows the SOG structure programmed
to a 3-input NAND gate .

 Channeled Gate Array

 Channel less Gate Array
 Structured Gate Array
Channeled Gate Array
 Only the interconnect is customized
 The interconnect uses predefined spaces between rows of base
cells
 Manufacturing lead time is between two days and two weeks

Channel less Gate Array

 There are no predefined areas set aside for routing - routing is
over the top of the gate-array devices
 Achievable logic density is higher than channeled gate arrays
 Manufacturing lead time is between two days and two weeks
 Structured Gate Array
 Only the interconnect is customized
 Custom blocks (the same for each design) can be embedded
 These can be complete blocks such as a processor or
memory array, or An array of different base cells better
suited to implementing a specific function
 Manufacturing lead time is between two days and two weeks.
Antifuse:
• Antifuse is opposite of regular fuse, an anti fuse is normally open circuit
until you force a programming current through it.
• In a poly diffusion antifuse the high current density causes a large power
dissipation in small area, which melts a thin insulating dielectric.
• This forms a thin, permanent, and resistive link.
Static RAM technology
• It is constructed from two-cross coupled inverters.
• The configuration cell drives the gates of other transistors.
• The advantage of SRAM programming technology is the designers can
reuse.
Programmable ASICs PLDs
PLDs are low-density devices which contain 1k – 10 k gates and are available
both in bipolar and CMOS technologies [PLA, PAL or GAL]
 CPLDs or FPLDs or FPGAs - FPGAs combine architecture of gate
arrays with programmability of PLDs.
User Configurable
 Contain Regular Structures - circuit elements such as AND, OR,
NAND/NOR gates, FFs, Mux, RAMs,
Allow Different Programming Technologies
 Allow both Matrix and Row-based Architectures
 Structure of a CPLD / FPGA
Design Flow
1. Design entry - Using a hardware description language (
HDL ) or schematic entry
2. Logic synthesis - Produces a netlist - logic cells and their
connections
3. System partitioning - Divide a large system into ASIC-
sized pieces
4. Prelayout simulation - Check to see if the design functions
correctly
5. Floorplanning - Arrange the blocks of the netlist on the
chip
6. Placement - Decide the locations of cells in a block
7. Routing - Make the connections between cells and blocks
8. Extraction - Determine the resistance and capacitance of
the interconnect
9. Postlayout simulation - Check to see the design still works
with the added loads of the interconnect
Design Economics
• The selling price Stotal of an integrated circuit may be given by

Stotal = Ctotal /(1-m)

Ctotal is the manufacturing cost of a single IC

m is the desired profit margin

The costs to produce an integrated circuit generally divided into following

elements
• Non-recurring engineering cost
• recurring cost
• Fixed costs
Non-recurring engineering cost
• Non-recurring engineering cost are those that are spent once during the
design of an integrated circuit

Engineering design cost(Etotal)

Prototype manufacturing cost(Ptotal)

Ftotal = Etotal + Ptotal

Engineering design cost: The cost of designing IC during the chip design
process (Personnel cost, support cost)
• Personnel cost:

Personnel cost include the labour for

Architectural design

Logic capture

Simulation and functionality

Layout of modules and chip

Timing verification

DRC and tapeout procedures

• support cost:

Computer costs

CAD software cost

Education cost
Prototype manufacturing cost
• The mask cost
• The fixture costs
• Package tooling

• The photo mask cost depends on the number of steps used in the process and precision
required in each step.
• A test fixture consists of a printed wiring for individual die.
• If a custom package is required, it may have to be designed and manufactured.
Recurring cost
• Fabrication cost
• Packaging cost
• Testing cost
Rtotal = Rprocess+Rpackage+Rtest

Fixed cost
• Data sheets
• User manual
• Application notes
Schedule
• It is important to estimate the design time to select a strategy by which
the ICs will be available in right time.
Different Programming Technologies
Antifuse:
• Antifuse is opposite of regular fuse, an anti fuse is normally open circuit
until you force a programming current through it.
• In a poly diffusion antifuse the high current density causes a large power
dissipation in small area, which melts a thin insulating dielectric.
• This forms a thin, permanent, and resistive link.
Static RAM technology
• It is constructed from two-cross coupled inverters.
• The configuration cell drives the gates of other transistors.
• The advantage of SRAM programming technology is the designers can
reuse.
EPROM –Erasable programmable ROM
• For programming EPROM memory, FAMOS (Floating gate avalanche injection MOS)
device will be used.
• When the higher gate voltage is applied to FAMOS device, the threshold voltage of the
device is increased and is programmed.
• Exposing memory to UV rays, electrons in floating gate acquire the energy and
overcome silicon dioxide barrier and move to silicon substrate.
• Part of the memory can not be erased.
Electrically erasable programmable ROM
• For programming EPROM memory, FLOTOX (Floating gate tunnelling
oxide MOS) device will be used.
• Over the drain the floating gate is present, and the oxide thickness is very
low.
• When small positive gate voltage is applied the electrons will implant on
floating gate.
• These electrons can be easily removed easily and can be erased bit by bit.