Experiment No: 12 Page No:47

Ref: GNITS/DSD/12 G.N.I.T.S – ETM DEPARTMENT

Realize and Design an 8 bit serial in and serial out shift

register using two 4 bit shift register

Aim: To study and implementation of 8 bit serial in and serial out shift
register using two 4 bit shift registers.

Apparatus:
1) Trainer kit
2) Patch chords
3) Power supply

Theory:
Shift registers are basically a type of registers which have the ability to
transfer (“shift”) data. Shift Registers are sequential logic circuits, capable of
storage and transfer of data. Shift registers are basically of 4 types. They are:

1. Serial In Serial Out shift register

2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register
Serial-in to Serial-out (SISO)  -  The data is shifted serially “IN” and “OUT” of the
register, one bit at a time in either a left or right direction under clock control.

Figure 1: logic diagram of 4-bit serial-in, serial-out, shift-right, shift register

Lab Incharge HOD, ETM

Experiment No: 12 Page No:48
Ref: GNITS/DSD/12 G.N.I.T.S – ETM DEPARTMENT

Figure 2: logic diagram of 4-bit serial-in, serial-out, shift-left, shift register

Figure 1 shows the logic diagram of serial-in, serial-out shift-right

register. The circuit consists of four flip flops and it can store four bits of
data. Serial input is applied at the D input of the first flip flop. The Q
output of the first flip flop is connected to the D input of the second flip
flop, the Q output of the second flip flop is connected to the D input of the
third flip flop and the Q output of the third flip flop is connected to the D
input of the fourth flip flop. The data is outputted from the Q terminal of
the last flip flop.
When serial data is transferred into a register each new bit is clocked
into the first flip flop at positive going edge of each clock pulse. And the bit
that was previously stored by the first flip flop is transferred to the second
flip fop. The bit that was stored by the second flip flop is transferred to
the third flip flop and so on. The bit that was stored by the last flip flop is
shifted out. And figure 2 shows the logic diagram of serial-in, serial-out
shift-left register. In this shift left register the data bits are shifted
towards left side.
This type of Shift Register also acts as a temporary storage device
or it can act as a time delay device for the data, with the amount of time
delay being controlled by the number of stages in the register, 4, 8, 16 etc
or by varying the application of the clock pulses. 
Experiment No: 12 Page No:49
Ref: GNITS/DSD/12 G.N.I.T.S – ETM DEPARTMENT

Pin diagram (74LS194):

Circuit diagram:
Experiment No: 12 Page No:50
Ref: GNITS/DSD/12 G.N.I.T.S – ETM DEPARTMENT

Procedure:
1) Connect the above circuit on the trainer kit.
2) Here the selection lines of the two IC can be shorted then it can be form
the S0 and S1.
3) Connect the first pin of the two Ic’s then it can be form a clear then it
connect to the logicswitch.
4) Short the pin number 11 of the both the ic’s then it forms a common clock
line then it is Connected to the 1Hz clock generator or the pulsar switch.
5) Connect the QA, QB, QC and QD of the first ic to the led’s shown in the
circuit.
6) Connect the QA, QB, QC and QD of the second ic to the led’s shown in
the circuit assume it as QE, QF, QG and QH.
7) Connect the 7pin of the first ic to the 15pin of the second ic.
8) Connect the 2pin of the second ic to the 12pin of the first ic.
9) Connect the serial input of the second IC pin7 to the logic switch.
10) Now put the selection lines S0=’0’ and S1=’1’ now apply the input data
through the pin7 of second ic Data serially by varying the logic switch.
Whatever you given it will be indicated on the LED’s and it is exited at the
top LED.
Ex: Shift right serial input=1010 0000
11) The input data serially exited at the QA you will observe that using the
pulsar switch Giving a single pulse at a time.
12) Observe the truth table below.
Experiment No: 12 Page No:51
Ref: GNITS/DSD/12 G.N.I.T.S – ETM DEPARTMENT

Truth table: Shift Right Operation

DATA: 10110101

S.N0 CLK CLR S1 S0 A B C D E F G H

1 H H 1 0 0 0 0 0 0 0 0 1
2 H H 1 0 0 0 0 0 0 0 1 0
3 H H 1 0 0 0 0 0 0 1 0 1
4 H H 1 0 0 0 0 0 1 0 1 1
5 H H 1 0 0 0 0 1 0 1 1 0
6 H H 1 0 0 0 1 0 1 1 0 1
7 H H 1 0 0 1 0 1 1 0 1 0
8 H H 1 0 1 0 1 1 0 1 0 1
9 H H 0 1 0 1 0 1 1 0 1 0
10 H H 0 1 0 0 1 0 1 1 0 1
11 H H 0 1 0 0 0 1 0 1 1 0
12 H H 0 1 0 0 0 0 1 0 1 1
13 H H 0 1 0 0 0 0 0 1 0 1
14 H H 0 1 0 0 0 0 0 0 1 0
15 H H 0 1 0 0 0 0 0 0 0 1

Result: Hence the 8 bit serial in and serial out using two 4 bit shift register.
Constructed and verified.

Reasoning Questions

1. Define shift register?

2. How SISO shift registers works?
3. What are the uses of SISO shift register?
4. How many clock pulses are required to complete SISO operation?
5. Give the characteristic equation of D flip flop?