Understanding Different Phases

Understanding Different Phases in
Timing Reports
Product Version 18.1
September 2018
Copyright Statement
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are
registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.
Learn more at Cadence Support Portal - https://support.cadence.com

© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Page 2
Understanding Different Phases in Timing Reports
Contents
Purpose ....................................................................................................................... 4
Audience...................................................................................................................... 4
Overview ...................................................................................................................... 4
Explanation of Different Phases .................................................................................. 4
Clock (C) Phase ....................................................................................................... 6
Data (D) Phase ........................................................................................................ 7
Clock Source Data Phase ...................................................................................... 10
Latency (L) Phase .................................................................................................. 12
Async Clock “@” Signal ......................................................................................... 13
Support ...................................................................................................................... 14
Feedback ................................................................................................................... 14

Purpose
The timing report in Innovus / Tempus shows the different phases associated with a
clock domain. This application note explains all phases and their polarities.
Audience
This is intended for Innovus / Tempus user who wants to understand phases reported in
the timing report and how these phases and polarities are derived.
Overview
The timing report has a “Phase” column that shows the clock domain and the
associated phase arriving at a pin. It is important to understand the different phases and
how the different values are derived.
Explanation of Different Phases

The phase represents a unique timing signal in the following format:
<Clock Name> <Phase> <Polarity>

<Clock Name> <C or D or L> <P or N>
The associated value of a clock can be as follows:
D - data signal in the clock domain

C - clock signal in the clock domain
L - latency phase
P - positive phase
N - negative phase
Asterisk (*) - timing exception associated with the signal

For example, running the report_cell_instance_timing command shows the

“Phase” column with various notations (D, C, L, P and N).
> report_cell_instance_timing f1 -view dtmf_view_setup
----------------------------------------------------------------------------------------
Instance f1 of DFFHQX1
----------------------------------------------------------------------------------------
Pin Dir Propagated Arrival Required Slack Phase
Slew
----------------------------------------------------------------------------------------
D ^ IN 0.004 2.000 7.844 5.844 vclk(D)(P)(dtmf_view_setup)*
D v IN 0.004 2.000 7.679 5.679 vclk(D)(P)(dtmf_view_setup)*
CK ^ IN 0.004 0.000 vclk(C)(P)(dtmf_view_setup)*
CK v IN 0.004 4.000 vclk(C)(P)(dtmf_view_setup)*
CK ^ IN 0.004 0.000 vclk(D)(P)(dtmf_view_setup)*
CK v IN 0.004 vclk(D)(P)(dtmf_view_setup)*
CK ^ IN 0.004 vclk(D)(N)(dtmf_view_setup)*
CK v IN 0.004 4.000 vclk(D)(N)(dtmf_view_setup)*
Q ^ OUT 0.158 0.354 6.000 5.647 vclk(D)(P)(dtmf_view_setup)
Q v OUT 0.125 0.302 6.000 5.698 vclk(D)(P)(dtmf_view_setup)
----------------------------------------------------------------------------------------
> report_cell_instance_timing b1 -view dtmf_view_setup

----------------------------------------------------------------------------------------
Instance b1 of BUFXL
----------------------------------------------------------------------------------------
Slew
----------------------------------------------------------------------------------------
A ^ IN 0.082 0.769 vclk(L)(P)(dtmf_view_setup)*
A v IN 0.073 0.721 vclk(L)(P)(dtmf_view_setup)*
A ^ IN 0.082 0.769 vclk(D)(P)(dtmf_view_setup)
A v IN 0.073 0.721 vclk(D)(P)(dtmf_view_setup)
Y ^ OUT 0.083 0.885 vclk(L)(P)(dtmf_view_setup)*
Y v OUT 0.059 0.862 vclk(L)(P)(dtmf_view_setup)*
Y ^ OUT 0.083 0.885 vclk(D)(P)(dtmf_view_setup)
Y v OUT 0.059 0.862 vclk(D)(P)(dtmf_view_setup)
----------------------------------------------------------------------------------------

Clock (C) Phase

The “C” phase represents the clock signal in a clock domain.
Clock is the most fundamental timing object, which has a waveform with leading and
trailing edges that form reference for all timings.
Following diagram shows the leading and trailing edges of a clock waveform.
The leading and trailing edges of a clock waveform can be “rise” or “fall”. The first edge
of a clock waveform is the leading edge, and the polarity of the clock phase depends on
the first edge of the clock waveform. The polarity can be either positive (P) or negative
(N). If the first edge of the clock is “rise”, the polarity of the clock will be “P”. If the first
edge of the clock is “fall”, the polarity of the clock will be “N”.
Positive polarity: rise first => (C)(P)

Negative polarity: fall first => (C)(N)
For example, you have the following clock definitions, where for the CK1 clock, the
leading edge is “rise” and for the CK2 clock, it is “fall”.
create_clock [get_ports {CLK1}] -name CK1 -period 2 -waveform
{0 1}
create_clock [get_ports {CLK2}] -name CK2 -period 2 -waveform
{1 2}
In this case, the clock phase at the CK1 port has “P” polarity since the leading edge of
this clock is “rise”. The polarity will get inverted to “N” after crossing an inverter as
shown in the diagram above. The clock phase at the CK2 port has “N” polarity since the
leading edge of this clock is “fall”.
Data (D) Phase

The “D” phase represent the data signal in a clock domain.
The clock has both rise and fall transitions during one clock period. But, the data has
either rise or fall transition during one clock period as shown in the following diagram:
The data phase derived from the leading edge of the clock waveform has “P” polarity,
and the data phase derived from the trailing edge of the clock waveform has “N”
polarity.
Clock with leading edge as “rise”:

Clock with leading edge as “fall”:
Following table also shows the relation between the related clock edge used for the
data phase and its polarity
Related Clock Edge Data Phase Polarity

Leading (Rise) P
Trailing (Fall) N
Leading (Fall) P
Trailing (Rise) N
You can refer to the following examples, which illustrate clock and data phase polarity in
various scenarios.
Case 1: Leading edge of clock is “rise” and flop is positive-edge-triggered
The leading edge of the CK1 clock is rise, and the flop triggered by this clock is positive-
edge-triggered. Here, the clock arriving at the clock pin of the flop and data at the output
pin are w.r.t. leading edge of the clock. Hence, both clock and data have “P” polarity.
create_clock [get_ports {CLK1}] -name CK1 -period 2 -

waveform {0 1}

Case 2: Leading edge of clock is “rise” and flop is negative-edge-triggered
The leading edge of the CK1 clock is rise, and the flop triggered by this clock is
negative-edge-triggered. Here, clock arriving at the clock pin of the flop is w.r.t leading
(rise) edge and data at the output pin of the flop is w.r.t. trailing (fall) edge. Hence, clock
has “P” polarity and data has “N” polarity.

waveform {0 1}
Case 3: Leading edge of clock is “fall” and flop is positive-edge-triggered
The leading edge of the CK1 clock is fall, and the flop triggered by this clock is positive-
edge-triggered. Here, both clock arriving at the clock pin of the flop and data at the
output pin of the flop are w.r.t. trailing (rise) edge. Hence, both clock and data have “N”
polarity.

waveform {1 2}
Case 4: Leading edge of clock is “fall” and flop is negative-edge-triggered
The leading edge of the CK1 clock is fall, and the flop triggered by this clock is negative-
edge-triggered. Here, the clock arriving at the clock pin of the flop is w.r.t trailing (rise)
edge and data at the output pin of the flop is w.r.t. leading (fall) edge. Hence, the clock
has “N” and data has “P” polarity.

waveform {1 2}

Clock Source Data Phase

Once a clock is defined at a clock root, two data phases start at the clock root along
with the clock phase.
1. (D)(P) is created for data phase w.r.t. leading edge of the clock. If the leading
edge is “rise”, (D)(P) for the fall edge will have a null value. If the leading edge is
“fall”, (D)(P) for the rise edge will have a null value.
2. (D)(N) is created for the data phase w.r.t. trailing edge of the clock. If the trailing
edge is “rise”, (D)(N) for the fall edge will have a null value. If the trailing edge is
“fall”, (D)(P) for the rise edge will have a null value.
For example, if you define a clock at the CLK1 port as follows, the two data phases are
reported at the clock port.

waveform {0 1}
To check phases at the clock port, you can query the phase at the instance pin
connected to this clock port using the report_cell_instance_timing command.
> report_cell_instance_timing C1
----------------------------------------------------------------------
Instance C1 of BUFX2
----------------------------------------------------------------------
Slew
----------------------------------------------------------------------
A ^ IN 0.000 0.000 CK1(C)(P)
A v IN 0.000 1.000 CK1(C)(P)
A ^ IN 0.004 0.000 CK1(D)(P) *
A v IN 0.004 CK1(D)(P) *
A ^ IN 0.004 CK1(D)(N) *
A v IN 0.004 1.000 CK1(D)(N) *
In this case, there are following phases:
1. Clock phase with “P” polarity w.r.t. leading (rise) edge of the clock with value 0.0
2. Clock phase with “P” polarity w.r.t. trailing (fall) edge of the clock and arrival
value 1.0
3. Data phase with “P” polarity and “rise” edge w.r.t. leading (rise) clock edge. The
arrival value is 0.0.
4. Data phase with “P” polarity and “fall” edge w.r.t. leading (rise) clock edge. Since
the fall edge for data is not possible w.r.t. leading (rise) clock edge, the arrival
value is null (empty).

5. Data phase with “N” polarity and “rise” edge w.r.t. trailing (fall) clock edge. Since
the rise edge for data is not possible w.r.t. leading (rise) clock edge, the arrival
value is null (empty).
6. Data phase with “N” polarity and “fall” edge w.r.t. trailing (fall) clock edge. The
arrival value is 1.0.
You can also check this with the following command:
> get_property [get_ports CLK1] arrival_window

ck1 {max_r_f 0.000 1.000 min_r_f 0.000 1.000}
ck1 {max_r_f 0.000 NA min_r_f 0.000 NA}
ck1 {max_r_f NA 1.000 min_r_f NA 1.000}
Here, the first row shows the clock phase and the respective arrival times.
The second and third rows show data phase w.r.t. the leading (rise) and trailing (fall)
clock edges, respectively.
This is also illustrated in the following diagram. The clock root has two data phases
along with a clock phase. Both data and clock phases will propagate to the clock pin,
and only data phases will propagate to the data pin.

Latency (L) Phase

Latency phase is a special type of clock phase used to create the generated clocks and
their phases. If a generated clock is created, the arrival time of the clock edge at the
attachment point is expected to be traceable from the provided source clock. Now, it
might happen that the trace includes sequential elements such as flops. In such cases,
the signal after the flop will have no clock phase. Because clock phases stop
propagation at the flop, the output of the flop in such a situation will not have the clock
phase. However, the clock phase will be there after the generated clock definition point.
In such cases, there will be a latency phase created between the generated clock
definition point and the output of the flop to trace the latency.
For example, a generated clock, GK, defined on the data path has latency tracing to the
master clock through a sequential element and hence, there is a latency phase created
between the output of the sequential element and the generated clock definition point.
You can run the report_cell_instance_timing command to check phases at

different pins of the flop and combinational logic where the generated clock is defined.
You can see there are latency (L) phases between the generated clock definition point
and the output of the sequential element.
> report_cell_instance_timing FF1

----------------------------------------------------------------------
Instance FF1 of DFFHQX2
----------------------------------------------------------------------
Slew
----------------------------------------------------------------------
D ^ IN 0.018 0.182 0.934 0.753 CK(D)(P) *
D v IN 0.020 0.200 0.854 0.653 CK(D)(P) *
CK ^ IN 0.000 0.000 CK(C)(P) *
CK v IN 0.000 0.500 CK(C)(P) *
CK ^ IN 0.000 0.130 CK(D)(P) *
CK v IN 0.000 CK(D)(P) *
CK ^ IN 0.000 CK(D)(N) *
CK v IN 0.000 0.640 CK(D)(N) *
Q ^ OUT 0.000 0.141 CK(L)(P) *
Q v OUT 0.000 0.119 CK(L)(P) *
Q ^ OUT 0.055 0.141 CK(D)(P)
Q v OUT 0.045 0.119 CK(D)(P)
----------------------------------------------------------------------

> report_cell_instance_timing B1
----------------------------------------------------------------------
Instance B1 of BUFX8
----------------------------------------------------------------------
Slew
----------------------------------------------------------------------
A ^ IN 0.000 0.141 CK(L)(P) *
A v IN 0.000 0.119 CK(L)(P) *
A ^ IN 0.055 0.141 CK(D)(P)
A v IN 0.045 0.119 CK(D)(P)
Y ^ OUT 0.000 0.000 GK(C)(P) *
Y v OUT 0.000 GK(C)(P) *
Y ^ OUT 0.000 0.185 CK(L)(P) *
Y v OUT 0.000 0.174 CK(L)(P) *
Y ^ OUT 0.000 GK(C)(P)
Y v OUT 0.000 0.500 GK(C)(P)
Y ^ OUT 0.020 0.000 GK(D)(P) *
Y v OUT 0.021 GK(D)(P) *
Y ^ OUT 0.020 0.185 CK(D)(P)
Y v OUT 0.021 0.174 CK(D)(P)
Y ^ OUT 0.020 GK(D)(N) *
Y v OUT 0.021 0.500 GK(D)(N) *
----------------------------------------------------------------------
Async Clock “@” Signal

A special clock is used to create clock phase at the flop/latch clock pins that have no
incoming clock phase. This is denoted by “@”. In such a case, arrival time is set to 0.

In the following example, there is no clock defined on the clock port driving the CK clock
pin of the flop. So, in this case, there is no incoming clock phase on the CK clock pin of
the flop. This is denoted by “@”.
> report_cell_instance_timing FF1

---------------------------------------------------------------------
Instance FF1 of DFFHQX2
---------------------------------------------------------------------
Slew
---------------------------------------------------------------------
D ^ IN 0.018 0.082 @(D)(P) *
D v IN 0.020 0.100 @(D)(P) *
CK ^ IN 0.068 0.000 @(C)(P)
CK v IN 0.046 0.000 @(C)(P)
CK ^ IN 0.068 0.130 @(D)(P) *
CK v IN 0.046 0.140 @(D)(P) *
Q ^ OUT 0.055 0.148 @(D)(P)
Q v OUT 0.045 0.126 @(D)(P)
---------------------------------------------------------------------
Support
Cadence Support Portal provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.


Understanding Different Phases

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Understanding Different Phases

Uploaded by

Copyright:

Available Formats

Understanding Different Phases in

Learn more at Cadence Support Portal - https://support.cadence.com

Learn more at Cadence Support Portal - https://support.cadence.com

Explanation of Different Phases

<Clock Name> <Phase> <Polarity>

The associated value of a clock can be as follows:

D - data signal in the clock domain

Learn more at Cadence Support Portal - https://support.cadence.com

For example, running the report_cell_instance_timing command shows the

> report_cell_instance_timing b1 -view dtmf_view_setup

Learn more at Cadence Support Portal - https://support.cadence.com

Clock (C) Phase

Positive polarity: rise first => (C)(P)

Data (D) Phase

Clock with leading edge as “rise”:

Learn more at Cadence Support Portal - https://support.cadence.com

Clock with leading edge as “fall”:

Related Clock Edge Data Phase Polarity

Case 1: Leading edge of clock is “rise” and flop is positive-edge-triggered

create_clock [get_ports {CLK1}] -name CK1 -period 2 -

Learn more at Cadence Support Portal - https://support.cadence.com

Case 2: Leading edge of clock is “rise” and flop is negative-edge-triggered

create_clock [get_ports {CLK1}] -name CK1 -period 2 -

Case 3: Leading edge of clock is “fall” and flop is positive-edge-triggered

create_clock [get_ports {CLK1}] -name CK1 -period 2 -

Case 4: Leading edge of clock is “fall” and flop is negative-edge-triggered

create_clock [get_ports {CLK1}] -name CK1 -period 2 -

Learn more at Cadence Support Portal - https://support.cadence.com

Clock Source Data Phase

create_clock [get_ports {CLK1}] -name CK1 -period 2 -

In this case, there are following phases:

Learn more at Cadence Support Portal - https://support.cadence.com

You can also check this with the following command:

> get_property [get_ports CLK1] arrival_window

Learn more at Cadence Support Portal - https://support.cadence.com

Latency (L) Phase

You can run the report_cell_instance_timing command to check phases at

> report_cell_instance_timing FF1

Learn more at Cadence Support Portal - https://support.cadence.com

Async Clock “@” Signal

Learn more at Cadence Support Portal - https://support.cadence.com

> report_cell_instance_timing FF1

Learn more at Cadence Support Portal - https://support.cadence.com

You might also like