CHAPTER 1

DIGITAL CONCEPTS AND NUMBER SYSTEMS

1.1 Digital and Analog Quantities

Definition : Analog & Digital

• Analog?

– Varies over a continuous range of values

– Examples of analog quantities: time, pressure, sound.

• Digital?

– A discrete set of values.

– Varies in discrete (separate) steps.

Analog vs Digital

Analog

• Use base 10 (decimal)

• Represented by 10 different level : 0,1,2,3,4,5,6,7,8,9

• Analog system: A combination of devices that manipulate values represented in analog

form

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Digital

◼ Use base 2 (binary)

◼ Represented by 2 different levels: 0 and 1 or low and high.

◼ Digital system: A combination of devices that manipulate values represented in digital

form.

The Digital Advantages

• Advantages of digital

– Ease of design

– Ease of storage

– Accuracy and precision are easier to maintain

– Programmable operation

– Less affected by noise

– Ease of fabrication on IC chips

• Thus, the systems is more efficient and reliable:

􀂊 - Data Processing

􀂊 - Data Transmission

􀂊 - Data Storage

A System Using Digital and Analog Methods

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Audio CD

• The audio CD is a typical hybrid (combination) system.

– Analog sound is converted into analog voltage.

– Analog voltage is changed into digital through an ADC in the recorder.

– Digital information is stored on the CD .

– At playback the digital information is changed into analog by a DAC in the CD

player.

– The analog voltage is amplified and used to drive a speaker that produces the
original analog sound.

1.2 Binary Digits, Logic Levels and Digital Waveform

Binary Digits = Bit

Examples of digital waveforms:

-> Periodic

-> Non-Periodic

Frequency (f) vs. Period (T)

 Frequency (f) is the rate at which it repeat itself at a fixed interval. Is measured in cycles
per second or Hertz (Hz)

f = 1/T Hz

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  Period (T) is the time from the edge of one pulse to the corresponding edge of the next
pulse. Is measured in second

T = 1/f s

 Example :

 clock frequency : f = 100Hz,

so, period : T = 1/100Hz = 0.01s = 0.01x 103 = 10 ms

Pulse Width

Pulse width (tW): A measure of the duration of the pulse.

90% 90%
Amplitude
50% 50%
Pulse
10% Width 10%

Rise Time Fall Time

Duty Cycle

Example : a periodic digital waveform has a pulse width

1ms and period time 10ms, calculate duty cycle?

Duty cycle = 1ms/10ms * 100% = 10%

Timing Diagram is a graph of digital waveform showing the actual time relationship of two or
more waveform and how each waveform changes in relation to the others.

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1.3 NUMBER SYSTEM, OPERATION AND CODES

Decimal Number

 The decimal numbering system has a base of 10 with each position weighted by a factor
of 10

 ….105 104 103 102 101 100. 10-110-2 10-3 10-4 10-5…

 Example :

Express decimal 47 as a sum of the values of each digit :

47 = (4 x 101) + (7 x 100)

= 40 + 7

= 47

Binary Number

• The binary numbering system has 2 digits 0 and 1

• The binary numbering system has a base of 2 with each position weighted by a factor of 2

24 23 22 21 20 2-1 2-2 2-3 2-4 2-5

increase increase

• Example :

101112 = (1 X 24 + 0 X 23 + 1 X 22 + 1 X 21 + 1 X 20 )

16 + 4 + 2 + 1 = 23 10

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Binary-to-Decimal Conversion

• Convert binary to decimal by summing the positions that contain a 1

1 0 0 1 0 12

25 + 2 4 + 23 + 2 2 + 21 + 20 = 32 + 4 + 1 = 3710

Binary Count

Binary-to-Decimal Conversion

• Step 1: Get n, total binary numbers

– 1101101 ➔ n = 7 binary numbers

• Step 2: Conversion will stop at 2 n-1 = 26

• Step 3: Multiply all the numbers with its appropriate weight

• Step 4: Sum the result from step 3, and binary is now decimal.

• Step 1: Binary number: 100101 ➔ n = 6

• Step 2: Stop at 2n-1 = 25

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Decimal-to-Binary Conversion

◼ Two methods to convert decimal to binary:

❑ 1) Sum-of-weights method (reverse process)

◼ Determine the set of binary weights whose sum is equal to the decimal
number

❑ 2) Repeated division-by-2 method

◼ Repeatedly dividing the decimal number by 2 and retrieving the remainder

1) Sum-of-weight method

Binary weights

256 128 64 32 16 8 4 2 1

357 = 256 + 64 + 32 + 4 + 1 101100101

= 28 + 26 + 25 + 22 + 20

Binary weights

1024 512 256 128 64 32 16 8 4 2 1

1937 = 1024 + 512 + 256 + 128 + 16 + 1 11110010001

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Try this for 25 and 125

Repeated division-by-2

• Repeated division steps:

– Divide the decimal number by 2

– Write the remainder after each division until a quotient of zero is obtained.

– The first remainder is the LSB and the last is the MSB

• Note, when done on a calculator, a fractional answer indicates a

remainder of 1.

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Converting Decimal Fractions-to-Binary

• 2 ways to convert:

– 1) Sum-of-weight

– 2) Repeated multiplication of 2

Repeated multiplication by 2

• Conversion of decimal-binary

– Whole numbers ➔ repeated division by 2

– Fractions ➔ repeated multiplication by 2

• Step 1: multiply number by 2

• Step 2: note the carry (1 or 0)

• Step 3: repeat with new fraction

Stop when fraction part = 0

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Converting Decimal Fractions-to-Binary

Using Sum-of-weights

Binary weights

64 32 16 8 4 2 1 .5 .25 .125 .0625

95.6875 = 64 + 16 + 8 + 4 + 2 + 1 + .5 + .125 + .0625

1011111.1011

Repeated division by 2 yields the whole number while repeated multiplication by 2 of the
fraction yields the binary fraction

Hexadecimal Number System

• Most digital systems deal with groups of bits in even powers of 2 such as 8, 16, 32, and
64 bits.

• Hexadecimal uses groups of 4 bits.

• Base 16

– 16 possible symbols

– 0-9 and A-F

• Allows for convenient handling of long binary strings.

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Hex-to-Decimal Conversion

• Convert from hex to decimal by multiplying each hex digit by its positional weight.

Example:

Decimal-to-Hex Conversion

• Convert from decimal to hex by using the repeated division method used for decimal to
binary and decimal to octal conversion.

• Divide the decimal number by 16

• The first remainder is the LSB and the last is the MSB.

– Note, when done on a calculator a decimal remainder can be multiplied by 16 to

get the result. If the remainder is greater than 9, the letters A through F are used.

Example
Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Hexadecimal 0 1 2 3 4 5 6 7 8 9 A B C D E F
Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Decimal-to-Hex

650 Right/LSB
= 40.625 x 16 = 10 = A
16
40 2 8 A
= 2.5 x 16 = 8
16
2
= 0.125 x 16 = 2
16
Left/MSB
done!
65010 = 28A16
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Binary-to-Hex Conversion

• Convert from binary to hex by grouping bits in four starting with the LSB.

• Each group is then converted to the hex equivalent

• Leading zeros can be added to the left of the MSB to fill out the last group.

• Example

• Example of binary to hex conversion.

(Note the addition of leading zeroes)

11101001102 = 0011 1010 0110

= 3 A 6

= 3A616

• Counting in hex requires a reset and carry after reaching F.

Octal Number

• The Octal Number System:

– uses base 8

– includes only the digits 0 through 7

The Octal system is based on the binary system with a 3-bit boundary

85 84 83 82 81 80

32768 4096 512 64 8 1

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  Gray Code

 is not an arithmetic code

 Only one bit changes from one code to the next in the sequence

 Gray code can be any amounts of bits.

 Below is example from Gray Code-to-Binary

 Eg : 1110 (Gray Code)

+ Penambahan dalam modul o 2

0 +0 = 0

0 +1 =1
1 1 1 0
1 +0 = 1
+ + +
1 +1 = 0
1 0 1 1

=10112

 Below is example from Binary-to-Gray Code

Eg : 11102

1 + 1 + 1 + 0

1 0 0 1

= 1001 (Kod Gray)

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 CHAPTER TWO
LOGIC GATES

The Inverter

• Performs inversion or complementation

– Changes a logic level to the opposite

– 0(LOW) ➔ 1(HIGH) ; 1 ➔ 0;

Symbols used:

• Logic expression for an Inverter:

A X
0 1
A X=A
1 0

X is the complement of A
A X is the inverse of A
X is NOT A
"A bar"
"not A"

The AND Gate

• Performs ‘logical multiplication’

– If all of the input are HIGH, then the output is HIGH.

– If any of the input are LOW, then the output is LOW.

– Symbols used:

&
A A
X X
B B

(a) Distinctive shape (b) Rectangular outline with

the AND (&) qualifying symbol

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AND gate operation:

Logic expressions for AND gate:

• AND gate performs Boolean multiplication

• Boolean multiplication follows the same basic rule as binary multiplication:

0.0=0

0.1=0

1.0=0

1.1=1

The OR Gate

• Performs ‘logical addition’

– If any of the input are HIGH, then the output is HIGH.

– If all of the input are LOW, then the output is LOW

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Symbols used:

The OR gate operation:

Logic expressions for OR gate:

• OR gate performs Boolean addition

• Boolean addition follows the basic rules as follows:

0+0=0

0+1=1

1+0=1

1+1=1

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The NAND Gate

• NAND ➔ NOT-AND combines the AND gate and an inverter

• Used as a universal gate

– Combinations of NAND gates can be used to perform AND, OR and inverter

operations

– If all or any of the input are LOW, then the output is HIGH.

– If all of the input are HIGH, then the output is LOW

Symbol used:

The NAND gate operation:

Logic expressions for NAND gate: Boolean expression for NAND is a combination of AND and
Inverter Boolean expressions.

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The NOR Gate

• NOR ➔ NOT-OR combines the OR gate and an inverter

• Used as a universal gate

– Combinations of NOR gates can be used to perform AND, OR and inverter

operations

– If all or any of the input are HIGH, then the output is LOW.

– If all of the input are LOW, then the output is HIGH

• Symbol used:
A A 1
X A
X X
B B B

(a) Distinctive shape: 2 input NOR (b) Rectangular outline with

gate and its NOT/OR equivalent the OR ( 1) qualifying symbol

The NOR gate operation:

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Logic expressions for NOR gate:

• Boolean expression for NOR is a combination of OR and Inverter Boolean expressions.

The Exclusive-OR gate

• Combines basic logic circuits of AND, OR and Inverter. Has only 2 inputs

• Used as a universal gate

– Can be connected to form an adder that allows a computer to do perform addition,

subtraction, multiplication and division in ALU (Arithmetic and Logic Unit).

– If both of the input are at the same logic level, then the output is LOW.

– If both of the input are at opposite logic levels, then the output is HIGH

Symbol used:

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The XOR gate operation:

The Exclusive-NOR gate

• Has only 2 inputs, but output of XNOR is the opposite of XOR

– If both of the input are at the same logic level, then the output is HIGH.

– If both of the input are at opposite logic levels, then the output is LOW.

• Symbol used:

The XNOR gate operation:

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 CHAPTER THREE
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION

Laws & Rules of Boolean Algebra

 Basic laws of BA

 Commutative Laws

◼ For addition and multiplication

◼ Associative Laws

◼ For addition and multiplication

 Distributive Laws

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Simplification of Boolean Expressions

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DeMorgan’s Theorems

• Provides mathematical verification for:

– NAND ≡ negative-OR

– NOR ≡ negative-AND

X X
XY X+Y
Y Y
NAND Negative-OR

X X
X+Y XY
Y Y

NOR Negative-AND

 DM theorem 1:

 The complement of a product of variables is equal to the sum of the complements

of the variables

 DM theorem 2:

 The complement of a sum of variables is equal to the product of the complements

of the variables

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Standard Form of Boolean Expressions

• Boolean expression can be converted into one of 2 standards forms:

– The sum-of-products (SOP) form

– The product-of-sums (POS) form

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 • Standardization makes the evaluation, simplification, and implementation of Boolean
expressions more systematic and easier

• Product term = a term with the product (Boolean multiplication) of literals

• Sum term = a term with the sum (Boolean addition) of literals

The Sum-of-Products (SOP) Form

 SOP = when 2 or more product terms are summed

 e.g ABP1 + ABCP2

ABC P1 + CDEP2 + BCD P3

 SOP can also contain a single variable term

In SOP a single overbar cannot extend over more than 1 variable, but more than 1 variable can
have an overbar.

• Domain = a set of variables contained in an expression

– E.g. AB + ABC ➔ domain = A, B, C

– ABC + CDE + BCD ➔ domain = A, B, C, D, E

• Implementation of the SOP expression AB + BCD + AC

• A logic expression can be changed to SOP form using Boolean algebra techniques.

– A(B + CD) = AB + ACD

– AB + B(CD + EF) = AB + BCD + BEF

– Standard SOP form = where all the variables in the domain appear in each product
term in the expression.

– To convert product terms to standard SOP

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 – Multiply each of the nonstandard term with the missing term using Boolean
algebra rule 6 ( ).

– Repeat until all variables appear in each product term.

• Convert this Boolean expression to standard SOP form:

• Domain = A, B, C, D.

• What is missing?

– Term 1: missing D or D’

– Term 2: missing (C/C’) and (D/D’)

• Complete these terms by applying Boolean rule 6

 Now we have

Binary representation of a standard product term

• A product = 1 only if ALL variables in the term is equal to 1.

– Remember: product = multiplication ➔ 1.1 = 1

• A sum = 1 when one or all of the variables in the term is equal to 1.

– Remember: sum = addition ➔ 1 + 0 = 1; 0 + 1 = 1; 1 + 1 = 1

Product-of-Sums (POS) Form

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  POS = when 2 or more sum terms are multiplied.

 (A + B)S1 (A + B + C)S2

 (A + B + C)S1(C + D + E)S2(B + C + D)S3

 Like SOP, POS

 can also contain a single variable term

 a single overbar cannot extend over more than 1 variable, but more than 1
variable can have an overbar.

• Domain = a set of variables contained in an expression

– (A + B + C)(A + B + D)(A + B + C + D) ➔ domain = A, B, C, D

– Implementation of the POS expression (A + B)(B + C + D)(A + C)

• Standard POS form = where all the variables in the domain appear in each sum term in
the expression.

• To convert product terms to standard POS

– Multiply each of the nonstandard term with the missing term using Boolean
algebra rule 8:

– Apply rule 12 : A + BC = (A + B)(A + C)

– Repeat until all variables appear in each sum term.

– Convert this Boolean expression to standard POS form

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 • Domain = A, B, C, D.

• What is missing?

– Term 1: missing D or D’

– Term 2: missing A or A’

• Apply rules 8 and 12

Term 1 : A + B + C = A + B + C + D D = ( A + B + C + D)( A + B + C + D)
Term 2 : B + C + D = B + C + D + A A
= ( A + B + C + D)( A + B + C + D)

Now we have

( A + B + C )( B + C + D )( A + B + C + D )
= ( A + B + C + D )( A + B + C + D )( A + B + C + D )( A + B + C + D )( A + B + C + D )

Binary representation of a standard sum term

• A product = 0 only if one or more of the sum term is equal to 0.

– Remember: product = multiplication ➔ 1.1 = 1

• A sum = 1 when one or all of the variables in the term is equal to 1.

– Remember: sum = addition ➔ 1 + 0 = 1; 0 + 1 = 1; 1 + 1 = 1

Converting Standard SOP to Standard POS

• Binary values in a standard SOP expression are not present in the equivalent standard
POS expression

Steps to follow : SOP to POS

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 • Step 1: Evaluate each product term in the SOP expression ➔ i.e. determine the binary
numbers of the product terms.

• Step 2: Determine all the binary numbers not included in Step 1.

• Step 3: Write equivalent sum term for each binary number from Step 2 and express in
POS form.

• ** Using a similar procedure, to go from POS to SOP

• Convert this SOP exp. to an equivalent POS exp.

• Domain = A, B, C = 3. So, 2 3 = 8 possible combinations.

The SOP have 5 of 8, so POS have the other 3 (001, 100, 110) ➔ These 3 make sum term = 0

Boolean Expressions and Truth Tables

• Step 1: determine domain and combinations of binary values ➔ input

• Step 2: convert expression to Standard SOP/POS.

• Step 3: find the binary values that make the product = 1 (SOP) or sum = 0 (POS)

• Step 4: the remaining combination will be

– Equal to 0 (SOP)

– Equal to 1 (POS)

Fill in the truth table

• Develop a truth table for the standard SOP expression

• Domain = A, B, C. combinations = 2 3 = 8

• What binary value makes the product term = 1?

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Karnaugh Map (K-Map)

• K-Map is similar to the truth table, but it presents all of the possible values of input and
output.

• This is shown in an array of cells.

• K-Maps can be used for expressions with 2,3,4 or 5 variables.

• The number of cells in a K-Map = total number of possible input variable combinations
➔ 3 = 23 = 8

• Cells that differ by only one variable are adjacent

– Cell 010 is adjacent to 000, 011 and 110

• Physically, cells that share their walls are adjacent

• In a K-map with 4-variable or more, the top-most & bottom-most cells of a column (and
row) are adjacent.

K-Map SOP Minimization

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 • K-Map is used to simplify Boolean expressions to their minimum form.

• A minimized SOP expression has the fewest possible term with each term having fewest
possible variables.

• A minimized SOP expression needs fewer logic gates than standard expression.

• To map an SOP expression to a map:

– Step 1: determine the binary value of each product term

Step 2: Place a 1 in a cell that have the same value as the product term

Example: Mapping SOP expression

• Map the following expression

• To use K-maps, expressions must be in standard form.

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 • For expressions that are not standard, it must be converted to a standard form.

• Recall: AB + ABC

– AB(C/C’) ➔ 11(1/0) ➔ ABC + ABC’

– So: ABC + ABC’ + ABC

• Map the following expression on a K-map:

K-Map Simplification of SOP Expressions

• There are 3 steps to obtain a minimum SOP expression from a K-map.

1. Grouping the 1s

2. Determine product term for each group

Summing the resulting product terms

Grouping the 1s

 Group must contain cells in 2 x combination (i.e. 1,2,4,8,16

 Each cell must be adjacent to at least 1 other cell in the group, but all cells in a group
need not be adjacent

 Try to have the biggest possible group of 1s

 Each 1 must be in at least one group.

 The 1s already in a group may be included in another group so long as the overlapping
group includes non-common 1s

Here are some examples:

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 CHAPTER FOUR
COMBINATIONAL LOGIC
Basic Combinational Logic Circuits

• AND-OR Logic

• AND-OR-Invert Logic

• Exclusive-OR Logic

• Exclusive-NOR Logic

AND-OR Logic

• A circuit consisting of any number of AND gates and an OR gate.

• Example: SOP expressions

• If any of the AND gates output are HIGH, the output in the OR gate is HIGH

If all of the AND gates outputs are LOW, the output in the OR gate is LOW

AND-OR-Invert Logic

• It’s the completed AND-OR circuit

• Example: POS expressions

• Results are the complement of AND-OR circuit.

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Exclusive-OR Logic

• Known as XOR & has its own unique symbol

• XOR is a combination of 2 AND gates, 1 OR gate and 2 inverters

• Output expression

Exclusive-NOR Logic (XNOR)

• The complement of XOR function

• Implemented by inverting XOR output.

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Boolean Expression to Logic Circuit

• Given the Boolean expression

X = AB + CDE

• we see that it is made of 2 terms

1. AB

2. CDE

Which are then OR-ed

 Both terms 1 and 2 are AND-terms

– These are done before the OR

– ***It is much like math: (AB)+(CDE)

 To implement this Boolean expression, we need:

– 1 2-input AND-gate ➔ AB

– 1 3-input AND-gate ➔ CDE

– 1 2-input OR-gate ➔ AB + CDE

How-to

• Given the expression, look at it carefully

• Step 1: Get the ‘big chunks’ of terms

• Step 2a: From each ‘big chunks’, get smaller chunks

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 • Step 2b: Repeat until you get the smallest possible chunk.

• Step 3: Assign the appropriate gates to all chunks

Put them all together ➔ Logic circuit!!

Logic circuits for X = AB(CD + EF) = ABCD + ABEF.

Truth Table to Logic Circuit

• If we have a truth table instead of an expression, logic circuit can still be implemented.

• Step 1: Get the product term from HIGH outputs

• Step 2: From the product term get the expression

– This is done by OR-ing the product terms

Step 3: Implement the logic circuit

• Step 1:

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 • Step 2:

• Step 3:

Reducing a combinational logic circuit

• Reducing a combinational logic circuit will result in lesser gates used

• How to do this?

– Step 1 : Read the logic circuit

– Step 2 : Get the final output expression

– Step 3a: Apply DeMorgan’s theorem and

Boolean algebra

– Step 3b: K-map can be used too.

Example

• Given the logic circuit below, simplify.

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 Step 2
Output Expression of the circuit is X = (ABC)C + ABC + D

Step 3
X = (A + B + C)C + A + B + C + D
= AC + BC + CC + A + B + C + D
= AC + BC + C + A + B + C + D
= C(A + B + 1) + A + B + D
X=A+B+C+D
DeMorgan's theorem
CC = C ; C + C = C
=> (A + AC) + (B + BC) + C + D
=> A + B + C + D

Simplified circuit :
A
B X
C
D

The Universal Property of NAND and NOR Gates

• The NAND Gate as a Universal Logic Element

The NOR Gate as a Universal Logic Element

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 CHAPTER FIVE
LATCHES and FLIP FLOPS
Latches

 A latch is a type of temporary storage device that has two stable states (bistable) a is
normally placed in a category separate from that of flip-flops.

 Latch are basically similar to flip-flop.

 The difference between latch and flip-flop is in the method used for changing their state.

 S – set; R-reset

 Type of Latch :

 A) S-R Latch

 B) Gated S-R Latch

 C) Gated D Latch

A) S-R (Set-Reset) Latch

B) The output of each gate is connected to an input of the opposite data.

C) This produces a regenerative feedback.

Logic Symbol : S-R and S-R Latch

Truth-Tables :
For Active-HIGH and Active-LOW input SR-Latch

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 ▪ The Q and not-Q outputs are supposed to be in opposite states.

▪ Q=1 and not-Q=0 is defined as set (by making S=1 and R=0)

▪ Q=0 and not-Q=1 is conversely defined as reset (by making S=0 and R=1)

▪ When S and R are both equal to 0, the multivibrator's outputs “not change" in

their prior states.

▪ If Q and not-Q happen to be forced to the same state (both 0 or both 1), that

state is referred to as invalid.

B) Gated S-R Latch

• Is a gated latch requires an enable input (EN).

• The S and R inputs control the state to which the latch will go when a HIGH level is
applied to the EN input.

• The latch will not change until EN is HIGH, but as long as it remains HIGH, the output is
controlled by the state of the S and R input.

• The invalid state occurs when both S and R are simultaneously HIGH.

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C) Gated D Latch

Edge-Triggered Flip-Flops

• Flip-flops are synchronous bi-stable storage devices capable of storing one bit.

• In this case synchronous means that the output state only changes at a specified point on a
triggering input called the clock (C).

That is, the output changes are synchronized with the clock signal.

• The main difference between latches and flip-flops is the method used to change their
states.

• Latches are level sensitive, or level-triggered. This means that the outputs are dependent
on the voltage level applied, not on any signal transition.

• Flip-flops are edge-triggered, that is that they depend on the transition of a signal.

• This may either be a LOW-to-HIGH (rising edge) or a HIGH-to-LOW (falling edge)

transition.

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Difference between latch and flip-flop

• Three types of Edge-Triggered FF:

– i) Edge-Triggered S-R Flip Flop

– ii) Edge-Triggered D Flip Flop

– iii) Edge-Triggered J-K Flip Flop

i) Edge-Triggered S-R Flip-Flops

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 ii) Edge-Triggered D Flip Flop

▪ D FF is useful when a single data bit (1 or 0) is to be stored.

▪ The addition of an inverter to an S-R FF creates basic D FF where a positive edge-

triggered type is shown.

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Example : Determine Q for the D input

iii) Edge-Triggered J-K Flip Flop

iv) The JK FF is versatile and is a widely used type of FF.

v) The difference between J-K and S-R is a J-K has no invalid state as SR.

Truth table

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Asynchronous : Presets (PRE) and Clear (CLR) inputs

• Synchronous ➔ inputs transferred on the triggering edge of the clock

• Asynchronous ➔ inputs effect FF state independent of the clock

– Normally labeled

• preset (PRE) & clear (CLR) OR

• direct set (SD) & direct reset (RD)

Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs.

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2 sections :

Master section - a) External JK input, b) A gated latch

Slave section - a) Inputs = outputs of Master, b) Inverted clock pulse

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 CHAPTER SIX
COUNTERS
ASYNCHRONOUS COUNTER (AC)

⚫ An AC is one in which the Flip-Flops (FF) within the counter do not change states at
exactly the same time because they do not have a common clock pulse.

⚫ The clock input of an AC is always connected only to the LSB FF.

⚫ An AC also known as ripple counter.

a) 2-Bit Asynchronous Counter

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 b) 3-Bit Asynchronous Counter

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SYNCHRONOUS COUNTER (SC)

⚫ A SC is one in which all the Flip-Flops (FF) in the counter clocked at the same time by a
common clock pulse.

⚫ The clock input goes to each FF in a SC

a) 2-Bit Synchronous Counter

b) 3-Bit Synchronous Counter

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DESIGN OF SYNCHRONOUS COUNTER

Step 1 : State Diagram

Step 2 : Create Next State Table

Step 3 : Flip-Flop Transition Table

Step 4: Karnaugh Maps

Step 5 and Step 6 : Logic Expressions and Counter Implementation

Step 1 : State Diagram

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Step 2 : Create Next State Table

Step 3: Flip-Flop Transition Table

Step 4: Karnaugh Maps

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Step 5 and Step 6 :
Logic Expressions and Counter Implementation

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 CHAPTER SEVEN
SHIFT REGISTERS
Basic shift register functions

• Shift registers (SR) consist of arrangements of FFs.

• Digital System : Important in application involving :

– a) Data storage

– b) Data transfer/movement

a ) The flip-flop as a storage element

b) Basic data movement in shift registers.

(Four bits are used for illustration. The bits move in the direction of the arrows.)

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Serial In/Serial Out (SISO)

• Accepts data serially, one bit at a time on a single line

• Output produced in serial form too

Figure 9.7 : Logic symbol for an 8-bit serial in/serial out shift register

Example 1

Figure .Four bits (1010) being entered serially into the register.

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Example 2

Serial In/Parallel Out (SIPO)

• Data bits are entered serially

• Output is parallel

– All bits are available simultaneously

Example SIPO :

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Parallel In/Serial Out (PISO)

• Inputs entered simultaneously into respective stages on parallel lines

• Outputs are one bit at a time

• SHIFT/LOAD

– = 0 ➔ Loads the input values

– =1 ➔ shifts them out at clock pulse

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Parallel In/Parallel Out (PIPO)

• Input and output done in parallel.

• Enter all inputs - Bits appear on the parallel outputs

Shift register counters

• A shift register with serial output connected back to the serial input to produce special
sequences.

• 2 most common types

– Johnson counter

– Ring counter

The Johnson Counter

• In the Johnson counter the last complemented output is fed back in as an input to the first
FF

• Examples shown with D FF, but can be implemented with other types of FF as well.

• Number of unique states are 2 times the number of bits (FF)

– 4 bits ➔ 4*2 = 8 states

– 5 bits ➔ 5*2 = 10 states

• Johnson counter will produce a modulus of 2n; (n = number of stages)

**modulus 10 a.k.a. mod 10

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4-bit Johnson Counter

The Ring Counter

• The ring counter uses 1 FF for each state in its sequence

• For a 10-bit ring counter, there is a unique output for each decimal digit

• Initially Q0 = 1 ➔ represents a zero

• The ‘1’ is shifted round the ring, so next Q 1 = 1 (represents a one)

• This goes on till Q9 = 1.

• Then the output Q9 is input back into the first FF

• **The ‘1’ is always retained and goes ‘round the ring’ at each clock pulse

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Shift register applications

• Time delay

• Serial-to-parallel converter

• Universal Asynchronous Receiver Transmitter (UART

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