The University of New South Wales

ELEC2141: Digital Circuit Design

Workshop Week 4 – Combinational Circuit Building Blocks and Arithmetic Circuits

1. (3-30) Design a 5-to-32-line decoder using a 3-to-8-line decoder, a 2-to-4-line decoder, and 32 2-input
AND gates.
2. Rewrite the Verilog description given below (from lectures) for the 2-to-4-line decoder using vector
notation for inputs, outputs and wires.

// 2-to-4-Line Decoder with Enable: Structural Verilog Description

module decoder_2_to_4_st_v(EN, A0, A1, D0, D1, D2, D3);
input EN, A0, A1;
output D0, D1, D2, D3;
wire A0_n, A1_n, N0, N1, N2, N3;

not gn0(A0_n, A0);

not gn1(A1_n, A1);

and ga3(N0, A0_n, A1_n);

and ga4(N1, A0, A1_n);
and ga5(N2, A0_n, A1);
and ga6(N3, A0, A1);
and ga7(D0, N0, EN);
and ga8(D1, N1, EN);
and ga9(D2, N2, EN);
and ga10(D3, N3, EN);
endmodule

3. (3-32) An electronic game uses an array of seven LEDs (light-emitting diodes) to display the results of a
random roll of a die. A decoder is to be designed to illuminate the appropriate diodes for the display of
each of the six die values. The desired display patterns are shown in the figure below.
a b
c d e
f g

a. Use a 3-to-8-line decoder and OR gates to map the 3-bit combinations on inputs X2, X1, and X0 for
values 1 through 6 to the outputs a through g. Input combinations 000 and 111 are don’t-cares.
b. Note that for the six die sides, only certain combinations of dots occur. For example, dot pattern
 = {} and dot pattern  = {, } can be used for representing input values 1, 2 and 3 as {},
{}, and {, }. Define four dot patterns A, B, C, and D, and compare its gate-input cost to that of
the 3-to-8 decoder and OR gates in part a.

Where referenced, questions are taken from the textbook:

M. Mano, C. R. Kime and T. Martin, Logic and Computer Design Fundamentals, 5th Edition (Global Edition), Pearson, 2016
 4. (3-35) Design a 4-input priority encoder with inputs and outputs as the priority encoder presented in
lectures, but with the truth table representing the case in which input D0 has the highest priority and
input D3 the lowest priority.
5. Write a dataflow description for the four-input priority encoder, presented in lectures, using the binary
decision dataflow concept.

6. (3-44) A combinational circuit is defined by the following three input Boolean functions:
1 = ̅ +  + ̅
2 = ̅ + 
3 =  + 
4 =  + ̅
Design the circuit with a decoder and external OR gates.
7. (3-45) The rear lights of a car are to be controlled by digital logic. There is a single lamp in each of the
rear lights.
The inputs are:
LT left turn switch - causes blinking of left side lamp
RT right turn switch - causes blinking of right side lamp
EM emergency flasher switch - causes blinking of both lamps
BR brake applied switch - causes both lamps to be on
BL blinking signal with 1 Hz frequency
The outputs are:
LR power control for left rear lamp
RR power control for right rear lamp
a. Write the equations for LR and RR. Assume that BR overrides EM and that LT and RT override
BR.
b. Implement each function LR(BL, BR, EM, LT) and RR(BL, BR, EM, RT) with a 4-to-16-line decoder
and external OR gates.
8. (3-38) Design an 8-to-1-line multiplexer using a 3-to-8-line decoder, eight 2-input AND gates and an 8-
input OR gate.
9. (3-46) Implement the following Boolean function with an 8-to-1-line multiplexer and a single inverter
with variable D as its input:
(, , , ) = Σ(0, 2, 3, 5, 6, 9, 10, 13)
10. (3-47) Implement the Boolean function
(, , , ) = Σ(1, 3, 4, 11, 12, 13, 14, 15)
with a 4-to-1-line multiplexer and external gates. Connect inputs A and B to the selection lines. The input
requirements for the four data lines will be a function of the variables C and D. The values of these
variables are obtained by expressing F as a function of C and D for each of the four cases when AB = 00,
01, 10, and 11. These functions must be implemented with external gates.
Where referenced, questions are taken from the textbook:
M. Mano, C. R. Kime and T. Martin, Logic and Computer Design Fundamentals, 5th Edition (Global Edition), Pearson, 2016
 11. Write a Verilog description for a 4-to-1-line multiplexer by using a process containing a case statement.

12. Repeat question 8 by using a Verilog process containing if-else statements.

13. (3-51) Obtain the 1s and 2s complements of the following unsigned binary numbers:

a. 1001 1100
b. 1001 1101
c. 1010 1000
d. 0000 0000
e. 1000 0000

14. Consider the number 0xF2. Write down the decimal value of this number when represented as an:

a. 8-bit unsigned number.

b. 8-bit sign-magnitude number.
c. 8-bit 1s complement.
d. 8-bit 2s complement.

15. (3-52) Perform the indicated subtraction with the following unsigned binary numbers by taking the 2’s
complement of the subtrahend:

a. 11010 - 10001
b. 11110 - 1110
c. 111 1110 – 111 1110
d. 101 001 – 101

16. For the following 8-bit binary additions, determine the result, all status flags (N, Z, C, V), and whether an
overflow occurred for both signed and unsigned numbers.

a. 1100 1000 + 0011 1000

b. 1000 0000 + 1000 0000
c. 1010 1010 + 1100 1110
d. 1010 1010 + 1110 0010

17. (3-54) Perform the following arithmetic operations in binary using signed 2s complement
representation for negative numbers.

a. (+36) + (-24)
b. (-35) - (-24)

18. (3-55) The following binary numbers have a sign in the leftmost position and, if negative, are in 2s
complement form. Perform the indicated arithmetic operations, determine the value of the status flags
(N, Z, C, V) and verify the answer in decimal. Indicate whether overflow occurs for each computation.
Where referenced, questions are taken from the textbook:
M. Mano, C. R. Kime and T. Martin, Logic and Computer Design Fundamentals, 5th Edition (Global Edition), Pearson, 2016
 a. 110 001 + 011 101
b. 011 0111 + 010 1111
c. 0000 0111 - 1111 0100
d. 011 0111 - 010 1111

19. (3-59) Design a combinational circuit that compares two 4-bit unsigned numbers A and B to see whether
B is greater than A. The circuit has one output X, so that X = 1 if A < B and X = 0 if A ≥ B.

20. (3-50 & 3-69) The logic diagram of the first stage of a 4-bit adder is shown below. Verify that the circuit
implements a full adder. Write a structural Verilog description for the circuit. Compile and simulate your
description. Apply all eight input combinations to check the description.

21. Design a circuit that generates the 9’s complement of a BCD digit. Note that the 9’s complement of a BCD
number d is 9-d.

22. Derive a scheme for performing subtraction using BCD operands. Show a block diagram for the
subtractor circuit.

Hint: Subtraction can be performed easily if the operands are in 10’s complement form. Here the sign bit
is 0 for a positive number and 9 for a negative number.

Where referenced, questions are taken from the textbook:

M. Mano, C. R. Kime and T. Martin, Logic and Computer Design Fundamentals, 5th Edition (Global Edition), Pearson, 2016