28.10.

2022

EE243 Homework #2

1) Using Xilinx ISE, create a schematic and simulate the following function using AND, OR and
NOT gates:

𝐹=𝑥⊕ 𝑦

• You must not use XOR gate in your schematics. You need to implement the functionality of
XOR gate by using AND, OR and NOT gates.
• You must create schematic to implement the function. You cannot use any other method.
• You must use a VHDL Test Bench for your simulation. Do not use Verilog Test Fixture!
• Input and output signals must be named as it is given above.
• Move the output waveform to the top on the simulation window.
• You need to simulate for every input combination so that the truth table of the function can
be obtained from your results.

You need to submit a “.zip” file which includes the following:

• Your schematic file with “.sch” file extension

• Your VHDL test bench file with “.vhd” file extension
• A snapshot that clearly shows the content of the schematic
• A snapshot of the simulated waveforms with the names of I/O signals clearly visible