5 Pin Diagram of 8085

Gursharan Singh 12-Dec-11
Maninder Kaur
Introduction to 8085
PIN DIAGRAM OF 8085  It was introduced in 1977.
 It is 8-bit microprocessor.
 Its actual name is 8085 A.
Gursharan Singh  It is single NMOS device.
mailme@gursharansingh.in  It contains 6200 transistors
approx.
Maninder Kaur  Its dimensions are
mailme@maninderkaur.in 164 mm x 222 mm.
www.eazynotes.com  It is having 40 pins Dual-
Inline-Package (DIP).
Gursharan Singh
Maninder Kaur www.eazynotes.com 12-Dec-11 2
Introduction to 8085 Introduction to 8085

 Ithas three advanced  The advanced versions
versions: consume 20% less power
◦ 8085 AH supply.
◦ 8085 AH2
◦ 8085 AH1  The clock frequencies of
8085 are:
 These advanced ◦ 8085 A 3 MHz
versions are designed ◦ 8085 AH3 MHz
◦ 8085 AH2 5 MHz
using HMOS
◦ 8085 AH1 6 MHz
technology.
Gursharan Singh Gursharan Singh
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X1 & X2
Pin Diagram of 8085 Pin 1 and Pin 2 (Input)
 These are also called
Crystal Input Pins.
 8085 can generate clock

signals internally.
 To generate clock
signals internally, 8085
requires external inputs
from X1 and X2.
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RESET IN and RESET OUT RESET IN and RESET OUT

Pin 36 (Input) and Pin 3 (Output) Pin 36 (Input) and Pin 3 (Output)
 RESET IN:  Resetting the
microprocessor means:
◦ It is used to reset the
microprocessor. ◦ Clearing the PC and IR.
◦ Disabling all interrupts
◦ It is active low signal. (except TRAP).
◦ Disabling the SOD pin.
◦ When the signal on this ◦ All the buses (data,
pin is low for at least 3 address, control) are tri-
clocking cycles, it forces stated.
the microprocessor to ◦ Gives HIGH output to
reset itself. RESET OUT pin.

RESET IN and RESET OUT SID and SOD

Pin 36 (Input) and Pin 3 (Output) Pin 4 (Input) and Pin 5 (Output)
 RESET OUT:  SID (Serial Input
Data):
◦ It is used to reset the peripheral
devices and other ICs on the
circuit. o It takes 1 bit input from
serial port of 8085.
◦ It is an output signal.
◦ It is an active high signal. o Stores the bit at the 8th

position (MSB) of the
◦ The output on this pin goes high Accumulator.
whenever RESET IN is given low
signal.
o RIM (Read Interrupt
◦ The output remains high as long Mask) instruction is used
as RESET IN is kept low. to transfer the bit.
SID and SOD Interrupt Pins

Pin 4 (Input) and Pin 5 (Output)
 SOD (Serial Output  Interrupt:
Data):
• It means interrupting the normal execution of the
microprocessor.
o It takes 1 bit from
Accumulator to serial port • When microprocessor receives interrupt signal, it discontinues
of 8085. whatever it was executing.
o Takes the bit from the 8th • It starts executing new program indicated by the interrupt
position (MSB) of the signal.
Accumulator.
• Interrupt signals are generated by external peripheral devices.
o SIM (Set Interrupt Mask)
instruction is used to • After execution of the new program, microprocessor goes
back to the previous program.
transfer the bit.
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Sequence of Steps Whenever There is

an Interrupt
Five Hardware Interrupts in 8085
 Microprocessor completes execution of current  TRAP
instruction of the program.
 PC contents are stored in stack.  RST 7.5

 PC is loaded with address of the new program.
 RST 6.5
 After executing the new program, the
microprocessor returns back to the previous
program.  RST 5.5
 It goes to the previous program by reading the top
value of stack.  INTR
Classification of Interrupts Maskable Interrupts

 Maskable and Non-Maskable  Maskable interrupts are those interrupts
which can be enabled or disabled.
 Vectored and Non-Vectored
 Enabling and Disabling is done by
 Edge Triggered and Level Triggered software instructions.
 Priority Based Interrupts

Maskable Interrupts Non--Maskable Interrupts

Non
 List of Maskable Interrupts:  The interrupts which are always in
enabled mode are called non-maskable
• RST 7.5 interrupts.
• RST 6.5  These interrupts can never be disabled

by any software instruction.
• RST 5.5
 TRAP is a non-maskable interrupt.
• INTR
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Vectored Interrupts Vectored Interrupts

 The interrupts which have fixed memory  List of vectored interrupts:
location for transfer of control from
normal execution. • RST 7.5
 Each vectored interrupt points to the • RST 6.5

particular location in memory.
• RST 5.5
• TRAP
Vectored Interrupts Non--Vectored Interrupts

Non
 The addresses to which program control  The interrupts which don't have fixed
goes: memory location for transfer of control
Name Vectored Address
from normal execution.
RST 7.5 003C H (7.5 x 0008 H)
RST 6.5 0034 H (6.5 x 0008 H)
RST 5.5 002C H (5.5 x 0008 H)
 The address of the memory location is
TRAP 0024 H (4.5 x 0008 H) sent along with the interrupt.
 Absolute address is calculated by

 INTR is a non-vectored interrupt.
multiplying the RST value with 0008 H.
Edge Triggered Interrupts Level Triggered Interrupts

 The interrupts which are triggered at  The interrupts which are triggered at high
leading or trailing edge are called edge or low level are called level triggered
triggered interrupts. interrupts.
 RST 7.5 is an edge triggered interrupt.  RST 6.5

 RST 5.5
 INTR
 It is triggered during the leading
(positive) edge.
 TRAP is edge and level triggered interrupt.
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Priority Based Interrupts Priority Based Interrupts

 Whenever there exists a simultaneous  Priority of interrupts:
request at two or more pins then the
pin with higher priority is selected by the Interrupt Priority
TRAP 1
microprocessor. RST 7.5 2
RST 6.5 3
RST 5.5 4
 Priority is considered only when there INTR 5
are simultaneous requests.

TRAP RST 7.5

Pin 6 (Input) Pin 7 (Input)
 It is a non-maskable interrupt.  It is a maskable interrupt.
 It has the highest priority.
 It has the second highest
 It cannot be disabled.
priority.
 It is both edge and level
triggered.  It is positive edge triggered
 It means TRAP signal must go only.
from low to high.
 The internal flip-flop is
 And must remain high for a triggered by the rising
certain period of time.
edge.
 TRAP is usually used for power
failure and emergency shutoff.  The flip-flop remains high
until it is cleared by RESET
IN.
RST 6.5 RST 5.5

Pin 8 (Input) Pin 9 (Input)
 It is a maskable interrupt.  It is a maskable
 It has the third highest interrupt.
priority.  It has the fourth highest
 It is level triggered only. priority.
 The pin has to be held high  It is also level triggered.
for a specific period of
time.  The pin has to be held
high for a specific period
 RST 6.5 can be enabled by of time.
EI instruction.
 This interrupt is very
 It can be disabled by DI
instruction. similar to RST 6.5.

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INTR INTA
Pin 10 (Input) Pin 11 (Output)
 It is a maskable interrupt.  It stands for interrupt
 It has the lowest priority. acknowledge.
 It is also level triggered.
 It is an out going signal.
 It is a general purpose
interrupt.  It is an active low signal.
 By general purpose we
mean that it can be used to  Low output on this pin
vector microprocessor to indicates that
any specific subroutine
having any address. microprocessor has
acknowledged the INTR
request.
Address and Data Pins Address and Data Pins

 Address Bus:  Data Bus:
• The address bus is used to send address to • It is used to transfer data between
memory. microprocessor and memory.
• It selects one of the many locations in • Data bus is of 8-bit.
memory.
• Its size is 16-bit.

AD0 – AD7 A8 – A15

Pin 19-
19-12 (Bidirectional) Pin 21
21--28 (Unidirectional)
 These pins serve the dual  These pins carry the
purpose of transmitting lower higher order of address
order address and data byte.
bus.
 During 1st clock cycle, these pins
act as lower half of address.  The address is sent from
microprocessor to
 In remaining clock cycles, these
memory.
pins act as data bus.
 These 8 pins are switched
 The separation of lower order to high impedance state
address and data is done by during HOLD and RESET
address latch.
mode.
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ALE S0 and S1
Pin 30 (Output) Pin 29 (Output) and Pin 33 (Output)
 It is used to enable Address  S0 and S1 are called Status
Latch.
Pins.
 It indicates whether bus

functions as address bus or data  They tell the current
bus.
operation which is in progress
in 8085.
 If ALE = 1 then
◦ Bus functions as address bus. S0 S1 Operation
0 0 Halt
 If ALE = 0 then 0 1 Write
◦ Bus functions as data bus. 1 0 Read

1 1 Opcode Fetch
IO/M IO/M
Pin 34 (Output) Pin 34 (Output)
 This pin tells whether I/O  The operation being performed is indicated by
or memory operation is S0 and S1.
being performed.
 If S0 = 0 and S1 = 1 then
 If IO/M = 1 then ◦ It indicates WRITE operation.
◦ I/O operation is being
performed.
 If IO/M = 0 then
◦ It indicates Memory operation.
 If IO/M = 0 then
◦ Memory operation is being
performed.  Combining these two we get Memory Write
Operation.
Table Showing IO/M, S0, S1 and RD

Corresponding Operations Pin 32 (Output)
 RD stands for Read.
Operations IO/M S0 S1
 It is an active low signal.
Opcode Fetch 0 1 1
Memory Read 0 1 0  It is a control signal used
Memory Write 0 0 1 for Read operation either
I/O Read 1 1 0 from memory or from
I/O Write 1 0 1 Input device.
Interrupt Ack. 1 1 1
 A low signal indicates that
Halt High Impedance 0 0
data on the data bus must
be placed either from
selected memory location
or from input device.
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WR READY
Pin 31 (Output) Pin 35 (Input)
 WR stands for Write.  This pin is used to
synchronize slower
 It is also active low signal. peripheral devices with
 It is a control signal used fast microprocessor.
for Write operation either
into memory or into  A low value causes the
output device. microprocessor to
enter into wait state.
 A low signal indicates that
data on the data bus must  The microprocessor
be written into selected remains in wait state
memory location or into until the input at this pin
output device. goes high.
HOLD HLDA
Pin 38 (Input) Pin 39 (Output)
 HOLD pin is used to request  HLDA stands for Hold
the microprocessor for DMA Acknowledge.
transfer.
 The microprocessor uses
 A high signal on this pin is a this pin to acknowledge the
request to microprocessor receipt of HOLD signal.
to relinquish the hold on
buses.  When HLDA signal goes high,
address bus, data bus, RD,
 This request is sent by DMA WR, IO/M pins are tri-
controller. stated.
 Intel 8257 and Intel 8237 are  This means they are cut-off
two DMA controllers. from external environment.

HLDA VSS and VCC

Pin 39 (Output) Pin 20 (Input) and Pin 40 (Input)
 The control of these  +5V power supply is
buses goes to DMA
Controller. connected to VCC .
 Control remains at  Ground signal is

DMA Controller until connected to VSS.
HOLD is held high.
 When HOLD goes low,
HLDA also goes low
and the microprocessor
takes control of the
buses.
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5 Pin Diagram of 8085

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5 Pin Diagram of 8085

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Gursharan Singh 12-Dec-11

Introduction to 8085 Introduction to 8085

 8085 can generate clock

RESET IN and RESET OUT RESET IN and RESET OUT

Gursharan Singh Gursharan Singh

RESET IN and RESET OUT SID and SOD

◦ It is an active high signal. o Stores the bit at the 8th

SID and SOD Interrupt Pins

Sequence of Steps Whenever There is

 PC contents are stored in stack.  RST 7.5

Classification of Interrupts Maskable Interrupts

 Priority Based Interrupts

Gursharan Singh Gursharan Singh

Maskable Interrupts Non--Maskable Interrupts

• RST 6.5  These interrupts can never be disabled

Vectored Interrupts Vectored Interrupts

 Each vectored interrupt points to the • RST 6.5

Vectored Interrupts Non--Vectored Interrupts

 Absolute address is calculated by

Edge Triggered Interrupts Level Triggered Interrupts

 RST 7.5 is an edge triggered interrupt.  RST 6.5

Priority Based Interrupts Priority Based Interrupts

Gursharan Singh Gursharan Singh

TRAP RST 7.5

RST 6.5 RST 5.5

Gursharan Singh Gursharan Singh

Address and Data Pins Address and Data Pins

Gursharan Singh Gursharan Singh

AD0 – AD7 A8 – A15

 It indicates whether bus

◦ Bus functions as data bus. 1 0 Read

Table Showing IO/M, S0, S1 and RD

Gursharan Singh Gursharan Singh

HLDA VSS and VCC

 Control remains at  Ground signal is

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