Evaluation of a physically defined silicon

quantum dot for design of matching circuit

for RF reflectometry charge sensing
Cite as: AIP Advances 13, 035219 (2023); https://doi.org/10.1063/5.0141092
Submitted: 05 January 2023 • Accepted: 15 February 2023 • Published Online: 14 March 2023

J. Kamioka, R. Matsuda, R. Mizokuchi, et al.

AIP Advances 13, 035219 (2023); https://doi.org/10.1063/5.0141092 13, 035219

© 2023 Author(s).
 AIP Advances ARTICLE scitation.org/journal/adv

Evaluation of a physically defined silicon

quantum dot for design of matching circuit
for RF reflectometry charge sensing
Cite as: AIP Advances 13, 035219 (2023); doi: 10.1063/5.0141092
Submitted: 5 January 2023 • Accepted: 15 February 2023 •
Published Online: 14 March 2023

J. Kamioka,1,a) R. Matsuda,2 R. Mizokuchi,2 J. Yoneda,3 and T. Kodera2,,b)

AFFILIATIONS
1
Information Technology R & D Center, Mitsubishi Electric Corporation, Kamakura, Kanagawa 247-8501, Japan
2
Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan
3
Tokyo Tech Academy for Super Smart Society, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan

a)
Author to whom correspondence should be addressed: Kamioka.Jun@bk.MitsubishiElectric.co.jp
b)
Electronic mail: kodera.t.ac@m.titech.ac.jp

ABSTRACT
This paper reports on the extraction of the equivalent circuit model parameters of a physically defined silicon quantum dot at a cryogenic tem-
perature and design of the impedance matching circuits to improve the performance of a charge sensor for radio-frequency (RF) reflectometry.
The I-V characteristics and the S-parameters of the quantum dot device are measured around a Coulomb peak at 4.2 K. The measured results
are modeled by an RC parallel circuit, and the model parameters for the quantum dot device were obtained. We consider three impedance
matching circuits for RF reflectometry of a quantum dot: shunt capacitor-series inductor type, shunt inductor-series capacitor type, and shunt
inductor-series inductor-type. We formulate and compare the sensitivity and bandwidth of RF reflectometry for the three types of circuits.
The analysis should be useful for selecting the optimal matching circuit and the circuit parameters for given equivalent circuit parameters
and working frequency. This procedure is demonstrated for a quantum dot with the characterized model circuit along with simulated perfor-
mance. This design technique of matching circuit for RF reflectometry can be applied to any device that can be represented by an RC parallel
circuit. These results will facilitate to realize fast semiconductor qubit readout in various quantum dot platforms.
© 2023 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license
(http://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1063/5.0141092

I. INTRODUCTION circuits proposed or utilized for the purpose of RF reflectometry

Radio-frequency (RF) reflectometry on a semiconductor quan-
tum dot (QD) charge sensor1–3 has high sensitivity to changes in
nearby electric fields and is useful for spin qubit readout.4–25 A typ-
ical QD charge sensor becomes most sensitive at a resistance of ∼1
MΩ, and it is generally understood that realizing a good impedance
matching of this sensor resistance to the 50 Ω circuit is a key to
achieve high reflectometry sensitivity. Therefore, it is important
to design the impedance matching circuit based on the effective
circuit model of the QD charge sensor. However, the QD charge
sensor is located in a cryogenic environment where precise calibra-
tion of the high-frequency transmission properties is challenging,
making detailed evaluations of the QD to extract the equivalent
circuit parameters elusive. Furthermore, there are several types of
measurements of a QD charge sensor, which necessitates design
methodology and trade-off analysis between the sensitivity and the
bandwidth for different circuits.
In this paper, a physically defined silicon QD26–28 is fabricated
and characterized as a testbed to establish the design scheme of a
matching circuit for RF reflectometry. The I-V characteristics and S-
parameters of the QD are measured to extract the equivalent circuit
parameters at the measurement plane located on the bonding pads
of the QD chip. The expected sensitivity and bandwidth are analyt-
ically obtained for three simple, typical kinds of matching circuits.
The result can be used to obtain the optimal circuit parameters given
the model parameters for the QD sensor and the target performance.
The circuit design formulations are derived to obtain impedance
matching between the 50 Ω input port and the QD equivalent circuit

AIP Advances 13, 035219 (2023); doi: 10.1063/5.0141092 13, 035219-1

© Author(s) 2023
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represented by an RC parallel circuit. The sensitivity to changes in
the resistance or capacitance and the frequency bandwidth are ana-
lyzed and compared among the circuits. A selection criterion for the
appropriate circuit in terms of sensitivity and bandwidth is given,
and its simulated performance for the quantum dot measured in the
experiment is presented.
between the source and drain bond pads are obtained by a de-
embedding technique from the measurement results of calibrated
S-parameters and the simulated S-parameters between the pads and
the SMA connectors on the PCB (S-parameters of the PCB and con-
nectors are simulated with Ansys HFSS, bonding wires simulated
with Keysight ADS).

II. DEVICE III. MEASUREMENTS

The device used in this study is an n-type physically defined sil-
icon QD fabricated as previously reported.27,28 Figure 1(a) shows a
scanning electron microscope image of the physically defined sili-
con QD device. The device has an n+-polysilicon top-gate on top of
an insulating layer that induces electrons in the silicon-on-insulator
(SOI) layer. The sensor QD is connected to the source and drain
electrodes, and one side-gate located nearby is biased to adjust the
potential of the sensor QD. The drain and source contacts of the
charge sensor QD are connected to ports one and two of the vector
network analyzer (VNA) via RF-through of bias tees, respectively,
as well as to DC measurement systems via DC-through of bias tees.
Figure 1(b) shows a photograph of the silicon QD chip mounted
on a printed circuit board (PCB). Each pad on the silicon chip is
connected to the external circuitry by bonding wires and transmis-
sion lines. Sub Miniature Type A (SMA) connectors are mounted on
the back side of the PCB and connected to the measurement system
via RF cables. The calibration planes of the S-parameter measure-
ment are at the SMA connectors on the PCB, and the S-parameters
A detailed equivalent circuit of a QD can be given by using a
parasitic capacitance, a tunnel junction (consisting of a parallel cir-
cuit of tunnel resistance and tunnel capacitance), and a gate-voltage
dependent current source.29 While this can reproduce various elec-
trical properties (including IV characteristics), for RF reflectometry,
it can be simplified to a good approximation as a parallel circuit with
only a resistor and a capacitor.4 Theoretically, both of these para-
meters can be evaluated only by measuring the S-parameters. The
reflection coefficient should ideally yield both the resistance (RQD )
and the capacitance (CQD ) of the QD. RQD can be calculated from
the reflection coefficient at low frequency. When the absolute value
of reflection coefficient at low frequencies, such as near DC, is Γ0 and
the port impedance is Z0 , RQD is calculated as
1 + Γ0
RQD = Z0. (1)
1 − Γ0
The capacitance of the QD (CQD ) is calculated as

√
RQD (Γ2 − 2Γ cos θ + 1) + R2QD (Γ2 − 2Γ cos θ + 1) − 16Z02 Γ2 sin2 θ
2

CQD = − , (2)
4ΓωRQD Z0 sin θ

where Γ is the absolute value of the reflection coefficient, θ is the
reflection phase, and ω is the angular frequency. However, RQD is
difficult to extract accurately only from the reflection amplitude
since it is very high compared to Z0 = 50 Ω. Therefore, in this paper,
we calculate the resistance from the I-V characteristic.
Figure 2 shows the I-V characteristic and S-parameters of the
QD device. All measurements were performed at a temperature
of 4.2 K, for a top-gate voltage of 10 V, and a drain voltage of
300 μV. The I-V characteristic is measured using a lock-in ampli-
fier technique at 71 Hz. I-V amplifier and AC voltmeter are used

FIG. 1. Pictures of the silicon QD device. (a) Scanning electron micrograph of the QD device nominally identical to the one measured in this work. A physically defined silicon
QD is formed by etching an undoped (100) silicon-on-insulator (SOI) substrate. The dark area shows where the silicon layer is etched and the buried oxide is revealed. The
part of the device characterized in this measurement is a charge sensor QD on the bottom side of the micrograph. A series triple QD with three gates on the upper side is not
used in this study (the gates are set at 0 V). (b) Picture of the Si QD chip mounted on a PCB. The measurement plane of the S-parameters is at the metal bond pads on the
silicon QD chip.

AIP Advances 13, 035219 (2023); doi: 10.1063/5.0141092 13, 035219-2

© Author(s) 2023
 AIP Advances
FIG. 2. Measurement results of the QD device. (a) Drain current dependence on the side-gate voltage. (b) Resistance of the charge sensor QD as a function of the side-gate
voltage. (c) Phase of the S11 . The solid red (dotted blue) line shows the result for V sg = −3.5 V, (−4.0 V) with smoothing applied. The dashed black line shows the fit result
to the parallel RC circuit model for V sg = −3.5 V, with the best values RQD = 1.4 MΩ and CQD = 65 fF. Fitting of the result for V sg = −4.0 V yields a very similar value of
CQD .
and the current values are calculated from their conversion fac-
tors. Figure 2(a) shows the side-gate voltage (V sg ) dependence of
the drain current (I ds ). The current shows a peak when the side-
gate voltage is swept between −2.5 and −4.0 V: a so-called Coulomb
peak30 of the QD. Figure 2(b) shows the V sg dependence of the resis-
tance of the charge sensor QD (RQD ). Figure 2(c) compares the phase
of S11 for V sg = −3.5 and −4.0 V, for which the change in conduc-
tance is large. We note that RF reflectometry can read out the change
in the resistance and/or the capacitance of a QD due to the varia-
tion in the QD potential or the energy dispersion. However, the V sg
dependence of the reflection phase of the QD is found small enough
to be neglected in this device, meaning that the reflection phase in
the present circuit is not sensitive to the resistance change. Its fre-
quency dependence can be well fit by the RC model circuit with RQD
= 1.4 MΩ and CQD = 65 fF using Eq. (2), suggesting the validity of
the model in this frequency range. The value of the resistance of the
QD is higher than that of typical gate defined Si/SiGe QD31 (∼100
kΩ) because we use physically defined QD. Physically defined QD
can be realized with fewer gates compared to gate defined QDs, but
it is difficult to adjust tunneling resistance electrically. The value of
CQD is smaller than the typical parasitic capacitance (on the order
of several hundreds of fF) seen in the conventional reflectome-
try measurements with bond wires or transmission lines of PCBs
included.5
IV. CIRCUIT DESIGN AND ANALYSIS
The circuit model obtained above should help to devise the
matching circuit toward improved sensing performance. In the fol-
lowing, three simple impedance matching circuits are considered as
schematically shown in Fig. 3 and a comparison is given in terms
of sensitivity and impedance matching bandwidth. In all types (a, b,
and c), the matching circuit consists of two elements, one series and
one shunt. The charge sensor QD is modeled by an RC parallel cir-
cuit, parameterized by RQD and CQD that take the values of R0 and
C0 , respectively, under the default bias condition. The values of the
components in the matching circuit for a given working (angular)
frequency ω = ω0 are then determined to match the input impedance
of the overall circuits (Zx with x = a, b, c) to the port impedance (Z0 ).
AIP Advances 13, 035219 (2023); doi: 10.1063/5.0141092
© Author(s) 2023
ARTICLE scitation.org/journal/adv
The sensitivity indices to a change in RQD (SR ) and to a change in
CQD (SC ) for circuit x are defined as
∂∣Zx ∣
SRx = ∣ , (3)
∂RQD RQD =R0 ,CQD =C0 ,ω=ω0
∂∣Zx ∣
SCx = ∣ , (4)
∂CQD RQD =R0 ,CQD =C0 ,ω=ω0
respectively. The larger the absolute value of the index, the higher the
sensitivity to the corresponding change. In addition, the frequency
derivative of the impedance
∂∣Zx ∣
Dωx = ∣ (5)
∂ω RQD =R0 ,CQD =C0 ,ω=ω0
can be used to evaluate the bandwidth of impedance matching at
the default bias. The smaller the absolute value of this value, the
wider the bandwidth of impedance matching. Table I shows the
calculation results for the three matching circuits. Note that in the
calculation, R0 > Z0 is assumed. The circuit parameters in Table I
give the values for which the impedance matching to Z0 is realized.
The calculated values of the circuit parameters for circuits (a), (b),
and (c) are shown by Eqs. (6), (7), (12), (13), (17), and (18), respec-
tively. Interestingly, the resistance sensitivity indices, ∣SRa ∣, ∣SRb ∣, and
∣SRc ∣, are the same values for the three circuit types, as given by Eqs.
(8), (14), and (19). These expressions show that higher sensitivity to
change in resistance of QD is obtained by lowering R0 (closer to Z0 ).
The capacitance sensitivity indices, ∣SCa ∣, ∣SCb ∣, and ∣SCc ∣, are also the
same for three circuits, as shown by Eqs. (9), (15), and (20). Based
on the calculation, the capacitance sensitivity will be enhanced by
increasing R0 and ω0 . We note that the sensitivity will be improved
for a smaller value of R0 for resistance readout while the opposite
is the case for capacitance readout, meaning that the optimal con-
dition depends on the readout mode. The bandwidth indices, ∣Dωa ∣,
∣Dωb ∣, and ∣Dωc ∣, are shown by Eqs. (10), (16), and (21). It can be
seen that the frequency bandwidths are wider in the order of cir-
cuits (c), (a), and (b). Based on the discussion up to this point, it
may seem that circuit (c) is the best among the three, with the widest
bandwidth ∣Dωx ∣ and the identical sensitivities (∣SRx ∣, ∣SCx ∣). However,
13, 035219-3
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FIG. 3. Schematics of a matching circuit and a QD charge sensor. QD charge sensors are represented as resistance (RQD ) and capacitance (CQD ) in parallel. (a) Matching
circuit composed of a shunt capacitor (Ca ) and a series inductor (La ). (b) Matching circuit composed of a shunt inductor (Lb ) and a series capacitor (Cb ). (c) Matching circuit
composed of a shunt inductor (Lc1 ) and a series inductor (Lc2 ).

TABLE I. Calculation results for matching circuits.

Circuit (a) Circuit (b) Circuit (c)

√
Ca = ω01R0 R0Z−Z 0
− C0 (6) Cb = √ 1
(12) Lc1 = √
R0 Z0
− C0 (17)
Circuit parameters 0 ω0 (R0 −Z0 )Z0 ω0 (ω0 C0 R0 Z0 − (R0 −Z0 )Z0 )
√ √
(R0 −Z0 )Z0 (R0 −Z0 )Z0
La = (7) Lb = √
R0 Z0
(13) Lc2 = (18)
ω0 ω0 (ω0 C0 R0 Z0 + (R0 −Z0 )Z0 ) ω0

2 2 2
∣SRx ∣ − 2( RZ00 )
Z0
R0
(8) Z0
R0
− 2( RZ00 ) (14) Z0
R0
− 2( RZ00 ) (19)
√ √ √
∣SCx ∣ 2ω0 Z0 (R0 − Z0 )Z0 (9) 2ω0 Z0 (R0 − Z0 )Z0 (15) 2ω0 Z0 (R0 − Z0 )Z0 (20)
2(R0 −Z0 )Z0 2(R0 −Z0 )Z0
√ 2(R0 −Z0 )Z0
√
∣Dωx ∣ ω0 R0
(10) ω0 R0
+ 4C0 Z0 (R0 − Z0 )Z0 (16) ω0 R0
− 4C0 Z0 (R0 − Z0 )Z0 (21)
√ √
R0 −Z0
Restrictions ω0 < 1
C0 R0 Z0
(11) ⋅⋅⋅ ω0 > C01R0 R0Z−Z 0
0
(22)

this circuit cannot be always used, since for a particular combina- Lc2 = 666 nH. The performance of the designed circuit is checked by
tion of the values of R0 and C0 , the shunt inductance value given by small-signal simulation (see Fig. 5). The reflection is calculated for
Eq. (17) becomes negative [see also expression (22)]. In this para- different values of V sg or RQD , which emulates the effect of the elec-
meter regime, circuit (a) becomes realizable and will be the best tric field change at the sensor QD. Figure 5(a) shows the frequency
choice among the three. The diagram of the best circuit as a function dependence of the reflection amplitude of the designed QD charge
of R0 and C0 is given in Fig. 4 for several different values of the work-
ing frequency, ω0 /(2π). In the lower left region of the line, circuit (a)
can be realized, and in the upper right region, circuit (c) can be real-
ized. On the lines, a matching circuit with only one series inductor
can be realized. The boundary is at 293 MHz for the extracted RC
parameters. Once the equivalent circuit parameters are known, the
optimal circuit configuration can be determined accordingly.
Based on the analysis above, an optimal impedance matching
circuit can be designed for our QD using the extracted equivalent
circuit parameters (R0 = 1.4 MΩ and C0 = 65 fF, that is, the default
bias is V sg = −3.5 V). The port impedance of the reflection mea-
surement is assumed to be 50 Ω, which is the standard for normal
measurement systems. The working frequency is assumed to be 2
GHz—we note that a higher frequency leads to wider matching
bandwidth [see (10), (16), and (21)] and compact circuit parameters
but it comes at the cost of the increased effects of parasitic com-
ponents. Figure 4 indicates that for the given parameters, circuit
(c) should be optimal in terms of the bandwidth with the resis- FIG. 4. Optimal circuit configuration when the resistance and the capacitance of
tance sensitivity equivalent to that from circuit (b) while circuit (a) the equivalent circuit of a QD are given. The red solid curve, the blue dashed
cannot realize impedance matching. Using expressions (17)) and curve, and the green dotted curve shows the boundary between the optimal circuit
(18), the circuit parameters are calculated as Lc1 = 114 nH and
configurations for the frequency of 100 MHz, 500 MHz, and 1 GHz, respectively.

AIP Advances 13, 035219 (2023); doi: 10.1063/5.0141092 13, 035219-4

© Author(s) 2023
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FIG. 5. Simulation results of the

designed QD charge sensor with
matching circuit (c). (a) Dependence of
the reflection amplitude on the carrier
frequency. The red solid line shows the
reflection amplitude when RQD = 1.4 MΩ
and CQD = 65 fF and the blue dashed
line shows when RQD = 5.1 MΩ and
CQD = 65 fF. (b) Dependence of the
reflection amplitude of the designed QD
charge sensor on RQD at 2 GHz with
CQD = 65 fF.

sensor for two conditions: RQD = 1.4 MΩ and CQD = 65 fF corre-
sponding to V sg = −3.5 V (the red solid trace) and RQD = 5.1 MΩ
and CQD = 65 fF corresponding to V sg = −4.0 V (the blue dashed
trace). When V sg is changed from V sg = −3.5 V to −4.0 V, the reflec-
tion amplitude at 2 GHz changes from less than −40 dB to about
−4.9 dB (due to design accuracy and measurement accuracy, there
is no predominant difference below −40 dB). The bandwidth with
reflection amplitude of less than −10 dB is 0.8 MHz, which is suffi-
cient for high-speed readout and multiplexing. Figure 5(b) shows the
RQD dependence of the reflection amplitude at 2 GHz. The reflection
amplitude is changed significantly when the value of RQD is varied
from RQD = 1.4 MΩ, where the circuit is impedance matched to the
50 Ω system.
V. CONCLUSION
In conclusion, a physically defined silicon QD device was mea-
sured, and the equivalent circuit parameters of the QD chip at a
cryogenic temperature were extracted from the S-parameter mea-
surements in combination with the deembedding technique. Design
methodology for the three matching circuits consisting of two LC
components was established, with comparisons made in terms of the
sensing sensitivity and bandwidth. The design and the simulation of
the impedance matching circuit with a series inductor and a shunt
inductor are performed. A concrete design procedure is outlined
once the equivalent circuit parameters for the QD chip are obtained.
These results should facilitate the realization of RF reflectometry of
semiconductor qubits on various QD platforms.
AUTHOR DECLARATIONS
Conflict of Interest
The authors have no conflicts to disclose.
Author Contributions
J. Kamioka: Conceptualization (equal); Data curation (equal); For-
mal analysis (equal); Methodology (equal); Validation (equal); Visu-
alization (equal); Writing – original draft (equal). R. Matsuda: Data
curation (supporting); Writing – review & editing (supporting).
R. Mizokuchi: Writing – review & editing (supporting). J. Yoneda:
Supervision (supporting); Writing – review & editing (equal).
T. Kodera: Project administration (lead); Resources (lead); Super-
vision (lead); Writing – review & editing (equal).
DATA AVAILABILITY
The data that support the findings of this study are available
from the corresponding author upon reasonable request.
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AIP Advances 13, 035219 (2023); doi: 10.1063/5.0141092 13, 035219-6

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