UE21EC251A

P.E.S. University
(Established Under Karnataka Act 16 of 2013)
100-ft Ring Road, BSK 3rd Stage, Bangalore – 560085
Department of Electronics and Communication Engg.

Digital VLSI Design Lab

UE21EC251A
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EXPERIMENT-1
CMOS Inverter
Aim: Design symmetrical CMOS inverter and determine
1. Critical voltages, Noise Margin NMH and NML, Power Dissipation
2. Determine rise time, fall time, propagation delay
3. Draw the Layout and do the following Verifications

i) Design Rule Check (DRC)

ii) Layout Vs Schematic Match (LVS)
iii) Generate the Parasitic View of the Layout
iv) Delay Calculation using Parasitic Elements

Theory:
The circuit topology is complementary push-pull in the sense that for high input, the nMOS
transistor drives (pulls down) the output node while the pMOS transistor acts as the load, and
for low input the pMOS transistor drives (pulls up) the output node while the nMOS transistor
acts as the load. Consequently, both devices contribute equally to the circuit operation
characteristics. This structure is called Complementary Metal Oxide Semiconductor (CMOS).

Design:

Assumptions: Symmetric Inverter is considered

VTH of the symmetrical inverter is given by

𝟏
(𝑽𝑻𝒐𝒏 + √𝑲 )𝑿(𝑽𝑫𝑫 + 𝑽𝑻𝒐𝒑 )
𝒓
𝑽𝑻𝑯 =
𝟏
𝟏 + √𝑲
𝒓

Ideally
𝑽
VTH is given by 𝑫𝑫
𝟐

𝑲𝑷
=𝟏
𝑲𝒏

𝑼𝑷
= 𝟐. 𝟓
𝑼𝒏

Ln=Lp=250nm

Therefore Wn=2.5Wp
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The DC Transfer Characteristics of the CMOS inverter operating in different

regions of operation is given in below figure. Table shows the operating regions pMOS
and nMOS device and Vout in different regions of the CMOS inverter.

Procedure:

1. Rig the CMOS inverter in the sedit

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2. Convert it into the sybmol

3. Use the symbol in the test bench, include voltage sources, IN / OUT ports,
Voltage print as shown in the fig below.

4. Setup the simulution environment

i. In general library file and enalbe voltage waveform
probing,
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ii. DC sweep analysis, (parameter name may change

according the order of the voltage sources used, may vv1
or vv2)

iii. Transient analysis)

5. Click on simulation, and verify the Transient and DC VTC waveforms in

waveform window

6. Click on Icon T in Sedit and check and note down the NETLIST
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7. To measure the input / output fall time, rise time, frequency, Noise Margin. From
the Spice_Measure choose TRAN_FALLTIME, TRAN_RISETIME,
TRAN_Frequency, TRAN_PULSEWIDTH and DC_NoiseMargin and place in
the schematic window as shown in the video.

8. Also include Tran_NONINVERTING_DELAY , connections are same as the

DC_NOISEMARGIN

9. Also include Voltage Power probe { click on Spice_plot, then select

Power_voltageSourcePrint and place one the input voltage source and one for
the Vdd supply }
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10. Then click on simulation and in the netlist type command for power analysis as
shown in screenshot below
.power vv1
.power vv2
And click on green arrow marks in the netlist window

11. From the TSpice simulation window note down all the values
Sample Values
Determine rise time, fall time, propagation delay

Noise Margin NMH and NML,

Power Dissipation
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Observations
1. Noise Margin NMH and NML, (Note down the readings of your experiment)

2. Power Dissipation (Note down the readings of your experiment)

3. Determine rise time, fall time, propagation delay (Note down the readings of your
experiment)

Note: Repeat same procedure for different KR and just verify the various in the VTC
(example the VTC shown below)

Results:

Student Name:
Student SRN:
Faculty Signature with date