An 18 mV Offset, 193 ps Sensing Delay, and Low
Static Current Sense Amplifier for SRAM
Pallab Pran Dutta∗ , Arun Mohan B † , and Saroj Mondal‡ , Member, IEEE
Department of Electrical and Electronics Engineering,
Birla Institute of Technology and Science − Pilani, Hyderabad Campus, Hyderabad 500078, India
Email: {∗ h20181230222, † p20170016, ‡ saroj}@hyderabad.bits-pilani.ac.in
Abstract—A highly sensitive sense amplifier for static random
access memory (SRAM) with a very low offset voltage, negligible
static current, and low kickback noise is presented in this paper.
We propose to use a preamplifier stage instead of positive
feedback between the input and the sense amplifier to improve
the sensitivity of the sense amplifier. The proposed sense amplifier
is designed and simulated using 0.18 µm CMOS technology node.
With a supply voltage of 1.4 V and an operating frequency of 1
GHz, the proposed sensing amplifier has a sensing delay of 193.2
ps, which is 85% better than conventional designs. The sense
amplifier has an offset voltage of 18 mV.
Index Terms—Memory, sense amplifier, sensitivity, SRAM,
offset voltage.
I. I NTRODUCTION
Advancements in CMOS process technology and microelec-
tronics circuits enable us to develop high speed and high-
end processors for various applications, ranging from car
electronics to handheld electronic devices, and from health
monitoring to edge computing devices. The speed/speed-up
factor of a processor depends on how fast one can access
the cache memory for a read/write operation [1]. Generally,
a cache memory comprises of static random-access memory
(SRAM) cells since it offers faster read and write operations
when compared to other volatile memory cells. The access
time/speed and sensitivity of an SRAM cell are determined by
the performance of the sense amplifier, which is an operational
transconductance amplifier (OTA).
Sense amplifier is considered as one of the most essential
peripheral circuits in memory devices and plays a vital role
in terms of functionality, reliability, and performance. A sense
amplifier amplifies the difference between the two bit lines
to quickly figure out the stored data in an SRAM cell. Apart
from that, a sense amplifier reduces the voltage swing required
in the highly capacitive bit lines as they amplify a small
differential voltage developed in the bit lines to full swing
outputs that drive the peripheral circuits, thereby reducing
power consumption and delay. On the contrary, due to the
noise, process, voltage, and temperature variation, the exact bit
line signals, 1 or 0, of a memory cell varies over a large range,
and to recognize the stored data correctly, sense amplifier plays
an important role. Therefore, the main function of a sense
amplifier in a memory circuit is amplification, delay and power
reduction, and signal restoration.
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Among the many different sense amplifiers reported, latch
type sense amplifiers are widely preferred since it offers
higher sensing speed and low power consumption [2]. Apart
from that, a sense amplifier must have high sensitivity, low
kickback noise, negligible static current, and quick abandon
of previous value, to compete with todays high-frequency
clocks. Generally, the static power consumption is reduced
by isolating the pull-up and pull-down parts and accessing
them by two different signals [3]. The power consumption can
be further reduced by increasing the sensitivity of the sense
amplifier using a preamplifier and an SR latch at the output
[4]. The kickback noise is reduced by isolating the high swing
output nodes from the input nodes [5]. To abandon previous
values one can periodically charge/discharge each node to
a known value. In this paper, we present a sense amplifier
that utilizes a preamplifier stage instead of positive feedback
stage between the input and the sense amplifier to improve the
sensitivity of the sense amplifier. The proposed sense amplifier
consumes a negligible static current as it breaks the p− and
n−sense parts during the negative phase of a clock.
The rest of the paper is organized as follows: Section II
introduces the basic latched type sense amplifier and how one
can improve the performance further. Section III describes
the proposed latched type sense amplifier and its operation.
Section IV presents post-layout simulation results to validate
the proposed topology and detailed comparison among the-
state-of-the-art sense amplifier, and finally section V concludes
the paper.
II. SENSE AMPLIFIERS
A. Latch Type Sense Amplifer (LTSA)
The conventional latch type sense amplifier is shown in Fig.
1. It comprises of two cross-coupled CMOS inverter pairs, M1 ,
M2 , and M3 , M4 , which acts as a positive feedback circuit
and hence makes it very fast. During the negative half cycle
of a clock, M7 is turned off and M5 and M6 are turned on.
For bit line signals greater than |VT HP |, drain terminals of
M1 , M2 , M3 , and M4 transistors in the cross-coupled inverter
pairs are charged up to bit line voltages. During this phase,
the output does not track any value and simply follows the
input at the bit lines. During the positive half cycle of the
clock, M7 is turned on and M5 and M6 are turned off.
Therefore, based on the input states, cross-coupled inverter
pair will latch 0 or 1, respectively. However, the high static
 VDD
M1 M3
BL M5 BL
M6
M2 M4
CLK
M7
Fig. 1. Conventional latch type sense amplifier.
current of this topology results in a significant power overhead.
Moreover, issues such as kickback noise and quick abandon of
previous values severely degrade its performance. Therefore,
these issues should be addressed before employing them in an
SRAM architecture.
B. Improved LTSA
To minimize the static current in an LTSA, an improved
version of the latch type sense amplifier is shown in Fig. 2.
It comprises of two basic sense amplifier viz. NMOS sense
amplifier (NSA) and PMOS sense amplifier (PSA), and an
equilibration circuitry (EC). The purpose of NSA and PSA is
to pull the bit line values from VDD /2 to 0 and VDD /2 to
VDD , respectively, whereas EC initializes bit lines to VDD /2
to start the sensing operation. To start the sensing operation,
precharge signal is raised to logic high value which will
eventually equilibrate both BL and BL to VDD /2. Now, assert
n − sense (to fire NSA) followed by p − sense (to fire PSA)
signal to pulled BL or BL to 0 or VDD from VDD /2. In this
topology, we are avoiding to fire the sense amplifiers (NSA and
PSA) at the same time to reduce the flow of contention current
[4]. As the bit line swing is reduced from VDD to VDD /2, one
may prefer this topology for low power application. However,
this topology suffers from kickback noise and has a memory
of previous sensing operation.
III. PROPOSED LTSA
The proposed sense amplifier is shown in Fig. 3. It uses
a preamplifier stage to enhance the sensitivity, a clock gated
mechanism (M10 −M13 ) to erase the sense amplifier memory,
and an SR-latch to quickly stabilize the output. The SR latch
helps the sense amplifier to deliver output at the rising edge
of the clock. The preamplifier stage increases the sensitivity
and allows a minimum input voltage less than the threshold
voltage of a MOS transistor. Transistors M12 and M13 are used
to break the p−sense and n−sense part which will eventually
stop the flow of static current and thereby reducing power
consumption. M14 and M15 are incorporated to isolate the
input of the sense amplifier from the high swing output node
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Vdd
p-sense M8
PSA
BL BL
M1 M2
M5
precharge
EC
M6 M7
VDD/2
M3 M4
NSA
n-sense M9
Fig. 2. Improved latch type sense amplifier.
and the positive feedback stage. Moreover, it ensures that the
sensing is not affected by the kickback noise and glitches.
During the precharge phase, when the clock is low, both
OUTX and OUTY are set to VDD . On the contrary, when
the clock goes high M12 and M13 transistors are turned on.
Initially, INY is higher than INX because, tristate buffer output
is logic zero, transistor M17 will be stronger than M16 , and
thus driving the OUTY node to zero, which will eventually
turn off M15 transistor. As a result, the voltage at OUTX
stays at VDD , and VDS of M12 is VDD −VT HN . Buffers are
employed at the output nodes OUTX and OUTY to remove
unwanted glitches from the output. The preamplifier stage
comprises of a single-stage OTA and a tristate buffer as shown
in Fig. 3. The tristate buffer is employed to reduce power
consumption. The OTA amplifies the difference between the
bit line voltages BL and BL. When the BL goes lower
than BL, the current flowing through M20 transistor is larger
than the current in M19 transistor since VSG,20 is higher
than VSG,19 . The current flowing through the branch of M19
and M21 will be mirrored by M22 transistor, but, the current
flowing through M22 transistor is lower than M20 transistor,
which will eventually lower the output voltage of the OTA.
Now, this will cause a transition from low to high at the
output of the tristate buffer. The entire circuit is self-biased
and no external references are used. Therefore, by employing
the preamplifier stage proposed LTSA enhances the sensing
speed and reduces the static power consumption by separating
p− and n−sense parts during the negative phase of the clock.
 VDD p-sense VDD 10

M10 M8 M9 M11
8

OUTY OUTX

Delay (ns)
6
CLK M12 M13 CLK Conventional

Improved

4 Proposed
M14 n-sense M15
INX INY 2
M16 M17

Pre-Amplifier 0

1.4 1.5 1.6 1.7 1.8 1.9 2.0

VDD VDD
V (V)
DD
M18 M23
Fig. 5. Sensing delay comparison among conventional, improved, and
M24 proposed LTSA with respect to supply voltage.
BL

CLK
BL

M19 M20 Tristate Buffer

Conventional
M21 M22 M25 CLK
25

Improved

20 Proposed

Differential Amplifier M26

Delay (ns)
15

SR Latch
OUTYY OUTXX 10

0
S R
0 0.1 0.2 0.3 0.4 0.5 0.6

Bit Line Capacitance (pF)

Fig. 3. Proposed latch type sense amplifier.

Fig. 6. Sensing delay comparison among conventional, improved, and

proposed LTSA with respect to bit line capacitance.

sense amplifier has a better performance compared to the

Fig. 4. Layout of the proposed latch type sense amplifier.
IV. P OST- LAYOUT SIMULATION RESULTS
The proposed sense amplifier is designed and simulated in
0.18 µm CMOS technology and its layout is shown in Fig.
4. The layout dimension of the sense amplifier is 15.641 ×
82.037 µm2 . Post layout simulations are carried out using
standard foundry model files to incorporate the parasitic effects
and process variation.
A. Variation in supply voltage
Constant scaling of device channel length has invariably
allowed designers to reduce the supply voltage. To ensure
robustness and proper functioning of the sense amplifier, the
supply voltage is varied from 1.4 V to 2 V with a step size of
0.1 V, and the corresponding simulation results are shown in
Fig. 5. It has been observed that the sensing delay increases
as the power supply goes down. In every case, the proposed
conventional, and improved LTSA and the variation of sensing
delay with supply voltages is very small.
B. Variation in Bit line capacitance
The variation of sensing delay with the bit line capacitance
is shown in Fig. 6. It is to be noted that the variation of the
bit line capacitance has a drastic effect in the sensing delay
of the improved sense amplifier, whereas it has an almost
negligible effect in the proposed sense amplifier. It depicts
a sub-linear characteristic with bit line capacitance, whereas
it exhibits a near linear variation for both conventional and
improved LTSA.
C. Transient response of the proposed sense amplifier
Fig. 7 shows the transient analysis during the read operation
of the proposed sense amplifier at a supply voltage of 1.8 V
and the operating frequency of 1 GHz. During the negative
half cycle of the clock, M12 and M13 will be turned off and
M8 and M11 will be turned on and drives the output nodes

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 TABLE I
P ERFORMANCE COMPARISON WITH THE STATE - OF - THE ART

Parameters Arora [6] Halim [7] Mehdi [8] Babayan [9] Evert [10] Wicht [11] Anh [12] Proposed
Process 65 nm 0.18 µm 65 nm 0.18 µm 0.18 µm 0.18 µm 0.18 µm 0.18 µm
Offset voltage (mV) 26.23 - - - - - - 18
I-mode V-mode Differential Double-Tail I-mode V-mode H-mode V-mode
Architecture
LTSA LTSA Comparator Comparator LTSA LTSA LTSA LTSA
Supply Voltage (V) 1.2 1.8 1.2 1.2 1.8 1.8 1.8 1.4
Oprt. Frequency - 100 MHz 1 GHz 2.5 GHz - - - 1 GHz
Static Pdiss Low Low Low - Medium Medium High Low
Kickback Noise Medium - Low High High High Medium Low
Sensing Delay (ps) 946 1699 219 - 230 1241 144 193
Total Pdiss (µW) 46 460 755 329 953 947 386 62
Area (µm2 ) - 47.12 55.27 19.80 - - - 35.81
Application NVM ADC ADC ADC SRAM SRAM SRAM SRAM

1.95 sensing speed over traditional sense amplifiers and works at

V (V)

1.30
an operating frequency of 1 GHz with a supply voltage of 1.8
0.65
CLK V. It has a sensing delay of 193.2 ps and an offset voltage
0.00

0.39 of 18 mV. The proposed topology exhibit very-low static

V (V)

0.38
0.37 power consumption because, during the negative phase, p−
0.36 BL
0.35 and n−sense parts are separated from each other and there is
2.5
2.0 no direct path from VDD to GND for tristate buffer. However,
1.5
V (V)

1.0
non-zero static current flow through the preamplifier stage.
0.5 OUTX The active power consumed by the proposed sense amplifier
0.0
2.0
is 62 µW and one can further reduce by adopting a clock gated
1.5
preamplifier instead of a normal preamplifier.
V (V)

1.0
OUTY
0.5
2.0 R EFERENCES
1.5
V (V)

1.0 [1] R. D. Chandankhede, D. P. Acharya, and P. K. Patra, “Design of high

0.5 OUTXX speed sense amplifier for sram,” in IEEE ICACCCT, 2014, pp. 340–343.
0.0
2.0
[2] T. Na, S.-H. Woo, J. Kim, H. Jeong, and S.-O. Jung, “Comparative study
1.5
of various latch-type sense amplifiers,” IEEE TVLSI Systems, vol. 22,
V (V)

1.0 no. 2, pp. 425–429, 2013.

0.5 OUTYY
0.0
0 10 20 30
Time (ns)
Fig. 7. Transient response of the proposed latch type sense amplifier.
OUTX and OUTY to VDD . On the other hand, during the
positive half cycle of the clock BL is higher than BL, node
INY goes higher than INX thus driving OUTX to zero and
OUTY to VDD. OUTXX and OUTYY are glitch-free outputs
after passing through the buffer stage.
Table I shows the performance comparison of the state-
of-the-art sense amplifier designed for SRAMs, non-volatile
memories (NVM), and analog to digital converters (ADC).
Anh et al. achieved a better sensing speed, but suffers from
high kickback noise and static current, and consumes much
higher power than the proposed one.
V. C ONCLUSION
In this paper, a high-performance sense amplifier with
high sensing speed, and low offset voltage is reported. The
proposed sense amplifier shows an 85% improvement in the
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