COMPUTER ARCHITECTURE

LAB 4

Datapath, Control Unit,

and Single-Cycle
Author: HAI CAO XUAN
Hai Cao Xuan EE3043 Computer Architecture 203B3 - DOE - HCMUT

Introduction 2
Objectives 2
Notice 2
Feedback 2

Assembly 3

Single-Cycle Processor 4
Preliminary 4
Problem 5
Requirements 5
Hints 6

Modified Processor 7

Report 9

Appendix 10

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 Hai Cao Xuan EE3043 Computer Architecture 203B3 - DOE - HCMUT

1. Introduction
1.1. Objectives
a. Review your understanding of RV32I instructions by using RISC-V assembly to program.
b. Design a Control Unit to drive the Single-Cycle Processor.
c. Design a Single-Cycle RV32I Processor.

1.2. Notice
Your report has to be formatted in APA style, as an example in Appendix b. You should use Google Docs to
write and then export your report in PDF format. The title will be lab4_student’s ID_student’s name.pdf.
Include your group members' names in the report, each group submits only ONE report.

1.3. Feedback
In case you meet an error or a typo or have any improvement in this document, please email the author:
cxhai.sdh221@hcmut.edu.vn

The subject will be: [COMPARCH203: FEEDBACK LAB 4]

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 Hai Cao Xuan EE3043 Computer Architecture 203B3 - DOE - HCMUT

2. Assembly
a. Convert this simple assembly code into hexadecimal.

1 addi x10, x0, 0x1CA

2 addi x11, x0, 0x784
3 and x12, x10, x11
4 or x13, x10, x11
5 add x14, x12, x13
6 blt x11, x14, _LESS_
7 addi x10, x0, 0x1
8 jal x0, _DONE_
9 _LESS_:
10 addi x10, x0, 0x0
11 _DONE_:

b. Write a code to find the largest number of the Fibonacci sequence less than 32’d500. You will put the
ceiling number in register x10 and save the value you find in 0x400.

c. Write a code in which you read an 8-bit binary in the address 0x500, convert it into 3 decimal digits,
and then write them into 0x420, 0x410, and 0x400, respectively. For example, the value in 0x500 is
0xEE, which is 238, so “2” will be in 0x420, “3” in 0x410, and “8” in 0x400.

To verify the code, use a RISC-V simulator to check. Please visit this: https://venus.cs61c.org/

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 Hai Cao Xuan EE3043 Computer Architecture 203B3 - DOE - HCMUT

3. Single-Cycle Processor
3.1. Preliminary
The figure on the next page is the single-cycle processor, forming from almost all of the students’ designs in the previous labs.

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Hai Cao Xuan EE3043 Computer Architecture 203B3 - DOE - HCMUT

3.2. Problem
Design a Single-Cycle Procesor.

In order to do that, you need to implement the rest of the diagram, which are muxes, PC, ImmGen,...

3.3. Requirements
a. The module name of Immediate Generator is immgen.sv. Its output is imm.

b. The register PC also has clk_i and rst_ni (positive clock and low negative reset).

c. The control unit follows the below guidance:

i. Name: ctrl_unit.sv

ii. Control unit’s inputs:

1. instr: the current instruction.

2. bl_less: the “less” result of the Branch Comparison.

3. bl_equal: the “equal” result of the Branch Comparison.

iii. Control unit’s outputs:

1. bl_sel: the select signal to choose between PC+4 (0) or PC calculated by ALU (1).

2. bl_unsigned: 1 if the two operands are unsigned.

3. rd_wren: 1 if writing to the RegFile, otherwise 0.

4. op_a_sel: the select signal to choose between rs1_data (0) or pc (1) to wire into
operand_a of ALU.

5. op_b_sel: the select signal to choose between rs2_data (0) or imm (1) to wire into
operand_b of ALU.

6. alu_op: an operation that the ALU has to perform.

7. mem_wren: 1 if writing to the LSU, otherwise 0.

8. wb_sel: the select signal to choose between alu_data (0), ld_data (1), or pc_four
(2) to write back into rd_data of RegFile.

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Hai Cao Xuan EE3043 Computer Architecture 203B3 - DOE - HCMUT

9. The module name is lsu.sv.

d. The processor’s name is singlecycle.sv.

e. The processor’s inputs:

i. clk_i, rst_ni: positive clock and low negative reset.

ii. io_sw: 18-bit data from 18 switches on the DE2 board.

f. The processor’s outputs:

i. io_lcd: 32-bit data to drive LCD.

ii. io_ledg: 32-bit data to drive green LEDs.

iii. io_ledr: 32-bit data to drive red LEDs.

iv. io_hex0 .. io_hex7: 8 32-bit data to drive 8 7-segment LEDs.

g. Write the specification of the Single-Cycle Processor, see Lab 1 example.

h. To verify your processor, use the code you write in exercise b of section 2. Assembly.

3.4. Hints
There is no hint for today 🙂

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 Hai Cao Xuan EE3043 Computer Architecture 203B3 - DOE - HCMUT

4. Modified Processor
For those who find the previous diagram basic or want to modify the processor for your own interest, here is a modified processor.

If you want to implement this, I suggest that you should learn Labs 2, 3, and 4 thoroughly first, then try to analyze this design.

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Hai Cao Xuan EE3043 Computer Architecture 203B3 - DOE - HCMUT

A demonstration for I-type instructions.

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 Hai Cao Xuan EE3043 Computer Architecture 203B3 - DOE - HCMUT

5. Report
Students must include those:

1. Design of a Single-Cycle Processor

a. Analysis
b. Design
i. Diagram
ii. Specification
c. Verification
d. Result
e. Discussion

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Hai Cao Xuan EE3043 Computer Architecture 203B3 - DOE - HCMUT

Appendix
a. Lab 0 SystemVerilog
b. Report Template
c. RISC-V Specification
https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-2019121
3.pdf

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