3.

An Analytical Model of Planar Inductors on Lowly Doped Silicon Substrates

for High Frequency Analog Design up to 3 GHz
Jan Crols, Peter Kinget, Jan Craninckx and Michiel Steyaert
Katholieke Universiteit L e u v e n , ESAT-MICAS,
Kardinaal Mercierlaan 94, B-3001 Heverlee, Belgium

Introduction
High frequency analog circuits are crucial components of
today's integrated systems. Especially the full integration of
transceivers for the wireless communication market is growing
enormously in importance. T h e use of planar inductors can
improve these designs drastically : higher operating frequencies
can b e a c h i e v e d , b a n d p a s s operation lowers the p o w e r
consumption and the use of low supply voltages is possible.
T w o main problems arise when using planar inductors on
silicon substrates. First of all there are the large resistive and (4 (b)
capacitive parasitics originating from losses in the aluminum Fig. I :Lqyout of (a) a square and (b) a near circular
conductors, losses in the conducting substrate and capacitive spiral inductor
coupling to this substrate In GaAs. where gold is used for
conductors and where the substrate is non-conductive. these 10 % can not b e obtained as the proposed model is a continuous
parasitics are far less important and planar inductors are widely representation of a device with a discrete parameter (the number of
used In silicon the substrate loss and coupling can be eliminated turns). T h e proposed expression for the inductance holds only for
by etching away, with an extra processing step. the substrate inductors in free air or on lowly doped substrates. Highly doped
under the inductor, either via front [ I ] or back etching [2] Such substrates have a high conductivity, allowing the generation of
an extra processing step is costly, reduces yield and reliability eddy-currents in the substrate. This results in a reduction of the
and is not available in any standard silicon process. magnetic field and thus of the effective inductance value. On
The second problem. which also occurs in GaAs, is h o u to lowly doped substrates, the inductance reduction is below I %.
design circuits with planar inductors. Only two methods are
available : either one uses planar inductors with a geometry
which has already been implemented and measured on a previous SxDlanation of p a r a m e t e r s :
run of t h e p r o c e s s 131, or o n e uses t i m e c o n s u m i n g A r = s 2 (square) or n.7' (circular)
electromagnetic simulations to determine the characteristics of a
chosen geometry [ I ] In both caseh. the performance of a circuit
Armeil,,- metal area
qA, =-_-
is determined by the fixed inductor geometr), without leaving any Ar total area
room to gain an insight in the trade-oft\ between specifications. W width
qx =-_
A structured analog design methodolog! requires the opposite w+sp width + spacing
approach where thc optimal inductor geometry is determined by K , = 1.3. HIm
the required circuit specifications
This paper introduces a model for planar inductors and their a = 1 / 4 (square) or / I 7 (circular)
parasitics on a lowly doped silicon substrate. T h e behavior of -
P,,t"I - sheet resistance of metal
inductors on lowly and heavily doped substrates is compared and I,,f
i t is shown that the electromapeiic losse\ due to the substrate are
U,, = operating frequency [rad I SI
negligible for processes which usc l o w l ~doped substrates Many
processes and even new11 developed deep suh-micron standard K , =3.6 IOy - 6 H z I R
CMOS processes use lowly doped substrates. creating in this way
E, - capacitance of metal
great opportunities to use planar inductors in standard silicon -_
processes without requiring an! special techniques like substrate 1, on fieldoxide
etching. I t is shown in this paper how the developed model can be Rsuh= substrate resistance [ .Q I s q ]
used to d o high frequency analog design with planar inductors
With this model the optimum process parameters. the optimum fsuh = substrate tickness
inductor geometry and the optimum geometr) parameters for a
certain circuit topology can be calculated and evaluated. Table 1 : The proposed analytical model f o r spiral inductors

Model for Planar Inductors
Fig. 1 shows two types of layout for planar spiral inductors
Table 1 gives a lumped model with analytical expressions for the
inductance and the parasitics of such planar inductors. T h e
inductancc L does not depend on the technology, only on the
geometry of the inductor. The proposed expression models the
inductance with an accuracy better than 10 % for a wide range of
different geometries. A less accurate analytical expression for the
inductance can be found in [4] The model presented in this paper
takes into account such parameters as the spacing between the
metal lines (via qAi and q , ) and the extend of the open area in
the middle of the inductor (via qa, I. An accuracy much better than
T h e series resistance R, is, for low frequencies, equal to the
number of squares times the sheet resistance of the metal
conductor [4].This DC model is extended to incorporate the skin
effect which increases the series resistance at high frequencies.
Here the skin effect is modeled for frequencies u p to 3 G H z by
means of an equivalent reduced line width 6 which depends on
frequency and geometry. It models the skin effect with an accuracy
of less than 40 7%. which is, for resistors. sufficient. T h e
inductance increases also due to the skin effect, but at 3 GHz the
increase is still less than 2 7%.
T h e parasitic capacitance C, is proportional to the occupied
metal area. For lowly doped substrates it is important to take the
resistance in series with this capacitance, R,, caused by the low

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conductivity of the substrate, into account. Its actual value
depends o n the geonietry and 011 the position of grounded
substrate contacts. For lowly doped substrates ir is approximately
100 R (for highly doped substrates it is smaller than 1 R). This
large value will, at high operating frequencies, reduce the
influence of the parasitic capacitor (7, on the design.
Verification of the Model
The presented mode:] for the inductance has been derived by
means of both physical interpretation and fittings to the results
of the semi-3D electromagnetic s,imulatIon of more than 5 0 0
different coils. T h e calculation technique of [6] has been used as
extra verification method. Fig. 2 shows, as an example. the ratio
between the simulated inductance and the inductance predicted by
the model versus the inductance valuc for the simulated planar
inductors with both square and circular geometries.
O h 1 low as possible (this is equal to making the quality factor Q
IO’’ 10 10-
L,
Fig.2 : Conrpurison ($tlie inductance mo&I with the results
of electromagnetic simulations (lines indicate 10 7r error)
As final verilicatiori the model has been compared with the
mcastirement results of several rahricated ]planar inductors.
Table 2 gives the comparison hetween the measured inductance
value and the nrodel for three fabricated square inductors. I t also
gives comparisons between the model and measurement values
given i i i literature [ 2 ] . [ 3 ] , [ 5 T
] .h e calculated values agree well
with the measurements. the remaining differences may appear due
to layout style. lead inductances and calibration errors (e.g. : in
131 thc predicted valuc is given to he 1.3 nH).
Tuhle 2 . Cornpurison oftlic rnodel with measurements
urd measurement datu from literature
The model for series resistance 15 derived from a DC-model [4]
which is extended with the frequency dependent skin effect The
skin effect can. at high frequencies (i.e. 3 GIHz), increase the
effective resistancc to 5 times the D C value. Good modeling of
this effect is thus important, hut difficult due to its complex
dependence on the inductor geometry. A trade-off must therefore
be made between a highly accurate and complex or an easy usable
model. T h e skin effect is modeled as an effective line width
reduction 6 reversely proportional to the operating frequency. 6
has again been fitted to t h e resulrs of the s e m i - 3 D
electromagnetic simulation. An accuracy of 40 % ’ for the
complete range ( u p to 3 G H z j is achieved But, for the most
commonly used inductors and for frequencies below 2 GHz is the
accuracy better than 20 %. This accuracy is sufficient because the
procesh variation of‘ the sheet resistance is also about 20 5%.
1996 Symposium on VLSl Circuits Digest of Technical Papers
Authorized licensed use limited to: Tsinghua University. Downloaded on April 11,2023 at 06:37:43 UTC from IEEE Xplore. Restrictions apply.
Design with Planar Inductors
The biggest advantage of the presented model is that It gives
an analytical expression f o r the relationship between layout
parameters ( A T , w , qa, , q,) and electrical parameters ( L , R ,
C). This allows the designer to get a good insight in the design
trade-off’s. With the model these trade-off’s can be rapidly
analyzed and they lead to an optimization on three levels :
Technolog? optimization
Apart from the obvious statement that the sheet resistance of
the conducl.or should be low and that the oxide thickness
should be high, less obvious technology aspects can be
analyzed with the proposed model. One example is whether or
not it is best to use only metal 2 and 3 (thick oxide, low
capacitance) or metal 1,2 and 3 (higher capacitance, lower
resistance).
Geomern optimization
For inductors there arc basically only two electrical
parameters which can be freely chosen (e.g. L and Rs).There
are however more layout parameters (circular or square, A r ,
w, qa, and 77,). Geometry optimization reduces this high
1
degree of freedom to two design parameters A r and w ) by
determining the most optimum values for the other
parameters. This is done by stating that for a given
inductance and a given area, the series resistance should be as
at a given frequency as high as possible).
Desiprr oprimizarion
During the design and optimization process of an analog
integrated Lircuit a hand-calculation model I S very useful. It
allow~sfor the development ot a forward calculation path
which give!.; an immediate translation of the circuit
specifications (operating frequency. bandwidth, gain) to the
layour parameters ( w . / , A r 1 of each component. This is a
great contrast with the time consuming iterative process of
choosing possible layout parameters. running lengthy
siin~lations.analyz.ing the circuil performance and then
choosing new, maybe hetter layout parameters.
Conclusions
An anai)-tic,dl model for planar inductors in air o r on lowly
doped substrates ha\ heen introduced. The model parameters have
been fitted 1.5 means o f electromagnetic himulation and its
validity ha< heen ierified with measurement results In this paper
i t has also been shown how this analytical model can be used to
gain a hetter insight in technology, layour and design trade-off‘s.
References
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