STUDENT ID NO

MULTIMEDIA UNIVERSITY
WI

MULTIMEDIA UNIVERSITY

THIRD TRIMESTER EXAMINATION, SESSION 2004/05

EEN 1046 ELECTRONICS III

(LE, EE, CE, ME, TE, MCE, OPT)

13 APRIL 2005
09:OO AM - 12:OO PM
(2 Hours)

INSTRUCTION TO STUDENT

1. This Question paper consists of 15 pages including cover page with 6 Questions only.

2. Attempt FOUR out of SIX questions. All questions carry equal marks and the
distribution of the marks for each question is given.

3. Please print ail your answers in the answer Booklet provided.

EN 1046
_----__I_ ELECTRONICS--l_l_--___-_l
111 APRIL 2005
IIF

Question 1

(a) For the circuit illustrated below, assume the op-amp is ideal,

R R
Vl JvvW

Figure Q1.l

(i) derive the expression the output voltage v,) in terms of the input voltages VI and
I!2 ,

17 marks]
(ii) determine the input resistance seen by VI alone
[I marks]

(b) For the given comparator in Figure Q1.2, sketch the output signal vONr with respect to
the input signal vin as depicted in Figure Q1.3. Let the output signal swing between
+ 10 V and - IO V and assume that the op-amp is ideal. Determine the times when t)(lU~
changes from +10 V to - 10 V and vice versa.
(7 marks]

Vin

RI R2
12 vm 1
50 kR

Figure 41.2
Continued.. .
EEN 1046 ELECTRONICS III APRIL 2005

Vi*(V)

Figure Ql.3

(c) Determine the output voltage v0 for the inverting summing amplifier in Figure Q1.4,
assuming that the op-amp is ideal, when the inputs are VI mV
v2 = 1 Ocos(1000t) mV.
14 marks]
250kQ

IOkR
v2 JvvW

Figure 41.4

Continued.. .

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KEN 1046 -____- ELECTRONICSI _____---lll--- APRIL 2005

(d) An differentiator shown in Figure Q 1.5 has an input signal of VM and output signal of
vcJUi illustrated in Figure Q1.6. Assuming that the op-amp is ideal.

-
-
-
Figure Q1.5

vou*( V)

20

-20

Figure 41.6

Continued.. .
 EEN 1046
____-. ELECTRONICS III APRIL 2005

(i) design the differentiator circuit when capacitor C is 2 nF. [5 marks]

(ii) this circuit is susceptible to high frequency noise, and the reactance of C
decreases with frequency, which causes an increase in the closed-loop gain.
Suggest a way to improve the noise handling capability at high frequencies.
[l mark]

Continued...

Y/CK W/S WOIRILTSISIA 5115

El.3 104h ___. -.__-_.._____
____- ELECTRONICS 111 APRIL 2005
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Question 2

(a) With the help of a frequency response curve of a Butterworth low-pass filter, define
and explain the definitions of the cutoff frequency and pass band of a Butterworth
filter? 14 marks)

(b) Draw a Sallen-Key circuit for a second-order high-pass filter. Design the filter to have
the Butterworth response with a cutoff frequency of 10 kMz and a maximum pass-
band voltage gain of 1.5858. Assume that only 1 nF capacitors are available and the
feedback resistor (RF) is 100 kQ. (6 marks]

(c) The voltage transfer function for the circuit in Figure Q2.1 is
1
- -..-
V,(s) R,C__I_-_
’
-=
viCs) $2 +__-LS+ 2 _-1_.___
R2C R’, R,C 72
where s =jcl), (11 is the angular frequency in rad/s and R’J = Rr//Rn.

(i) Derive the center angular frequency (ci)c), quality factor (Q) and maximum pass-
band voltage gain (Kpn) in terms of the RI, R’ 1, R2 and C. [S marks]

(ii) If RI = 50 k1(2 and R:! = 100 kC2, design the filter for O‘I~ = 10 k-r-ad/s and
bandwidth BW = 0.02o)c. [7 marks]

Figure Q2.1
 EEN 1046 _ ELECTRONICS 111 APRIL 2005

Question 3

(a) Determine the open-loop voltage gain, A,), of an op-amp for the operating frequency
of 1000 Hz. Assume that the open-loop cutoff frequency, fctOr)= 100 Hz and the mid-
range open-loop voltage gain, Aor(mid) = 100,000.
[3 marks]

00 Calculate the common-mode rejection ratio CMRR (in dB) for an operational
amplifier, given that the output voltage when the differential input voltage V,J= ImV
is 120 mV, and the output voltage when the common-mode input voltage V, = 1 mV
is 20 IrV.
[4 marks]

(4 A certain op amp is used in a feedback configuration having a voltage gain of 30 and

bandwidth of 100 kHz. If the external resistor values are changed to increase the gain
to 60, what is the new bandwidth?
[4 marks]
(4 Figure Q3. I shows the output voltage of an op amp in response to a step input. What
is the slew rate?
[3 marks)]
v o 4

12v

Figure 43.1

Continued...

YKKW/SWO/B/I TSISIA 7115

EENlO46
-_l-__l_- ELECTRONICS 111 lll_l-~l APRIL 2005
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(e) Calculate the total output offset voltage for the circuit in Figure 43.2 with the
specified op amp values in Table 1 below. Explain why the input bias current is not
included in the calculation.
(7 marks1
Parameter C o n d i t i o n s j-s -Units
Input offset Voltage TA=25’C 6
Input Offset Current TA=250C-%4
Input Bias Current TA2
- -5 ° - C 100 nA
Table 1

-
-
Figure Q3.2

(f) Assume the input bias current, Ia= 0 and the input offset current, Ito== 0, with clear
reasons and derivation, show that the output offset voltage for the circuit in Figure
Q3.? is ~VK,, where Vlo is the input offset voltage. [4 marks]
200kR

-
Figure 43.3
Continued...
 EEN 1046 -. - ELECTRONICS 111 APRIL 2005

Question 4

(4
(i) Give 2 internal functions of the IC regulator. [2 marks]

(ii) To overcome the heat dissipated in a pass-transistor, the heat sink must be properly
designed. Give 3 basic required parameters for heat sink design. [3 marks]

(b) Referring to the circuit diagram in Figure 44.1, explain separately how this circuit
works as a voltage regulator to maintain the output voltage when the output voltage
is increased and decreased by varying the load RL.
[4 marks]

Figure Q4. I

(4 Figure ($4.2 shows the basic series-transistor voltage regulator circuit with the
unregulated input voltage, V, = 16V. Given that the zener voltage, V, = 10 V, R =
1 k?$ RI4 = 470 S2 and the DC current gain of Ql, p = 100. Assume the base to
emitter I&ward voltage, VBE is 0.7 V.

Calculate the value for,

(i) ( jutput voltage, V, [2 marks]

(ii) %ener current, I, [5 marks]

(iii) Power dissipated in the pass-transistor, Q1. (3 marks]

Continued.. .

YICKWJSWCMM .‘SSJSIA 9115

 EEN 1046
1_~ ELECT‘RONICSIII APRIL 2005

Unregulated
voltage
v, = 16V

Figure 44.2

(4 The current limiter is designed to protect scientific equipments from overloading.

Figure Q4.3 shows the current limiter network with the unregulated power supply.
Given RI = 17 kR, R2 = 10 kSZ, VBE = 0.7 V. &s is set to 8 R to activate the Q3
during full-load condition.

Find:
(i) Maximum load current, IL crnCW) [2 marks]

(ii) What is the required zener voltage to obtain 9V regulated output voltage?
[4 marks]

Unregtila!ed
cower supply

Figure Q4.3

Continued.. .

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 EEN 1046
I__"-I__ ELECTRONICS111
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Question 5

(a) With the help of block diagram, explain the Barkhausen criterion.
[4 marks]

In context to it, on attaining the Steady State Condition explain what will be the
consequences if
(i) Combined gain of feedback amplifier and feedback network is less than
unity. [2 marks]

(ii) Combined gain of feedback amplifier and feedback network is more than
unity. [2 marks]

(b) Design the Wein-Bridge oscillator to operate at frequency of oscillations 20 kIIz.

The value of capacitor used in feedback network is 1 nF. In oscillator Rl is
the input resistor and IX2 is the feedback resistor of feedback amplifier, whereas
the resistor R is series arm and shunt arm component of feedback network.
[7 marks]

Sketch the design circuit diagrams with labeled component values.

[2 marks]

(c) Design the square-wave generator as shown in Figure 5.1 below.

Figure Q5. I
Continued...

YICKWISWOIB!I .TSISIA 11115

 EEN 1046 ELECTRONICS III APRIL 200.5

For given specification as

f, =4kHz , V,, =I-VEE I=15V

I+Vth j=I+h( =5 V Assume that saturation voltage vary as per relation

I+V,,,) =j-VSatI=Vcc -0.51+V& wh ere R = 10 KQ, assume suitable values for

other resistors if needed.
[S marks]

Continued.. .

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 EEN 1046 ELECTRONICS 111 APRIL 2005
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Question 6

(a) A fu!l-wave precision rectifier, shown in Figure Q6.1, is desired with an input
resistance of 100 kCJ and a peak output signal, vi, , at + IO V for a +3 V peak sinusoidal
input signal, VI . Assume that the op-amps are ideal.
R,/2

A
5
I I

vo
Vi RI 4-

*
-

Figure Q6. I

(9 Reproduce the following schematic in your answer complete with the missing
components essential to construct a full-wave precision rectifier in the right
configuration. (2 marks]

(ii) Determine the values of the resistors to be used. [S marks]

(iii) If the input signal vI has the following waveform in Figure Q6.2, sketch the
output waveform vfj with all the relevant information
[2 marks]

Continued.. .

Y/CKW/SWC)/~4II.TSISIA 13115
 EEN 1046 ELECTRONICS III ll_-____- APRIL 2005

Vi(V)

Figure Q6.2

(b) (i) A comparator is needed to limit the output voltage \‘r, to the zener voltage, VZ,
shown in Figure 46.3 when the input voltage vl is in the negative cycle. Sketch
the comparator configuration using resistor R, an op-amp and a zener diode to
achieve this. [2 marks]
VW

Figure 46.3

(ii) How would you modify the circuit to limit the output voltage, vtv, in both
directions? For the same input signal, vI above. sketch the output voltage.
(4 marks]

Continued.. .

Y/(‘KW/SWO/B/I.TSiS,‘A 14115
.

EEN 1046 ELECTRONICS III APRIL 2005

(c) Using block diagram, design a squarer, where its output, vO is equal to the square of
its input, L’). Derive the expressions for the output from each block systematically.
[7 marks]

End of Paper

YICKWIS WO/R! LTSISIA 15115