Green University of Bangladesh

Department of Computer Science and Engineering(CSE)

Faculty of Sciences and Engineering
Semester: (Spring, Year:2023), B.Sc. in CSE (Day)

LAB REPORT NO #01

Course Title: Digital Logic Design Lab
Course Code: CSE-204 Section: 221-D10

Lab Experiment Name: Consider the truth tables in the given figure and find the SOP
and POS expressions for them.

Student Details

Name ID
1. Nahid Raihan 221002304

Lab Date : 22-03-2023

Submission Date : 17-04-2023
Course Teacher’s Name : Mahmuda Rahman

For Teachers use only:

Lab Report Status
Marks: ………………………………… Signature:.....................
Comments:.............................................. Date:..............................
1. TITLE OF THE LAB EXPERIMENT
Consider the truth tables in the given figure and find the SOP and POS expressions for them.

2. OBJECTIVES
● To attain knowledge on Boolean expression.
● To implement Boolean expression using integrated circuits (IC’s) and verify the truth
table.
● To implement De-Morgan’s Law and verify the truth table.

3. DESIGN
The canonical sum-of-products
(SOP) form for F is,
F (A, B, C) = m1 + m2 + m3 + m5 + m6 + m7
= A’B’C + A’BC’ + A’BC
+ AB’C + ABC’ + ABC
The canonical product-of-sums
(POS) form for F is
F (A, B, C) = M0 • M4
= (A + B + C) • (A’ + B + C)

The canonical SOP form for F is,

F (A, B, C) = m0 + m2 + m4 + m5 + m6
= A’B’C’ + A’BC’ + AB’C’
+ AB’C + ABC’
The canonical POS form for F is
f(A, B, C) = M1 • M3
= (A+ B + C’) • (A+ B’ + C’)
4. IMPLEMENTATION

Fig. A’B’C + A’BC’ + A’BC + AB’C + ABC’ + ABC

Fig. (A + B + C) • (A’ + B + C)
Fig. A’B’C’ + A’BC’ + AB’C’ + AB’C + ABC’

Fig. (A+ B + C’) • (A+ B’ + C’)

5. TEST RESULT
1. Design a circuit diagram for F (A, B, C) = A’B’C + A’BC’ + A’BC + AB’C + ABC’
+ ABC: By testing, it is confirmed that the gate is working as truth table.

2. Design a circuit diagram for F (A, B, C) = (A + B + C) • (A’ + B + C): By testing, it

is confirmed that the gate is working as truth table.
 3. Design a circuit diagram for F (A, B, C) = A’B’C’ + A’BC’ + AB’C’ + AB’C +
ABC’: By testing, it is confirmed that the gate is working as truth table.

4. Design a circuit diagram for F (A, B, C) = (A+ B + C’) • (A+ B’ + C’): By testing, it
is confirmed that the gate is working as truth table.

6. ANALYSIS AND DISCUSSION

1. Every result is expected. Output of every gate gives the exact same output as the truth
tables.
2. Implication of SOP and POS went well.
3. Combining the gates has caused trouble.
4. Adding the inverted gates was the most difficult part.
5. The assignment helps to implement functions using SOP and POS.
6. I’ve learned SOP, POS, truth table, implementation, designing a circuit, and canonical
forms.
7. We have attained knowledge on DeMorgan's Law, basic gates, universal gates, truth
table, canonical forms, implementation, designing a circuit, SOP, POS and function
simplification. using an IC circuit , making gates and verified the truth tables. That
means, we've achieved our objectives.